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[97.113.13.231]) by smtp.gmail.com with ESMTPSA id m9sm2751274pgd.23.2019.05.18.12.02.13 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 18 May 2019 12:02:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=2Z/xMZNbQQoNoZQShCqBViE6D5UwKBhH3tq+yJTAfz4=; b=SHVMKSlAm8YY9ESIqjMGZia8cRwr3363o57U/3uAfbatVFlhJLlx8pqzt7ynOMBp7A m4CiWEwVrQ6bQUPH12TBqjsE6GZbIQvqxBM9ziC2lzahrUREbSXdsYw8o3tU8tJyACoS d1tByaWRjzHeTsr5SKs7xnvxcT06T4K0Qro51hfvWC2ry3OUek6MdzACEJSGfUKpnm9Q JoKuptpsb0lwENFPTWLBPi4e4qtF1oDZaLIeBoitZ6bTBJsLxLOiZ30zjOZvqlAfziA6 bYT83o9KwvgIPCiYjGsGFPGHZdkiPYfqQ5fBKTQ3OJB9E0vt3CVSIn4lZkqxDk/oa6a6 PTjg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=2Z/xMZNbQQoNoZQShCqBViE6D5UwKBhH3tq+yJTAfz4=; b=hMcg6hXu1rH9oH42vHrGbelGD6GFwoJIa8PTzSOWLMQCLeHKpGySBodq3wDW5T5NCP 2YRTQ2WDWE0AtQDoPSNNDoOKeXdTbEeRDTHaWWNIM976HkV+lRhgfKy9mlXe4pU01TDS 4vHv42tWQv5mu4AJ07xeWq5cVHuiQNID31nwrZ5c1Q2t26PFecU+GoVceojOt3GTrn7r ni+C+VDXsWbaEqOaEWLuqp0fOgYjqErVyTQ33jYQEfzHdQ+vnwZwBJtwuCS1o8o4KlZ2 j+/3EVsBf8wNESCCxa1LGpndugCjNJhTMwSLe5iMiQIL7zqGVSr/a+mFM7mf/vEnDsVn NiVQ== X-Gm-Message-State: APjAAAXtEgeVzO97ITT2fjLNwTRtQsU/MpoHSxOYUMBt8mlLNL6wfLJJ ELQWT7QZkjz0C3TAR3eS69tKkEZuToY= X-Google-Smtp-Source: APXvYqwB0P5y20DjUa71qneTcQGLHvEtiqkowjlaTrbiQyGPnXEsMTPDhz6ZaQzOmSwSYdKu0rii5Q== X-Received: by 2002:a62:ea0a:: with SMTP id t10mr69243715pfh.236.1558206134214; Sat, 18 May 2019 12:02:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 18 May 2019 12:01:52 -0700 Message-Id: <20190518190157.21255-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190518190157.21255-1-richard.henderson@linaro.org> References: <20190518190157.21255-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH 11/16] tcg/aarch64: Support vector bitwise select value X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The instruction set has 3 insns that perform the same operation, only varying in which operand must overlap the destination. We can represent the operation without overlap and choose based on the operands seen. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.h | 2 +- tcg/aarch64/tcg-target.inc.c | 24 +++++++++++++++++++++++- 2 files changed, 24 insertions(+), 2 deletions(-) diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index b4a9d36bbc..ca214f6909 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -140,7 +140,7 @@ typedef enum { #define TCG_TARGET_HAS_mul_vec 1 #define TCG_TARGET_HAS_sat_vec 1 #define TCG_TARGET_HAS_minmax_vec 1 -#define TCG_TARGET_HAS_bitsel_vec 0 +#define TCG_TARGET_HAS_bitsel_vec 1 #define TCG_TARGET_HAS_cmpsel_vec 0 =20 #define TCG_TARGET_DEFAULT_MO (0) diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c index 40bf35079a..e99149cda7 100644 --- a/tcg/aarch64/tcg-target.inc.c +++ b/tcg/aarch64/tcg-target.inc.c @@ -523,6 +523,9 @@ typedef enum { I3616_ADD =3D 0x0e208400, I3616_AND =3D 0x0e201c00, I3616_BIC =3D 0x0e601c00, + I3616_BIF =3D 0x2ee01c00, + I3616_BIT =3D 0x2ea01c00, + I3616_BSL =3D 0x2e601c00, I3616_EOR =3D 0x2e201c00, I3616_MUL =3D 0x0e209c00, I3616_ORR =3D 0x0ea01c00, @@ -2181,7 +2184,7 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode o= pc, =20 TCGType type =3D vecl + TCG_TYPE_V64; unsigned is_q =3D vecl; - TCGArg a0, a1, a2; + TCGArg a0, a1, a2, a3; =20 a0 =3D args[0]; a1 =3D args[1]; @@ -2304,6 +2307,20 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, } break; =20 + case INDEX_op_bitsel_vec: + a3 =3D args[3]; + if (a0 =3D=3D a3) { + tcg_out_insn(s, 3616, BIT, is_q, 0, a0, a2, a1); + } else if (a0 =3D=3D a2) { + tcg_out_insn(s, 3616, BIF, is_q, 0, a0, a3, a1); + } else { + if (a0 !=3D a1) { + tcg_out_mov(s, type, a0, a1); + } + tcg_out_insn(s, 3616, BSL, is_q, 0, a0, a2, a3); + } + break; + case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */ case INDEX_op_dupi_vec: /* Always emitted via tcg_out_movi. */ case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */ @@ -2334,6 +2351,7 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, = unsigned vece) case INDEX_op_usadd_vec: case INDEX_op_ussub_vec: case INDEX_op_shlv_vec: + case INDEX_op_bitsel_vec: return 1; case INDEX_op_shrv_vec: case INDEX_op_sarv_vec: @@ -2408,6 +2426,8 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) =3D { .args_ct_str =3D { "r", "r", "rA", "rZ", "rZ" } }; static const TCGTargetOpDef add2 =3D { .args_ct_str =3D { "r", "r", "rZ", "rZ", "rA", "rMZ" } }; + static const TCGTargetOpDef w_w_w_w + =3D { .args_ct_str =3D { "w", "w", "w", "w" } }; =20 switch (op) { case INDEX_op_goto_ptr: @@ -2580,6 +2600,8 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) return &w_wr; case INDEX_op_cmp_vec: return &w_w_wZ; + case INDEX_op_bitsel_vec: + return &w_w_w_w; =20 default: return NULL; --=20 2.17.1