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X-Received-From: 2607:f8b0:4864:20::b41 Subject: [Qemu-devel] [RISU v2 03/11] risu_i386: move reginfo-related code to risu_reginfo_i386.c X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jan Bobek , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) In order to build risu successfully for i386, we need files risu_reginfo_i386.{h,c}; this patch adds the latter by extracting the relevant code from risu_i386.c. This patch is pure code motion; no functional changes were made. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Jan Bobek Reviewed-by: Richard Henderson --- risu_i386.c | 54 ----------------------------------- risu_reginfo_i386.c | 68 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 68 insertions(+), 54 deletions(-) create mode 100644 risu_reginfo_i386.c diff --git a/risu_i386.c b/risu_i386.c index 6798a78..2d2f325 100644 --- a/risu_i386.c +++ b/risu_i386.c @@ -33,43 +33,6 @@ void advance_pc(void *vuc) uc->uc_mcontext.gregs[REG_EIP] +=3D 2; } =20 -static void fill_reginfo(struct reginfo *ri, ucontext_t * uc) -{ - int i; - for (i =3D 0; i < NGREG; i++) { - switch (i) { - case REG_ESP: - case REG_UESP: - case REG_GS: - case REG_FS: - case REG_ES: - case REG_DS: - case REG_TRAPNO: - case REG_EFL: - /* Don't store these registers as it results in mismatches. - * In particular valgrind has different values for some - * segment registers, and they're boring anyway. - * We really shouldn't be ignoring EFL but valgrind doesn't - * seem to set it right and I don't care to investigate. - */ - ri->gregs[i] =3D 0xDEADBEEF; - break; - case REG_EIP: - /* Store the offset from the start of the test image */ - ri->gregs[i] =3D uc->uc_mcontext.gregs[i] - image_start_addres= s; - break; - default: - ri->gregs[i] =3D uc->uc_mcontext.gregs[i]; - break; - } - } - /* x86 insns aren't 32 bit but we're not really testing x86 so - * this is just to distinguish 'do compare' from 'stop' - */ - ri->faulting_insn =3D *((uint32_t *) uc->uc_mcontext.gregs[REG_EIP]); -} - - int send_register_info(int sock, void *uc) { struct reginfo ri; @@ -100,23 +63,6 @@ int recv_and_compare_register_info(int sock, void *uc) return resp; } =20 -static char *regname[] =3D { - "GS", "FS", "ES", "DS", "EDI", "ESI", "EBP", "ESP", - "EBX", "EDX", "ECX", "EAX", "TRAPNO", "ERR", "EIP", - "CS", "EFL", "UESP", "SS", 0 -}; - -static void dump_reginfo(struct reginfo *ri) -{ - int i; - fprintf(stderr, " faulting insn %x\n", ri->faulting_insn); - for (i =3D 0; i < NGREG; i++) { - fprintf(stderr, " %s: %x\n", regname[i] ? regname[i] : "???", - ri->gregs[i]); - } -} - - /* Print a useful report on the status of the last comparison * done in recv_and_compare_register_info(). This is called on * exit, so need not restrict itself to signal-safe functions. diff --git a/risu_reginfo_i386.c b/risu_reginfo_i386.c new file mode 100644 index 0000000..e8d671f --- /dev/null +++ b/risu_reginfo_i386.c @@ -0,0 +1,68 @@ +/*************************************************************************= ****** + * Copyright (c) 2010 Linaro Limited + * All rights reserved. This program and the accompanying materials + * are made available under the terms of the Eclipse Public License v1.0 + * which accompanies this distribution, and is available at + * http://www.eclipse.org/legal/epl-v10.html + * + * Contributors: + * Peter Maydell (Linaro) - initial implementation + *************************************************************************= *****/ + +#include +#include + +#include "risu.h" +#include "risu_reginfo_i386.h" + +static void fill_reginfo(struct reginfo *ri, ucontext_t * uc) +{ + int i; + for (i =3D 0; i < NGREG; i++) { + switch (i) { + case REG_ESP: + case REG_UESP: + case REG_GS: + case REG_FS: + case REG_ES: + case REG_DS: + case REG_TRAPNO: + case REG_EFL: + /* Don't store these registers as it results in mismatches. + * In particular valgrind has different values for some + * segment registers, and they're boring anyway. + * We really shouldn't be ignoring EFL but valgrind doesn't + * seem to set it right and I don't care to investigate. + */ + ri->gregs[i] =3D 0xDEADBEEF; + break; + case REG_EIP: + /* Store the offset from the start of the test image */ + ri->gregs[i] =3D uc->uc_mcontext.gregs[i] - image_start_addres= s; + break; + default: + ri->gregs[i] =3D uc->uc_mcontext.gregs[i]; + break; + } + } + /* x86 insns aren't 32 bit but we're not really testing x86 so + * this is just to distinguish 'do compare' from 'stop' + */ + ri->faulting_insn =3D *((uint32_t *) uc->uc_mcontext.gregs[REG_EIP]); +} + +static char *regname[] =3D { + "GS", "FS", "ES", "DS", "EDI", "ESI", "EBP", "ESP", + "EBX", "EDX", "ECX", "EAX", "TRAPNO", "ERR", "EIP", + "CS", "EFL", "UESP", "SS", 0 +}; + +static void dump_reginfo(struct reginfo *ri) +{ + int i; + fprintf(stderr, " faulting insn %x\n", ri->faulting_insn); + for (i =3D 0; i < NGREG; i++) { + fprintf(stderr, " %s: %x\n", regname[i] ? regname[i] : "???", + ri->gregs[i]); + } +} --=20 2.20.1