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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id y18sm5418641wmd.29.2019.05.17.10.40.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 17 May 2019 10:40:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=7QU2E61ExLPRQ5cVFAuMwBaju416G00wlZEn+t3cGhw=; b=g4tE6OQp4CPXBvjCv3gkW1ESF6ZYG/bQbX38fjpp8rGCiARyxkmapH/GZ6TsnFN8v6 V3+u7yuf9heD7f2QbIG5qK4WyahSPlwaY+UIu3kof/agaWmcNgyvACS6dHGSsiDFfZI0 z4lICVyIK/2ka2qsXpq9Fwzp7GN6Abf4EZ+8UPUfI2DjOW3EN3QZFZ7xfgdVFb3vFkvJ 3xnqlZTnwx2qBTRpUh2FDk/pTrYrRuUz+a7nUV38nUSWN0o5U2xc3w5JB7L2JLFpntkD nTBzZTB2ndhcgK3LfeUAKEFIAZRr96EVDg/g7enOpDXA9fD5MqDqiAP/CFs7jD2B429t un3Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7QU2E61ExLPRQ5cVFAuMwBaju416G00wlZEn+t3cGhw=; b=Vo5UCB2rNUNOBilOMJ2S+Ya7AFehIxgrghXe3cbbPNFkl/K4f7dIPxWibbHuKhYRZ+ fsBP6++5ZDlaUSCYnI5Tru8TcLojNY+ZwcqQ+N44i3V7/XRMHk1b+dqUlNCmJTY2NHCJ aR8tBiI/sHZYyKPOyzgFsH4nX0wYj7t5sfZzSt8ZLXQ1NS008OUrMuW/u7b2hBG6tLPo NBczs2Ph9Oz8xZQCXTBWx8+zEWbl+0PEt5TE2ONEJEpbLcCJBBG/rsJIe8xed3VwTvn/ bA8SA29iQIQu56EqtyN94mmUZdP5BuelnUzCvkKi4ZOMpnMUK3jh2MhvPuX6/rqton0c /p/w== X-Gm-Message-State: APjAAAWnp1y6e9XlSwjkJSahEABOBxTu+YbxKfkqqW2+op09xZTIMfgx zrgttOn4bsnIKNqIScgYpiacebEaOWc= X-Google-Smtp-Source: APXvYqzv9P7GBozUr6OCS4pzol/BcTKHwMiCNd/tlXS3EN9f86BwKFPiAG++cAwDYGulsdx7xyqS2w== X-Received: by 2002:a7b:ce84:: with SMTP id q4mr3044698wmj.41.1558114853382; Fri, 17 May 2019 10:40:53 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Fri, 17 May 2019 18:40:46 +0100 Message-Id: <20190517174046.11146-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190517174046.11146-1-peter.maydell@linaro.org> References: <20190517174046.11146-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::342 Subject: [Qemu-devel] [PATCH 4/4] hw/arm: Correctly disable FPU/DSP for some ARMSSE-based boards X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The SSE-200 hardware has configurable integration settings which determine whether its two CPUs have the FPU and DSP: * CPU0_FPU (default 0) * CPU0_DSP (default 0) * CPU1_FPU (default 1) * CPU1_DSP (default 1) Similarly, the IoTKit has settings for its single CPU: * CPU0_FPU (default 1) * CPU0_DSP (default 1) Of our four boards that use either the IoTKit or the SSE-200: * mps2-an505, mps2-an521 and musca-a use the default settings * musca-b1 enables FPU and DSP on both CPUs Currently QEMU models all these boards using CPUs with both FPU and DSP enabled. This means that we are incorrect for mps2-an521 and musca-a, which should not have FPU or DSP on CPU0. Create QOM properties on the ARMSSE devices corresponding to the default h/w integration settings, and make the Musca-B1 board enable FPU and DSP on both CPUs. This fixes the mps2-an521 and musca-a behaviour, and leaves the musca-b1 and mps2-an505 behaviour unchanged. Signed-off-by: Peter Maydell Reviewed-by: Alex Benn=C3=A9e --- include/hw/arm/armsse.h | 7 +++++ hw/arm/armsse.c | 58 ++++++++++++++++++++++++++++++++--------- hw/arm/musca.c | 8 ++++++ 3 files changed, 61 insertions(+), 12 deletions(-) diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h index 81e082cccf8..84080c22993 100644 --- a/include/hw/arm/armsse.h +++ b/include/hw/arm/armsse.h @@ -50,6 +50,11 @@ * address of each SRAM bank (and thus the total amount of internal SRA= M) * + QOM property "init-svtor" sets the initial value of the CPU SVTOR re= gister * (where it expects to load the PC and SP from the vector table on res= et) + * + QOM properties "CPU0_FPU", "CPU0_DSP", "CPU1_FPU" and "CPU1_DSP" whi= ch + * set whether the CPUs have the FPU and DSP features present. The defa= ult + * (matching the hardware) is that for CPU0 in an IoTKit and CPU1 in an + * SSE-200 both are present; CPU0 in an SSE-200 has neither. + * Since the IoTKit has only one CPU, it does not have the CPU1_* prope= rties. * + Named GPIO inputs "EXP_IRQ" 0..n are the expansion interrupts for CP= U 0, * which are wired to its NVIC lines 32 .. n+32 * + Named GPIO inputs "EXP_CPU1_IRQ" 0..n are the expansion interrupts f= or @@ -208,6 +213,8 @@ typedef struct ARMSSE { uint32_t mainclk_frq; uint32_t sram_addr_width; uint32_t init_svtor; + bool cpu_fpu[SSE_MAX_CPUS]; + bool cpu_dsp[SSE_MAX_CPUS]; } ARMSSE; =20 typedef struct ARMSSEInfo ARMSSEInfo; diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index 76cc6905798..e138aee673f 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -37,6 +37,33 @@ struct ARMSSEInfo { bool has_cachectrl; bool has_cpusecctrl; bool has_cpuid; + Property *props; +}; + +static Property iotkit_properties[] =3D { + DEFINE_PROP_LINK("memory", ARMSSE, board_memory, TYPE_MEMORY_REGION, + MemoryRegion *), + DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64), + DEFINE_PROP_UINT32("MAINCLK", ARMSSE, mainclk_frq, 0), + DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 15), + DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000), + DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], true), + DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], true), + DEFINE_PROP_END_OF_LIST() +}; + +static Property armsse_properties[] =3D { + DEFINE_PROP_LINK("memory", ARMSSE, board_memory, TYPE_MEMORY_REGION, + MemoryRegion *), + DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64), + DEFINE_PROP_UINT32("MAINCLK", ARMSSE, mainclk_frq, 0), + DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 15), + DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000), + DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], false), + DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], false), + DEFINE_PROP_BOOL("CPU1_FPU", ARMSSE, cpu_fpu[1], true), + DEFINE_PROP_BOOL("CPU1_DSP", ARMSSE, cpu_dsp[1], true), + DEFINE_PROP_END_OF_LIST() }; =20 static const ARMSSEInfo armsse_variants[] =3D { @@ -52,6 +79,7 @@ static const ARMSSEInfo armsse_variants[] =3D { .has_cachectrl =3D false, .has_cpusecctrl =3D false, .has_cpuid =3D false, + .props =3D iotkit_properties, }, { .name =3D TYPE_SSE200, @@ -65,6 +93,7 @@ static const ARMSSEInfo armsse_variants[] =3D { .has_cachectrl =3D true, .has_cpusecctrl =3D true, .has_cpuid =3D true, + .props =3D armsse_properties, }, }; =20 @@ -532,6 +561,20 @@ static void armsse_realize(DeviceState *dev, Error **e= rrp) return; } } + if (!s->cpu_fpu[i]) { + object_property_set_bool(cpuobj, false, "vfp", &err); + if (err) { + error_propagate(errp, err); + return; + } + } + if (!s->cpu_dsp[i]) { + object_property_set_bool(cpuobj, false, "dsp", &err); + if (err) { + error_propagate(errp, err); + return; + } + } =20 if (i > 0) { memory_region_add_subregion_overlap(&s->cpu_container[i], 0, @@ -1221,16 +1264,6 @@ static const VMStateDescription armsse_vmstate =3D { } }; =20 -static Property armsse_properties[] =3D { - DEFINE_PROP_LINK("memory", ARMSSE, board_memory, TYPE_MEMORY_REGION, - MemoryRegion *), - DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64), - DEFINE_PROP_UINT32("MAINCLK", ARMSSE, mainclk_frq, 0), - DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 15), - DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000), - DEFINE_PROP_END_OF_LIST() -}; - static void armsse_reset(DeviceState *dev) { ARMSSE *s =3D ARMSSE(dev); @@ -1243,13 +1276,14 @@ static void armsse_class_init(ObjectClass *klass, v= oid *data) DeviceClass *dc =3D DEVICE_CLASS(klass); IDAUInterfaceClass *iic =3D IDAU_INTERFACE_CLASS(klass); ARMSSEClass *asc =3D ARMSSE_CLASS(klass); + const ARMSSEInfo *info =3D data; =20 dc->realize =3D armsse_realize; dc->vmsd =3D &armsse_vmstate; - dc->props =3D armsse_properties; + dc->props =3D info->props; dc->reset =3D armsse_reset; iic->check =3D armsse_idau_check; - asc->info =3D data; + asc->info =3D info; } =20 static const TypeInfo armsse_info =3D { diff --git a/hw/arm/musca.c b/hw/arm/musca.c index 23aff43f4bc..736f37b774c 100644 --- a/hw/arm/musca.c +++ b/hw/arm/musca.c @@ -385,6 +385,14 @@ static void musca_init(MachineState *machine) qdev_prop_set_uint32(ssedev, "init-svtor", mmc->init_svtor); qdev_prop_set_uint32(ssedev, "SRAM_ADDR_WIDTH", mmc->sram_addr_width); qdev_prop_set_uint32(ssedev, "MAINCLK", SYSCLK_FRQ); + /* + * Musca-A takes the default SSE-200 FPU/DSP settings (ie no for + * CPU0 and yes for CPU1); Musca-B1 explicitly enables them for CPU0. + */ + if (mmc->type =3D=3D MUSCA_B1) { + qdev_prop_set_bit(ssedev, "CPU0_FPU", true); + qdev_prop_set_bit(ssedev, "CPU0_DSP", true); + } object_property_set_bool(OBJECT(&mms->sse), true, "realized", &error_fatal); =20 --=20 2.20.1