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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id y18sm5418641wmd.29.2019.05.17.10.40.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 17 May 2019 10:40:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=Qyh9QRofBjuXAYy2j4FsTuWpdCj9fZJCXoA469HqUHk=; b=bsNKYk4R/MBsNaGj2AZlQYTfBpoUNo5zdvxpGcorOY1dyNNvio7yaB1xh0wzIcsFgZ jznO5LYvWDwPEVPj5laOBYeSlGGT41fRcgJuB9g5NHTpHVjn9nvR8x2nMb5TFES/2bON hS51k/R3yPtK9ctNACuvio1IipK7cEuMdBtB9ZaY7ym1uJSjuVB5Isb7HLQ8aKcGH2Cj FENbFRGDS0YaAxe5fvYrawgxXg20IyjfOxDT37ab+T7dmtw8tC5IAhNoob7ot5Lv9d6q i+WtZwLj7C7iWBQU+ldSOv9PxkehKGK5K24Qw5OvrpPaY7MKD4tJZe+FTIBVu1ke76qZ OEog== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Qyh9QRofBjuXAYy2j4FsTuWpdCj9fZJCXoA469HqUHk=; b=kfqQvpekh4sp8MtRsa/kRH9GmvS9wXlpwyVsvirnQT9kAWlyaiawpi3udvrM/8AX9q lyBRd8VpJI6Vm1w0UJoVfqNQSWzsvi8ShcBGAOyvIlqcINtr0ML7QMFtbTPq/waoR8He Sd6pE710jXrixCWyfHiP2HoAZj5QgqmAuHrWqOBXNDEHEbCk3Oyt2IxcWhrnA31jnxQo Et+12ZBMoRvCQ58/Rrhe0p7Ycd1xeIA5l1EQWS8g/Sc/H1bXvQRhmUO1OxXHmfhnhkld UYb/epASWdcWzK2KAl9+vM3Zlktr8JA6MIi/DPq24XVBS3J4euc3QLJ8Wn4VFkQeAH6P 1t/w== X-Gm-Message-State: APjAAAWk/wlViYBQHIZOgNWFZrpA8iYN4lOEe8AyrrAzevvYAVPXa8FC Mak+EKK71HafvrPl1WixDN+XLLmquP0= X-Google-Smtp-Source: APXvYqwAdqenrWcdn82f3UQlbUEWBKxBHQ5/rEHOmikuBbywOXn436fHisoalMSo39kD2d+g35TsOg== X-Received: by 2002:a5d:534b:: with SMTP id t11mr19267565wrv.297.1558114850121; Fri, 17 May 2019 10:40:50 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Fri, 17 May 2019 18:40:43 +0100 Message-Id: <20190517174046.11146-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190517174046.11146-1-peter.maydell@linaro.org> References: <20190517174046.11146-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 Subject: [Qemu-devel] [PATCH 1/4] target/arm: Allow VFP and Neon to be disabled via a CPU property X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Allow VFP and neon to be disabled via a CPU property. As with the "pmu" property, we only allow these features to be removed from CPUs which have it by default, not added to CPUs which don't have it. The primary motivation here is to be able to optionally create Cortex-M33 CPUs with no FPU, but we provide switches for both VFP and Neon because the two interact: * AArch64 can't have one without the other * Some ID register fields only change if both are disabled Signed-off-by: Peter Maydell Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/cpu.h | 4 ++ target/arm/cpu.c | 150 +++++++++++++++++++++++++++++++++++++++++++++-- 2 files changed, 148 insertions(+), 6 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 733b840a712..778fb293e7c 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -797,6 +797,10 @@ struct ARMCPU { bool has_el3; /* CPU has PMU (Performance Monitor Unit) */ bool has_pmu; + /* CPU has VFP */ + bool has_vfp; + /* CPU has Neon */ + bool has_neon; =20 /* CPU has memory protection unit */ bool has_mpu; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 8eee1d8c59a..406fd360a2a 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -763,6 +763,12 @@ static Property arm_cpu_cfgend_property =3D static Property arm_cpu_has_pmu_property =3D DEFINE_PROP_BOOL("pmu", ARMCPU, has_pmu, true); =20 +static Property arm_cpu_has_vfp_property =3D + DEFINE_PROP_BOOL("vfp", ARMCPU, has_vfp, true); + +static Property arm_cpu_has_neon_property =3D + DEFINE_PROP_BOOL("neon", ARMCPU, has_neon, true); + static Property arm_cpu_has_mpu_property =3D DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true); =20 @@ -803,6 +809,13 @@ void arm_cpu_post_init(Object *obj) if (arm_feature(&cpu->env, ARM_FEATURE_M)) { set_feature(&cpu->env, ARM_FEATURE_PMSA); } + /* Similarly for the VFP feature bits */ + if (arm_feature(&cpu->env, ARM_FEATURE_VFP4)) { + set_feature(&cpu->env, ARM_FEATURE_VFP3); + } + if (arm_feature(&cpu->env, ARM_FEATURE_VFP3)) { + set_feature(&cpu->env, ARM_FEATURE_VFP); + } =20 if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { @@ -847,6 +860,27 @@ void arm_cpu_post_init(Object *obj) &error_abort); } =20 + /* + * Allow user to turn off VFP and Neon support, but only for TCG -- + * KVM does not currently allow us to lie to the guest about its + * ID/feature registers, so the guest always sees what the host has. + */ + if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) { + cpu->has_vfp =3D true; + if (!kvm_enabled()) { + qdev_property_add_static(DEVICE(obj), &arm_cpu_has_vfp_propert= y, + &error_abort); + } + } + + if (arm_feature(&cpu->env, ARM_FEATURE_NEON)) { + cpu->has_neon =3D true; + if (!kvm_enabled()) { + qdev_property_add_static(DEVICE(obj), &arm_cpu_has_neon_proper= ty, + &error_abort); + } + } + if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) { qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property, &error_abort); @@ -956,6 +990,116 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) return; } =20 + if (arm_feature(env, ARM_FEATURE_AARCH64) && + cpu->has_vfp !=3D cpu->has_neon) { + /* + * This is an architectural requirement for AArch64; AArch32 is + * more flexible and permits VFP-no-Neon and Neon-no-VFP. + */ + error_setg(errp, + "AArch64 CPUs must have both VFP and Neon or neither"); + return; + } + + if (!cpu->has_vfp) { + uint64_t t; + uint32_t u; + + unset_feature(env, ARM_FEATURE_VFP); + unset_feature(env, ARM_FEATURE_VFP3); + unset_feature(env, ARM_FEATURE_VFP4); + + t =3D cpu->isar.id_aa64isar1; + t =3D FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 0); + cpu->isar.id_aa64isar1 =3D t; + + t =3D cpu->isar.id_aa64pfr0; + t =3D FIELD_DP64(t, ID_AA64PFR0, FP, 0xf); + cpu->isar.id_aa64pfr0 =3D t; + + u =3D cpu->isar.id_isar6; + u =3D FIELD_DP32(u, ID_ISAR6, JSCVT, 0); + cpu->isar.id_isar6 =3D u; + + u =3D cpu->isar.mvfr0; + u =3D FIELD_DP32(u, MVFR0, FPSP, 0); + u =3D FIELD_DP32(u, MVFR0, FPDP, 0); + u =3D FIELD_DP32(u, MVFR0, FPTRAP, 0); + u =3D FIELD_DP32(u, MVFR0, FPDIVIDE, 0); + u =3D FIELD_DP32(u, MVFR0, FPSQRT, 0); + u =3D FIELD_DP32(u, MVFR0, FPSHVEC, 0); + u =3D FIELD_DP32(u, MVFR0, FPROUND, 0); + cpu->isar.mvfr0 =3D u; + + u =3D cpu->isar.mvfr1; + u =3D FIELD_DP32(u, MVFR1, FPFTZ, 0); + u =3D FIELD_DP32(u, MVFR1, FPDNAN, 0); + u =3D FIELD_DP32(u, MVFR1, FPHP, 0); + cpu->isar.mvfr1 =3D u; + + u =3D cpu->isar.mvfr2; + u =3D FIELD_DP32(u, MVFR2, FPMISC, 0); + cpu->isar.mvfr2 =3D u; + } + + if (!cpu->has_neon) { + uint64_t t; + uint32_t u; + + unset_feature(env, ARM_FEATURE_NEON); + + t =3D cpu->isar.id_aa64isar0; + t =3D FIELD_DP64(t, ID_AA64ISAR0, DP, 0); + cpu->isar.id_aa64isar0 =3D t; + + t =3D cpu->isar.id_aa64isar1; + t =3D FIELD_DP64(t, ID_AA64ISAR1, FCMA, 0); + cpu->isar.id_aa64isar1 =3D t; + + t =3D cpu->isar.id_aa64pfr0; + t =3D FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 0xf); + cpu->isar.id_aa64pfr0 =3D t; + + u =3D cpu->isar.id_isar5; + u =3D FIELD_DP32(u, ID_ISAR5, RDM, 0); + u =3D FIELD_DP32(u, ID_ISAR5, VCMA, 0); + cpu->isar.id_isar5 =3D u; + + u =3D cpu->isar.id_isar6; + u =3D FIELD_DP32(u, ID_ISAR6, DP, 0); + u =3D FIELD_DP32(u, ID_ISAR6, FHM, 0); + cpu->isar.id_isar6 =3D u; + + u =3D cpu->isar.mvfr1; + u =3D FIELD_DP32(u, MVFR1, SIMDLS, 0); + u =3D FIELD_DP32(u, MVFR1, SIMDINT, 0); + u =3D FIELD_DP32(u, MVFR1, SIMDSP, 0); + u =3D FIELD_DP32(u, MVFR1, SIMDHP, 0); + u =3D FIELD_DP32(u, MVFR1, SIMDFMAC, 0); + cpu->isar.mvfr1 =3D u; + + u =3D cpu->isar.mvfr2; + u =3D FIELD_DP32(u, MVFR2, SIMDMISC, 0); + cpu->isar.mvfr2 =3D u; + } + + if (!cpu->has_neon && !cpu->has_vfp) { + uint64_t t; + uint32_t u; + + t =3D cpu->isar.id_aa64isar0; + t =3D FIELD_DP64(t, ID_AA64ISAR0, FHM, 0); + cpu->isar.id_aa64isar0 =3D t; + + t =3D cpu->isar.id_aa64isar1; + t =3D FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 0); + cpu->isar.id_aa64isar1 =3D t; + + u =3D cpu->isar.mvfr0; + u =3D FIELD_DP32(u, MVFR0, SIMDREG, 0); + cpu->isar.mvfr0 =3D u; + } + /* Some features automatically imply others: */ if (arm_feature(env, ARM_FEATURE_V8)) { if (arm_feature(env, ARM_FEATURE_M)) { @@ -1016,12 +1160,6 @@ static void arm_cpu_realizefn(DeviceState *dev, Erro= r **errp) if (arm_feature(env, ARM_FEATURE_V5)) { set_feature(env, ARM_FEATURE_V4T); } - if (arm_feature(env, ARM_FEATURE_VFP4)) { - set_feature(env, ARM_FEATURE_VFP3); - } - if (arm_feature(env, ARM_FEATURE_VFP3)) { - set_feature(env, ARM_FEATURE_VFP); - } if (arm_feature(env, ARM_FEATURE_LPAE)) { set_feature(env, ARM_FEATURE_V7MP); set_feature(env, ARM_FEATURE_PXN); --=20 2.20.1 From nobody Mon Nov 10 17:57:12 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id y18sm5418641wmd.29.2019.05.17.10.40.50 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 17 May 2019 10:40:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=NHqcTeUCaIUf4K7nIsxAw0DoSlAJnoOlQ+lc04URKg4=; b=dp3Aa9foUBrPnuFoCEsOi/CuDhovzp1J6NLcdqvH8dxaogF1KZ9W0mqZX4cdg4qfPo MydfdJeCrh2IKEIv4/MQq+fxRW/AgKa5mjJPLhxAWH5rVoPPSO9yU61MRJQB6GgdnjEd s4Fm26EB6uNTSQnSOMjDfBVscCL87W63D1SqEobdirlUwEuTxkRZYvHZoPFMVwiTKZEL W8UTI8uaj7MffvaQeQQZo4w0Q4aMocgnAK8NN8iRjgeAGa5MMU+OnFuTu9dYof48FHrq 7tKQMLo/cA+8/FpLGan44kNcsb89eiFfTH1kBXR8WlRoJF9QIrPz+/ttbTyzvqOjfJT2 CwlA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NHqcTeUCaIUf4K7nIsxAw0DoSlAJnoOlQ+lc04URKg4=; b=qwhtoNVBp5tAJJLtkDSQ2TsXnNnBsQBsfT8Q6RMLKeoonqrPLHIDCSSMsxA5Y6LsKE 6qQZUJtFr7BLaaQ8ijZEC2u3VhFKkUhHNCNS8+rh23fE+4roh1uOa3+lyeLOGUA+FT5h 5sP9oPGwlx4SGzrhaERUhhbGt1sdEwcwghdLnRw8HAZ3suJEef5W3KotTXh5sK8PHKad 1pnbTn0xo3hQmykiuln+2rOGKsLacSRGvhKiXHByJJ3+y9ZJ5xhDVZNzNsVfxa6AGtt5 97UXQhX4tQsEHN+lWZCkm6sZ+wv0TIfPQSViJwIHVQfU1Kqa0xUFizWREpLjQx5xtqup i/1g== X-Gm-Message-State: APjAAAWZPuSv9FFplR5NE3Z523//gP7y+hf4P3ws2iv1bkNU3rxw0hv1 J6y6/zU8rcJWDz/eqeSbLuj1rJI/qs4= X-Google-Smtp-Source: APXvYqzKp5+fGf/uA6OzhmDKE0JpYu93miAk6hyaWQDRSeK53Dlc9KXQXY7g0JQ9ikYZJ6zzSJ22Yg== X-Received: by 2002:a05:6000:41:: with SMTP id k1mr3794790wrx.332.1558114851174; Fri, 17 May 2019 10:40:51 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Fri, 17 May 2019 18:40:44 +0100 Message-Id: <20190517174046.11146-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190517174046.11146-1-peter.maydell@linaro.org> References: <20190517174046.11146-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 Subject: [Qemu-devel] [PATCH 2/4] target/arm: Allow M-profile CPUs to disable the DSP extension via CPU property X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Allow the DSP extension to be disabled via a CPU property for M-profile CPUs. (A and R-profile CPUs don't have this extension as a defined separate optional architecture extension, so they don't need the property.) Signed-off-by: Peter Maydell Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/cpu.h | 2 ++ target/arm/cpu.c | 29 +++++++++++++++++++++++++++++ 2 files changed, 31 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 778fb293e7c..b1c7ab3ee94 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -801,6 +801,8 @@ struct ARMCPU { bool has_vfp; /* CPU has Neon */ bool has_neon; + /* CPU has M-profile DSP extension */ + bool has_dsp; =20 /* CPU has memory protection unit */ bool has_mpu; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 406fd360a2a..c43139ba897 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -769,6 +769,9 @@ static Property arm_cpu_has_vfp_property =3D static Property arm_cpu_has_neon_property =3D DEFINE_PROP_BOOL("neon", ARMCPU, has_neon, true); =20 +static Property arm_cpu_has_dsp_property =3D + DEFINE_PROP_BOOL("dsp", ARMCPU, has_dsp, true); + static Property arm_cpu_has_mpu_property =3D DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true); =20 @@ -881,6 +884,12 @@ void arm_cpu_post_init(Object *obj) } } =20 + if (arm_feature(&cpu->env, ARM_FEATURE_M) && + arm_feature(&cpu->env, ARM_FEATURE_THUMB_DSP)) { + qdev_property_add_static(DEVICE(obj), &arm_cpu_has_dsp_property, + &error_abort); + } + if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) { qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property, &error_abort); @@ -1100,6 +1109,26 @@ static void arm_cpu_realizefn(DeviceState *dev, Erro= r **errp) cpu->isar.mvfr0 =3D u; } =20 + if (arm_feature(env, ARM_FEATURE_M) && !cpu->has_dsp) { + uint32_t u; + + unset_feature(env, ARM_FEATURE_THUMB_DSP); + + u =3D cpu->isar.id_isar1; + u =3D FIELD_DP32(u, ID_ISAR1, EXTEND, 1); + cpu->isar.id_isar1 =3D u; + + u =3D cpu->isar.id_isar2; + u =3D FIELD_DP32(u, ID_ISAR2, MULTU, 1); + u =3D FIELD_DP32(u, ID_ISAR2, MULTS, 1); + cpu->isar.id_isar2 =3D u; + + u =3D cpu->isar.id_isar3; + u =3D FIELD_DP32(u, ID_ISAR3, SIMD, 1); + u =3D FIELD_DP32(u, ID_ISAR3, SATURATE, 0); + cpu->isar.id_isar3 =3D u; + } + /* Some features automatically imply others: */ if (arm_feature(env, ARM_FEATURE_V8)) { if (arm_feature(env, ARM_FEATURE_M)) { --=20 2.20.1 From nobody Mon Nov 10 17:57:12 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1558114998; cv=none; d=zoho.com; s=zohoarc; b=UgrfmCWr4+hDQr1/CXknGCztgiXWyKHri87zErEvk0IZfDh6EM5Qq2koS8Od3zUnTLu5SNZbvpXA5eC8lllwCImWhHV4tUxO0lDUqxT176pv812A8y/5Kdp8WiRAYEyLY1Xc4UdCaLQi9lNIY4OnOMfLKbde0P7ijK/3gq8V3M8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1558114998; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=K1PYSu9pA1oky++yuIlXAuhJhMUCXE5jcIih2/bVKYA=; b=eznAMGkcpfdYRLPfch0boiiyOAdGl30bUpb4g/fnUf67lOxftDZl+Xpla6EdfsAGtBDWZvoiY6/EC7Ukk4DHh+tp69RyoiwIJVamDkN+JJ3LaycDwebccb0FXcKaC4TbVKGYp7iLgSTBlLvTxRhdKF0qpFeVp8vG7GBVqU3w54k= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1558114998022162.6557751871644; Fri, 17 May 2019 10:43:18 -0700 (PDT) Received: from localhost ([127.0.0.1]:51724 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hRgsz-0000oS-TD for importer@patchew.org; Fri, 17 May 2019 13:43:13 -0400 Received: from eggs.gnu.org ([209.51.188.92]:47735) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hRgqq-0007tL-Qw for qemu-devel@nongnu.org; Fri, 17 May 2019 13:41:02 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hRgqo-00038l-CV for qemu-devel@nongnu.org; Fri, 17 May 2019 13:41:00 -0400 Received: from mail-wm1-x344.google.com ([2a00:1450:4864:20::344]:55672) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hRgqm-00030u-N7 for qemu-devel@nongnu.org; Fri, 17 May 2019 13:40:57 -0400 Received: by mail-wm1-x344.google.com with SMTP id x64so7685513wmb.5 for ; Fri, 17 May 2019 10:40:53 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id y18sm5418641wmd.29.2019.05.17.10.40.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 17 May 2019 10:40:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=K1PYSu9pA1oky++yuIlXAuhJhMUCXE5jcIih2/bVKYA=; b=UFWTOmBijaNUh7m6PjBYAFkE6uvTOMBUJoUJXqPtQAsh8TiBQAYe1r+YOSqtM7YRu0 RfEfVh2gnfa7vF3Xc9sq+AqVci7jkeTeZ3GFLqIrn9syFpaG3Ug7d8TPxvZWz4lhA9k8 YgdGaW/7BWK0THVAqneWXtGATuiLY5JhKSb1E/Ty3qxhsXpWimI5jyxxUJxa00Nq2+9d 6cTEjoZTfl7kAOahNt35HWDmlkg3QQLN49MmiLj2bU+3gvUoqM0ZKiNveybanWsnRM8y L1AsU8C+gj77EwRME7rDty/G3QG5MSpRFQ0UxNqWQ9EvNRp5oU66jemXazAUEgKB7Cel BHAQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=K1PYSu9pA1oky++yuIlXAuhJhMUCXE5jcIih2/bVKYA=; b=l3U1YOcZOv8WTjO+Yn/pPNeSbzIae76HbueEf8+R/1YD23UHHr3KK8BO7bodgaUdIs T7uHFXRYiNQT/b9s7i9vY4rcKf75iWgOW7MrV1J35VobgcQ7T+C1LDSYuHmt+SwZOilK 1U/riWI+sJ4boB7vrNNdRne8FbK3HxF5QYA0rYGHJnW9HrSdcqtIIec47fjKcBG6JA09 lBojQ5WNHpS7v6AOIljiGecXQ2Q4aLKuAiJ7xtX5TWCtgApvURDH09KL2LfyLrS7xm4D 5wlRsQMVcI7kHWqvFJD3Em+0Wamt85wTeSrNRaYdoL72kRDdQAGf9q9oxz7W+B2vZ5tr nw6A== X-Gm-Message-State: APjAAAVAOR6YZBit17RYNrMMohMtHNKJOJq3E8qoCBcRWqs8YmuSlwt6 ECqNhyrzKan9kN+FsTUBbg0dfg== X-Google-Smtp-Source: APXvYqxVKXd51QsCvxC+E9BQmldaJ0s4F7uY6mdywl4ns1VbOvm7LqbpDpGsUM623TjY/liEC9bGbw== X-Received: by 2002:a05:600c:2116:: with SMTP id u22mr3033642wml.58.1558114852224; Fri, 17 May 2019 10:40:52 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Fri, 17 May 2019 18:40:45 +0100 Message-Id: <20190517174046.11146-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190517174046.11146-1-peter.maydell@linaro.org> References: <20190517174046.11146-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::344 Subject: [Qemu-devel] [PATCH 3/4] hw/arm/armv7m: Forward "vfp" and "dsp" properties to CPU X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Create "vfp" and "dsp" properties on the armv7m container object which will be forwarded to its CPU object, so that SoCs can configure whether the CPU has these features. Signed-off-by: Peter Maydell Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/arm/armv7m.h | 4 ++++ hw/arm/armv7m.c | 18 ++++++++++++++++++ 2 files changed, 22 insertions(+) diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h index e96a98f8093..d2c74d3872a 100644 --- a/include/hw/arm/armv7m.h +++ b/include/hw/arm/armv7m.h @@ -43,6 +43,8 @@ typedef struct { * devices will be automatically layered on top of this view.) * + Property "idau": IDAU interface (forwarded to CPU object) * + Property "init-svtor": secure VTOR reset value (forwarded to CPU obje= ct) + * + Property "vfp": enable VFP (forwarded to CPU object) + * + Property "dsp": enable DSP (forwarded to CPU object) * + Property "enable-bitband": expose bitbanded IO */ typedef struct ARMv7MState { @@ -66,6 +68,8 @@ typedef struct ARMv7MState { uint32_t init_svtor; bool enable_bitband; bool start_powered_off; + bool vfp; + bool dsp; } ARMv7MState; =20 #endif diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c index c4b2a9a1f5c..7caf9bd3364 100644 --- a/hw/arm/armv7m.c +++ b/hw/arm/armv7m.c @@ -190,6 +190,22 @@ static void armv7m_realize(DeviceState *dev, Error **e= rrp) return; } } + if (object_property_find(OBJECT(s->cpu), "vfp", NULL)) { + object_property_set_bool(OBJECT(s->cpu), s->vfp, + "vfp", &err); + if (err !=3D NULL) { + error_propagate(errp, err); + return; + } + } + if (object_property_find(OBJECT(s->cpu), "dsp", NULL)) { + object_property_set_bool(OBJECT(s->cpu), s->dsp, + "dsp", &err); + if (err !=3D NULL) { + error_propagate(errp, err); + return; + } + } =20 /* * Tell the CPU where the NVIC is; it will fail realize if it doesn't @@ -260,6 +276,8 @@ static Property armv7m_properties[] =3D { DEFINE_PROP_BOOL("enable-bitband", ARMv7MState, enable_bitband, false), DEFINE_PROP_BOOL("start-powered-off", ARMv7MState, start_powered_off, false), + DEFINE_PROP_BOOL("vfp", ARMv7MState, vfp, true), + DEFINE_PROP_BOOL("dsp", ARMv7MState, dsp, true), DEFINE_PROP_END_OF_LIST(), }; =20 --=20 2.20.1 From nobody Mon Nov 10 17:57:12 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1558115121; cv=none; d=zoho.com; s=zohoarc; b=ScwqdksLdwT5apgDNvEPiDcokkxwVphIwjH8bCD3YdngQRXwq/OdR0juHE9vxKMeP4aw1T5nW9LdyeefP4wVnT48AsrcRPEtA0mqUKhtpT8WLwuBcV/EmBy+UmW+nLKSWEEouvXLLnauDk3c1HajCjbEVkqvHQ4OYvZwMgx9+zo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1558115121; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=7QU2E61ExLPRQ5cVFAuMwBaju416G00wlZEn+t3cGhw=; b=ni1qHzS1fTOlbvx16iiwR55+Y6YNrtH3e32QTnG3aLJb30urPoe8HG3ZVVXO0EfNj7TXNw3/e+785aRDolMKT3A8AGbSMLZj8/udQw72s29brpbML27+o1MVsWAax//QTG0d+S5F2O07N2ntg1DGkm2cazEKsIzK29OI06AAIVg= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1558115121312547.7975161036687; Fri, 17 May 2019 10:45:21 -0700 (PDT) Received: from localhost ([127.0.0.1]:51751 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hRgur-0002FE-6U for importer@patchew.org; Fri, 17 May 2019 13:45:09 -0400 Received: from eggs.gnu.org ([209.51.188.92]:47814) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hRgqy-00082S-LY for qemu-devel@nongnu.org; Fri, 17 May 2019 13:41:10 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hRgqu-0003IK-Im for qemu-devel@nongnu.org; Fri, 17 May 2019 13:41:06 -0400 Received: from mail-wm1-x342.google.com ([2a00:1450:4864:20::342]:53630) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hRgqq-00032O-TD for qemu-devel@nongnu.org; Fri, 17 May 2019 13:41:02 -0400 Received: by mail-wm1-x342.google.com with SMTP id 198so7688527wme.3 for ; Fri, 17 May 2019 10:40:54 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id y18sm5418641wmd.29.2019.05.17.10.40.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 17 May 2019 10:40:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=7QU2E61ExLPRQ5cVFAuMwBaju416G00wlZEn+t3cGhw=; b=g4tE6OQp4CPXBvjCv3gkW1ESF6ZYG/bQbX38fjpp8rGCiARyxkmapH/GZ6TsnFN8v6 V3+u7yuf9heD7f2QbIG5qK4WyahSPlwaY+UIu3kof/agaWmcNgyvACS6dHGSsiDFfZI0 z4lICVyIK/2ka2qsXpq9Fwzp7GN6Abf4EZ+8UPUfI2DjOW3EN3QZFZ7xfgdVFb3vFkvJ 3xnqlZTnwx2qBTRpUh2FDk/pTrYrRuUz+a7nUV38nUSWN0o5U2xc3w5JB7L2JLFpntkD nTBzZTB2ndhcgK3LfeUAKEFIAZRr96EVDg/g7enOpDXA9fD5MqDqiAP/CFs7jD2B429t un3Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7QU2E61ExLPRQ5cVFAuMwBaju416G00wlZEn+t3cGhw=; b=Vo5UCB2rNUNOBilOMJ2S+Ya7AFehIxgrghXe3cbbPNFkl/K4f7dIPxWibbHuKhYRZ+ fsBP6++5ZDlaUSCYnI5Tru8TcLojNY+ZwcqQ+N44i3V7/XRMHk1b+dqUlNCmJTY2NHCJ aR8tBiI/sHZYyKPOyzgFsH4nX0wYj7t5sfZzSt8ZLXQ1NS008OUrMuW/u7b2hBG6tLPo NBczs2Ph9Oz8xZQCXTBWx8+zEWbl+0PEt5TE2ONEJEpbLcCJBBG/rsJIe8xed3VwTvn/ bA8SA29iQIQu56EqtyN94mmUZdP5BuelnUzCvkKi4ZOMpnMUK3jh2MhvPuX6/rqton0c /p/w== X-Gm-Message-State: APjAAAWnp1y6e9XlSwjkJSahEABOBxTu+YbxKfkqqW2+op09xZTIMfgx zrgttOn4bsnIKNqIScgYpiacebEaOWc= X-Google-Smtp-Source: APXvYqzv9P7GBozUr6OCS4pzol/BcTKHwMiCNd/tlXS3EN9f86BwKFPiAG++cAwDYGulsdx7xyqS2w== X-Received: by 2002:a7b:ce84:: with SMTP id q4mr3044698wmj.41.1558114853382; Fri, 17 May 2019 10:40:53 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Fri, 17 May 2019 18:40:46 +0100 Message-Id: <20190517174046.11146-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190517174046.11146-1-peter.maydell@linaro.org> References: <20190517174046.11146-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::342 Subject: [Qemu-devel] [PATCH 4/4] hw/arm: Correctly disable FPU/DSP for some ARMSSE-based boards X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The SSE-200 hardware has configurable integration settings which determine whether its two CPUs have the FPU and DSP: * CPU0_FPU (default 0) * CPU0_DSP (default 0) * CPU1_FPU (default 1) * CPU1_DSP (default 1) Similarly, the IoTKit has settings for its single CPU: * CPU0_FPU (default 1) * CPU0_DSP (default 1) Of our four boards that use either the IoTKit or the SSE-200: * mps2-an505, mps2-an521 and musca-a use the default settings * musca-b1 enables FPU and DSP on both CPUs Currently QEMU models all these boards using CPUs with both FPU and DSP enabled. This means that we are incorrect for mps2-an521 and musca-a, which should not have FPU or DSP on CPU0. Create QOM properties on the ARMSSE devices corresponding to the default h/w integration settings, and make the Musca-B1 board enable FPU and DSP on both CPUs. This fixes the mps2-an521 and musca-a behaviour, and leaves the musca-b1 and mps2-an505 behaviour unchanged. Signed-off-by: Peter Maydell Reviewed-by: Alex Benn=C3=A9e --- include/hw/arm/armsse.h | 7 +++++ hw/arm/armsse.c | 58 ++++++++++++++++++++++++++++++++--------- hw/arm/musca.c | 8 ++++++ 3 files changed, 61 insertions(+), 12 deletions(-) diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h index 81e082cccf8..84080c22993 100644 --- a/include/hw/arm/armsse.h +++ b/include/hw/arm/armsse.h @@ -50,6 +50,11 @@ * address of each SRAM bank (and thus the total amount of internal SRA= M) * + QOM property "init-svtor" sets the initial value of the CPU SVTOR re= gister * (where it expects to load the PC and SP from the vector table on res= et) + * + QOM properties "CPU0_FPU", "CPU0_DSP", "CPU1_FPU" and "CPU1_DSP" whi= ch + * set whether the CPUs have the FPU and DSP features present. The defa= ult + * (matching the hardware) is that for CPU0 in an IoTKit and CPU1 in an + * SSE-200 both are present; CPU0 in an SSE-200 has neither. + * Since the IoTKit has only one CPU, it does not have the CPU1_* prope= rties. * + Named GPIO inputs "EXP_IRQ" 0..n are the expansion interrupts for CP= U 0, * which are wired to its NVIC lines 32 .. n+32 * + Named GPIO inputs "EXP_CPU1_IRQ" 0..n are the expansion interrupts f= or @@ -208,6 +213,8 @@ typedef struct ARMSSE { uint32_t mainclk_frq; uint32_t sram_addr_width; uint32_t init_svtor; + bool cpu_fpu[SSE_MAX_CPUS]; + bool cpu_dsp[SSE_MAX_CPUS]; } ARMSSE; =20 typedef struct ARMSSEInfo ARMSSEInfo; diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index 76cc6905798..e138aee673f 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -37,6 +37,33 @@ struct ARMSSEInfo { bool has_cachectrl; bool has_cpusecctrl; bool has_cpuid; + Property *props; +}; + +static Property iotkit_properties[] =3D { + DEFINE_PROP_LINK("memory", ARMSSE, board_memory, TYPE_MEMORY_REGION, + MemoryRegion *), + DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64), + DEFINE_PROP_UINT32("MAINCLK", ARMSSE, mainclk_frq, 0), + DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 15), + DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000), + DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], true), + DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], true), + DEFINE_PROP_END_OF_LIST() +}; + +static Property armsse_properties[] =3D { + DEFINE_PROP_LINK("memory", ARMSSE, board_memory, TYPE_MEMORY_REGION, + MemoryRegion *), + DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64), + DEFINE_PROP_UINT32("MAINCLK", ARMSSE, mainclk_frq, 0), + DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 15), + DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000), + DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], false), + DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], false), + DEFINE_PROP_BOOL("CPU1_FPU", ARMSSE, cpu_fpu[1], true), + DEFINE_PROP_BOOL("CPU1_DSP", ARMSSE, cpu_dsp[1], true), + DEFINE_PROP_END_OF_LIST() }; =20 static const ARMSSEInfo armsse_variants[] =3D { @@ -52,6 +79,7 @@ static const ARMSSEInfo armsse_variants[] =3D { .has_cachectrl =3D false, .has_cpusecctrl =3D false, .has_cpuid =3D false, + .props =3D iotkit_properties, }, { .name =3D TYPE_SSE200, @@ -65,6 +93,7 @@ static const ARMSSEInfo armsse_variants[] =3D { .has_cachectrl =3D true, .has_cpusecctrl =3D true, .has_cpuid =3D true, + .props =3D armsse_properties, }, }; =20 @@ -532,6 +561,20 @@ static void armsse_realize(DeviceState *dev, Error **e= rrp) return; } } + if (!s->cpu_fpu[i]) { + object_property_set_bool(cpuobj, false, "vfp", &err); + if (err) { + error_propagate(errp, err); + return; + } + } + if (!s->cpu_dsp[i]) { + object_property_set_bool(cpuobj, false, "dsp", &err); + if (err) { + error_propagate(errp, err); + return; + } + } =20 if (i > 0) { memory_region_add_subregion_overlap(&s->cpu_container[i], 0, @@ -1221,16 +1264,6 @@ static const VMStateDescription armsse_vmstate =3D { } }; =20 -static Property armsse_properties[] =3D { - DEFINE_PROP_LINK("memory", ARMSSE, board_memory, TYPE_MEMORY_REGION, - MemoryRegion *), - DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64), - DEFINE_PROP_UINT32("MAINCLK", ARMSSE, mainclk_frq, 0), - DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 15), - DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000), - DEFINE_PROP_END_OF_LIST() -}; - static void armsse_reset(DeviceState *dev) { ARMSSE *s =3D ARMSSE(dev); @@ -1243,13 +1276,14 @@ static void armsse_class_init(ObjectClass *klass, v= oid *data) DeviceClass *dc =3D DEVICE_CLASS(klass); IDAUInterfaceClass *iic =3D IDAU_INTERFACE_CLASS(klass); ARMSSEClass *asc =3D ARMSSE_CLASS(klass); + const ARMSSEInfo *info =3D data; =20 dc->realize =3D armsse_realize; dc->vmsd =3D &armsse_vmstate; - dc->props =3D armsse_properties; + dc->props =3D info->props; dc->reset =3D armsse_reset; iic->check =3D armsse_idau_check; - asc->info =3D data; + asc->info =3D info; } =20 static const TypeInfo armsse_info =3D { diff --git a/hw/arm/musca.c b/hw/arm/musca.c index 23aff43f4bc..736f37b774c 100644 --- a/hw/arm/musca.c +++ b/hw/arm/musca.c @@ -385,6 +385,14 @@ static void musca_init(MachineState *machine) qdev_prop_set_uint32(ssedev, "init-svtor", mmc->init_svtor); qdev_prop_set_uint32(ssedev, "SRAM_ADDR_WIDTH", mmc->sram_addr_width); qdev_prop_set_uint32(ssedev, "MAINCLK", SYSCLK_FRQ); + /* + * Musca-A takes the default SSE-200 FPU/DSP settings (ie no for + * CPU0 and yes for CPU1); Musca-B1 explicitly enables them for CPU0. + */ + if (mmc->type =3D=3D MUSCA_B1) { + qdev_prop_set_bit(ssedev, "CPU0_FPU", true); + qdev_prop_set_bit(ssedev, "CPU0_DSP", true); + } object_property_set_bool(OBJECT(&mms->sse), true, "realized", &error_fatal); =20 --=20 2.20.1