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[2001:470:27:1fa::2]) by smtp.gmail.com with ESMTPSA id 78sm4011lje.81.2019.05.14.13.45.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 14 May 2019 13:45:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=IkhMNMK+Km3YXVzPE7/k37mvtEbVmKcfhC7w5xerFoU=; b=hoyk/kO4WdlEEGBdC2efMClje89uRLZpTuT557KXH54GCdPu0jGzwNwmDs1P03IdN8 +UZgoTnAwRF7aD+CiGGwfZ76szH8iP/rn+jv2C2KzfF09aQLvxuy2pn+MHwGsq191PeE QQznMdwWEOrnjN2TLARcpGrSrlkC4Lwx+xXWVItBHrejzIex+i3AoTlPbolc8prD7dBa Pkt5NCgy9jSJVfqwvMLQoejB8eBKuZmp8JVmsv/CBJtm2mBLjhhmm+aG82f/XC60O9ei br9eH9ZmjNckWcZRbtnoDZMDu+QkGS3769z9EZfyT7IMnDvO1G8n5l48ACb2CLS942V0 EZow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=IkhMNMK+Km3YXVzPE7/k37mvtEbVmKcfhC7w5xerFoU=; b=J2YBpBFTL/FK7MJbnNBLvj0kjLBfY4nNcG0ARxJK6D15+ziK3CGJ3MUBsPwb1IWapi I4DePkPvpL6iPWB0twJcXZCp08/oDD42opXoiPqXTn49CgRKP5vRxzHil+DDzU8O3uIY uizTMy7xhb7MSRlbAfW4VPv8rBcc2RmtHdjM/f9EDmVZ0ghnYtS3KJdpWsAyHCBfNVer egQwslZGITFFC1aDZeDcNCFMJ0lLb8dysmMCWcjbEXWBez95sYUn3lkezvlPREQLbJlC 1DyIgVsqWRa5IxaKBQNs3wdVxct0d35JHZGvzx9IjvhHtfsuNocSdH3GYOwQiN28f3Rz 0GrA== X-Gm-Message-State: APjAAAUpc9/XWf9Squi6wduM4n1ZQuKKoXg8+5fSziEsrdoo71qhEAZt lOOD7CmcHRjjVk0wF/k1gOdXkSEPwao= X-Google-Smtp-Source: APXvYqxAbZNtI8Dgjg5I3ZCG9bzZfY/9hlV+IrW+ZswQ6db8g6mXYUqyp3eKvzKf0wkbUkQm8ke3Ww== X-Received: by 2002:ac2:510b:: with SMTP id q11mr16237325lfb.11.1557866710260; Tue, 14 May 2019 13:45:10 -0700 (PDT) From: Max Filippov To: qemu-devel@nongnu.org Date: Tue, 14 May 2019 13:44:39 -0700 Message-Id: <20190514204447.17486-2-jcmvbkbc@gmail.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190514204447.17486-1-jcmvbkbc@gmail.com> References: <20190514204447.17486-1-jcmvbkbc@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::143 Subject: [Qemu-devel] [PATCH 1/9] target/xtensa: get rid of centralized SR properties X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Max Filippov Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" SR numbers are not unique: different Xtensa options may reuse SR number for different purposes. Introduce generic rsr/wsr functions and xsr template and use them instead of centralized SR access functions. Change prototypes of specific rsr/wsr functions to match XtensaOpcodeOp and use them instead of centralized SR access functions. Put xtensa option that introduces SR into the second opcode description parameter and use it to test for rsr/wsr/xsr opcode validity. Extract SR and UR names for the xtensa_cpu_dump_state from libisa. Merge SRs and URs in the dump. Register names of used SR/UR in init_libisa and use these names for TCG globals referencing these SR/UR. Signed-off-by: Max Filippov --- target/xtensa/cpu.h | 1 + target/xtensa/helper.c | 1 + target/xtensa/translate.c | 2503 +++++++++++++++++++++++++++--------------= ---- 3 files changed, 1492 insertions(+), 1013 deletions(-) diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 5d23e1345be5..539033fccb61 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -589,6 +589,7 @@ void xtensa_cpu_do_unaligned_access(CPUState *cpu, vadd= r addr, #define XTENSA_DEFAULT_CPU_NOMMU_TYPE \ XTENSA_CPU_TYPE_NAME(XTENSA_DEFAULT_CPU_NOMMU_MODEL) =20 +void xtensa_collect_sr_names(const XtensaConfig *config); void xtensa_translate_init(void); void **xtensa_get_regfile_by_name(const char *name); void xtensa_breakpoint_handler(CPUState *cs); diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c index 5f37f378a311..ed0108a81209 100644 --- a/target/xtensa/helper.c +++ b/target/xtensa/helper.c @@ -141,6 +141,7 @@ static void init_libisa(XtensaConfig *config) } #endif } + xtensa_collect_sr_names(config); } =20 static void xtensa_finalize_config(XtensaConfig *config) diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index 301c8e31613c..100d6e126590 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -92,128 +92,40 @@ static GHashTable *xtensa_regfile_table; =20 #include "exec/gen-icount.h" =20 -typedef struct XtensaReg { - const char *name; - uint64_t opt_bits; - enum { - SR_R =3D 1, - SR_W =3D 2, - SR_X =3D 4, - SR_RW =3D 3, - SR_RWX =3D 7, - } access; -} XtensaReg; - -#define XTENSA_REG_ACCESS(regname, opt, acc) { \ - .name =3D (regname), \ - .opt_bits =3D XTENSA_OPTION_BIT(opt), \ - .access =3D (acc), \ - } +static char *sr_name[256]; +static char *ur_name[256]; =20 -#define XTENSA_REG(regname, opt) XTENSA_REG_ACCESS(regname, opt, SR_RWX) +void xtensa_collect_sr_names(const XtensaConfig *config) +{ + xtensa_isa isa =3D config->isa; + int n =3D xtensa_isa_num_sysregs(isa); + int i; =20 -#define XTENSA_REG_BITS_ACCESS(regname, opt, acc) { \ - .name =3D (regname), \ - .opt_bits =3D (opt), \ - .access =3D (acc), \ + for (i =3D 0; i < n; ++i) { + int sr =3D xtensa_sysreg_number(isa, i); + + if (sr >=3D 0 && sr < 256) { + const char *name =3D xtensa_sysreg_name(isa, i); + char **pname =3D + (xtensa_sysreg_is_user(isa, i) ? ur_name : sr_name) + sr; + + if (*pname) { + if (strstr(*pname, name) =3D=3D NULL) { + char *new_name =3D + malloc(strlen(*pname) + strlen(name) + 2); + + strcpy(new_name, *pname); + strcat(new_name, "/"); + strcat(new_name, name); + free(*pname); + *pname =3D new_name; + } + } else { + *pname =3D strdup(name); + } + } } - -#define XTENSA_REG_BITS(regname, opt) \ - XTENSA_REG_BITS_ACCESS(regname, opt, SR_RWX) - -static const XtensaReg sregnames[256] =3D { - [LBEG] =3D XTENSA_REG("LBEG", XTENSA_OPTION_LOOP), - [LEND] =3D XTENSA_REG("LEND", XTENSA_OPTION_LOOP), - [LCOUNT] =3D XTENSA_REG("LCOUNT", XTENSA_OPTION_LOOP), - [SAR] =3D XTENSA_REG_BITS("SAR", XTENSA_OPTION_ALL), - [BR] =3D XTENSA_REG("BR", XTENSA_OPTION_BOOLEAN), - [LITBASE] =3D XTENSA_REG("LITBASE", XTENSA_OPTION_EXTENDED_L32R), - [SCOMPARE1] =3D XTENSA_REG("SCOMPARE1", XTENSA_OPTION_CONDITIONAL_STOR= E), - [ACCLO] =3D XTENSA_REG("ACCLO", XTENSA_OPTION_MAC16), - [ACCHI] =3D XTENSA_REG("ACCHI", XTENSA_OPTION_MAC16), - [MR] =3D XTENSA_REG("MR0", XTENSA_OPTION_MAC16), - [MR + 1] =3D XTENSA_REG("MR1", XTENSA_OPTION_MAC16), - [MR + 2] =3D XTENSA_REG("MR2", XTENSA_OPTION_MAC16), - [MR + 3] =3D XTENSA_REG("MR3", XTENSA_OPTION_MAC16), - [PREFCTL] =3D XTENSA_REG_BITS("PREFCTL", XTENSA_OPTION_ALL), - [WINDOW_BASE] =3D XTENSA_REG("WINDOW_BASE", XTENSA_OPTION_WINDOWED_REG= ISTER), - [WINDOW_START] =3D XTENSA_REG("WINDOW_START", - XTENSA_OPTION_WINDOWED_REGISTER), - [PTEVADDR] =3D XTENSA_REG("PTEVADDR", XTENSA_OPTION_MMU), - [MMID] =3D XTENSA_REG_BITS("MMID", XTENSA_OPTION_ALL), - [RASID] =3D XTENSA_REG("RASID", XTENSA_OPTION_MMU), - [ITLBCFG] =3D XTENSA_REG("ITLBCFG", XTENSA_OPTION_MMU), - [DTLBCFG] =3D XTENSA_REG("DTLBCFG", XTENSA_OPTION_MMU), - [IBREAKENABLE] =3D XTENSA_REG("IBREAKENABLE", XTENSA_OPTION_DEBUG), - [MEMCTL] =3D XTENSA_REG_BITS("MEMCTL", XTENSA_OPTION_ALL), - [CACHEATTR] =3D XTENSA_REG("CACHEATTR", XTENSA_OPTION_CACHEATTR), - [ATOMCTL] =3D XTENSA_REG("ATOMCTL", XTENSA_OPTION_ATOMCTL), - [DDR] =3D XTENSA_REG("DDR", XTENSA_OPTION_DEBUG), - [IBREAKA] =3D XTENSA_REG("IBREAKA0", XTENSA_OPTION_DEBUG), - [IBREAKA + 1] =3D XTENSA_REG("IBREAKA1", XTENSA_OPTION_DEBUG), - [DBREAKA] =3D XTENSA_REG("DBREAKA0", XTENSA_OPTION_DEBUG), - [DBREAKA + 1] =3D XTENSA_REG("DBREAKA1", XTENSA_OPTION_DEBUG), - [DBREAKC] =3D XTENSA_REG("DBREAKC0", XTENSA_OPTION_DEBUG), - [DBREAKC + 1] =3D XTENSA_REG("DBREAKC1", XTENSA_OPTION_DEBUG), - [CONFIGID0] =3D XTENSA_REG_BITS_ACCESS("CONFIGID0", XTENSA_OPTION_ALL,= SR_R), - [EPC1] =3D XTENSA_REG("EPC1", XTENSA_OPTION_EXCEPTION), - [EPC1 + 1] =3D XTENSA_REG("EPC2", XTENSA_OPTION_HIGH_PRIORITY_INTERRUP= T), - [EPC1 + 2] =3D XTENSA_REG("EPC3", XTENSA_OPTION_HIGH_PRIORITY_INTERRUP= T), - [EPC1 + 3] =3D XTENSA_REG("EPC4", XTENSA_OPTION_HIGH_PRIORITY_INTERRUP= T), - [EPC1 + 4] =3D XTENSA_REG("EPC5", XTENSA_OPTION_HIGH_PRIORITY_INTERRUP= T), - [EPC1 + 5] =3D XTENSA_REG("EPC6", XTENSA_OPTION_HIGH_PRIORITY_INTERRUP= T), - [EPC1 + 6] =3D XTENSA_REG("EPC7", XTENSA_OPTION_HIGH_PRIORITY_INTERRUP= T), - [DEPC] =3D XTENSA_REG("DEPC", XTENSA_OPTION_EXCEPTION), - [EPS2] =3D XTENSA_REG("EPS2", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), - [EPS2 + 1] =3D XTENSA_REG("EPS3", XTENSA_OPTION_HIGH_PRIORITY_INTERRUP= T), - [EPS2 + 2] =3D XTENSA_REG("EPS4", XTENSA_OPTION_HIGH_PRIORITY_INTERRUP= T), - [EPS2 + 3] =3D XTENSA_REG("EPS5", XTENSA_OPTION_HIGH_PRIORITY_INTERRUP= T), - [EPS2 + 4] =3D XTENSA_REG("EPS6", XTENSA_OPTION_HIGH_PRIORITY_INTERRUP= T), - [EPS2 + 5] =3D XTENSA_REG("EPS7", XTENSA_OPTION_HIGH_PRIORITY_INTERRUP= T), - [CONFIGID1] =3D XTENSA_REG_BITS_ACCESS("CONFIGID1", XTENSA_OPTION_ALL,= SR_R), - [EXCSAVE1] =3D XTENSA_REG("EXCSAVE1", XTENSA_OPTION_EXCEPTION), - [EXCSAVE1 + 1] =3D XTENSA_REG("EXCSAVE2", - XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), - [EXCSAVE1 + 2] =3D XTENSA_REG("EXCSAVE3", - XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), - [EXCSAVE1 + 3] =3D XTENSA_REG("EXCSAVE4", - XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), - [EXCSAVE1 + 4] =3D XTENSA_REG("EXCSAVE5", - XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), - [EXCSAVE1 + 5] =3D XTENSA_REG("EXCSAVE6", - XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), - [EXCSAVE1 + 6] =3D XTENSA_REG("EXCSAVE7", - XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), - [CPENABLE] =3D XTENSA_REG("CPENABLE", XTENSA_OPTION_COPROCESSOR), - [INTSET] =3D XTENSA_REG_ACCESS("INTSET", XTENSA_OPTION_INTERRUPT, SR_R= W), - [INTCLEAR] =3D XTENSA_REG_ACCESS("INTCLEAR", XTENSA_OPTION_INTERRUPT, = SR_W), - [INTENABLE] =3D XTENSA_REG("INTENABLE", XTENSA_OPTION_INTERRUPT), - [PS] =3D XTENSA_REG_BITS("PS", XTENSA_OPTION_ALL), - [VECBASE] =3D XTENSA_REG("VECBASE", XTENSA_OPTION_RELOCATABLE_VECTOR), - [EXCCAUSE] =3D XTENSA_REG("EXCCAUSE", XTENSA_OPTION_EXCEPTION), - [DEBUGCAUSE] =3D XTENSA_REG_ACCESS("DEBUGCAUSE", XTENSA_OPTION_DEBUG, = SR_R), - [CCOUNT] =3D XTENSA_REG("CCOUNT", XTENSA_OPTION_TIMER_INTERRUPT), - [PRID] =3D XTENSA_REG_ACCESS("PRID", XTENSA_OPTION_PROCESSOR_ID, SR_R), - [ICOUNT] =3D XTENSA_REG("ICOUNT", XTENSA_OPTION_DEBUG), - [ICOUNTLEVEL] =3D XTENSA_REG("ICOUNTLEVEL", XTENSA_OPTION_DEBUG), - [EXCVADDR] =3D XTENSA_REG("EXCVADDR", XTENSA_OPTION_EXCEPTION), - [CCOMPARE] =3D XTENSA_REG("CCOMPARE0", XTENSA_OPTION_TIMER_INTERRUPT), - [CCOMPARE + 1] =3D XTENSA_REG("CCOMPARE1", - XTENSA_OPTION_TIMER_INTERRUPT), - [CCOMPARE + 2] =3D XTENSA_REG("CCOMPARE2", - XTENSA_OPTION_TIMER_INTERRUPT), - [MISC] =3D XTENSA_REG("MISC0", XTENSA_OPTION_MISC_SR), - [MISC + 1] =3D XTENSA_REG("MISC1", XTENSA_OPTION_MISC_SR), - [MISC + 2] =3D XTENSA_REG("MISC2", XTENSA_OPTION_MISC_SR), - [MISC + 3] =3D XTENSA_REG("MISC3", XTENSA_OPTION_MISC_SR), -}; - -static const XtensaReg uregnames[256] =3D { - [EXPSTATE] =3D XTENSA_REG_BITS("EXPSTATE", XTENSA_OPTION_ALL), - [THREADPTR] =3D XTENSA_REG("THREADPTR", XTENSA_OPTION_THREAD_POINTER), - [FCR] =3D XTENSA_REG("FCR", XTENSA_OPTION_FP_COPROCESSOR), - [FSR] =3D XTENSA_REG("FSR", XTENSA_OPTION_FP_COPROCESSOR), -}; +} =20 void xtensa_translate_init(void) { @@ -283,18 +195,20 @@ void xtensa_translate_init(void) } =20 for (i =3D 0; i < 256; ++i) { - if (sregnames[i].name) { + if (sr_name[i]) { cpu_SR[i] =3D tcg_global_mem_new_i32(cpu_env, - offsetof(CPUXtensaState, sregs[i]), - sregnames[i].name); + offsetof(CPUXtensaState, + sregs[i]), + sr_name[i]); } } =20 for (i =3D 0; i < 256; ++i) { - if (uregnames[i].name) { + if (ur_name[i]) { cpu_UR[i] =3D tcg_global_mem_new_i32(cpu_env, - offsetof(CPUXtensaState, uregs[i]), - uregnames[i].name); + offsetof(CPUXtensaState, + uregs[i]), + ur_name[i]); } } =20 @@ -536,313 +450,57 @@ static void gen_brcondi(DisasContext *dc, TCGCond co= nd, tcg_temp_free(tmp); } =20 -static bool check_sr(DisasContext *dc, uint32_t sr, unsigned access) -{ - if (!xtensa_option_bits_enabled(dc->config, sregnames[sr].opt_bits)) { - if (sregnames[sr].name) { - qemu_log_mask(LOG_GUEST_ERROR, "SR %s is not configured\n", sr= egnames[sr].name); - } else { - qemu_log_mask(LOG_UNIMP, "SR %d is not implemented\n", sr); - } - return false; - } else if (!(sregnames[sr].access & access)) { - static const char * const access_text[] =3D { - [SR_R] =3D "rsr", - [SR_W] =3D "wsr", - [SR_X] =3D "xsr", - }; - assert(access < ARRAY_SIZE(access_text) && access_text[access]); - qemu_log_mask(LOG_GUEST_ERROR, "SR %s is not available for %s\n", = sregnames[sr].name, - access_text[access]); - return false; - } - return true; -} - -#ifndef CONFIG_USER_ONLY -static void gen_rsr_ccount(DisasContext *dc, TCGv_i32 d, uint32_t sr) -{ - if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } - gen_helper_update_ccount(cpu_env); - tcg_gen_mov_i32(d, cpu_SR[sr]); - if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { - gen_io_end(); - } -} - -static void gen_rsr_ptevaddr(DisasContext *dc, TCGv_i32 d, uint32_t sr) -{ - tcg_gen_shri_i32(d, cpu_SR[EXCVADDR], 10); - tcg_gen_or_i32(d, d, cpu_SR[sr]); - tcg_gen_andi_i32(d, d, 0xfffffffc); -} -#endif - -static void gen_rsr(DisasContext *dc, TCGv_i32 d, uint32_t sr) -{ - static void (* const rsr_handler[256])(DisasContext *dc, - TCGv_i32 d, uint32_t sr) =3D { -#ifndef CONFIG_USER_ONLY - [CCOUNT] =3D gen_rsr_ccount, - [INTSET] =3D gen_rsr_ccount, - [PTEVADDR] =3D gen_rsr_ptevaddr, -#endif - }; - - if (rsr_handler[sr]) { - rsr_handler[sr](dc, d, sr); - } else { - tcg_gen_mov_i32(d, cpu_SR[sr]); - } -} - -static void gen_wsr_sar(DisasContext *dc, uint32_t sr, TCGv_i32 s) -{ - tcg_gen_andi_i32(cpu_SR[sr], s, 0x3f); - if (dc->sar_m32_5bit) { - tcg_gen_discard_i32(dc->sar_m32); - } - dc->sar_5bit =3D false; - dc->sar_m32_5bit =3D false; -} - -static void gen_wsr_br(DisasContext *dc, uint32_t sr, TCGv_i32 s) -{ - tcg_gen_andi_i32(cpu_SR[sr], s, 0xffff); -} - -static void gen_wsr_litbase(DisasContext *dc, uint32_t sr, TCGv_i32 s) -{ - tcg_gen_andi_i32(cpu_SR[sr], s, 0xfffff001); -} - -static void gen_wsr_acchi(DisasContext *dc, uint32_t sr, TCGv_i32 s) -{ - tcg_gen_ext8s_i32(cpu_SR[sr], s); -} - -#ifndef CONFIG_USER_ONLY -static void gen_wsr_windowbase(DisasContext *dc, uint32_t sr, TCGv_i32 v) -{ - tcg_gen_mov_i32(cpu_windowbase_next, v); -} - -static void gen_wsr_windowstart(DisasContext *dc, uint32_t sr, TCGv_i32 v) -{ - tcg_gen_andi_i32(cpu_SR[sr], v, (1 << dc->config->nareg / 4) - 1); -} - -static void gen_wsr_ptevaddr(DisasContext *dc, uint32_t sr, TCGv_i32 v) -{ - tcg_gen_andi_i32(cpu_SR[sr], v, 0xffc00000); -} - -static void gen_wsr_rasid(DisasContext *dc, uint32_t sr, TCGv_i32 v) -{ - gen_helper_wsr_rasid(cpu_env, v); -} - -static void gen_wsr_tlbcfg(DisasContext *dc, uint32_t sr, TCGv_i32 v) -{ - tcg_gen_andi_i32(cpu_SR[sr], v, 0x01130000); -} - -static void gen_wsr_ibreakenable(DisasContext *dc, uint32_t sr, TCGv_i32 v) -{ - gen_helper_wsr_ibreakenable(cpu_env, v); -} - -static void gen_wsr_memctl(DisasContext *dc, uint32_t sr, TCGv_i32 v) -{ - gen_helper_wsr_memctl(cpu_env, v); -} - -static void gen_wsr_atomctl(DisasContext *dc, uint32_t sr, TCGv_i32 v) -{ - tcg_gen_andi_i32(cpu_SR[sr], v, 0x3f); -} - -static void gen_wsr_ibreaka(DisasContext *dc, uint32_t sr, TCGv_i32 v) -{ - unsigned id =3D sr - IBREAKA; - TCGv_i32 tmp =3D tcg_const_i32(id); - - assert(id < dc->config->nibreak); - gen_helper_wsr_ibreaka(cpu_env, tmp, v); - tcg_temp_free(tmp); -} - -static void gen_wsr_dbreaka(DisasContext *dc, uint32_t sr, TCGv_i32 v) -{ - unsigned id =3D sr - DBREAKA; - TCGv_i32 tmp =3D tcg_const_i32(id); - - assert(id < dc->config->ndbreak); - gen_helper_wsr_dbreaka(cpu_env, tmp, v); - tcg_temp_free(tmp); -} - -static void gen_wsr_dbreakc(DisasContext *dc, uint32_t sr, TCGv_i32 v) -{ - unsigned id =3D sr - DBREAKC; - TCGv_i32 tmp =3D tcg_const_i32(id); - - assert(id < dc->config->ndbreak); - gen_helper_wsr_dbreakc(cpu_env, tmp, v); - tcg_temp_free(tmp); -} - -static void gen_wsr_cpenable(DisasContext *dc, uint32_t sr, TCGv_i32 v) -{ - tcg_gen_andi_i32(cpu_SR[sr], v, 0xff); -} - -static void gen_check_interrupts(DisasContext *dc) -{ - if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } - gen_helper_check_interrupts(cpu_env); - if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { - gen_io_end(); - } -} - -static void gen_wsr_intset(DisasContext *dc, uint32_t sr, TCGv_i32 v) +static bool test_ill_sr(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) { - gen_helper_intset(cpu_env, v); + return !xtensa_option_enabled(dc->config, par[1]); } =20 -static void gen_wsr_intclear(DisasContext *dc, uint32_t sr, TCGv_i32 v) +static bool test_ill_ccompare(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) { - gen_helper_intclear(cpu_env, v); -} + unsigned n =3D par[0] - CCOMPARE; =20 -static void gen_wsr_intenable(DisasContext *dc, uint32_t sr, TCGv_i32 v) -{ - tcg_gen_mov_i32(cpu_SR[sr], v); + return test_ill_sr(dc, arg, par) || n >=3D dc->config->nccompare; } =20 -static void gen_wsr_ps(DisasContext *dc, uint32_t sr, TCGv_i32 v) +static bool test_ill_dbreak(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) { - uint32_t mask =3D PS_WOE | PS_CALLINC | PS_OWB | - PS_UM | PS_EXCM | PS_INTLEVEL; + unsigned n =3D MAX_NDBREAK; =20 - if (option_enabled(dc, XTENSA_OPTION_MMU)) { - mask |=3D PS_RING; - } - tcg_gen_andi_i32(cpu_SR[sr], v, mask); -} - -static void gen_wsr_ccount(DisasContext *dc, uint32_t sr, TCGv_i32 v) -{ - if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); + if (par[0] >=3D DBREAKA && par[0] < DBREAKA + MAX_NDBREAK) { + n =3D par[0] - DBREAKA; } - gen_helper_wsr_ccount(cpu_env, v); - if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { - gen_io_end(); + if (par[0] >=3D DBREAKC && par[0] < DBREAKC + MAX_NDBREAK) { + n =3D par[0] - DBREAKC; } + return test_ill_sr(dc, arg, par) || n >=3D dc->config->ndbreak; } =20 -static void gen_wsr_icount(DisasContext *dc, uint32_t sr, TCGv_i32 v) +static bool test_ill_ibreak(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) { - if (dc->icount) { - tcg_gen_mov_i32(dc->next_icount, v); - } else { - tcg_gen_mov_i32(cpu_SR[sr], v); - } -} + unsigned n =3D par[0] - IBREAKA; =20 -static void gen_wsr_icountlevel(DisasContext *dc, uint32_t sr, TCGv_i32 v) -{ - tcg_gen_andi_i32(cpu_SR[sr], v, 0xf); + return test_ill_sr(dc, arg, par) || n >=3D dc->config->nibreak; } =20 -static void gen_wsr_ccompare(DisasContext *dc, uint32_t sr, TCGv_i32 v) +static bool test_ill_hpi(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) { - uint32_t id =3D sr - CCOMPARE; - TCGv_i32 tmp =3D tcg_const_i32(id); + unsigned n =3D MAX_NLEVEL + 1; =20 - assert(id < dc->config->nccompare); - tcg_gen_mov_i32(cpu_SR[sr], v); - if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } - gen_helper_update_ccompare(cpu_env, tmp); - tcg_temp_free(tmp); - if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { - gen_io_end(); + if (par[0] >=3D EXCSAVE1 && par[0] < EXCSAVE1 + MAX_NLEVEL) { + n =3D par[0] - EXCSAVE1 + 1; } -} -#else -static void gen_check_interrupts(DisasContext *dc) -{ -} -#endif - -static void gen_wsr(DisasContext *dc, uint32_t sr, TCGv_i32 s) -{ - static void (* const wsr_handler[256])(DisasContext *dc, - uint32_t sr, TCGv_i32 v) =3D { - [SAR] =3D gen_wsr_sar, - [BR] =3D gen_wsr_br, - [LITBASE] =3D gen_wsr_litbase, - [ACCHI] =3D gen_wsr_acchi, -#ifndef CONFIG_USER_ONLY - [WINDOW_BASE] =3D gen_wsr_windowbase, - [WINDOW_START] =3D gen_wsr_windowstart, - [PTEVADDR] =3D gen_wsr_ptevaddr, - [RASID] =3D gen_wsr_rasid, - [ITLBCFG] =3D gen_wsr_tlbcfg, - [DTLBCFG] =3D gen_wsr_tlbcfg, - [IBREAKENABLE] =3D gen_wsr_ibreakenable, - [MEMCTL] =3D gen_wsr_memctl, - [ATOMCTL] =3D gen_wsr_atomctl, - [IBREAKA] =3D gen_wsr_ibreaka, - [IBREAKA + 1] =3D gen_wsr_ibreaka, - [DBREAKA] =3D gen_wsr_dbreaka, - [DBREAKA + 1] =3D gen_wsr_dbreaka, - [DBREAKC] =3D gen_wsr_dbreakc, - [DBREAKC + 1] =3D gen_wsr_dbreakc, - [CPENABLE] =3D gen_wsr_cpenable, - [INTSET] =3D gen_wsr_intset, - [INTCLEAR] =3D gen_wsr_intclear, - [INTENABLE] =3D gen_wsr_intenable, - [PS] =3D gen_wsr_ps, - [CCOUNT] =3D gen_wsr_ccount, - [ICOUNT] =3D gen_wsr_icount, - [ICOUNTLEVEL] =3D gen_wsr_icountlevel, - [CCOMPARE] =3D gen_wsr_ccompare, - [CCOMPARE + 1] =3D gen_wsr_ccompare, - [CCOMPARE + 2] =3D gen_wsr_ccompare, -#endif - }; - - if (wsr_handler[sr]) { - wsr_handler[sr](dc, sr, s); - } else { - tcg_gen_mov_i32(cpu_SR[sr], s); + if (par[0] >=3D EPC1 && par[0] < EPC1 + MAX_NLEVEL) { + n =3D par[0] - EPC1 + 1; } -} - -static void gen_wur(uint32_t ur, TCGv_i32 s) -{ - switch (ur) { - case FCR: - gen_helper_wur_fcr(cpu_env, s); - break; - - case FSR: - tcg_gen_andi_i32(cpu_UR[ur], s, 0xffffff80); - break; - - default: - tcg_gen_mov_i32(cpu_UR[ur], s); - break; + if (par[0] >=3D EPS2 && par[0] < EPS2 + MAX_NLEVEL - 1) { + n =3D par[0] - EPS2 + 2; } + return test_ill_sr(dc, arg, par) || n > dc->config->nlevel; } =20 static void gen_load_store_alignment(DisasContext *dc, int shift, @@ -925,9 +583,17 @@ static int gen_postprocess(DisasContext *dc, int slot) { uint32_t op_flags =3D dc->op_flags; =20 +#ifndef CONFIG_USER_ONLY if (op_flags & XTENSA_OP_CHECK_INTERRUPTS) { - gen_check_interrupts(dc); + if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { + gen_io_start(); + } + gen_helper_check_interrupts(cpu_env); + if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { + gen_io_end(); + } } +#endif if (op_flags & XTENSA_OP_SYNC_REGISTER_WINDOW) { gen_helper_sync_windowbase(cpu_env); } @@ -1645,24 +1311,20 @@ void xtensa_cpu_dump_state(CPUState *cs, FILE *f, i= nt flags) { XtensaCPU *cpu =3D XTENSA_CPU(cs); CPUXtensaState *env =3D &cpu->env; + xtensa_isa isa =3D env->config->isa; int i, j; =20 qemu_fprintf(f, "PC=3D%08x\n\n", env->pc); =20 - for (i =3D j =3D 0; i < 256; ++i) { - if (xtensa_option_bits_enabled(env->config, sregnames[i].opt_bits)= ) { - qemu_fprintf(f, "%12s=3D%08x%c", - sregnames[i].name, env->sregs[i], - (j++ % 4) =3D=3D 3 ? '\n' : ' '); - } - } - - qemu_fprintf(f, (j % 4) =3D=3D 0 ? "\n" : "\n\n"); + for (i =3D j =3D 0; i < xtensa_isa_num_sysregs(isa); ++i) { + const uint32_t *reg =3D + xtensa_sysreg_is_user(isa, i) ? env->uregs : env->sregs; + int regno =3D xtensa_sysreg_number(isa, i); =20 - for (i =3D j =3D 0; i < 256; ++i) { - if (xtensa_option_bits_enabled(env->config, uregnames[i].opt_bits)= ) { - qemu_fprintf(f, "%s=3D%08x%c", - uregnames[i].name, env->uregs[i], + if (regno >=3D 0) { + qemu_fprintf(f, "%12s=3D%08x%c", + xtensa_sysreg_name(isa, i), + reg[regno], (j++ % 4) =3D=3D 3 ? '\n' : ' '); } } @@ -2472,16 +2134,38 @@ static void translate_rsil(DisasContext *dc, const = OpcodeArg arg[], tcg_gen_ori_i32(cpu_SR[PS], cpu_SR[PS], arg[1].imm); } =20 -static bool test_ill_rsr(DisasContext *dc, const OpcodeArg arg[], - const uint32_t par[]) +static void translate_rsr(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) { - return !check_sr(dc, par[0], SR_R); + tcg_gen_mov_i32(arg[0].out, cpu_SR[par[0]]); } =20 -static void translate_rsr(DisasContext *dc, const OpcodeArg arg[], - const uint32_t par[]) +static void translate_rsr_ccount(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) +{ +#ifndef CONFIG_USER_ONLY + if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { + gen_io_start(); + } + gen_helper_update_ccount(cpu_env); + tcg_gen_mov_i32(arg[0].out, cpu_SR[par[0]]); + if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { + gen_io_end(); + } +#endif +} + +static void translate_rsr_ptevaddr(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) { - gen_rsr(dc, arg[0].out, par[0]); +#ifndef CONFIG_USER_ONLY + TCGv_i32 tmp =3D tcg_temp_new_i32(); + + tcg_gen_shri_i32(tmp, cpu_SR[EXCVADDR], 10); + tcg_gen_or_i32(tmp, tmp, cpu_SR[PTEVADDR]); + tcg_gen_andi_i32(arg[0].out, tmp, 0xfffffffc); + tcg_temp_free(tmp); +#endif } =20 static void translate_rtlb(DisasContext *dc, const OpcodeArg arg[], @@ -2503,11 +2187,7 @@ static void translate_rtlb(DisasContext *dc, const O= pcodeArg arg[], static void translate_rur(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - if (uregnames[par[0]].name) { - tcg_gen_mov_i32(arg[0].out, cpu_UR[par[0]]); - } else { - qemu_log_mask(LOG_UNIMP, "RUR %d not implemented\n", par[0]); - } + tcg_gen_mov_i32(arg[0].out, cpu_UR[par[0]]); } =20 static void translate_setb_expstate(DisasContext *dc, const OpcodeArg arg[= ], @@ -2778,52 +2458,288 @@ static void translate_wrmsk_expstate(DisasContext = *dc, const OpcodeArg arg[], tcg_gen_and_i32(cpu_UR[EXPSTATE], arg[0].in, arg[1].in); } =20 -static bool test_ill_wsr(DisasContext *dc, const OpcodeArg arg[], - const uint32_t par[]) +static void translate_wsr(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) { - return !check_sr(dc, par[0], SR_W); + tcg_gen_mov_i32(cpu_SR[par[0]], arg[0].in); } =20 -static void translate_wsr(DisasContext *dc, const OpcodeArg arg[], - const uint32_t par[]) +static void translate_wsr_mask(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) { - gen_wsr(dc, par[0], arg[0].in); + tcg_gen_andi_i32(cpu_SR[par[0]], arg[0].in, par[2]); } =20 -static void translate_wur(DisasContext *dc, const OpcodeArg arg[], - const uint32_t par[]) +static void translate_wsr_acchi(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) { - if (uregnames[par[0]].name) { - gen_wur(par[0], arg[0].in); - } else { - qemu_log_mask(LOG_UNIMP, "WUR %d not implemented\n", par[0]); - } + tcg_gen_ext8s_i32(cpu_SR[par[0]], arg[0].in); } =20 -static void translate_xor(DisasContext *dc, const OpcodeArg arg[], - const uint32_t par[]) +static void translate_wsr_ccompare(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) { - tcg_gen_xor_i32(arg[0].out, arg[1].in, arg[2].in); +#ifndef CONFIG_USER_ONLY + uint32_t id =3D par[0] - CCOMPARE; + TCGv_i32 tmp =3D tcg_const_i32(id); + + assert(id < dc->config->nccompare); + if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { + gen_io_start(); + } + tcg_gen_mov_i32(cpu_SR[par[0]], arg[0].in); + gen_helper_update_ccompare(cpu_env, tmp); + tcg_temp_free(tmp); + if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { + gen_io_end(); + } +#endif } =20 -static bool test_ill_xsr(DisasContext *dc, const OpcodeArg arg[], - const uint32_t par[]) +static void translate_wsr_ccount(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) { - return !check_sr(dc, par[0], SR_X); +#ifndef CONFIG_USER_ONLY + if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { + gen_io_start(); + } + gen_helper_wsr_ccount(cpu_env, arg[0].in); + if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { + gen_io_end(); + } +#endif } =20 -static void translate_xsr(DisasContext *dc, const OpcodeArg arg[], - const uint32_t par[]) +static void translate_wsr_dbreaka(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) { - TCGv_i32 tmp =3D tcg_temp_new_i32(); +#ifndef CONFIG_USER_ONLY + unsigned id =3D par[0] - DBREAKA; + TCGv_i32 tmp =3D tcg_const_i32(id); =20 - tcg_gen_mov_i32(tmp, arg[0].in); - gen_rsr(dc, arg[0].out, par[0]); - gen_wsr(dc, par[0], tmp); + assert(id < dc->config->ndbreak); + gen_helper_wsr_dbreaka(cpu_env, tmp, arg[0].in); tcg_temp_free(tmp); +#endif } =20 -static const XtensaOpcodeOps core_ops[] =3D { +static void translate_wsr_dbreakc(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) +{ +#ifndef CONFIG_USER_ONLY + unsigned id =3D par[0] - DBREAKC; + TCGv_i32 tmp =3D tcg_const_i32(id); + + assert(id < dc->config->ndbreak); + gen_helper_wsr_dbreakc(cpu_env, tmp, arg[0].in); + tcg_temp_free(tmp); +#endif +} + +static void translate_wsr_ibreaka(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) +{ +#ifndef CONFIG_USER_ONLY + unsigned id =3D par[0] - IBREAKA; + TCGv_i32 tmp =3D tcg_const_i32(id); + + assert(id < dc->config->nibreak); + gen_helper_wsr_ibreaka(cpu_env, tmp, arg[0].in); + tcg_temp_free(tmp); +#endif +} + +static void translate_wsr_ibreakenable(DisasContext *dc, const OpcodeArg a= rg[], + const uint32_t par[]) +{ +#ifndef CONFIG_USER_ONLY + gen_helper_wsr_ibreakenable(cpu_env, arg[0].in); +#endif +} + +static void translate_wsr_icount(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) +{ +#ifndef CONFIG_USER_ONLY + if (dc->icount) { + tcg_gen_mov_i32(dc->next_icount, arg[0].in); + } else { + tcg_gen_mov_i32(cpu_SR[par[0]], arg[0].in); + } +#endif +} + +static void translate_wsr_intclear(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) +{ +#ifndef CONFIG_USER_ONLY + gen_helper_intclear(cpu_env, arg[0].in); +#endif +} + +static void translate_wsr_intset(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) +{ +#ifndef CONFIG_USER_ONLY + gen_helper_intset(cpu_env, arg[0].in); +#endif +} + +static void translate_wsr_memctl(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) +{ +#ifndef CONFIG_USER_ONLY + gen_helper_wsr_memctl(cpu_env, arg[0].in); +#endif +} + +static void translate_wsr_ps(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) +{ +#ifndef CONFIG_USER_ONLY + uint32_t mask =3D PS_WOE | PS_CALLINC | PS_OWB | + PS_UM | PS_EXCM | PS_INTLEVEL; + + if (option_enabled(dc, XTENSA_OPTION_MMU)) { + mask |=3D PS_RING; + } + tcg_gen_andi_i32(cpu_SR[par[0]], arg[0].in, mask); +#endif +} + +static void translate_wsr_rasid(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) +{ +#ifndef CONFIG_USER_ONLY + gen_helper_wsr_rasid(cpu_env, arg[0].in); +#endif +} + +static void translate_wsr_sar(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) +{ + tcg_gen_andi_i32(cpu_SR[par[0]], arg[0].in, 0x3f); + if (dc->sar_m32_5bit) { + tcg_gen_discard_i32(dc->sar_m32); + } + dc->sar_5bit =3D false; + dc->sar_m32_5bit =3D false; +} + +static void translate_wsr_windowbase(DisasContext *dc, const OpcodeArg arg= [], + const uint32_t par[]) +{ +#ifndef CONFIG_USER_ONLY + tcg_gen_mov_i32(cpu_windowbase_next, arg[0].in); +#endif +} + +static void translate_wsr_windowstart(DisasContext *dc, const OpcodeArg ar= g[], + const uint32_t par[]) +{ +#ifndef CONFIG_USER_ONLY + tcg_gen_andi_i32(cpu_SR[par[0]], arg[0].in, + (1 << dc->config->nareg / 4) - 1); +#endif +} + +static void translate_wur(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) +{ + tcg_gen_mov_i32(cpu_UR[par[0]], arg[0].in); +} + +static void translate_wur_fcr(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) +{ + gen_helper_wur_fcr(cpu_env, arg[0].in); +} + +static void translate_wur_fsr(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) +{ + tcg_gen_andi_i32(cpu_UR[par[0]], arg[0].in, 0xffffff80); +} + +static void translate_xor(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) +{ + tcg_gen_xor_i32(arg[0].out, arg[1].in, arg[2].in); +} + +static void translate_xsr(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) +{ + TCGv_i32 tmp =3D tcg_temp_new_i32(); + + tcg_gen_mov_i32(tmp, arg[0].in); + tcg_gen_mov_i32(arg[0].out, cpu_SR[par[0]]); + tcg_gen_mov_i32(cpu_SR[par[0]], tmp); + tcg_temp_free(tmp); +} + +static void translate_xsr_mask(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) +{ + TCGv_i32 tmp =3D tcg_temp_new_i32(); + + tcg_gen_mov_i32(tmp, arg[0].in); + tcg_gen_mov_i32(arg[0].out, cpu_SR[par[0]]); + tcg_gen_andi_i32(cpu_SR[par[0]], tmp, par[2]); + tcg_temp_free(tmp); +} + +static void translate_xsr_ccount(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) +{ +#ifndef CONFIG_USER_ONLY + TCGv_i32 tmp =3D tcg_temp_new_i32(); + + if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { + gen_io_start(); + } + + gen_helper_update_ccount(cpu_env); + tcg_gen_mov_i32(tmp, cpu_SR[par[0]]); + gen_helper_wsr_ccount(cpu_env, arg[0].in); + tcg_gen_mov_i32(arg[0].out, tmp); + tcg_temp_free(tmp); + + if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { + gen_io_end(); + } +#endif +} + +#define gen_translate_xsr(name) \ + static void translate_xsr_##name(DisasContext *dc, const OpcodeArg arg= [], \ + const uint32_t par[]) \ +{ \ + TCGv_i32 tmp =3D tcg_temp_new_i32(); \ + \ + tcg_gen_mov_i32(tmp, cpu_SR[par[0]]); \ + translate_wsr_##name(dc, arg, par); \ + tcg_gen_mov_i32(arg[0].out, tmp); \ + tcg_temp_free(tmp); \ +} + +gen_translate_xsr(acchi) +gen_translate_xsr(ccompare) +gen_translate_xsr(dbreaka) +gen_translate_xsr(dbreakc) +gen_translate_xsr(ibreaka) +gen_translate_xsr(ibreakenable) +gen_translate_xsr(icount) +gen_translate_xsr(memctl) +gen_translate_xsr(ps) +gen_translate_xsr(rasid) +gen_translate_xsr(sar) +gen_translate_xsr(windowbase) +gen_translate_xsr(windowstart) + +#undef gen_translate_xsr + +static const XtensaOpcodeOps core_ops[] =3D { { .name =3D "abs", .translate =3D translate_abs, @@ -3766,450 +3682,653 @@ static const XtensaOpcodeOps core_ops[] =3D { }, { .name =3D "rsr.176", .translate =3D translate_rsr, - .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){176}, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.208", .translate =3D translate_rsr, - .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){208}, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.acchi", .translate =3D translate_rsr, - .test_ill =3D test_ill_rsr, - .par =3D (const uint32_t[]){ACCHI}, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + ACCHI, + XTENSA_OPTION_MAC16, + }, }, { .name =3D "rsr.acclo", .translate =3D translate_rsr, - .test_ill =3D test_ill_rsr, - .par =3D (const uint32_t[]){ACCLO}, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + ACCLO, + XTENSA_OPTION_MAC16, + }, }, { .name =3D "rsr.atomctl", .translate =3D translate_rsr, - .test_ill =3D test_ill_rsr, - .par =3D (const uint32_t[]){ATOMCTL}, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + ATOMCTL, + XTENSA_OPTION_ATOMCTL, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.br", .translate =3D translate_rsr, - .test_ill =3D test_ill_rsr, - .par =3D (const uint32_t[]){BR}, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + BR, + XTENSA_OPTION_BOOLEAN, + }, }, { .name =3D "rsr.cacheattr", .translate =3D translate_rsr, - .test_ill =3D test_ill_rsr, - .par =3D (const uint32_t[]){CACHEATTR}, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + CACHEATTR, + XTENSA_OPTION_CACHEATTR, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.ccompare0", .translate =3D translate_rsr, - .test_ill =3D test_ill_rsr, - .par =3D (const uint32_t[]){CCOMPARE}, + .test_ill =3D test_ill_ccompare, + .par =3D (const uint32_t[]){ + CCOMPARE, + XTENSA_OPTION_TIMER_INTERRUPT, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.ccompare1", .translate =3D translate_rsr, - .test_ill =3D test_ill_rsr, - .par =3D (const uint32_t[]){CCOMPARE + 1}, + .test_ill =3D test_ill_ccompare, + .par =3D (const uint32_t[]){ + CCOMPARE + 1, + XTENSA_OPTION_TIMER_INTERRUPT, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.ccompare2", .translate =3D translate_rsr, - .test_ill =3D test_ill_rsr, - .par =3D (const uint32_t[]){CCOMPARE + 2}, + .test_ill =3D test_ill_ccompare, + .par =3D (const uint32_t[]){ + CCOMPARE + 2, + XTENSA_OPTION_TIMER_INTERRUPT, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.ccount", - .translate =3D translate_rsr, - .test_ill =3D test_ill_rsr, - .par =3D (const uint32_t[]){CCOUNT}, + .translate =3D translate_rsr_ccount, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + CCOUNT, + XTENSA_OPTION_TIMER_INTERRUPT, + }, .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, }, { .name =3D "rsr.configid0", .translate =3D translate_rsr, - .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){CONFIGID0}, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.configid1", .translate =3D translate_rsr, - .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){CONFIGID1}, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.cpenable", .translate =3D translate_rsr, - .test_ill =3D test_ill_rsr, - .par =3D (const uint32_t[]){CPENABLE}, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + CPENABLE, + XTENSA_OPTION_COPROCESSOR, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.dbreaka0", .translate =3D translate_rsr, - .test_ill =3D test_ill_rsr, - .par =3D (const uint32_t[]){DBREAKA}, + .test_ill =3D test_ill_dbreak, + .par =3D (const uint32_t[]){ + DBREAKA, + XTENSA_OPTION_DEBUG, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.dbreaka1", .translate =3D translate_rsr, - .test_ill =3D test_ill_rsr, - .par =3D (const uint32_t[]){DBREAKA + 1}, + .test_ill =3D test_ill_dbreak, + .par =3D (const uint32_t[]){ + DBREAKA + 1, + XTENSA_OPTION_DEBUG, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.dbreakc0", .translate =3D translate_rsr, - .test_ill =3D test_ill_rsr, - .par =3D (const uint32_t[]){DBREAKC}, + .test_ill =3D test_ill_dbreak, + .par =3D (const uint32_t[]){ + DBREAKC, + XTENSA_OPTION_DEBUG, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.dbreakc1", .translate =3D translate_rsr, - .test_ill =3D test_ill_rsr, - .par =3D (const uint32_t[]){DBREAKC + 1}, + .test_ill =3D test_ill_dbreak, + .par =3D (const uint32_t[]){ + DBREAKC + 1, + XTENSA_OPTION_DEBUG, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.ddr", .translate =3D translate_rsr, - .test_ill =3D test_ill_rsr, - .par =3D (const uint32_t[]){DDR}, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + DDR, + XTENSA_OPTION_DEBUG, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.debugcause", .translate =3D translate_rsr, - .test_ill =3D test_ill_rsr, - .par =3D (const uint32_t[]){DEBUGCAUSE}, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + DEBUGCAUSE, + XTENSA_OPTION_DEBUG, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.depc", .translate =3D translate_rsr, - .test_ill =3D test_ill_rsr, - .par =3D (const uint32_t[]){DEPC}, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + DEPC, + XTENSA_OPTION_EXCEPTION, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.dtlbcfg", .translate =3D translate_rsr, - .test_ill =3D test_ill_rsr, - .par =3D (const uint32_t[]){DTLBCFG}, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + DTLBCFG, + XTENSA_OPTION_MMU, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.epc1", .translate =3D translate_rsr, - .test_ill =3D test_ill_rsr, - .par =3D (const uint32_t[]){EPC1}, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + EPC1, + XTENSA_OPTION_EXCEPTION, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.epc2", .translate =3D translate_rsr, - .test_ill =3D test_ill_rsr, - .par =3D (const uint32_t[]){EPC1 + 1}, + .test_ill =3D test_ill_hpi, + .par =3D (const uint32_t[]){ + EPC1 + 1, + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.epc3", .translate =3D translate_rsr, - .test_ill =3D test_ill_rsr, - .par =3D (const uint32_t[]){EPC1 + 2}, + .test_ill =3D test_ill_hpi, + .par =3D (const uint32_t[]){ + EPC1 + 2, + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.epc4", .translate =3D translate_rsr, - .test_ill =3D test_ill_rsr, - .par =3D (const uint32_t[]){EPC1 + 3}, + .test_ill =3D test_ill_hpi, + .par =3D (const uint32_t[]){ + EPC1 + 3, + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.epc5", .translate =3D translate_rsr, - .test_ill =3D test_ill_rsr, - .par =3D (const uint32_t[]){EPC1 + 4}, + .test_ill =3D test_ill_hpi, + .par =3D (const uint32_t[]){ + EPC1 + 4, + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.epc6", .translate =3D translate_rsr, - .test_ill =3D test_ill_rsr, - .par =3D (const uint32_t[]){EPC1 + 5}, + .test_ill =3D test_ill_hpi, + .par =3D (const uint32_t[]){ + EPC1 + 5, + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.epc7", .translate =3D translate_rsr, - .test_ill =3D test_ill_rsr, - .par =3D (const uint32_t[]){EPC1 + 6}, + .test_ill =3D test_ill_hpi, + .par =3D (const uint32_t[]){ + EPC1 + 6, + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.eps2", .translate =3D translate_rsr, - .test_ill =3D test_ill_rsr, - .par =3D (const uint32_t[]){EPS2}, + .test_ill =3D test_ill_hpi, + .par =3D (const uint32_t[]){ + EPS2, + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.eps3", .translate =3D translate_rsr, - .test_ill =3D test_ill_rsr, - .par =3D (const uint32_t[]){EPS2 + 1}, + .test_ill =3D test_ill_hpi, + .par =3D (const uint32_t[]){ + EPS2 + 1, + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.eps4", .translate =3D translate_rsr, - .test_ill =3D test_ill_rsr, - .par =3D (const uint32_t[]){EPS2 + 2}, + .test_ill =3D test_ill_hpi, + .par =3D (const uint32_t[]){ + EPS2 + 2, + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.eps5", .translate =3D translate_rsr, - .test_ill =3D test_ill_rsr, - .par =3D (const uint32_t[]){EPS2 + 3}, + .test_ill =3D test_ill_hpi, + .par =3D (const uint32_t[]){ + EPS2 + 3, + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.eps6", .translate =3D translate_rsr, - .test_ill =3D test_ill_rsr, - .par =3D (const uint32_t[]){EPS2 + 4}, + .test_ill =3D test_ill_hpi, + .par =3D (const uint32_t[]){ + EPS2 + 4, + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.eps7", .translate =3D translate_rsr, - .test_ill =3D test_ill_rsr, - .par =3D (const uint32_t[]){EPS2 + 5}, + .test_ill =3D test_ill_hpi, + .par =3D (const uint32_t[]){ + EPS2 + 5, + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.exccause", .translate =3D translate_rsr, - .test_ill =3D test_ill_rsr, - .par =3D (const uint32_t[]){EXCCAUSE}, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + EXCCAUSE, + XTENSA_OPTION_EXCEPTION, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.excsave1", .translate =3D translate_rsr, - .test_ill =3D test_ill_rsr, - .par =3D (const uint32_t[]){EXCSAVE1}, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + EXCSAVE1, + XTENSA_OPTION_EXCEPTION, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.excsave2", .translate =3D translate_rsr, - .test_ill =3D test_ill_rsr, - .par =3D (const uint32_t[]){EXCSAVE1 + 1}, + .test_ill =3D test_ill_hpi, + .par =3D (const uint32_t[]){ + EXCSAVE1 + 1, + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.excsave3", .translate =3D translate_rsr, - .test_ill =3D test_ill_rsr, - .par =3D (const uint32_t[]){EXCSAVE1 + 2}, + .test_ill =3D test_ill_hpi, + .par =3D (const uint32_t[]){ + EXCSAVE1 + 2, + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.excsave4", .translate =3D translate_rsr, - .test_ill =3D test_ill_rsr, - .par =3D (const uint32_t[]){EXCSAVE1 + 3}, + .test_ill =3D test_ill_hpi, + .par =3D (const uint32_t[]){ + EXCSAVE1 + 3, + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.excsave5", .translate =3D translate_rsr, - .test_ill =3D test_ill_rsr, - .par =3D (const uint32_t[]){EXCSAVE1 + 4}, + .test_ill =3D test_ill_hpi, + .par =3D (const uint32_t[]){ + EXCSAVE1 + 4, + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.excsave6", .translate =3D translate_rsr, - .test_ill =3D test_ill_rsr, - .par =3D (const uint32_t[]){EXCSAVE1 + 5}, + .test_ill =3D test_ill_hpi, + .par =3D (const uint32_t[]){ + EXCSAVE1 + 5, + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.excsave7", .translate =3D translate_rsr, - .test_ill =3D test_ill_rsr, - .par =3D (const uint32_t[]){EXCSAVE1 + 6}, + .test_ill =3D test_ill_hpi, + .par =3D (const uint32_t[]){ + EXCSAVE1 + 6, + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.excvaddr", .translate =3D translate_rsr, - .test_ill =3D test_ill_rsr, - .par =3D (const uint32_t[]){EXCVADDR}, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + EXCVADDR, + XTENSA_OPTION_EXCEPTION, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.ibreaka0", .translate =3D translate_rsr, - .test_ill =3D test_ill_rsr, - .par =3D (const uint32_t[]){IBREAKA}, + .test_ill =3D test_ill_ibreak, + .par =3D (const uint32_t[]){ + IBREAKA, + XTENSA_OPTION_DEBUG, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.ibreaka1", .translate =3D translate_rsr, - .test_ill =3D test_ill_rsr, - .par =3D (const uint32_t[]){IBREAKA + 1}, + .test_ill =3D test_ill_ibreak, + .par =3D (const uint32_t[]){ + IBREAKA + 1, + XTENSA_OPTION_DEBUG, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.ibreakenable", .translate =3D translate_rsr, - .test_ill =3D test_ill_rsr, - .par =3D (const uint32_t[]){IBREAKENABLE}, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + IBREAKENABLE, + XTENSA_OPTION_DEBUG, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.icount", .translate =3D translate_rsr, - .test_ill =3D test_ill_rsr, - .par =3D (const uint32_t[]){ICOUNT}, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + ICOUNT, + XTENSA_OPTION_DEBUG, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.icountlevel", .translate =3D translate_rsr, - .test_ill =3D test_ill_rsr, - .par =3D (const uint32_t[]){ICOUNTLEVEL}, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + ICOUNTLEVEL, + XTENSA_OPTION_DEBUG, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.intclear", .translate =3D translate_rsr, - .test_ill =3D test_ill_rsr, - .par =3D (const uint32_t[]){INTCLEAR}, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + INTCLEAR, + XTENSA_OPTION_INTERRUPT, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.intenable", .translate =3D translate_rsr, - .test_ill =3D test_ill_rsr, - .par =3D (const uint32_t[]){INTENABLE}, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + INTENABLE, + XTENSA_OPTION_INTERRUPT, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.interrupt", - .translate =3D translate_rsr, - .test_ill =3D test_ill_rsr, - .par =3D (const uint32_t[]){INTSET}, + .translate =3D translate_rsr_ccount, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + INTSET, + XTENSA_OPTION_INTERRUPT, + }, .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, }, { .name =3D "rsr.intset", - .translate =3D translate_rsr, - .test_ill =3D test_ill_rsr, - .par =3D (const uint32_t[]){INTSET}, + .translate =3D translate_rsr_ccount, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + INTSET, + XTENSA_OPTION_INTERRUPT, + }, .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, }, { .name =3D "rsr.itlbcfg", .translate =3D translate_rsr, - .test_ill =3D test_ill_rsr, - .par =3D (const uint32_t[]){ITLBCFG}, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + ITLBCFG, + XTENSA_OPTION_MMU, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.lbeg", .translate =3D translate_rsr, - .test_ill =3D test_ill_rsr, - .par =3D (const uint32_t[]){LBEG}, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + LBEG, + XTENSA_OPTION_LOOP, + }, }, { .name =3D "rsr.lcount", .translate =3D translate_rsr, - .test_ill =3D test_ill_rsr, - .par =3D (const uint32_t[]){LCOUNT}, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + LCOUNT, + XTENSA_OPTION_LOOP, + }, }, { .name =3D "rsr.lend", .translate =3D translate_rsr, - .test_ill =3D test_ill_rsr, - .par =3D (const uint32_t[]){LEND}, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + LEND, + XTENSA_OPTION_LOOP, + }, }, { .name =3D "rsr.litbase", .translate =3D translate_rsr, - .test_ill =3D test_ill_rsr, - .par =3D (const uint32_t[]){LITBASE}, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + LITBASE, + XTENSA_OPTION_EXTENDED_L32R, + }, }, { .name =3D "rsr.m0", .translate =3D translate_rsr, - .test_ill =3D test_ill_rsr, - .par =3D (const uint32_t[]){MR}, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + MR, + XTENSA_OPTION_MAC16, + }, }, { .name =3D "rsr.m1", .translate =3D translate_rsr, - .test_ill =3D test_ill_rsr, - .par =3D (const uint32_t[]){MR + 1}, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + MR + 1, + XTENSA_OPTION_MAC16, + }, }, { .name =3D "rsr.m2", .translate =3D translate_rsr, - .test_ill =3D test_ill_rsr, - .par =3D (const uint32_t[]){MR + 2}, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + MR + 2, + XTENSA_OPTION_MAC16, + }, }, { .name =3D "rsr.m3", .translate =3D translate_rsr, - .test_ill =3D test_ill_rsr, - .par =3D (const uint32_t[]){MR + 3}, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + MR + 3, + XTENSA_OPTION_MAC16, + }, }, { .name =3D "rsr.memctl", .translate =3D translate_rsr, - .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){MEMCTL}, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.misc0", .translate =3D translate_rsr, - .test_ill =3D test_ill_rsr, - .par =3D (const uint32_t[]){MISC}, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + MISC, + XTENSA_OPTION_MISC_SR, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.misc1", .translate =3D translate_rsr, - .test_ill =3D test_ill_rsr, - .par =3D (const uint32_t[]){MISC + 1}, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + MISC + 1, + XTENSA_OPTION_MISC_SR, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.misc2", .translate =3D translate_rsr, - .test_ill =3D test_ill_rsr, - .par =3D (const uint32_t[]){MISC + 2}, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + MISC + 2, + XTENSA_OPTION_MISC_SR, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.misc3", .translate =3D translate_rsr, - .test_ill =3D test_ill_rsr, - .par =3D (const uint32_t[]){MISC + 3}, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + MISC + 3, + XTENSA_OPTION_MISC_SR, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.prefctl", .translate =3D translate_rsr, - .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){PREFCTL}, }, { .name =3D "rsr.prid", .translate =3D translate_rsr, - .test_ill =3D test_ill_rsr, - .par =3D (const uint32_t[]){PRID}, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + PRID, + XTENSA_OPTION_PROCESSOR_ID, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.ps", .translate =3D translate_rsr, - .test_ill =3D test_ill_rsr, - .par =3D (const uint32_t[]){PS}, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + PS, + XTENSA_OPTION_EXCEPTION, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.ptevaddr", - .translate =3D translate_rsr, - .test_ill =3D test_ill_rsr, - .par =3D (const uint32_t[]){PTEVADDR}, + .translate =3D translate_rsr_ptevaddr, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + PTEVADDR, + XTENSA_OPTION_MMU, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.rasid", .translate =3D translate_rsr, - .test_ill =3D test_ill_rsr, - .par =3D (const uint32_t[]){RASID}, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + RASID, + XTENSA_OPTION_MMU, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.sar", .translate =3D translate_rsr, - .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){SAR}, }, { .name =3D "rsr.scompare1", .translate =3D translate_rsr, - .test_ill =3D test_ill_rsr, - .par =3D (const uint32_t[]){SCOMPARE1}, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + SCOMPARE1, + XTENSA_OPTION_CONDITIONAL_STORE, + }, }, { .name =3D "rsr.vecbase", .translate =3D translate_rsr, - .test_ill =3D test_ill_rsr, - .par =3D (const uint32_t[]){VECBASE}, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + VECBASE, + XTENSA_OPTION_RELOCATABLE_VECTOR, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.windowbase", .translate =3D translate_rsr, - .test_ill =3D test_ill_rsr, - .par =3D (const uint32_t[]){WINDOW_BASE}, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + WINDOW_BASE, + XTENSA_OPTION_WINDOWED_REGISTER, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.windowstart", .translate =3D translate_rsr, - .test_ill =3D test_ill_rsr, - .par =3D (const uint32_t[]){WINDOW_START}, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + WINDOW_START, + XTENSA_OPTION_WINDOWED_REGISTER, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsync", @@ -4374,300 +4493,425 @@ static const XtensaOpcodeOps core_ops[] =3D { .translate =3D translate_wrmsk_expstate, }, { .name =3D "wsr.176", - .translate =3D translate_wsr, - .test_ill =3D test_ill_wsr, - .par =3D (const uint32_t[]){176}, - .op_flags =3D XTENSA_OP_PRIVILEGED, + .op_flags =3D XTENSA_OP_ILL, }, { .name =3D "wsr.208", - .translate =3D translate_wsr, - .test_ill =3D test_ill_wsr, - .par =3D (const uint32_t[]){208}, - .op_flags =3D XTENSA_OP_PRIVILEGED, + .op_flags =3D XTENSA_OP_ILL, }, { .name =3D "wsr.acchi", - .translate =3D translate_wsr, - .test_ill =3D test_ill_wsr, - .par =3D (const uint32_t[]){ACCHI}, + .translate =3D translate_wsr_acchi, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + ACCHI, + XTENSA_OPTION_MAC16, + }, }, { .name =3D "wsr.acclo", .translate =3D translate_wsr, - .test_ill =3D test_ill_wsr, - .par =3D (const uint32_t[]){ACCLO}, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + ACCLO, + XTENSA_OPTION_MAC16, + }, }, { .name =3D "wsr.atomctl", - .translate =3D translate_wsr, - .test_ill =3D test_ill_wsr, - .par =3D (const uint32_t[]){ATOMCTL}, + .translate =3D translate_wsr_mask, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + ATOMCTL, + XTENSA_OPTION_ATOMCTL, + 0x3f, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.br", - .translate =3D translate_wsr, - .test_ill =3D test_ill_wsr, - .par =3D (const uint32_t[]){BR}, + .translate =3D translate_wsr_mask, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + BR, + XTENSA_OPTION_BOOLEAN, + 0xffff, + }, }, { .name =3D "wsr.cacheattr", .translate =3D translate_wsr, - .test_ill =3D test_ill_wsr, - .par =3D (const uint32_t[]){CACHEATTR}, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + CACHEATTR, + XTENSA_OPTION_CACHEATTR, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.ccompare0", - .translate =3D translate_wsr, - .test_ill =3D test_ill_wsr, - .par =3D (const uint32_t[]){CCOMPARE}, + .translate =3D translate_wsr_ccompare, + .test_ill =3D test_ill_ccompare, + .par =3D (const uint32_t[]){ + CCOMPARE, + XTENSA_OPTION_TIMER_INTERRUPT, + }, .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, }, { .name =3D "wsr.ccompare1", - .translate =3D translate_wsr, - .test_ill =3D test_ill_wsr, - .par =3D (const uint32_t[]){CCOMPARE + 1}, + .translate =3D translate_wsr_ccompare, + .test_ill =3D test_ill_ccompare, + .par =3D (const uint32_t[]){ + CCOMPARE + 1, + XTENSA_OPTION_TIMER_INTERRUPT, + }, .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, }, { .name =3D "wsr.ccompare2", - .translate =3D translate_wsr, - .test_ill =3D test_ill_wsr, - .par =3D (const uint32_t[]){CCOMPARE + 2}, + .translate =3D translate_wsr_ccompare, + .test_ill =3D test_ill_ccompare, + .par =3D (const uint32_t[]){ + CCOMPARE + 2, + XTENSA_OPTION_TIMER_INTERRUPT, + }, .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, }, { .name =3D "wsr.ccount", - .translate =3D translate_wsr, - .test_ill =3D test_ill_wsr, - .par =3D (const uint32_t[]){CCOUNT}, + .translate =3D translate_wsr_ccount, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + CCOUNT, + XTENSA_OPTION_TIMER_INTERRUPT, + }, .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, }, { .name =3D "wsr.configid0", - .translate =3D translate_wsr, - .test_ill =3D test_ill_wsr, - .par =3D (const uint32_t[]){CONFIGID0}, - .op_flags =3D XTENSA_OP_PRIVILEGED, + .op_flags =3D XTENSA_OP_ILL, }, { .name =3D "wsr.configid1", - .translate =3D translate_wsr, - .test_ill =3D test_ill_wsr, - .par =3D (const uint32_t[]){CONFIGID1}, - .op_flags =3D XTENSA_OP_PRIVILEGED, + .op_flags =3D XTENSA_OP_ILL, }, { .name =3D "wsr.cpenable", - .translate =3D translate_wsr, - .test_ill =3D test_ill_wsr, - .par =3D (const uint32_t[]){CPENABLE}, + .translate =3D translate_wsr_mask, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + CPENABLE, + XTENSA_OPTION_COPROCESSOR, + 0xff, + }, .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, }, { .name =3D "wsr.dbreaka0", - .translate =3D translate_wsr, - .test_ill =3D test_ill_wsr, - .par =3D (const uint32_t[]){DBREAKA}, + .translate =3D translate_wsr_dbreaka, + .test_ill =3D test_ill_dbreak, + .par =3D (const uint32_t[]){ + DBREAKA, + XTENSA_OPTION_DEBUG, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.dbreaka1", - .translate =3D translate_wsr, - .test_ill =3D test_ill_wsr, - .par =3D (const uint32_t[]){DBREAKA + 1}, + .translate =3D translate_wsr_dbreaka, + .test_ill =3D test_ill_dbreak, + .par =3D (const uint32_t[]){ + DBREAKA + 1, + XTENSA_OPTION_DEBUG, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.dbreakc0", - .translate =3D translate_wsr, - .test_ill =3D test_ill_wsr, - .par =3D (const uint32_t[]){DBREAKC}, + .translate =3D translate_wsr_dbreakc, + .test_ill =3D test_ill_dbreak, + .par =3D (const uint32_t[]){ + DBREAKC, + XTENSA_OPTION_DEBUG, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.dbreakc1", - .translate =3D translate_wsr, - .test_ill =3D test_ill_wsr, - .par =3D (const uint32_t[]){DBREAKC + 1}, + .translate =3D translate_wsr_dbreakc, + .test_ill =3D test_ill_dbreak, + .par =3D (const uint32_t[]){ + DBREAKC + 1, + XTENSA_OPTION_DEBUG, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.ddr", .translate =3D translate_wsr, - .test_ill =3D test_ill_wsr, - .par =3D (const uint32_t[]){DDR}, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + DDR, + XTENSA_OPTION_DEBUG, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.debugcause", - .translate =3D translate_wsr, - .test_ill =3D test_ill_wsr, - .par =3D (const uint32_t[]){DEBUGCAUSE}, - .op_flags =3D XTENSA_OP_PRIVILEGED, + .op_flags =3D XTENSA_OP_ILL, }, { .name =3D "wsr.depc", .translate =3D translate_wsr, - .test_ill =3D test_ill_wsr, - .par =3D (const uint32_t[]){DEPC}, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + DEPC, + XTENSA_OPTION_EXCEPTION, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.dtlbcfg", - .translate =3D translate_wsr, - .test_ill =3D test_ill_wsr, - .par =3D (const uint32_t[]){DTLBCFG}, + .translate =3D translate_wsr_mask, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + DTLBCFG, + XTENSA_OPTION_MMU, + 0x01130000, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.epc1", .translate =3D translate_wsr, - .test_ill =3D test_ill_wsr, - .par =3D (const uint32_t[]){EPC1}, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + EPC1, + XTENSA_OPTION_EXCEPTION, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.epc2", .translate =3D translate_wsr, - .test_ill =3D test_ill_wsr, - .par =3D (const uint32_t[]){EPC1 + 1}, + .test_ill =3D test_ill_hpi, + .par =3D (const uint32_t[]){ + EPC1 + 1, + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.epc3", .translate =3D translate_wsr, - .test_ill =3D test_ill_wsr, - .par =3D (const uint32_t[]){EPC1 + 2}, + .test_ill =3D test_ill_hpi, + .par =3D (const uint32_t[]){ + EPC1 + 2, + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.epc4", .translate =3D translate_wsr, - .test_ill =3D test_ill_wsr, - .par =3D (const uint32_t[]){EPC1 + 3}, + .test_ill =3D test_ill_hpi, + .par =3D (const uint32_t[]){ + EPC1 + 3, + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.epc5", .translate =3D translate_wsr, - .test_ill =3D test_ill_wsr, - .par =3D (const uint32_t[]){EPC1 + 4}, + .test_ill =3D test_ill_hpi, + .par =3D (const uint32_t[]){ + EPC1 + 4, + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.epc6", .translate =3D translate_wsr, - .test_ill =3D test_ill_wsr, - .par =3D (const uint32_t[]){EPC1 + 5}, + .test_ill =3D test_ill_hpi, + .par =3D (const uint32_t[]){ + EPC1 + 5, + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.epc7", .translate =3D translate_wsr, - .test_ill =3D test_ill_wsr, - .par =3D (const uint32_t[]){EPC1 + 6}, + .test_ill =3D test_ill_hpi, + .par =3D (const uint32_t[]){ + EPC1 + 6, + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.eps2", .translate =3D translate_wsr, - .test_ill =3D test_ill_wsr, - .par =3D (const uint32_t[]){EPS2}, + .test_ill =3D test_ill_hpi, + .par =3D (const uint32_t[]){ + EPS2, + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.eps3", .translate =3D translate_wsr, - .test_ill =3D test_ill_wsr, - .par =3D (const uint32_t[]){EPS2 + 1}, + .test_ill =3D test_ill_hpi, + .par =3D (const uint32_t[]){ + EPS2 + 1, + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.eps4", .translate =3D translate_wsr, - .test_ill =3D test_ill_wsr, - .par =3D (const uint32_t[]){EPS2 + 2}, + .test_ill =3D test_ill_hpi, + .par =3D (const uint32_t[]){ + EPS2 + 2, + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.eps5", .translate =3D translate_wsr, - .test_ill =3D test_ill_wsr, - .par =3D (const uint32_t[]){EPS2 + 3}, + .test_ill =3D test_ill_hpi, + .par =3D (const uint32_t[]){ + EPS2 + 3, + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.eps6", .translate =3D translate_wsr, - .test_ill =3D test_ill_wsr, - .par =3D (const uint32_t[]){EPS2 + 4}, + .test_ill =3D test_ill_hpi, + .par =3D (const uint32_t[]){ + EPS2 + 4, + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.eps7", .translate =3D translate_wsr, - .test_ill =3D test_ill_wsr, - .par =3D (const uint32_t[]){EPS2 + 5}, + .test_ill =3D test_ill_hpi, + .par =3D (const uint32_t[]){ + EPS2 + 5, + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.exccause", .translate =3D translate_wsr, - .test_ill =3D test_ill_wsr, - .par =3D (const uint32_t[]){EXCCAUSE}, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + EXCCAUSE, + XTENSA_OPTION_EXCEPTION, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.excsave1", .translate =3D translate_wsr, - .test_ill =3D test_ill_wsr, - .par =3D (const uint32_t[]){EXCSAVE1}, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + EXCSAVE1, + XTENSA_OPTION_EXCEPTION, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.excsave2", .translate =3D translate_wsr, - .test_ill =3D test_ill_wsr, - .par =3D (const uint32_t[]){EXCSAVE1 + 1}, + .test_ill =3D test_ill_hpi, + .par =3D (const uint32_t[]){ + EXCSAVE1 + 1, + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.excsave3", .translate =3D translate_wsr, - .test_ill =3D test_ill_wsr, - .par =3D (const uint32_t[]){EXCSAVE1 + 2}, + .test_ill =3D test_ill_hpi, + .par =3D (const uint32_t[]){ + EXCSAVE1 + 2, + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.excsave4", .translate =3D translate_wsr, - .test_ill =3D test_ill_wsr, - .par =3D (const uint32_t[]){EXCSAVE1 + 3}, + .test_ill =3D test_ill_hpi, + .par =3D (const uint32_t[]){ + EXCSAVE1 + 3, + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.excsave5", .translate =3D translate_wsr, - .test_ill =3D test_ill_wsr, - .par =3D (const uint32_t[]){EXCSAVE1 + 4}, + .test_ill =3D test_ill_hpi, + .par =3D (const uint32_t[]){ + EXCSAVE1 + 4, + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.excsave6", .translate =3D translate_wsr, - .test_ill =3D test_ill_wsr, - .par =3D (const uint32_t[]){EXCSAVE1 + 5}, + .test_ill =3D test_ill_hpi, + .par =3D (const uint32_t[]){ + EXCSAVE1 + 5, + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.excsave7", .translate =3D translate_wsr, - .test_ill =3D test_ill_wsr, - .par =3D (const uint32_t[]){EXCSAVE1 + 6}, + .test_ill =3D test_ill_hpi, + .par =3D (const uint32_t[]){ + EXCSAVE1 + 6, + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.excvaddr", .translate =3D translate_wsr, - .test_ill =3D test_ill_wsr, - .par =3D (const uint32_t[]){EXCVADDR}, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + EXCVADDR, + XTENSA_OPTION_EXCEPTION, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.ibreaka0", - .translate =3D translate_wsr, - .test_ill =3D test_ill_wsr, - .par =3D (const uint32_t[]){IBREAKA}, + .translate =3D translate_wsr_ibreaka, + .test_ill =3D test_ill_ibreak, + .par =3D (const uint32_t[]){ + IBREAKA, + XTENSA_OPTION_DEBUG, + }, .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, }, { .name =3D "wsr.ibreaka1", - .translate =3D translate_wsr, - .test_ill =3D test_ill_wsr, - .par =3D (const uint32_t[]){IBREAKA + 1}, + .translate =3D translate_wsr_ibreaka, + .test_ill =3D test_ill_ibreak, + .par =3D (const uint32_t[]){ + IBREAKA + 1, + XTENSA_OPTION_DEBUG, + }, .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, }, { .name =3D "wsr.ibreakenable", - .translate =3D translate_wsr, - .test_ill =3D test_ill_wsr, - .par =3D (const uint32_t[]){IBREAKENABLE}, + .translate =3D translate_wsr_ibreakenable, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + IBREAKENABLE, + XTENSA_OPTION_DEBUG, + }, .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, }, { .name =3D "wsr.icount", - .translate =3D translate_wsr, - .test_ill =3D test_ill_wsr, - .par =3D (const uint32_t[]){ICOUNT}, + .translate =3D translate_wsr_icount, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + ICOUNT, + XTENSA_OPTION_DEBUG, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.icountlevel", - .translate =3D translate_wsr, - .test_ill =3D test_ill_wsr, - .par =3D (const uint32_t[]){ICOUNTLEVEL}, + .translate =3D translate_wsr_mask, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + ICOUNTLEVEL, + XTENSA_OPTION_DEBUG, + 0xf, + }, .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, }, { .name =3D "wsr.intclear", - .translate =3D translate_wsr, - .test_ill =3D test_ill_wsr, - .par =3D (const uint32_t[]){INTCLEAR}, + .translate =3D translate_wsr_intclear, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + INTCLEAR, + XTENSA_OPTION_INTERRUPT, + }, .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0 | @@ -4675,8 +4919,11 @@ static const XtensaOpcodeOps core_ops[] =3D { }, { .name =3D "wsr.intenable", .translate =3D translate_wsr, - .test_ill =3D test_ill_wsr, - .par =3D (const uint32_t[]){INTENABLE}, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + INTENABLE, + XTENSA_OPTION_INTERRUPT, + }, .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0 | @@ -4684,167 +4931,233 @@ static const XtensaOpcodeOps core_ops[] =3D { }, { .name =3D "wsr.interrupt", .translate =3D translate_wsr, - .test_ill =3D test_ill_wsr, - .par =3D (const uint32_t[]){INTSET}, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + INTSET, + XTENSA_OPTION_INTERRUPT, + }, .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0 | XTENSA_OP_CHECK_INTERRUPTS, }, { .name =3D "wsr.intset", - .translate =3D translate_wsr, - .test_ill =3D test_ill_wsr, - .par =3D (const uint32_t[]){INTSET}, + .translate =3D translate_wsr_intset, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + INTSET, + XTENSA_OPTION_INTERRUPT, + }, .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0 | XTENSA_OP_CHECK_INTERRUPTS, }, { .name =3D "wsr.itlbcfg", - .translate =3D translate_wsr, - .test_ill =3D test_ill_wsr, - .par =3D (const uint32_t[]){ITLBCFG}, + .translate =3D translate_wsr_mask, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + ITLBCFG, + XTENSA_OPTION_MMU, + 0x01130000, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.lbeg", .translate =3D translate_wsr, - .test_ill =3D test_ill_wsr, - .par =3D (const uint32_t[]){LBEG}, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + LBEG, + XTENSA_OPTION_LOOP, + }, .op_flags =3D XTENSA_OP_EXIT_TB_M1, }, { .name =3D "wsr.lcount", .translate =3D translate_wsr, - .test_ill =3D test_ill_wsr, - .par =3D (const uint32_t[]){LCOUNT}, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + LCOUNT, + XTENSA_OPTION_LOOP, + }, }, { .name =3D "wsr.lend", .translate =3D translate_wsr, - .test_ill =3D test_ill_wsr, - .par =3D (const uint32_t[]){LEND}, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + LEND, + XTENSA_OPTION_LOOP, + }, .op_flags =3D XTENSA_OP_EXIT_TB_M1, }, { .name =3D "wsr.litbase", - .translate =3D translate_wsr, - .test_ill =3D test_ill_wsr, - .par =3D (const uint32_t[]){LITBASE}, + .translate =3D translate_wsr_mask, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + LITBASE, + XTENSA_OPTION_EXTENDED_L32R, + 0xfffff001, + }, .op_flags =3D XTENSA_OP_EXIT_TB_M1, }, { .name =3D "wsr.m0", .translate =3D translate_wsr, - .test_ill =3D test_ill_wsr, - .par =3D (const uint32_t[]){MR}, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + MR, + XTENSA_OPTION_MAC16, + }, }, { .name =3D "wsr.m1", .translate =3D translate_wsr, - .test_ill =3D test_ill_wsr, - .par =3D (const uint32_t[]){MR + 1}, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + MR + 1, + XTENSA_OPTION_MAC16, + }, }, { .name =3D "wsr.m2", .translate =3D translate_wsr, - .test_ill =3D test_ill_wsr, - .par =3D (const uint32_t[]){MR + 2}, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + MR + 2, + XTENSA_OPTION_MAC16, + }, }, { .name =3D "wsr.m3", .translate =3D translate_wsr, - .test_ill =3D test_ill_wsr, - .par =3D (const uint32_t[]){MR + 3}, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + MR + 3, + XTENSA_OPTION_MAC16, + }, }, { .name =3D "wsr.memctl", - .translate =3D translate_wsr, - .test_ill =3D test_ill_wsr, + .translate =3D translate_wsr_memctl, .par =3D (const uint32_t[]){MEMCTL}, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.misc0", .translate =3D translate_wsr, - .test_ill =3D test_ill_wsr, - .par =3D (const uint32_t[]){MISC}, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + MISC, + XTENSA_OPTION_MISC_SR, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.misc1", .translate =3D translate_wsr, - .test_ill =3D test_ill_wsr, - .par =3D (const uint32_t[]){MISC + 1}, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + MISC + 1, + XTENSA_OPTION_MISC_SR, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.misc2", .translate =3D translate_wsr, - .test_ill =3D test_ill_wsr, - .par =3D (const uint32_t[]){MISC + 2}, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + MISC + 2, + XTENSA_OPTION_MISC_SR, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.misc3", .translate =3D translate_wsr, - .test_ill =3D test_ill_wsr, - .par =3D (const uint32_t[]){MISC + 3}, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + MISC + 3, + XTENSA_OPTION_MISC_SR, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.mmid", .translate =3D translate_wsr, - .test_ill =3D test_ill_wsr, - .par =3D (const uint32_t[]){MMID}, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + MMID, + XTENSA_OPTION_TRACE_PORT, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.prefctl", .translate =3D translate_wsr, - .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){PREFCTL}, }, { .name =3D "wsr.prid", - .translate =3D translate_wsr, - .test_ill =3D test_ill_wsr, - .par =3D (const uint32_t[]){PRID}, - .op_flags =3D XTENSA_OP_PRIVILEGED, + .op_flags =3D XTENSA_OP_ILL, }, { .name =3D "wsr.ps", - .translate =3D translate_wsr, - .test_ill =3D test_ill_wsr, - .par =3D (const uint32_t[]){PS}, + .translate =3D translate_wsr_ps, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + PS, + XTENSA_OPTION_EXCEPTION, + }, .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1 | XTENSA_OP_CHECK_INTERRUPTS, }, { .name =3D "wsr.ptevaddr", - .translate =3D translate_wsr, - .test_ill =3D test_ill_wsr, - .par =3D (const uint32_t[]){PTEVADDR}, + .translate =3D translate_wsr_mask, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + PTEVADDR, + XTENSA_OPTION_MMU, + 0xffc00000, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.rasid", - .translate =3D translate_wsr, - .test_ill =3D test_ill_wsr, - .par =3D (const uint32_t[]){RASID}, + .translate =3D translate_wsr_rasid, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + RASID, + XTENSA_OPTION_MMU, + }, .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, }, { .name =3D "wsr.sar", - .translate =3D translate_wsr, - .test_ill =3D test_ill_wsr, + .translate =3D translate_wsr_sar, .par =3D (const uint32_t[]){SAR}, }, { .name =3D "wsr.scompare1", .translate =3D translate_wsr, - .test_ill =3D test_ill_wsr, - .par =3D (const uint32_t[]){SCOMPARE1}, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + SCOMPARE1, + XTENSA_OPTION_CONDITIONAL_STORE, + }, }, { .name =3D "wsr.vecbase", .translate =3D translate_wsr, - .test_ill =3D test_ill_wsr, - .par =3D (const uint32_t[]){VECBASE}, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + VECBASE, + XTENSA_OPTION_RELOCATABLE_VECTOR, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.windowbase", - .translate =3D translate_wsr, - .test_ill =3D test_ill_wsr, - .par =3D (const uint32_t[]){WINDOW_BASE}, + .translate =3D translate_wsr_windowbase, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + WINDOW_BASE, + XTENSA_OPTION_WINDOWED_REGISTER, + }, .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1 | XTENSA_OP_SYNC_REGISTER_WINDOW, }, { .name =3D "wsr.windowstart", - .translate =3D translate_wsr, - .test_ill =3D test_ill_wsr, - .par =3D (const uint32_t[]){WINDOW_START}, + .translate =3D translate_wsr_windowstart, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + WINDOW_START, + XTENSA_OPTION_WINDOWED_REGISTER, + }, .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, }, { .name =3D "wur.expstate", @@ -4852,12 +5165,12 @@ static const XtensaOpcodeOps core_ops[] =3D { .par =3D (const uint32_t[]){EXPSTATE}, }, { .name =3D "wur.fcr", - .translate =3D translate_wur, + .translate =3D translate_wur_fcr, .par =3D (const uint32_t[]){FCR}, .coprocessor =3D 0x1, }, { .name =3D "wur.fsr", - .translate =3D translate_wur, + .translate =3D translate_wur_fsr, .par =3D (const uint32_t[]){FSR}, .coprocessor =3D 0x1, }, { @@ -4873,471 +5186,635 @@ static const XtensaOpcodeOps core_ops[] =3D { .par =3D (const uint32_t[]){BOOLEAN_XOR}, }, { .name =3D "xsr.176", - .translate =3D translate_xsr, - .test_ill =3D test_ill_xsr, - .par =3D (const uint32_t[]){176}, - .op_flags =3D XTENSA_OP_PRIVILEGED, + .op_flags =3D XTENSA_OP_ILL, }, { .name =3D "xsr.208", - .translate =3D translate_xsr, - .test_ill =3D test_ill_xsr, - .par =3D (const uint32_t[]){208}, - .op_flags =3D XTENSA_OP_PRIVILEGED, + .op_flags =3D XTENSA_OP_ILL, }, { .name =3D "xsr.acchi", - .translate =3D translate_xsr, - .test_ill =3D test_ill_xsr, - .par =3D (const uint32_t[]){ACCHI}, + .translate =3D translate_xsr_acchi, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + ACCHI, + XTENSA_OPTION_MAC16, + }, }, { .name =3D "xsr.acclo", .translate =3D translate_xsr, - .test_ill =3D test_ill_xsr, - .par =3D (const uint32_t[]){ACCLO}, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + ACCLO, + XTENSA_OPTION_MAC16, + }, }, { .name =3D "xsr.atomctl", - .translate =3D translate_xsr, - .test_ill =3D test_ill_xsr, - .par =3D (const uint32_t[]){ATOMCTL}, + .translate =3D translate_xsr_mask, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + ATOMCTL, + XTENSA_OPTION_ATOMCTL, + 0x3f, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.br", - .translate =3D translate_xsr, - .test_ill =3D test_ill_xsr, - .par =3D (const uint32_t[]){BR}, + .translate =3D translate_xsr_mask, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + BR, + XTENSA_OPTION_BOOLEAN, + 0xffff, + }, }, { .name =3D "xsr.cacheattr", .translate =3D translate_xsr, - .test_ill =3D test_ill_xsr, - .par =3D (const uint32_t[]){CACHEATTR}, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + CACHEATTR, + XTENSA_OPTION_CACHEATTR, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.ccompare0", - .translate =3D translate_xsr, - .test_ill =3D test_ill_xsr, - .par =3D (const uint32_t[]){CCOMPARE}, + .translate =3D translate_xsr_ccompare, + .test_ill =3D test_ill_ccompare, + .par =3D (const uint32_t[]){ + CCOMPARE, + XTENSA_OPTION_TIMER_INTERRUPT, + }, .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, }, { .name =3D "xsr.ccompare1", - .translate =3D translate_xsr, - .test_ill =3D test_ill_xsr, - .par =3D (const uint32_t[]){CCOMPARE + 1}, + .translate =3D translate_xsr_ccompare, + .test_ill =3D test_ill_ccompare, + .par =3D (const uint32_t[]){ + CCOMPARE + 1, + XTENSA_OPTION_TIMER_INTERRUPT, + }, .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, }, { .name =3D "xsr.ccompare2", - .translate =3D translate_xsr, - .test_ill =3D test_ill_xsr, - .par =3D (const uint32_t[]){CCOMPARE + 2}, + .translate =3D translate_xsr_ccompare, + .test_ill =3D test_ill_ccompare, + .par =3D (const uint32_t[]){ + CCOMPARE + 2, + XTENSA_OPTION_TIMER_INTERRUPT, + }, .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, }, { .name =3D "xsr.ccount", - .translate =3D translate_xsr, - .test_ill =3D test_ill_xsr, - .par =3D (const uint32_t[]){CCOUNT}, + .translate =3D translate_xsr_ccount, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + CCOUNT, + XTENSA_OPTION_TIMER_INTERRUPT, + }, .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, }, { .name =3D "xsr.configid0", - .translate =3D translate_xsr, - .test_ill =3D test_ill_xsr, - .par =3D (const uint32_t[]){CONFIGID0}, - .op_flags =3D XTENSA_OP_PRIVILEGED, + .op_flags =3D XTENSA_OP_ILL, }, { .name =3D "xsr.configid1", - .translate =3D translate_xsr, - .test_ill =3D test_ill_xsr, - .par =3D (const uint32_t[]){CONFIGID1}, - .op_flags =3D XTENSA_OP_PRIVILEGED, + .op_flags =3D XTENSA_OP_ILL, }, { .name =3D "xsr.cpenable", - .translate =3D translate_xsr, - .test_ill =3D test_ill_xsr, - .par =3D (const uint32_t[]){CPENABLE}, + .translate =3D translate_xsr_mask, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + CPENABLE, + XTENSA_OPTION_COPROCESSOR, + 0xff, + }, .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, }, { .name =3D "xsr.dbreaka0", - .translate =3D translate_xsr, - .test_ill =3D test_ill_xsr, - .par =3D (const uint32_t[]){DBREAKA}, + .translate =3D translate_xsr_dbreaka, + .test_ill =3D test_ill_dbreak, + .par =3D (const uint32_t[]){ + DBREAKA, + XTENSA_OPTION_DEBUG, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.dbreaka1", - .translate =3D translate_xsr, - .test_ill =3D test_ill_xsr, - .par =3D (const uint32_t[]){DBREAKA + 1}, + .translate =3D translate_xsr_dbreaka, + .test_ill =3D test_ill_dbreak, + .par =3D (const uint32_t[]){ + DBREAKA + 1, + XTENSA_OPTION_DEBUG, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.dbreakc0", - .translate =3D translate_xsr, - .test_ill =3D test_ill_xsr, - .par =3D (const uint32_t[]){DBREAKC}, + .translate =3D translate_xsr_dbreakc, + .test_ill =3D test_ill_dbreak, + .par =3D (const uint32_t[]){ + DBREAKC, + XTENSA_OPTION_DEBUG, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.dbreakc1", - .translate =3D translate_xsr, - .test_ill =3D test_ill_xsr, - .par =3D (const uint32_t[]){DBREAKC + 1}, + .translate =3D translate_xsr_dbreakc, + .test_ill =3D test_ill_dbreak, + .par =3D (const uint32_t[]){ + DBREAKC + 1, + XTENSA_OPTION_DEBUG, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.ddr", .translate =3D translate_xsr, - .test_ill =3D test_ill_xsr, - .par =3D (const uint32_t[]){DDR}, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + DDR, + XTENSA_OPTION_DEBUG, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.debugcause", - .translate =3D translate_xsr, - .test_ill =3D test_ill_xsr, - .par =3D (const uint32_t[]){DEBUGCAUSE}, - .op_flags =3D XTENSA_OP_PRIVILEGED, + .op_flags =3D XTENSA_OP_ILL, }, { .name =3D "xsr.depc", .translate =3D translate_xsr, - .test_ill =3D test_ill_xsr, - .par =3D (const uint32_t[]){DEPC}, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + DEPC, + XTENSA_OPTION_EXCEPTION, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.dtlbcfg", - .translate =3D translate_xsr, - .test_ill =3D test_ill_xsr, - .par =3D (const uint32_t[]){DTLBCFG}, + .translate =3D translate_xsr_mask, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + DTLBCFG, + XTENSA_OPTION_MMU, + 0x01130000, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.epc1", .translate =3D translate_xsr, - .test_ill =3D test_ill_xsr, - .par =3D (const uint32_t[]){EPC1}, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + EPC1, + XTENSA_OPTION_EXCEPTION, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.epc2", .translate =3D translate_xsr, - .test_ill =3D test_ill_xsr, - .par =3D (const uint32_t[]){EPC1 + 1}, + .test_ill =3D test_ill_hpi, + .par =3D (const uint32_t[]){ + EPC1 + 1, + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.epc3", .translate =3D translate_xsr, - .test_ill =3D test_ill_xsr, - .par =3D (const uint32_t[]){EPC1 + 2}, + .test_ill =3D test_ill_hpi, + .par =3D (const uint32_t[]){ + EPC1 + 2, + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.epc4", .translate =3D translate_xsr, - .test_ill =3D test_ill_xsr, - .par =3D (const uint32_t[]){EPC1 + 3}, + .test_ill =3D test_ill_hpi, + .par =3D (const uint32_t[]){ + EPC1 + 3, + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.epc5", .translate =3D translate_xsr, - .test_ill =3D test_ill_xsr, - .par =3D (const uint32_t[]){EPC1 + 4}, + .test_ill =3D test_ill_hpi, + .par =3D (const uint32_t[]){ + EPC1 + 4, + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.epc6", .translate =3D translate_xsr, - .test_ill =3D test_ill_xsr, - .par =3D (const uint32_t[]){EPC1 + 5}, + .test_ill =3D test_ill_hpi, + .par =3D (const uint32_t[]){ + EPC1 + 5, + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.epc7", .translate =3D translate_xsr, - .test_ill =3D test_ill_xsr, - .par =3D (const uint32_t[]){EPC1 + 6}, + .test_ill =3D test_ill_hpi, + .par =3D (const uint32_t[]){ + EPC1 + 6, + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.eps2", .translate =3D translate_xsr, - .test_ill =3D test_ill_xsr, - .par =3D (const uint32_t[]){EPS2}, + .test_ill =3D test_ill_hpi, + .par =3D (const uint32_t[]){ + EPS2, + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.eps3", .translate =3D translate_xsr, - .test_ill =3D test_ill_xsr, - .par =3D (const uint32_t[]){EPS2 + 1}, + .test_ill =3D test_ill_hpi, + .par =3D (const uint32_t[]){ + EPS2 + 1, + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.eps4", .translate =3D translate_xsr, - .test_ill =3D test_ill_xsr, - .par =3D (const uint32_t[]){EPS2 + 2}, + .test_ill =3D test_ill_hpi, + .par =3D (const uint32_t[]){ + EPS2 + 2, + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.eps5", .translate =3D translate_xsr, - .test_ill =3D test_ill_xsr, - .par =3D (const uint32_t[]){EPS2 + 3}, + .test_ill =3D test_ill_hpi, + .par =3D (const uint32_t[]){ + EPS2 + 3, + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.eps6", .translate =3D translate_xsr, - .test_ill =3D test_ill_xsr, - .par =3D (const uint32_t[]){EPS2 + 4}, + .test_ill =3D test_ill_hpi, + .par =3D (const uint32_t[]){ + EPS2 + 4, + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.eps7", .translate =3D translate_xsr, - .test_ill =3D test_ill_xsr, - .par =3D (const uint32_t[]){EPS2 + 5}, + .test_ill =3D test_ill_hpi, + .par =3D (const uint32_t[]){ + EPS2 + 5, + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.exccause", .translate =3D translate_xsr, - .test_ill =3D test_ill_xsr, - .par =3D (const uint32_t[]){EXCCAUSE}, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + EXCCAUSE, + XTENSA_OPTION_EXCEPTION, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.excsave1", .translate =3D translate_xsr, - .test_ill =3D test_ill_xsr, - .par =3D (const uint32_t[]){EXCSAVE1}, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + EXCSAVE1, + XTENSA_OPTION_EXCEPTION, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.excsave2", .translate =3D translate_xsr, - .test_ill =3D test_ill_xsr, - .par =3D (const uint32_t[]){EXCSAVE1 + 1}, + .test_ill =3D test_ill_hpi, + .par =3D (const uint32_t[]){ + EXCSAVE1 + 1, + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.excsave3", .translate =3D translate_xsr, - .test_ill =3D test_ill_xsr, - .par =3D (const uint32_t[]){EXCSAVE1 + 2}, + .test_ill =3D test_ill_hpi, + .par =3D (const uint32_t[]){ + EXCSAVE1 + 2, + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.excsave4", .translate =3D translate_xsr, - .test_ill =3D test_ill_xsr, - .par =3D (const uint32_t[]){EXCSAVE1 + 3}, + .test_ill =3D test_ill_hpi, + .par =3D (const uint32_t[]){ + EXCSAVE1 + 3, + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.excsave5", .translate =3D translate_xsr, - .test_ill =3D test_ill_xsr, - .par =3D (const uint32_t[]){EXCSAVE1 + 4}, + .test_ill =3D test_ill_hpi, + .par =3D (const uint32_t[]){ + EXCSAVE1 + 4, + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.excsave6", .translate =3D translate_xsr, - .test_ill =3D test_ill_xsr, - .par =3D (const uint32_t[]){EXCSAVE1 + 5}, + .test_ill =3D test_ill_hpi, + .par =3D (const uint32_t[]){ + EXCSAVE1 + 5, + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.excsave7", .translate =3D translate_xsr, - .test_ill =3D test_ill_xsr, - .par =3D (const uint32_t[]){EXCSAVE1 + 6}, + .test_ill =3D test_ill_hpi, + .par =3D (const uint32_t[]){ + EXCSAVE1 + 6, + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.excvaddr", .translate =3D translate_xsr, - .test_ill =3D test_ill_xsr, - .par =3D (const uint32_t[]){EXCVADDR}, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + EXCVADDR, + XTENSA_OPTION_EXCEPTION, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.ibreaka0", - .translate =3D translate_xsr, - .test_ill =3D test_ill_xsr, - .par =3D (const uint32_t[]){IBREAKA}, + .translate =3D translate_xsr_ibreaka, + .test_ill =3D test_ill_ibreak, + .par =3D (const uint32_t[]){ + IBREAKA, + XTENSA_OPTION_DEBUG, + }, .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, }, { .name =3D "xsr.ibreaka1", - .translate =3D translate_xsr, - .test_ill =3D test_ill_xsr, - .par =3D (const uint32_t[]){IBREAKA + 1}, + .translate =3D translate_xsr_ibreaka, + .test_ill =3D test_ill_ibreak, + .par =3D (const uint32_t[]){ + IBREAKA + 1, + XTENSA_OPTION_DEBUG, + }, .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, }, { .name =3D "xsr.ibreakenable", - .translate =3D translate_xsr, - .test_ill =3D test_ill_xsr, - .par =3D (const uint32_t[]){IBREAKENABLE}, + .translate =3D translate_xsr_ibreakenable, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + IBREAKENABLE, + XTENSA_OPTION_DEBUG, + }, .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, }, { .name =3D "xsr.icount", - .translate =3D translate_xsr, - .test_ill =3D test_ill_xsr, - .par =3D (const uint32_t[]){ICOUNT}, + .translate =3D translate_xsr_icount, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + ICOUNT, + XTENSA_OPTION_DEBUG, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.icountlevel", - .translate =3D translate_xsr, - .test_ill =3D test_ill_xsr, - .par =3D (const uint32_t[]){ICOUNTLEVEL}, + .translate =3D translate_xsr_mask, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + ICOUNTLEVEL, + XTENSA_OPTION_DEBUG, + 0xf, + }, .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, }, { .name =3D "xsr.intclear", - .translate =3D translate_xsr, - .test_ill =3D test_ill_xsr, - .par =3D (const uint32_t[]){INTCLEAR}, - .op_flags =3D - XTENSA_OP_PRIVILEGED | - XTENSA_OP_EXIT_TB_0 | - XTENSA_OP_CHECK_INTERRUPTS, + .op_flags =3D XTENSA_OP_ILL, }, { .name =3D "xsr.intenable", .translate =3D translate_xsr, - .test_ill =3D test_ill_xsr, - .par =3D (const uint32_t[]){INTENABLE}, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + INTENABLE, + XTENSA_OPTION_INTERRUPT, + }, .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0 | XTENSA_OP_CHECK_INTERRUPTS, }, { .name =3D "xsr.interrupt", - .translate =3D translate_xsr, - .test_ill =3D test_ill_xsr, - .par =3D (const uint32_t[]){INTSET}, - .op_flags =3D - XTENSA_OP_PRIVILEGED | - XTENSA_OP_EXIT_TB_0 | - XTENSA_OP_CHECK_INTERRUPTS, + .op_flags =3D XTENSA_OP_ILL, }, { .name =3D "xsr.intset", - .translate =3D translate_xsr, - .test_ill =3D test_ill_xsr, - .par =3D (const uint32_t[]){INTSET}, - .op_flags =3D - XTENSA_OP_PRIVILEGED | - XTENSA_OP_EXIT_TB_0 | - XTENSA_OP_CHECK_INTERRUPTS, + .op_flags =3D XTENSA_OP_ILL, }, { .name =3D "xsr.itlbcfg", - .translate =3D translate_xsr, - .test_ill =3D test_ill_xsr, - .par =3D (const uint32_t[]){ITLBCFG}, + .translate =3D translate_xsr_mask, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + ITLBCFG, + XTENSA_OPTION_MMU, + 0x01130000, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.lbeg", .translate =3D translate_xsr, - .test_ill =3D test_ill_xsr, - .par =3D (const uint32_t[]){LBEG}, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + LBEG, + XTENSA_OPTION_LOOP, + }, .op_flags =3D XTENSA_OP_EXIT_TB_M1, }, { .name =3D "xsr.lcount", .translate =3D translate_xsr, - .test_ill =3D test_ill_xsr, - .par =3D (const uint32_t[]){LCOUNT}, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + LCOUNT, + XTENSA_OPTION_LOOP, + }, }, { .name =3D "xsr.lend", .translate =3D translate_xsr, - .test_ill =3D test_ill_xsr, - .par =3D (const uint32_t[]){LEND}, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + LEND, + XTENSA_OPTION_LOOP, + }, .op_flags =3D XTENSA_OP_EXIT_TB_M1, }, { .name =3D "xsr.litbase", - .translate =3D translate_xsr, - .test_ill =3D test_ill_xsr, - .par =3D (const uint32_t[]){LITBASE}, + .translate =3D translate_xsr_mask, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + LITBASE, + XTENSA_OPTION_EXTENDED_L32R, + 0xfffff001, + }, .op_flags =3D XTENSA_OP_EXIT_TB_M1, }, { .name =3D "xsr.m0", .translate =3D translate_xsr, - .test_ill =3D test_ill_xsr, - .par =3D (const uint32_t[]){MR}, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + MR, + XTENSA_OPTION_MAC16, + }, }, { .name =3D "xsr.m1", .translate =3D translate_xsr, - .test_ill =3D test_ill_xsr, - .par =3D (const uint32_t[]){MR + 1}, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + MR + 1, + XTENSA_OPTION_MAC16, + }, }, { .name =3D "xsr.m2", .translate =3D translate_xsr, - .test_ill =3D test_ill_xsr, - .par =3D (const uint32_t[]){MR + 2}, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + MR + 2, + XTENSA_OPTION_MAC16, + }, }, { .name =3D "xsr.m3", .translate =3D translate_xsr, - .test_ill =3D test_ill_xsr, - .par =3D (const uint32_t[]){MR + 3}, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + MR + 3, + XTENSA_OPTION_MAC16, + }, }, { .name =3D "xsr.memctl", - .translate =3D translate_xsr, - .test_ill =3D test_ill_xsr, + .translate =3D translate_xsr_memctl, .par =3D (const uint32_t[]){MEMCTL}, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.misc0", .translate =3D translate_xsr, - .test_ill =3D test_ill_xsr, - .par =3D (const uint32_t[]){MISC}, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + MISC, + XTENSA_OPTION_MISC_SR, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.misc1", .translate =3D translate_xsr, - .test_ill =3D test_ill_xsr, - .par =3D (const uint32_t[]){MISC + 1}, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + MISC + 1, + XTENSA_OPTION_MISC_SR, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.misc2", .translate =3D translate_xsr, - .test_ill =3D test_ill_xsr, - .par =3D (const uint32_t[]){MISC + 2}, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + MISC + 2, + XTENSA_OPTION_MISC_SR, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.misc3", .translate =3D translate_xsr, - .test_ill =3D test_ill_xsr, - .par =3D (const uint32_t[]){MISC + 3}, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + MISC + 3, + XTENSA_OPTION_MISC_SR, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.prefctl", .translate =3D translate_xsr, - .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){PREFCTL}, }, { .name =3D "xsr.prid", - .translate =3D translate_xsr, - .test_ill =3D test_ill_xsr, - .par =3D (const uint32_t[]){PRID}, - .op_flags =3D XTENSA_OP_PRIVILEGED, + .op_flags =3D XTENSA_OP_ILL, }, { .name =3D "xsr.ps", - .translate =3D translate_xsr, - .test_ill =3D test_ill_xsr, - .par =3D (const uint32_t[]){PS}, + .translate =3D translate_xsr_ps, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + PS, + XTENSA_OPTION_EXCEPTION, + }, .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1 | XTENSA_OP_CHECK_INTERRUPTS, }, { .name =3D "xsr.ptevaddr", - .translate =3D translate_xsr, - .test_ill =3D test_ill_xsr, - .par =3D (const uint32_t[]){PTEVADDR}, + .translate =3D translate_xsr_mask, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + PTEVADDR, + XTENSA_OPTION_MMU, + 0xffc00000, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.rasid", - .translate =3D translate_xsr, - .test_ill =3D test_ill_xsr, - .par =3D (const uint32_t[]){RASID}, + .translate =3D translate_xsr_rasid, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + RASID, + XTENSA_OPTION_MMU, + }, .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, }, { .name =3D "xsr.sar", - .translate =3D translate_xsr, - .test_ill =3D test_ill_xsr, + .translate =3D translate_xsr_sar, .par =3D (const uint32_t[]){SAR}, }, { .name =3D "xsr.scompare1", .translate =3D translate_xsr, - .test_ill =3D test_ill_xsr, - .par =3D (const uint32_t[]){SCOMPARE1}, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + SCOMPARE1, + XTENSA_OPTION_CONDITIONAL_STORE, + }, }, { .name =3D "xsr.vecbase", .translate =3D translate_xsr, - .test_ill =3D test_ill_xsr, - .par =3D (const uint32_t[]){VECBASE}, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + VECBASE, + XTENSA_OPTION_RELOCATABLE_VECTOR, + }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.windowbase", - .translate =3D translate_xsr, - .test_ill =3D test_ill_xsr, - .par =3D (const uint32_t[]){WINDOW_BASE}, + .translate =3D translate_xsr_windowbase, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + WINDOW_BASE, + XTENSA_OPTION_WINDOWED_REGISTER, + }, .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1 | XTENSA_OP_SYNC_REGISTER_WINDOW, }, { .name =3D "xsr.windowstart", - .translate =3D translate_xsr, - .test_ill =3D test_ill_xsr, - .par =3D (const uint32_t[]){WINDOW_START}, + .translate =3D translate_xsr_windowstart, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + WINDOW_START, + XTENSA_OPTION_WINDOWED_REGISTER, + }, .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, }, }; --=20 2.11.0 From nobody Thu Apr 25 07:57:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1557868178; cv=none; d=zoho.com; s=zohoarc; b=NtWWXJVZjpJ/0dU7wU3+lEP/nGWbRm3DC3YgcD7Esbnet/xCQbZFmRA0tQYVBU1YNVDLA+67cCLiJGI4YvCYlQ+bGtNGH3Lua66Y6Zno3M2JLdLZQ6RIay4rtewgauba9YQ+iQMZ3p7uK4YQh3VlsbAJZKiKEBcBpXFXFcMpzbw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1557868178; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=ycNp4Qh4WZ1+j69cmldUs9hpgiZ5r/F5FvZ4/Ss2hCM=; b=Vr82xDZ9YOmD3P5WwCJp/6YQ17f3WdtNP9pnI8QcFJZM4EpFaYyFTgbouOvSO3OcHc+R5n8dMesGRi1kLESbSMF2zkMF8ZrrPfDIddg75g5RPFtEWWM0wf2wybZ3l6oWsNOwrn6lURyZac+dSTdLOYDkn49xF0/3Ne2Eb8yPqSo= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1557868178506413.3063684161077; Tue, 14 May 2019 14:09:38 -0700 (PDT) Received: from localhost ([127.0.0.1]:54240 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hQeg3-0007dS-Ex for importer@patchew.org; Tue, 14 May 2019 17:09:35 -0400 Received: from eggs.gnu.org ([209.51.188.92]:39003) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hQeV6-0007lu-8f for qemu-devel@nongnu.org; Tue, 14 May 2019 16:58:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hQeIU-0007C3-Lr for qemu-devel@nongnu.org; Tue, 14 May 2019 16:45:16 -0400 Received: from mail-lf1-x141.google.com ([2a00:1450:4864:20::141]:37183) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hQeIT-00077c-Qe for qemu-devel@nongnu.org; Tue, 14 May 2019 16:45:14 -0400 Received: by mail-lf1-x141.google.com with SMTP id q17so251535lfo.4 for ; Tue, 14 May 2019 13:45:13 -0700 (PDT) Received: from octofox.cadence.com (jcmvbkbc-1-pt.tunnel.tserv24.sto1.ipv6.he.net. [2001:470:27:1fa::2]) by smtp.gmail.com with ESMTPSA id 78sm4011lje.81.2019.05.14.13.45.10 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 14 May 2019 13:45:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ycNp4Qh4WZ1+j69cmldUs9hpgiZ5r/F5FvZ4/Ss2hCM=; b=o1shyKB/PSjAxK/khrCuiBCvnQ+Q07IfIRGdM2I157kuQc/FIqb/GECI+SqOs5i34+ z6/IjVSpM7V3JIU+F7sbY0ITvbK9VkLI8KLDcmZ4h9ymb/Z+OSn0vVTK4zja9nrIvVE2 nyQ7uGyuxPwmNB205O6Xpfs6JQJICV5cZgpf+B7f0IN+02V7xulJeV4FDK9sy7lqVoSA PLwtt4hUYXyvBF7Ea6FRPp8rNYlPNwMdZKqh7pyobq/zxg2uIlObR0Azibh5zTT0oVSK uPG2v+Z6fTI8mqkwPSht+SDm6pyDjMKQk5dzrRLdgWAPVZnNwKq7oYgXLgnXW/fpR6NF 8F4w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ycNp4Qh4WZ1+j69cmldUs9hpgiZ5r/F5FvZ4/Ss2hCM=; b=H31CpmbUe+2LHrWR+eZ15B0dQq50j54JJClH3u1OW6T32FCO229n59vPacDCqzNeu7 Lry7jBpFTQw6tVkdCGuJNWCJAfmgzEkP1kwjem+CtkCfLprDF2RtoPMwQd5K9NJPpS0E TyFSY/jiPl2Tg+DHZJK6sa7AN2o6a9p4wdxu5ZGdyDxfrullBHPlgqoYS1xk/315jyhC 6/9CBSrE32RWN5TPeweI/htxAU6tXYgyKKWFOIBSG9m9pOGJvrZEJHaFpQSeFZ8ePcwM uwAPonkMLzOFE69o+aX9EfG5P7smrv6GK++E9vP+tMVvAghhHDAGFfuf1RmKKoKoEdJv 9EWQ== X-Gm-Message-State: APjAAAVquDJx+5U92EdN+DU/MMh59yr00Yx125cfXAWuHMINbAh6cUIw ZimF1frsQ78wBLIlzb3PkQ8X8m68F0k= X-Google-Smtp-Source: APXvYqxJmI6GVxhxlvhdtaFr1cLuhsF4iHzYRBsPb/X0iIV+xbqS7qSzYqLDbFyI7kVbHnq3+xKTsQ== X-Received: by 2002:a19:5015:: with SMTP id e21mr18606306lfb.62.1557866712257; Tue, 14 May 2019 13:45:12 -0700 (PDT) From: Max Filippov To: qemu-devel@nongnu.org Date: Tue, 14 May 2019 13:44:40 -0700 Message-Id: <20190514204447.17486-3-jcmvbkbc@gmail.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190514204447.17486-1-jcmvbkbc@gmail.com> References: <20190514204447.17486-1-jcmvbkbc@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::141 Subject: [Qemu-devel] [PATCH 2/9] target/xtensa: make internal MMU functions static X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Max Filippov Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Remove declarations of the internal mmu_helper functions from the cpu.h, make these functions static and shuffle them. Signed-off-by: Max Filippov --- target/xtensa/cpu.h | 19 ------ target/xtensa/mmu_helper.c | 163 ++++++++++++++++++++++++-----------------= ---- 2 files changed, 87 insertions(+), 95 deletions(-) diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 539033fccb61..502d41688365 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -658,17 +658,6 @@ static inline int xtensa_get_cring(const CPUXtensaStat= e *env) } =20 #ifndef CONFIG_USER_ONLY -uint32_t xtensa_tlb_get_addr_mask(const CPUXtensaState *env, - bool dtlb, uint32_t way); -void split_tlb_entry_spec_way(const CPUXtensaState *env, uint32_t v, bool = dtlb, - uint32_t *vpn, uint32_t wi, uint32_t *ei); -int xtensa_tlb_lookup(const CPUXtensaState *env, uint32_t addr, bool dtlb, - uint32_t *pwi, uint32_t *pei, uint8_t *pring); -void xtensa_tlb_set_entry_mmu(const CPUXtensaState *env, - xtensa_tlb_entry *entry, bool dtlb, - unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte); -void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb, - unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte); int xtensa_get_physical_addr(CPUXtensaState *env, bool update_tlb, uint32_t vaddr, int is_write, int mmu_idx, uint32_t *paddr, uint32_t *page_size, unsigned *access); @@ -679,14 +668,6 @@ static inline MemoryRegion *xtensa_get_er_region(CPUXt= ensaState *env) { return env->system_er; } - -static inline xtensa_tlb_entry *xtensa_tlb_get_entry(CPUXtensaState *env, - bool dtlb, unsigned wi, unsigned ei) -{ - return dtlb ? - env->dtlb[wi] + ei : - env->itlb[wi] + ei; -} #endif =20 static inline uint32_t xtensa_replicate_windowstart(CPUXtensaState *env) diff --git a/target/xtensa/mmu_helper.c b/target/xtensa/mmu_helper.c index 79a10da2310e..465cfbf61359 100644 --- a/target/xtensa/mmu_helper.c +++ b/target/xtensa/mmu_helper.c @@ -78,8 +78,8 @@ static uint32_t get_page_size(const CPUXtensaState *env, /*! * Get bit mask for the virtual address bits translated by the TLB way */ -uint32_t xtensa_tlb_get_addr_mask(const CPUXtensaState *env, - bool dtlb, uint32_t way) +static uint32_t xtensa_tlb_get_addr_mask(const CPUXtensaState *env, + bool dtlb, uint32_t way) { if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { bool varway56 =3D dtlb ? @@ -145,8 +145,9 @@ static uint32_t get_vpn_mask(const CPUXtensaState *env,= bool dtlb, uint32_t way) * Split virtual address into VPN (with index) and entry index * for the given TLB way */ -void split_tlb_entry_spec_way(const CPUXtensaState *env, uint32_t v, bool = dtlb, - uint32_t *vpn, uint32_t wi, uint32_t *ei) +static void split_tlb_entry_spec_way(const CPUXtensaState *env, uint32_t v, + bool dtlb, uint32_t *vpn, + uint32_t wi, uint32_t *ei) { bool varway56 =3D dtlb ? env->config->dtlb.varway56 : @@ -213,6 +214,14 @@ static void split_tlb_entry_spec(CPUXtensaState *env, = uint32_t v, bool dtlb, } } =20 +static xtensa_tlb_entry *xtensa_tlb_get_entry(CPUXtensaState *env, bool dt= lb, + unsigned wi, unsigned ei) +{ + return dtlb ? + env->dtlb[wi] + ei : + env->itlb[wi] + ei; +} + static xtensa_tlb_entry *get_tlb_entry(CPUXtensaState *env, uint32_t v, bool dtlb, uint32_t *pwi) { @@ -227,65 +236,10 @@ static xtensa_tlb_entry *get_tlb_entry(CPUXtensaState= *env, return xtensa_tlb_get_entry(env, dtlb, wi, ei); } =20 -uint32_t HELPER(rtlb0)(CPUXtensaState *env, uint32_t v, uint32_t dtlb) -{ - if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { - uint32_t wi; - const xtensa_tlb_entry *entry =3D get_tlb_entry(env, v, dtlb, &wi); - return (entry->vaddr & get_vpn_mask(env, dtlb, wi)) | entry->asid; - } else { - return v & REGION_PAGE_MASK; - } -} - -uint32_t HELPER(rtlb1)(CPUXtensaState *env, uint32_t v, uint32_t dtlb) -{ - const xtensa_tlb_entry *entry =3D get_tlb_entry(env, v, dtlb, NULL); - return entry->paddr | entry->attr; -} - -void HELPER(itlb)(CPUXtensaState *env, uint32_t v, uint32_t dtlb) -{ - if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { - uint32_t wi; - xtensa_tlb_entry *entry =3D get_tlb_entry(env, v, dtlb, &wi); - if (entry->variable && entry->asid) { - tlb_flush_page(CPU(xtensa_env_get_cpu(env)), entry->vaddr); - entry->asid =3D 0; - } - } -} - -uint32_t HELPER(ptlb)(CPUXtensaState *env, uint32_t v, uint32_t dtlb) -{ - if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { - uint32_t wi; - uint32_t ei; - uint8_t ring; - int res =3D xtensa_tlb_lookup(env, v, dtlb, &wi, &ei, &ring); - - switch (res) { - case 0: - if (ring >=3D xtensa_get_ring(env)) { - return (v & 0xfffff000) | wi | (dtlb ? 0x10 : 0x8); - } - break; - - case INST_TLB_MULTI_HIT_CAUSE: - case LOAD_STORE_TLB_MULTI_HIT_CAUSE: - HELPER(exception_cause_vaddr)(env, env->pc, res, v); - break; - } - return 0; - } else { - return (v & REGION_PAGE_MASK) | 0x1; - } -} - -void xtensa_tlb_set_entry_mmu(const CPUXtensaState *env, - xtensa_tlb_entry *entry, bool dtlb, - unsigned wi, unsigned ei, uint32_t vpn, - uint32_t pte) +static void xtensa_tlb_set_entry_mmu(const CPUXtensaState *env, + xtensa_tlb_entry *entry, bool dtlb, + unsigned wi, unsigned ei, uint32_t vp= n, + uint32_t pte) { entry->vaddr =3D vpn; entry->paddr =3D pte & xtensa_tlb_get_addr_mask(env, dtlb, wi); @@ -293,8 +247,9 @@ void xtensa_tlb_set_entry_mmu(const CPUXtensaState *env, entry->attr =3D pte & 0xf; } =20 -void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb, - unsigned wi, unsigned ei, uint32_t vpn, uint32_t= pte) +static void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb, + unsigned wi, unsigned ei, + uint32_t vpn, uint32_t pte) { XtensaCPU *cpu =3D xtensa_env_get_cpu(env); CPUState *cs =3D CPU(cpu); @@ -322,15 +277,6 @@ void xtensa_tlb_set_entry(CPUXtensaState *env, bool dt= lb, } } =20 -void HELPER(wtlb)(CPUXtensaState *env, uint32_t p, uint32_t v, uint32_t dt= lb) -{ - uint32_t vpn; - uint32_t wi; - uint32_t ei; - split_tlb_entry_spec(env, v, dtlb, &vpn, &wi, &ei); - xtensa_tlb_set_entry(env, dtlb, wi, ei, vpn, p); -} - hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) { XtensaCPU *cpu =3D XTENSA_CPU(cs); @@ -462,8 +408,9 @@ static unsigned get_ring(const CPUXtensaState *env, uin= t8_t asid) * \param pring: [out] access ring * \return 0 if ok, exception cause code otherwise */ -int xtensa_tlb_lookup(const CPUXtensaState *env, uint32_t addr, bool dtlb, - uint32_t *pwi, uint32_t *pei, uint8_t *pring) +static int xtensa_tlb_lookup(const CPUXtensaState *env, + uint32_t addr, bool dtlb, + uint32_t *pwi, uint32_t *pei, uint8_t *pring) { const xtensa_tlb *tlb =3D dtlb ? &env->config->dtlb : &env->config->itlb; @@ -495,6 +442,70 @@ int xtensa_tlb_lookup(const CPUXtensaState *env, uint3= 2_t addr, bool dtlb, (dtlb ? LOAD_STORE_TLB_MISS_CAUSE : INST_TLB_MISS_CAUSE); } =20 +uint32_t HELPER(rtlb0)(CPUXtensaState *env, uint32_t v, uint32_t dtlb) +{ + if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { + uint32_t wi; + const xtensa_tlb_entry *entry =3D get_tlb_entry(env, v, dtlb, &wi); + return (entry->vaddr & get_vpn_mask(env, dtlb, wi)) | entry->asid; + } else { + return v & REGION_PAGE_MASK; + } +} + +uint32_t HELPER(rtlb1)(CPUXtensaState *env, uint32_t v, uint32_t dtlb) +{ + const xtensa_tlb_entry *entry =3D get_tlb_entry(env, v, dtlb, NULL); + return entry->paddr | entry->attr; +} + +void HELPER(itlb)(CPUXtensaState *env, uint32_t v, uint32_t dtlb) +{ + if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { + uint32_t wi; + xtensa_tlb_entry *entry =3D get_tlb_entry(env, v, dtlb, &wi); + if (entry->variable && entry->asid) { + tlb_flush_page(CPU(xtensa_env_get_cpu(env)), entry->vaddr); + entry->asid =3D 0; + } + } +} + +uint32_t HELPER(ptlb)(CPUXtensaState *env, uint32_t v, uint32_t dtlb) +{ + if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { + uint32_t wi; + uint32_t ei; + uint8_t ring; + int res =3D xtensa_tlb_lookup(env, v, dtlb, &wi, &ei, &ring); + + switch (res) { + case 0: + if (ring >=3D xtensa_get_ring(env)) { + return (v & 0xfffff000) | wi | (dtlb ? 0x10 : 0x8); + } + break; + + case INST_TLB_MULTI_HIT_CAUSE: + case LOAD_STORE_TLB_MULTI_HIT_CAUSE: + HELPER(exception_cause_vaddr)(env, env->pc, res, v); + break; + } + return 0; + } else { + return (v & REGION_PAGE_MASK) | 0x1; + } +} + +void HELPER(wtlb)(CPUXtensaState *env, uint32_t p, uint32_t v, uint32_t dt= lb) +{ + uint32_t vpn; + uint32_t wi; + uint32_t ei; + split_tlb_entry_spec(env, v, dtlb, &vpn, &wi, &ei); + xtensa_tlb_set_entry(env, dtlb, wi, ei, vpn, p); +} + /*! * Convert MMU ATTR to PAGE_{READ,WRITE,EXEC} mask. * See ISA, 4.6.5.10 --=20 2.11.0 From nobody Thu Apr 25 07:57:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1557867620; cv=none; d=zoho.com; s=zohoarc; b=VSFoW3B5M/myASpeSIp7/uy9scTCLf53iZ3tOEGZaidO/A5JI6v2gFpiAScfEQxYlCeGoXBiV+wnW4CKVOhubebUCQtqlyJJcMDIbi6rv4NR6rWkJo+cKehphFaO+bwliUsMQV63wZ2YG/CJxITWLfPVVD+ENK2fdq/DyRTKjPE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1557867620; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=6XuVQs+UbdqBAxCFcAT1em7q9SaDATzG83gL/sJvK+Y=; b=FmxOTEd6s/jWyAYIT8JlKW4jMvckK7wU+Etj2Uzq+XxzFBwMgl9KJBF2NaGFZzlBwBtwzwJ8sRlhERclO0wAQEeeqea0adQdDKpspZz4HBM+DRDV8mB4fXTmG7huMWA9yYFIVO2+d8o5wFR8aFG2I8AK0Dx8RnRVJ/hCLpIftCw= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 15578676206351020.4574275534749; Tue, 14 May 2019 14:00:20 -0700 (PDT) Received: from localhost ([127.0.0.1]:54041 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hQeX3-0000cM-8D for importer@patchew.org; Tue, 14 May 2019 17:00:17 -0400 Received: from eggs.gnu.org ([209.51.188.92]:39078) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hQeUz-0007pr-OZ for qemu-devel@nongnu.org; Tue, 14 May 2019 16:58:10 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hQeIW-0007Fc-36 for qemu-devel@nongnu.org; Tue, 14 May 2019 16:45:17 -0400 Received: from mail-lf1-x144.google.com ([2a00:1450:4864:20::144]:35271) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hQeIV-0007Bz-Fg for qemu-devel@nongnu.org; Tue, 14 May 2019 16:45:16 -0400 Received: by mail-lf1-x144.google.com with SMTP id c17so261317lfi.2 for ; Tue, 14 May 2019 13:45:15 -0700 (PDT) Received: from octofox.cadence.com (jcmvbkbc-1-pt.tunnel.tserv24.sto1.ipv6.he.net. [2001:470:27:1fa::2]) by smtp.gmail.com with ESMTPSA id 78sm4011lje.81.2019.05.14.13.45.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 14 May 2019 13:45:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=6XuVQs+UbdqBAxCFcAT1em7q9SaDATzG83gL/sJvK+Y=; b=HVQFqmA4xlQXaLzwLSp4bPZD8cQeF+msCahRfoJdaD/Qi+IvYwqtEqOOiYD5ZQgESE QGKdzrLN/uISL9pvNrE96nbdlbrJk8BjccYjtsQDzKLyMOdMStVhPUzzSjORQXNaP6sk xwqXi9+bzgt6p3M++O0+75YUjzPXqZGOTV2PCzqayDaw6uhDbRXfLaKf+xpXwWqpLEjV PvbWHJmP9Kh93mF8B1SGnteJbVEhnGoEPWTCdsZvnS5rja+JtnkLRrzygeecsTDvlOlQ OUfqHnYCisK5x63ak6Sz+6bTIiL+gehccJBhzlk2j3IZT9TjSdajnfDQTyear29Oncx3 p5/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=6XuVQs+UbdqBAxCFcAT1em7q9SaDATzG83gL/sJvK+Y=; b=cxe3WCf0S0sxEDBYkoagcR1gZP6w0wzEkJnWPfFoeAZykC9PAQSqpx8GoHOjSqpOeo f4hHxAWJLHsVeC5lcGZeVBQFXQpkwEx8ZIHLW9ytZTEJik0l+qMAFZ3plRV95lLnhNq2 1Rl7M1S92iCzT6C9O9RIEwegkIk+2Gm9PYJgyyIHWNezI98OVRP4wqcqCP1i9Kqk7/55 kG3mP9i0yUFi3w014AWTT8Tjk8ku1GhKFRvG+oFtD8y6d+0ku3uVO3oBkzv2Pih+427m zXThDfQm4lTNyXINOD644b4foSEbf0HhKA1viTmibOH1bw5+01CV7qyBD8OZGl+ScyvG uRFg== X-Gm-Message-State: APjAAAVeBT5XQ1CeHfzk1I8SBDuV6gZp5X9FTspsSpk/HUkbLe1W53sE XuFbAHRuhUSTiMBOw4+rMFhtExO/6RQ= X-Google-Smtp-Source: APXvYqwgaB+XP3GWIHAopJCdjUY/U1ovWNM0GiU3jbX/UUmfdjvKPPQxcjv+D4xWGzqWMlPoKMssgA== X-Received: by 2002:ac2:41da:: with SMTP id d26mr17719241lfi.34.1557866714106; Tue, 14 May 2019 13:45:14 -0700 (PDT) From: Max Filippov To: qemu-devel@nongnu.org Date: Tue, 14 May 2019 13:44:41 -0700 Message-Id: <20190514204447.17486-4-jcmvbkbc@gmail.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190514204447.17486-1-jcmvbkbc@gmail.com> References: <20190514204447.17486-1-jcmvbkbc@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::144 Subject: [Qemu-devel] [PATCH 3/9] target/xtensa: define IDMA and gather/scatter IRQ types X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Max Filippov Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" IDMA and scatter/gather features introduced new IRQ types that overlay_tool.h need to initialize Xtensa configuration. Signed-off-by: Max Filippov --- target/xtensa/cpu.h | 3 +++ target/xtensa/overlay_tool.h | 3 +++ 2 files changed, 6 insertions(+) diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 502d41688365..d4258fcc6199 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -298,6 +298,9 @@ typedef enum { INTTYPE_DEBUG, INTTYPE_WRITE_ERR, INTTYPE_PROFILING, + INTTYPE_IDMA_DONE, + INTTYPE_IDMA_ERR, + INTTYPE_GS_ERR, INTTYPE_MAX } interrupt_type; =20 diff --git a/target/xtensa/overlay_tool.h b/target/xtensa/overlay_tool.h index ea07576bc921..8b380ce5e329 100644 --- a/target/xtensa/overlay_tool.h +++ b/target/xtensa/overlay_tool.h @@ -200,6 +200,9 @@ #define XTHAL_INTTYPE_TBD2 INTTYPE_WRITE_ERR #define XTHAL_INTTYPE_WRITE_ERROR INTTYPE_WRITE_ERR #define XTHAL_INTTYPE_PROFILING INTTYPE_PROFILING +#define XTHAL_INTTYPE_IDMA_DONE INTTYPE_IDMA_DONE +#define XTHAL_INTTYPE_IDMA_ERR INTTYPE_IDMA_ERR +#define XTHAL_INTTYPE_GS_ERR INTTYPE_GS_ERR =20 =20 #define INTERRUPT(i) { \ --=20 2.11.0 From nobody Thu Apr 25 07:57:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1557868152; cv=none; d=zoho.com; s=zohoarc; b=QbaybrfmkPyWBbTcab0AvD6bWrJ3IzNKcbiDdtZhNLLs1BhLOSMf2rgpncwUGeuN4sFiNdCqGBjXzTQcSPWfJUO1fssqvZAQaep7e8DR+iijKtGdegZEXFZSYo5kw5MePYzNpwtrHHsH5SKZ8KJ2M8Lu4f2e7TD3n5lpUuNhbxc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1557868152; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=hm1pySXCYRyqzKQMsacqw1+6viA6OKMUTJF5TynmyL0=; b=Vbkz1Y4v0g+tEOlEUe4eBqpjmuOZNV8jVhvShAKLAKBwFv8mtJfpinohbmWhcDrpypILexACiQUh9JtepgCdoREcQpgXi4LL5LOQsv3JuXzw30XVfAnognnVHIa2If8IDCytUEOFPTmaTLs4uWf7Hu18A5mjL1GP1EpXS4SEM0o= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1557868152254639.6767240828852; Tue, 14 May 2019 14:09:12 -0700 (PDT) Received: from localhost ([127.0.0.1]:54222 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hQefY-00072g-2s for importer@patchew.org; Tue, 14 May 2019 17:09:04 -0400 Received: from eggs.gnu.org ([209.51.188.92]:39003) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hQeV4-0007lu-PB for qemu-devel@nongnu.org; Tue, 14 May 2019 16:58:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hQeIi-0007W1-I0 for qemu-devel@nongnu.org; Tue, 14 May 2019 16:45:30 -0400 Received: from mail-lj1-x242.google.com ([2a00:1450:4864:20::242]:36819) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hQeIb-0007H4-Pi for qemu-devel@nongnu.org; Tue, 14 May 2019 16:45:23 -0400 Received: by mail-lj1-x242.google.com with SMTP id z1so510734ljb.3 for ; Tue, 14 May 2019 13:45:17 -0700 (PDT) Received: from octofox.cadence.com (jcmvbkbc-1-pt.tunnel.tserv24.sto1.ipv6.he.net. [2001:470:27:1fa::2]) by smtp.gmail.com with ESMTPSA id 78sm4011lje.81.2019.05.14.13.45.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 14 May 2019 13:45:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=hm1pySXCYRyqzKQMsacqw1+6viA6OKMUTJF5TynmyL0=; b=S0V2dexG17iC1iWmg+LukVUPWeX1ZOy5gO3+sUlQ5TK+8MjfHAKuNQLAG5PCIlMBgs jt57yZO9B2RFndZp/f+URFr6hNF/CpO4IrLtKhiqV7EZlruqXoIHMd5PLHeupxO17NgN 0Kw40ImRwSgmCdgNV6YXvhYZnPRNChGeYtIZy99r8ajeSjECTY/RAr497duWK6Ii3Lcm pUVO3BWJX4Cww8rfzaVaZ9bx8Sck/cH0vEU4ucEOcVBUIdUuoohul05328F4e2p2NfSt bOgK3Lw4nBfc9k+PX15M7hgScwKmnGq+bmOibsk2B1C0N7kzMs4C7upNPihwN9wVlT5g c7fg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=hm1pySXCYRyqzKQMsacqw1+6viA6OKMUTJF5TynmyL0=; b=eou27rs+Bm6wodf5ffh5D2sj2T6Xbc2UbPhSvhEokP5GAzcAOt63eygjKPgOymgL9B npFvql53cHpRGQJrRpWXPObRZWYg422i0Tnjgd/nonfUXnwnTJUMyCbvWszMi/mVZdQY 9t9+B+IwMZ/XC+L+cfRrd/bFvWADW0+TD42wE4UJOf+xUrWqCjud7uj1KJvy9xGS9my7 So7vw1xKn+UIGdtudIfoNye8pWltlhPjtb1cJAQxcOambilFjXLVEm0t7ZOX2Wx2ZXOL rjPYPPjf8ngLE1paPHaBYKd/gvd6vR0/ipQZkCEYzHREblYw+hdycDInWKPXIBlApRna wBkg== X-Gm-Message-State: APjAAAVeaczYq+QlBh/p5o1HWWwdhiS7P/bzBz2UZrhhBZR+mEeLbiR7 ZF5pvjid9IFYBBOoFPxMIj5X+12RgOQ= X-Google-Smtp-Source: APXvYqyR923CIrLtuXBWFXuI2Fa22yH/Ancp6Sr+NSy0RmG6NtMMSuJTCHfWndqKX1e/GVLOasKmew== X-Received: by 2002:a2e:9a1a:: with SMTP id o26mr3344579lji.174.1557866716300; Tue, 14 May 2019 13:45:16 -0700 (PDT) From: Max Filippov To: qemu-devel@nongnu.org Date: Tue, 14 May 2019 13:44:42 -0700 Message-Id: <20190514204447.17486-5-jcmvbkbc@gmail.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190514204447.17486-1-jcmvbkbc@gmail.com> References: <20190514204447.17486-1-jcmvbkbc@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::242 Subject: [Qemu-devel] [PATCH 4/9] target/xtensa: add parity/ECC option SRs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Max Filippov Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add SRs and rsr/wsr/xsr opcodes defined by the parity/ECC xtensa option. The implementation is trivial since we don't emulate parity/ECC yet. Signed-off-by: Max Filippov --- target/xtensa/cpu.h | 6 ++ target/xtensa/overlay_tool.h | 2 + target/xtensa/translate.c | 162 +++++++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 170 insertions(+) diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index d4258fcc6199..74ee7d125360 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -144,6 +144,12 @@ enum { CACHEATTR =3D 98, ATOMCTL =3D 99, DDR =3D 104, + MEPC =3D 106, + MEPS =3D 107, + MESAVE =3D 108, + MESR =3D 109, + MECR =3D 110, + MEVADDR =3D 111, IBREAKA =3D 128, DBREAKA =3D 144, DBREAKC =3D 160, diff --git a/target/xtensa/overlay_tool.h b/target/xtensa/overlay_tool.h index 8b380ce5e329..ffaab4b094cc 100644 --- a/target/xtensa/overlay_tool.h +++ b/target/xtensa/overlay_tool.h @@ -112,6 +112,8 @@ XCHAL_OPTION(XCHAL_DCACHE_LINE_LOCKABLE, \ XTENSA_OPTION_DCACHE_INDEX_LOCK) | \ XCHAL_OPTION(XCHAL_UNALIGNED_LOAD_HW, XTENSA_OPTION_HW_ALIGNMENT) | \ + XCHAL_OPTION(XCHAL_HAVE_MEM_ECC_PARITY, \ + XTENSA_OPTION_MEMORY_ECC_PARITY) | \ /* Memory protection and translation */ \ XCHAL_OPTION(XCHAL_HAVE_MIMIC_CACHEATTR, \ XTENSA_OPTION_REGION_PROTECTION) | \ diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index 100d6e126590..63a90fdd17dc 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -4216,6 +4216,60 @@ static const XtensaOpcodeOps core_ops[] =3D { .par =3D (const uint32_t[]){MEMCTL}, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { + .name =3D "rsr.mecr", + .translate =3D translate_rsr, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + MECR, + XTENSA_OPTION_MEMORY_ECC_PARITY, + }, + .op_flags =3D XTENSA_OP_PRIVILEGED, + }, { + .name =3D "rsr.mepc", + .translate =3D translate_rsr, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + MEPC, + XTENSA_OPTION_MEMORY_ECC_PARITY, + }, + .op_flags =3D XTENSA_OP_PRIVILEGED, + }, { + .name =3D "rsr.meps", + .translate =3D translate_rsr, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + MEPS, + XTENSA_OPTION_MEMORY_ECC_PARITY, + }, + .op_flags =3D XTENSA_OP_PRIVILEGED, + }, { + .name =3D "rsr.mesave", + .translate =3D translate_rsr, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + MESAVE, + XTENSA_OPTION_MEMORY_ECC_PARITY, + }, + .op_flags =3D XTENSA_OP_PRIVILEGED, + }, { + .name =3D "rsr.mesr", + .translate =3D translate_rsr, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + MESR, + XTENSA_OPTION_MEMORY_ECC_PARITY, + }, + .op_flags =3D XTENSA_OP_PRIVILEGED, + }, { + .name =3D "rsr.mevaddr", + .translate =3D translate_rsr, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + MESR, + XTENSA_OPTION_MEMORY_ECC_PARITY, + }, + .op_flags =3D XTENSA_OP_PRIVILEGED, + }, { .name =3D "rsr.misc0", .translate =3D translate_rsr, .test_ill =3D test_ill_sr, @@ -5036,6 +5090,60 @@ static const XtensaOpcodeOps core_ops[] =3D { .par =3D (const uint32_t[]){MEMCTL}, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { + .name =3D "wsr.mecr", + .translate =3D translate_wsr, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + MECR, + XTENSA_OPTION_MEMORY_ECC_PARITY, + }, + .op_flags =3D XTENSA_OP_PRIVILEGED, + }, { + .name =3D "wsr.mepc", + .translate =3D translate_wsr, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + MEPC, + XTENSA_OPTION_MEMORY_ECC_PARITY, + }, + .op_flags =3D XTENSA_OP_PRIVILEGED, + }, { + .name =3D "wsr.meps", + .translate =3D translate_wsr, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + MEPS, + XTENSA_OPTION_MEMORY_ECC_PARITY, + }, + .op_flags =3D XTENSA_OP_PRIVILEGED, + }, { + .name =3D "wsr.mesave", + .translate =3D translate_wsr, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + MESAVE, + XTENSA_OPTION_MEMORY_ECC_PARITY, + }, + .op_flags =3D XTENSA_OP_PRIVILEGED, + }, { + .name =3D "wsr.mesr", + .translate =3D translate_wsr, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + MESR, + XTENSA_OPTION_MEMORY_ECC_PARITY, + }, + .op_flags =3D XTENSA_OP_PRIVILEGED, + }, { + .name =3D "wsr.mevaddr", + .translate =3D translate_wsr, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + MESR, + XTENSA_OPTION_MEMORY_ECC_PARITY, + }, + .op_flags =3D XTENSA_OP_PRIVILEGED, + }, { .name =3D "wsr.misc0", .translate =3D translate_wsr, .test_ill =3D test_ill_sr, @@ -5702,6 +5810,60 @@ static const XtensaOpcodeOps core_ops[] =3D { .par =3D (const uint32_t[]){MEMCTL}, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { + .name =3D "xsr.mecr", + .translate =3D translate_xsr, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + MECR, + XTENSA_OPTION_MEMORY_ECC_PARITY, + }, + .op_flags =3D XTENSA_OP_PRIVILEGED, + }, { + .name =3D "xsr.mepc", + .translate =3D translate_xsr, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + MEPC, + XTENSA_OPTION_MEMORY_ECC_PARITY, + }, + .op_flags =3D XTENSA_OP_PRIVILEGED, + }, { + .name =3D "xsr.meps", + .translate =3D translate_xsr, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + MEPS, + XTENSA_OPTION_MEMORY_ECC_PARITY, + }, + .op_flags =3D XTENSA_OP_PRIVILEGED, + }, { + .name =3D "xsr.mesave", + .translate =3D translate_xsr, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + MESAVE, + XTENSA_OPTION_MEMORY_ECC_PARITY, + }, + .op_flags =3D XTENSA_OP_PRIVILEGED, + }, { + .name =3D "xsr.mesr", + .translate =3D translate_xsr, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + MESR, + XTENSA_OPTION_MEMORY_ECC_PARITY, + }, + .op_flags =3D XTENSA_OP_PRIVILEGED, + }, { + .name =3D "xsr.mevaddr", + .translate =3D translate_xsr, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + MESR, + XTENSA_OPTION_MEMORY_ECC_PARITY, + }, + .op_flags =3D XTENSA_OP_PRIVILEGED, + }, { .name =3D "xsr.misc0", .translate =3D translate_xsr, .test_ill =3D test_ill_sr, --=20 2.11.0 From nobody Thu Apr 25 07:57:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) 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X-Received-From: 2a00:1450:4864:20::244 Subject: [Qemu-devel] [PATCH 5/9] target/xtensa: implement MPU option X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Max Filippov Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The Memory Protection Unit Option (MPU) is a combined instruction and data memory protection unit with more protection flexibility than the Region Protection Option or the Region Translation Option but without any translation capability. It does no demand paging and does not reference a memory-based page table. Add memory protection unit option, internal state, SRs and opcodes. Implement MPU entries dumping in dump_mmu. Signed-off-by: Max Filippov --- target/xtensa/cpu.c | 1 - target/xtensa/cpu.h | 17 ++ target/xtensa/helper.h | 5 + target/xtensa/mmu_helper.c | 369 +++++++++++++++++++++++++++++++++++++++= ++++ target/xtensa/overlay_tool.h | 29 ++++ target/xtensa/translate.c | 146 +++++++++++++++++ 6 files changed, 566 insertions(+), 1 deletion(-) diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index a54dbe42602d..4215a1881ec7 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -78,7 +78,6 @@ static void xtensa_cpu_reset(CPUState *s) env->sregs[VECBASE] =3D env->config->vecbase; env->sregs[IBREAKENABLE] =3D 0; env->sregs[MEMCTL] =3D MEMCTL_IL0EN & env->config->memctl_mask; - env->sregs[CACHEATTR] =3D 0x22222222; env->sregs[ATOMCTL] =3D xtensa_option_enabled(env->config, XTENSA_OPTION_ATOMCTL) ? 0x28 : 0x15; env->sregs[CONFIGID0] =3D env->config->configid[0]; diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 74ee7d125360..d6e6bf6ca183 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -99,6 +99,7 @@ enum { /* Memory protection and translation */ XTENSA_OPTION_REGION_PROTECTION, XTENSA_OPTION_REGION_TRANSLATION, + XTENSA_OPTION_MPU, XTENSA_OPTION_MMU, XTENSA_OPTION_CACHEATTR, =20 @@ -137,11 +138,15 @@ enum { PTEVADDR =3D 83, MMID =3D 89, RASID =3D 90, + MPUENB =3D 90, ITLBCFG =3D 91, DTLBCFG =3D 92, + MPUCFG =3D 92, + ERACCESS =3D 95, IBREAKENABLE =3D 96, MEMCTL =3D 97, CACHEATTR =3D 98, + CACHEADRDIS =3D 98, ATOMCTL =3D 99, DDR =3D 104, MEPC =3D 106, @@ -234,6 +239,7 @@ enum { #define MAX_TLB_WAY_SIZE 8 #define MAX_NDBREAK 2 #define MAX_NMEMORY 4 +#define MAX_MPU_FOREGROUND_SEGMENTS 32 =20 #define REGION_PAGE_MASK 0xe0000000 =20 @@ -327,6 +333,11 @@ typedef struct xtensa_tlb { unsigned nrefillentries; } xtensa_tlb; =20 +typedef struct xtensa_mpu_entry { + uint32_t vaddr; + uint32_t attr; +} xtensa_mpu_entry; + typedef struct XtensaGdbReg { int targno; unsigned flags; @@ -477,6 +488,11 @@ struct XtensaConfig { =20 xtensa_tlb itlb; xtensa_tlb dtlb; + + uint32_t mpu_align; + unsigned n_mpu_fg_segments; + unsigned n_mpu_bg_segments; + const xtensa_mpu_entry *mpu_bg; }; =20 typedef struct XtensaConfigList { @@ -513,6 +529,7 @@ typedef struct CPUXtensaState { #ifndef CONFIG_USER_ONLY xtensa_tlb_entry itlb[7][MAX_TLB_WAY_SIZE]; xtensa_tlb_entry dtlb[10][MAX_TLB_WAY_SIZE]; + xtensa_mpu_entry mpu_fg[MAX_MPU_FOREGROUND_SEGMENTS]; unsigned autorefill_idx; bool runstall; AddressSpace *address_space_er; diff --git a/target/xtensa/helper.h b/target/xtensa/helper.h index 0b9ec670c86e..9216bee57e9a 100644 --- a/target/xtensa/helper.h +++ b/target/xtensa/helper.h @@ -33,6 +33,11 @@ DEF_HELPER_FLAGS_3(rtlb1, TCG_CALL_NO_RWG_SE, i32, env, = i32, i32) DEF_HELPER_3(itlb, void, env, i32, i32) DEF_HELPER_3(ptlb, i32, env, i32, i32) DEF_HELPER_4(wtlb, void, env, i32, i32, i32) +DEF_HELPER_2(wsr_mpuenb, void, env, i32) +DEF_HELPER_3(wptlb, void, env, i32, i32) +DEF_HELPER_FLAGS_2(rptlb0, TCG_CALL_NO_RWG_SE, i32, env, i32) +DEF_HELPER_FLAGS_2(rptlb1, TCG_CALL_NO_RWG_SE, i32, env, i32) +DEF_HELPER_2(pptlb, i32, env, i32) =20 DEF_HELPER_2(wsr_ibreakenable, void, env, i32) DEF_HELPER_3(wsr_ibreaka, void, env, i32, i32) diff --git a/target/xtensa/mmu_helper.c b/target/xtensa/mmu_helper.c index 465cfbf61359..cab39f687a21 100644 --- a/target/xtensa/mmu_helper.c +++ b/target/xtensa/mmu_helper.c @@ -35,6 +35,31 @@ #include "exec/exec-all.h" #include "exec/cpu_ldst.h" =20 +#define XTENSA_MPU_SEGMENT_MASK 0x0000001f +#define XTENSA_MPU_ACC_RIGHTS_MASK 0x00000f00 +#define XTENSA_MPU_ACC_RIGHTS_SHIFT 8 +#define XTENSA_MPU_MEM_TYPE_MASK 0x001ff000 +#define XTENSA_MPU_MEM_TYPE_SHIFT 12 +#define XTENSA_MPU_ATTR_MASK 0x001fff00 + +#define XTENSA_MPU_PROBE_B 0x40000000 +#define XTENSA_MPU_PROBE_V 0x80000000 + +#define XTENSA_MPU_SYSTEM_TYPE_DEVICE 0x0001 +#define XTENSA_MPU_SYSTEM_TYPE_NC 0x0002 +#define XTENSA_MPU_SYSTEM_TYPE_C 0x0003 +#define XTENSA_MPU_SYSTEM_TYPE_MASK 0x0003 + +#define XTENSA_MPU_TYPE_SYS_C 0x0010 +#define XTENSA_MPU_TYPE_SYS_W 0x0020 +#define XTENSA_MPU_TYPE_SYS_R 0x0040 +#define XTENSA_MPU_TYPE_CPU_C 0x0100 +#define XTENSA_MPU_TYPE_CPU_W 0x0200 +#define XTENSA_MPU_TYPE_CPU_R 0x0400 +#define XTENSA_MPU_TYPE_CPU_CACHE 0x0800 +#define XTENSA_MPU_TYPE_B 0x1000 +#define XTENSA_MPU_TYPE_INT 0x2000 + void HELPER(itlb_hit_test)(CPUXtensaState *env, uint32_t vaddr) { /* @@ -382,7 +407,20 @@ void reset_mmu(CPUXtensaState *env) reset_tlb_mmu_all_ways(env, &env->config->dtlb, env->dtlb); reset_tlb_mmu_ways56(env, &env->config->itlb, env->itlb); reset_tlb_mmu_ways56(env, &env->config->dtlb, env->dtlb); + } else if (xtensa_option_enabled(env->config, XTENSA_OPTION_MPU)) { + unsigned i; + + env->sregs[MPUENB] =3D 0; + env->sregs[MPUCFG] =3D env->config->n_mpu_fg_segments; + env->sregs[CACHEADRDIS] =3D 0; + assert(env->config->n_mpu_bg_segments > 0 && + env->config->mpu_bg[0].vaddr =3D=3D 0); + for (i =3D 1; i < env->config->n_mpu_bg_segments; ++i) { + assert(env->config->mpu_bg[i].vaddr >=3D + env->config->mpu_bg[i - 1].vaddr); + } } else { + env->sregs[CACHEATTR] =3D 0x22222222; reset_tlb_region_way0(env, env->itlb); reset_tlb_region_way0(env, env->dtlb); } @@ -579,6 +617,149 @@ static unsigned cacheattr_attr_to_access(uint32_t att= r) return access[attr & 0xf]; } =20 +struct attr_pattern { + uint32_t mask; + uint32_t value; +}; + +static int attr_pattern_match(uint32_t attr, + const struct attr_pattern *pattern, + size_t n) +{ + size_t i; + + for (i =3D 0; i < n; ++i) { + if ((attr & pattern[i].mask) =3D=3D pattern[i].value) { + return 1; + } + } + return 0; +} + +static unsigned mpu_attr_to_cpu_cache(uint32_t attr) +{ + static const struct attr_pattern cpu_c[] =3D { + { .mask =3D 0x18f, .value =3D 0x089 }, + { .mask =3D 0x188, .value =3D 0x080 }, + { .mask =3D 0x180, .value =3D 0x180 }, + }; + + unsigned type =3D 0; + + if (attr_pattern_match(attr, cpu_c, ARRAY_SIZE(cpu_c))) { + type |=3D XTENSA_MPU_TYPE_CPU_CACHE; + if (attr & 0x10) { + type |=3D XTENSA_MPU_TYPE_CPU_C; + } + if (attr & 0x20) { + type |=3D XTENSA_MPU_TYPE_CPU_W; + } + if (attr & 0x40) { + type |=3D XTENSA_MPU_TYPE_CPU_R; + } + } + return type; +} + +static unsigned mpu_attr_to_type(uint32_t attr) +{ + static const struct attr_pattern device_type[] =3D { + { .mask =3D 0x1f6, .value =3D 0x000 }, + { .mask =3D 0x1f6, .value =3D 0x006 }, + }; + static const struct attr_pattern sys_nc_type[] =3D { + { .mask =3D 0x1fe, .value =3D 0x018 }, + { .mask =3D 0x1fe, .value =3D 0x01e }, + { .mask =3D 0x18f, .value =3D 0x089 }, + }; + static const struct attr_pattern sys_c_type[] =3D { + { .mask =3D 0x1f8, .value =3D 0x010 }, + { .mask =3D 0x188, .value =3D 0x080 }, + { .mask =3D 0x1f0, .value =3D 0x030 }, + { .mask =3D 0x180, .value =3D 0x180 }, + }; + static const struct attr_pattern b[] =3D { + { .mask =3D 0x1f7, .value =3D 0x001 }, + { .mask =3D 0x1f7, .value =3D 0x007 }, + { .mask =3D 0x1ff, .value =3D 0x019 }, + { .mask =3D 0x1ff, .value =3D 0x01f }, + }; + + unsigned type =3D 0; + + attr =3D (attr & XTENSA_MPU_MEM_TYPE_MASK) >> XTENSA_MPU_MEM_TYPE_SHIF= T; + if (attr_pattern_match(attr, device_type, ARRAY_SIZE(device_type))) { + type |=3D XTENSA_MPU_SYSTEM_TYPE_DEVICE; + if (attr & 0x80) { + type |=3D XTENSA_MPU_TYPE_INT; + } + } + if (attr_pattern_match(attr, sys_nc_type, ARRAY_SIZE(sys_nc_type))) { + type |=3D XTENSA_MPU_SYSTEM_TYPE_NC; + } + if (attr_pattern_match(attr, sys_c_type, ARRAY_SIZE(sys_c_type))) { + type |=3D XTENSA_MPU_SYSTEM_TYPE_C; + if (attr & 0x1) { + type |=3D XTENSA_MPU_TYPE_SYS_C; + } + if (attr & 0x2) { + type |=3D XTENSA_MPU_TYPE_SYS_W; + } + if (attr & 0x4) { + type |=3D XTENSA_MPU_TYPE_SYS_R; + } + } + if (attr_pattern_match(attr, b, ARRAY_SIZE(b))) { + type |=3D XTENSA_MPU_TYPE_B; + } + type |=3D mpu_attr_to_cpu_cache(attr); + + return type; +} + +static unsigned mpu_attr_to_access(uint32_t attr, unsigned ring) +{ + static const unsigned access[2][16] =3D { + [0] =3D { + [4] =3D PAGE_READ, + [5] =3D PAGE_READ | PAGE_EXEC, + [6] =3D PAGE_READ | PAGE_WRITE, + [7] =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC, + [8] =3D PAGE_WRITE, + [9] =3D PAGE_READ | PAGE_WRITE, + [10] =3D PAGE_READ | PAGE_WRITE, + [11] =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC, + [12] =3D PAGE_READ, + [13] =3D PAGE_READ | PAGE_EXEC, + [14] =3D PAGE_READ | PAGE_WRITE, + [15] =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC, + }, + [1] =3D { + [8] =3D PAGE_WRITE, + [9] =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC, + [10] =3D PAGE_READ, + [11] =3D PAGE_READ | PAGE_EXEC, + [12] =3D PAGE_READ, + [13] =3D PAGE_READ | PAGE_EXEC, + [14] =3D PAGE_READ | PAGE_WRITE, + [15] =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC, + }, + }; + unsigned rv; + unsigned type; + + type =3D mpu_attr_to_cpu_cache(attr); + rv =3D access[ring !=3D 0][(attr & XTENSA_MPU_ACC_RIGHTS_MASK) >> + XTENSA_MPU_ACC_RIGHTS_SHIFT]; + + if (type & XTENSA_MPU_TYPE_CPU_CACHE) { + rv |=3D (type & XTENSA_MPU_TYPE_CPU_C) ? PAGE_CACHE_WB : PAGE_CACH= E_WT; + } else { + rv |=3D PAGE_CACHE_BYPASS; + } + return rv; +} + static bool is_access_granted(unsigned access, int is_write) { switch (is_write) { @@ -723,6 +904,129 @@ static int get_physical_addr_region(CPUXtensaState *e= nv, return 0; } =20 +static int xtensa_mpu_lookup(const xtensa_mpu_entry *entry, unsigned n, + uint32_t vaddr, unsigned *segment) +{ + unsigned nhits =3D 0; + unsigned i; + + for (i =3D 0; i < n; ++i) { + if (vaddr >=3D entry[i].vaddr && + (i =3D=3D n - 1 || vaddr < entry[i + 1].vaddr)) { + if (nhits++) { + break; + } + *segment =3D i; + } + } + return nhits; +} + +void HELPER(wsr_mpuenb)(CPUXtensaState *env, uint32_t v) +{ + XtensaCPU *cpu =3D xtensa_env_get_cpu(env); + + v &=3D (2u << (env->config->n_mpu_fg_segments - 1)) - 1; + + if (v !=3D env->sregs[MPUENB]) { + env->sregs[MPUENB] =3D v; + tlb_flush(CPU(cpu)); + } +} + +void HELPER(wptlb)(CPUXtensaState *env, uint32_t p, uint32_t v) +{ + unsigned segment =3D p & XTENSA_MPU_SEGMENT_MASK; + + if (segment < env->config->n_mpu_fg_segments) { + env->mpu_fg[segment].vaddr =3D v & -env->config->mpu_align; + env->mpu_fg[segment].attr =3D p & XTENSA_MPU_ATTR_MASK; + env->sregs[MPUENB] =3D deposit32(env->sregs[MPUENB], segment, 1, v= ); + tlb_flush(CPU(xtensa_env_get_cpu(env))); + } +} + +uint32_t HELPER(rptlb0)(CPUXtensaState *env, uint32_t s) +{ + unsigned segment =3D s & XTENSA_MPU_SEGMENT_MASK; + + if (segment < env->config->n_mpu_fg_segments) { + return env->mpu_fg[segment].vaddr | + extract32(env->sregs[MPUENB], segment, 1); + } else { + return 0; + } +} + +uint32_t HELPER(rptlb1)(CPUXtensaState *env, uint32_t s) +{ + unsigned segment =3D s & XTENSA_MPU_SEGMENT_MASK; + + if (segment < env->config->n_mpu_fg_segments) { + return env->mpu_fg[segment].attr; + } else { + return 0; + } +} + +uint32_t HELPER(pptlb)(CPUXtensaState *env, uint32_t v) +{ + unsigned nhits; + unsigned segment =3D XTENSA_MPU_PROBE_B; + unsigned bg_segment; + + nhits =3D xtensa_mpu_lookup(env->mpu_fg, env->config->n_mpu_fg_segment= s, + v, &segment); + if (nhits > 1) { + HELPER(exception_cause_vaddr)(env, env->pc, + LOAD_STORE_TLB_MULTI_HIT_CAUSE, v); + } else if (nhits =3D=3D 1 && (env->sregs[MPUENB] & (1u << segment))) { + return env->mpu_fg[segment].attr | segment | XTENSA_MPU_PROBE_V; + } else { + xtensa_mpu_lookup(env->config->mpu_bg, + env->config->n_mpu_bg_segments, + v, &bg_segment); + return env->config->mpu_bg[bg_segment].attr | segment; + } +} + +static int get_physical_addr_mpu(CPUXtensaState *env, + uint32_t vaddr, int is_write, int mmu_idx, + uint32_t *paddr, uint32_t *page_size, + unsigned *access) +{ + unsigned nhits; + unsigned segment; + uint32_t attr; + + nhits =3D xtensa_mpu_lookup(env->mpu_fg, env->config->n_mpu_fg_segment= s, + vaddr, &segment); + if (nhits > 1) { + return is_write < 2 ? + LOAD_STORE_TLB_MULTI_HIT_CAUSE : + INST_TLB_MULTI_HIT_CAUSE; + } else if (nhits =3D=3D 1 && (env->sregs[MPUENB] & (1u << segment))) { + attr =3D env->mpu_fg[segment].attr; + } else { + xtensa_mpu_lookup(env->config->mpu_bg, + env->config->n_mpu_bg_segments, + vaddr, &segment); + attr =3D env->config->mpu_bg[segment].attr; + } + + *access =3D mpu_attr_to_access(attr, mmu_idx); + if (!is_access_granted(*access, is_write)) { + return is_write < 2 ? + (is_write ? + STORE_PROHIBITED_CAUSE : + LOAD_PROHIBITED_CAUSE) : + INST_FETCH_PROHIBITED_CAUSE; + } + *paddr =3D vaddr; + *page_size =3D env->config->mpu_align; + return 0; +} + /*! * Convert virtual address to physical addr. * MMU may issue pagewalk and change xtensa autorefill TLB way entry. @@ -743,6 +1047,9 @@ int xtensa_get_physical_addr(CPUXtensaState *env, bool= update_tlb, XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION))) { return get_physical_addr_region(env, vaddr, is_write, mmu_idx, paddr, page_size, access); + } else if (xtensa_option_enabled(env->config, XTENSA_OPTION_MPU)) { + return get_physical_addr_mpu(env, vaddr, is_write, mmu_idx, + paddr, page_size, access); } else { *paddr =3D vaddr; *page_size =3D TARGET_PAGE_SIZE; @@ -810,6 +1117,63 @@ static void dump_tlb(CPUXtensaState *env, bool dtlb) } } =20 +static void dump_mpu(CPUXtensaState *env, + const xtensa_mpu_entry *entry, unsigned n) +{ + unsigned i; + + qemu_printf("\t%s Vaddr Attr Ring0 Ring1 System Type = CPU cache\n" + "\t%s ---------- ---------- ----- ----- -------------= ---------\n", + env ? "En" : " ", + env ? "--" : " "); + + for (i =3D 0; i < n; ++i) { + uint32_t attr =3D entry[i].attr; + unsigned access0 =3D mpu_attr_to_access(attr, 0); + unsigned access1 =3D mpu_attr_to_access(attr, 1); + unsigned type =3D mpu_attr_to_type(attr); + char cpu_cache =3D (type & XTENSA_MPU_TYPE_CPU_CACHE) ? '-' : ' '; + + qemu_printf("\t %c 0x%08x 0x%08x %c%c%c %c%c%c ", + env ? + ((env->sregs[MPUENB] & (1u << i)) ? '+' : '-') : ' ', + entry[i].vaddr, attr, + (access0 & PAGE_READ) ? 'R' : '-', + (access0 & PAGE_WRITE) ? 'W' : '-', + (access0 & PAGE_EXEC) ? 'X' : '-', + (access1 & PAGE_READ) ? 'R' : '-', + (access1 & PAGE_WRITE) ? 'W' : '-', + (access1 & PAGE_EXEC) ? 'X' : '-'); + + switch (type & XTENSA_MPU_SYSTEM_TYPE_MASK) { + case XTENSA_MPU_SYSTEM_TYPE_DEVICE: + qemu_printf("Device %cB %3s\n", + (type & XTENSA_MPU_TYPE_B) ? ' ' : 'n', + (type & XTENSA_MPU_TYPE_INT) ? "int" : ""); + break; + case XTENSA_MPU_SYSTEM_TYPE_NC: + qemu_printf("Sys NC %cB %c%c%c\n", + (type & XTENSA_MPU_TYPE_B) ? ' ' : 'n', + (type & XTENSA_MPU_TYPE_CPU_R) ? 'r' : cpu_cache, + (type & XTENSA_MPU_TYPE_CPU_W) ? 'w' : cpu_cache, + (type & XTENSA_MPU_TYPE_CPU_C) ? 'c' : cpu_cache); + break; + case XTENSA_MPU_SYSTEM_TYPE_C: + qemu_printf("Sys C %c%c%c %c%c%c\n", + (type & XTENSA_MPU_TYPE_SYS_R) ? 'R' : '-', + (type & XTENSA_MPU_TYPE_SYS_W) ? 'W' : '-', + (type & XTENSA_MPU_TYPE_SYS_C) ? 'C' : '-', + (type & XTENSA_MPU_TYPE_CPU_R) ? 'r' : cpu_cache, + (type & XTENSA_MPU_TYPE_CPU_W) ? 'w' : cpu_cache, + (type & XTENSA_MPU_TYPE_CPU_C) ? 'c' : cpu_cache); + break; + default: + qemu_printf("Unknown\n"); + break; + } + } +} + void dump_mmu(CPUXtensaState *env) { if (xtensa_option_bits_enabled(env->config, @@ -821,6 +1185,11 @@ void dump_mmu(CPUXtensaState *env) dump_tlb(env, false); qemu_printf("\nDTLB:\n"); dump_tlb(env, true); + } else if (xtensa_option_enabled(env->config, XTENSA_OPTION_MPU)) { + qemu_printf("Foreground map:\n"); + dump_mpu(env, env->mpu_fg, env->config->n_mpu_fg_segments); + qemu_printf("\nBackground map:\n"); + dump_mpu(NULL, env->config->mpu_bg, env->config->n_mpu_bg_segments= ); } else { qemu_printf("No TLB for this CPU core\n"); } diff --git a/target/xtensa/overlay_tool.h b/target/xtensa/overlay_tool.h index ffaab4b094cc..b61c92539861 100644 --- a/target/xtensa/overlay_tool.h +++ b/target/xtensa/overlay_tool.h @@ -72,6 +72,10 @@ #define XCHAL_HAVE_EXTERN_REGS 0 #endif =20 +#ifndef XCHAL_HAVE_MPU +#define XCHAL_HAVE_MPU 0 +#endif + #define XCHAL_OPTION(xchal, qemu) ((xchal) ? XTENSA_OPTION_BIT(qemu) : 0) =20 #define XTENSA_OPTIONS ( \ @@ -119,6 +123,7 @@ XTENSA_OPTION_REGION_PROTECTION) | \ XCHAL_OPTION(XCHAL_HAVE_XLT_CACHEATTR, \ XTENSA_OPTION_REGION_TRANSLATION) | \ + XCHAL_OPTION(XCHAL_HAVE_MPU, XTENSA_OPTION_MPU) | \ XCHAL_OPTION(XCHAL_HAVE_PTP_MMU, XTENSA_OPTION_MMU) | \ XCHAL_OPTION(XCHAL_HAVE_CACHEATTR, XTENSA_OPTION_CACHEATTR) | \ /* Other, TODO */ \ @@ -361,6 +366,30 @@ #define XCHAL_SYSRAM0_SIZE 0x04000000 #endif =20 +#elif XCHAL_HAVE_MPU + +#ifndef XTENSA_MPU_BG_MAP +#define XTENSA_MPU_BG_MAP (xtensa_mpu_entry []){\ + { .vaddr =3D 0, .attr =3D 0x00006700, }, \ +} +#endif + +#define TLB_SECTION \ + .mpu_align =3D XCHAL_MPU_ALIGN, \ + .n_mpu_fg_segments =3D XCHAL_MPU_ENTRIES, \ + .n_mpu_bg_segments =3D 1, \ + .mpu_bg =3D XTENSA_MPU_BG_MAP + +#ifndef XCHAL_SYSROM0_PADDR +#define XCHAL_SYSROM0_PADDR 0x50000000 +#define XCHAL_SYSROM0_SIZE 0x04000000 +#endif + +#ifndef XCHAL_SYSRAM0_PADDR +#define XCHAL_SYSRAM0_PADDR 0x60000000 +#define XCHAL_SYSRAM0_SIZE 0x04000000 +#endif + #else =20 #ifndef XCHAL_SYSROM0_PADDR diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index 63a90fdd17dc..782f2ec62099 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -1992,6 +1992,15 @@ static void translate_ptlb(DisasContext *dc, const O= pcodeArg arg[], #endif } =20 +static void translate_pptlb(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) +{ +#ifndef CONFIG_USER_ONLY + tcg_gen_movi_i32(cpu_pc, dc->pc); + gen_helper_pptlb(arg[0].out, cpu_env, arg[1].in); +#endif +} + static void translate_quos(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { @@ -2184,6 +2193,22 @@ static void translate_rtlb(DisasContext *dc, const O= pcodeArg arg[], #endif } =20 +static void translate_rptlb0(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) +{ +#ifndef CONFIG_USER_ONLY + gen_helper_rptlb0(arg[0].out, cpu_env, arg[1].in); +#endif +} + +static void translate_rptlb1(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) +{ +#ifndef CONFIG_USER_ONLY + gen_helper_rptlb1(arg[0].out, cpu_env, arg[1].in); +#endif +} + static void translate_rur(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { @@ -2445,6 +2470,14 @@ static void translate_wtlb(DisasContext *dc, const O= pcodeArg arg[], #endif } =20 +static void translate_wptlb(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) +{ +#ifndef CONFIG_USER_ONLY + gen_helper_wptlb(cpu_env, arg[0].in, arg[1].in); +#endif +} + static void translate_wer(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { @@ -2593,6 +2626,14 @@ static void translate_wsr_memctl(DisasContext *dc, c= onst OpcodeArg arg[], #endif } =20 +static void translate_wsr_mpuenb(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) +{ +#ifndef CONFIG_USER_ONLY + gen_helper_wsr_mpuenb(cpu_env, arg[0].in); +#endif +} + static void translate_wsr_ps(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { @@ -2731,6 +2772,7 @@ gen_translate_xsr(ibreaka) gen_translate_xsr(ibreakenable) gen_translate_xsr(icount) gen_translate_xsr(memctl) +gen_translate_xsr(mpuenb) gen_translate_xsr(ps) gen_translate_xsr(rasid) gen_translate_xsr(sar) @@ -3581,6 +3623,10 @@ static const XtensaOpcodeOps core_ops[] =3D { .par =3D (const uint32_t[]){false}, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { + .name =3D "pptlb", + .translate =3D translate_pptlb, + .op_flags =3D XTENSA_OP_PRIVILEGED, + }, { .name =3D "quos", .translate =3D translate_quos, .par =3D (const uint32_t[]){true}, @@ -3667,6 +3713,14 @@ static const XtensaOpcodeOps core_ops[] =3D { .par =3D (const uint32_t[]){false, 1}, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { + .name =3D "rptlb0", + .translate =3D translate_rptlb0, + .op_flags =3D XTENSA_OP_PRIVILEGED, + }, { + .name =3D "rptlb1", + .translate =3D translate_rptlb1, + .op_flags =3D XTENSA_OP_PRIVILEGED, + }, { .name =3D "rotw", .translate =3D translate_rotw, .op_flags =3D XTENSA_OP_PRIVILEGED | @@ -3723,6 +3777,15 @@ static const XtensaOpcodeOps core_ops[] =3D { XTENSA_OPTION_BOOLEAN, }, }, { + .name =3D "rsr.cacheadrdis", + .translate =3D translate_rsr, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + CACHEADRDIS, + XTENSA_OPTION_MPU, + }, + .op_flags =3D XTENSA_OP_PRIVILEGED, + }, { .name =3D "rsr.cacheattr", .translate =3D translate_rsr, .test_ill =3D test_ill_sr, @@ -3976,6 +4039,11 @@ static const XtensaOpcodeOps core_ops[] =3D { }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { + .name =3D "rsr.eraccess", + .translate =3D translate_rsr, + .par =3D (const uint32_t[]){ERACCESS}, + .op_flags =3D XTENSA_OP_PRIVILEGED, + }, { .name =3D "rsr.exccause", .translate =3D translate_rsr, .test_ill =3D test_ill_sr, @@ -4306,6 +4374,24 @@ static const XtensaOpcodeOps core_ops[] =3D { }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { + .name =3D "rsr.mpucfg", + .translate =3D translate_rsr, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + MPUCFG, + XTENSA_OPTION_MPU, + }, + .op_flags =3D XTENSA_OP_PRIVILEGED, + }, { + .name =3D "rsr.mpuenb", + .translate =3D translate_rsr, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + MPUENB, + XTENSA_OPTION_MPU, + }, + .op_flags =3D XTENSA_OP_PRIVILEGED, + }, { .name =3D "rsr.prefctl", .translate =3D translate_rsr, .par =3D (const uint32_t[]){PREFCTL}, @@ -4543,6 +4629,10 @@ static const XtensaOpcodeOps core_ops[] =3D { .par =3D (const uint32_t[]){false}, .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, }, { + .name =3D "wptlb", + .translate =3D translate_wptlb, + .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, + }, { .name =3D "wrmsk_expstate", .translate =3D translate_wrmsk_expstate, }, { @@ -4587,6 +4677,16 @@ static const XtensaOpcodeOps core_ops[] =3D { 0xffff, }, }, { + .name =3D "wsr.cacheadrdis", + .translate =3D translate_wsr_mask, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + CACHEADRDIS, + XTENSA_OPTION_MPU, + 0xff, + }, + .op_flags =3D XTENSA_OP_PRIVILEGED, + }, { .name =3D "wsr.cacheattr", .translate =3D translate_wsr, .test_ill =3D test_ill_sr, @@ -4832,6 +4932,15 @@ static const XtensaOpcodeOps core_ops[] =3D { }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { + .name =3D "wsr.eraccess", + .translate =3D translate_wsr_mask, + .par =3D (const uint32_t[]){ + ERACCESS, + 0, + 0xffff, + }, + .op_flags =3D XTENSA_OP_PRIVILEGED, + }, { .name =3D "wsr.exccause", .translate =3D translate_wsr, .test_ill =3D test_ill_sr, @@ -5189,6 +5298,15 @@ static const XtensaOpcodeOps core_ops[] =3D { }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { + .name =3D "wsr.mpuenb", + .translate =3D translate_wsr_mpuenb, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + MPUENB, + XTENSA_OPTION_MPU, + }, + .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, + }, { .name =3D "wsr.prefctl", .translate =3D translate_wsr, .par =3D (const uint32_t[]){PREFCTL}, @@ -5334,6 +5452,16 @@ static const XtensaOpcodeOps core_ops[] =3D { 0xffff, }, }, { + .name =3D "xsr.cacheadrdis", + .translate =3D translate_xsr_mask, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + CACHEADRDIS, + XTENSA_OPTION_MPU, + 0xff, + }, + .op_flags =3D XTENSA_OP_PRIVILEGED, + }, { .name =3D "xsr.cacheattr", .translate =3D translate_xsr, .test_ill =3D test_ill_sr, @@ -5579,6 +5707,15 @@ static const XtensaOpcodeOps core_ops[] =3D { }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { + .name =3D "xsr.eraccess", + .translate =3D translate_xsr_mask, + .par =3D (const uint32_t[]){ + ERACCESS, + 0, + 0xffff, + }, + .op_flags =3D XTENSA_OP_PRIVILEGED, + }, { .name =3D "xsr.exccause", .translate =3D translate_xsr, .test_ill =3D test_ill_sr, @@ -5900,6 +6037,15 @@ static const XtensaOpcodeOps core_ops[] =3D { }, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { + .name =3D "xsr.mpuenb", + .translate =3D translate_xsr_mpuenb, + .test_ill =3D test_ill_sr, + .par =3D (const uint32_t[]){ + MPUENB, + XTENSA_OPTION_MPU, + }, + .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, + }, { .name =3D "xsr.prefctl", .translate =3D translate_xsr, .par =3D (const uint32_t[]){PREFCTL}, --=20 2.11.0 From nobody Thu Apr 25 07:57:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1557867876; cv=none; d=zoho.com; s=zohoarc; b=D48hrPxuuQf4YVcxqkb5V5bUNRXR7IDG0MP8QsPoTO0sva+h/nFggsMY3RdfTH7DWQ1XhqkMVeEy0pYwihGuLgtmRj3PZ19k8yJINg2wH/kc5Vu4Xs0FJpiYQR94+RyAgi/IDH1mxaJyNP3c3zDW01nFsGVlOHvNQurw7uxtIL4= ARC-Message-Signature: i=1; a=rsa-sha256; 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[2001:470:27:1fa::2]) by smtp.gmail.com with ESMTPSA id 78sm4011lje.81.2019.05.14.13.45.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 14 May 2019 13:45:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=TNwKj3NK4xpLU3quun8/1/87vC9zwSKuxU85t6b9WuA=; b=naeemU+B3Dsr9Pb9887eyk9hKazrAQqLIV+zE8jsRV/UhSUadUFy0KyFnlfRBpaCal cH5oBrYFH9kZHO4qk1Ylhs+GdZzJ3+izuEaT+3SaJ74WucyLnkYyh8xdIuhr6X6Hmlzk JEsGweJwKd+4iCVEQvos2czMF0zpB7Qt2ih5U+Q/yEgeiDO0ybkIhQfhp6oJOh7DcolC wPFvw5VTQaIoHsHEatmfGLT8y64nMk4iAgTm9WAZtIJdo0mpCPcY8mBu/FqGAktC672a kJSYp6Qfv3272bPzlQi9hubtMYdoBFPCo85QGI6PcBbhlZiIckFyvjjCwARCGADdJzjQ VDXA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=TNwKj3NK4xpLU3quun8/1/87vC9zwSKuxU85t6b9WuA=; b=eZUESdFylfK1LIxPo6sBUzoLB4rQAfeUTlzaBpRDLyMTD5cmseHePEbX1e0dlYSrBJ 6cw8jeEyVllOZIaqduLpH+Byb3qt43jADzfdikXWhDuB9hn2zh6a/2J4fI6BZBrGBVBx yg94oUmBFUg3i73Fp4kDEdIUB4znN47ldAgJc7SCu3bZj+a7k1xxhcKzqRkbznT98HOy IvgZlaMgNffYmb97AYYeWhwj2Xz9WiZlH1CYt2VoyQqSm0x6gtSOCat56TVz8PR5X6c+ COQLZQheCtRqDvuuKL81okSzfM8PcXdkk0tmo2JMEK+Nwd98SCgIQ3RAYgHG0Vx+wkjE iKNQ== X-Gm-Message-State: APjAAAXMWbKAuZyjpcvLw3q5Qt9Yu7g7rNAS6Gw7uk5kxSx7XdiR3wgv riREi7sPYGAHb/LQw59mtoQFlrAkT24= X-Google-Smtp-Source: APXvYqyyEJ5GTQ6YtPzM+dXpqNHh6PtiJL6IchaRThMLl/uTogIYxWtOkLS8WrcnXck1CHXzchdDNg== X-Received: by 2002:a2e:28d:: with SMTP id y13mr17667712lje.177.1557866720808; Tue, 14 May 2019 13:45:20 -0700 (PDT) From: Max Filippov To: qemu-devel@nongnu.org Date: Tue, 14 May 2019 13:44:44 -0700 Message-Id: <20190514204447.17486-7-jcmvbkbc@gmail.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190514204447.17486-1-jcmvbkbc@gmail.com> References: <20190514204447.17486-1-jcmvbkbc@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::244 Subject: [Qemu-devel] [PATCH 6/9] target/xtensa: implement DIWBUI.P opcode X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Max Filippov Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This is a recent addition to the set of data cache opcodes. Signed-off-by: Max Filippov --- target/xtensa/cpu.h | 1 + target/xtensa/overlay_tool.h | 1 + target/xtensa/translate.c | 10 ++++++++++ 3 files changed, 12 insertions(+) diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index d6e6bf6ca183..ba4ef2b6a729 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -466,6 +466,7 @@ struct XtensaConfig { =20 unsigned icache_ways; unsigned dcache_ways; + unsigned dcache_line_bytes; uint32_t memctl_mask; =20 XtensaMemory instrom; diff --git a/target/xtensa/overlay_tool.h b/target/xtensa/overlay_tool.h index b61c92539861..4925b21f0edf 100644 --- a/target/xtensa/overlay_tool.h +++ b/target/xtensa/overlay_tool.h @@ -425,6 +425,7 @@ #define CACHE_SECTION \ .icache_ways =3D XCHAL_ICACHE_WAYS, \ .dcache_ways =3D XCHAL_DCACHE_WAYS, \ + .dcache_line_bytes =3D XCHAL_DCACHE_LINESIZE, \ .memctl_mask =3D \ (XCHAL_ICACHE_SIZE ? MEMCTL_IUSEWAYS_MASK : 0) | \ (XCHAL_DCACHE_SIZE ? \ diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index 782f2ec62099..24eb70d619d5 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -1620,6 +1620,12 @@ static void translate_depbits(DisasContext *dc, cons= t OpcodeArg arg[], arg[2].imm, arg[3].imm); } =20 +static void translate_diwbuip(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) +{ + tcg_gen_addi_i32(arg[0].out, arg[0].in, dc->config->dcache_line_bytes); +} + static bool test_ill_entry(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { @@ -3098,6 +3104,10 @@ static const XtensaOpcodeOps core_ops[] =3D { .translate =3D translate_nop, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { + .name =3D "diwbui.p", + .translate =3D translate_diwbuip, + .op_flags =3D XTENSA_OP_PRIVILEGED, + }, { .name =3D "dpfl", .translate =3D translate_dcache, .op_flags =3D XTENSA_OP_PRIVILEGED, --=20 2.11.0 From nobody Thu Apr 25 07:57:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1557867684; cv=none; d=zoho.com; s=zohoarc; b=CQGL+3Mgo/n3v60iNECU9zBYgwM/IecAIIHDnMmZ9YT8syUA3Qm/BDsJSURi0TXJXuVwpGNJU30qoOnh+EXA4TaLvTDqozNY7HxJ1zZXNjK075YqyhVqSyuRjN7s5Dh9o01Fj2fOI58HsOT4B4vnP/WqMGXU4vdqEbXy6FQSyJI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1557867684; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=wQy3/F5joNergsR/ABXk05EEEem/roqnfLo8tHgTfa8=; b=Qv/uOdvyXOT38lFbEaY4thYMXCa0bNUcykQE/lNJSiNw1pJUVkENe9r3is0hD7B8MaYgXX1UPc3kbcxxKvdZLq1ru2Sm9GGCVTI4slLOSkluR1z6Qq4p8AI9Ka5W6tXvxeKgwiliIksAOs0EN8V6WDELQJcdvjseccAl4SmSvdI= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1557867684334317.1840630916363; Tue, 14 May 2019 14:01:24 -0700 (PDT) Received: from localhost ([127.0.0.1]:54079 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hQeY3-0001Rk-BA for importer@patchew.org; Tue, 14 May 2019 17:01:19 -0400 Received: from eggs.gnu.org ([209.51.188.92]:38999) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hQeV3-0007lo-IS for qemu-devel@nongnu.org; Tue, 14 May 2019 16:58:14 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hQeIj-0007Yw-MZ for qemu-devel@nongnu.org; Tue, 14 May 2019 16:45:30 -0400 Received: from mail-lj1-x243.google.com ([2a00:1450:4864:20::243]:38450) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hQeIj-0007Tz-4H for qemu-devel@nongnu.org; Tue, 14 May 2019 16:45:29 -0400 Received: by mail-lj1-x243.google.com with SMTP id 14so501763ljj.5 for ; Tue, 14 May 2019 13:45:24 -0700 (PDT) Received: from octofox.cadence.com (jcmvbkbc-1-pt.tunnel.tserv24.sto1.ipv6.he.net. [2001:470:27:1fa::2]) by smtp.gmail.com with ESMTPSA id 78sm4011lje.81.2019.05.14.13.45.21 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 14 May 2019 13:45:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=wQy3/F5joNergsR/ABXk05EEEem/roqnfLo8tHgTfa8=; b=aYHsbDOpRKkHD1//NPrG1MNWmGTXj4BQKpBZ5pmGn10shL69RFedWr+h1TT5qApvVP 3RLXY2/mNS4pAkNPf6Qr38+H9TU0OvJyZJm8LmsHibCRTgybKqwtxTKyf7Navx74PaPG DeTxF7CAGxNw5ZAR92oO/9gT1hN1C3H444BLnqBJWnFozmeEGX1euzxtm+bQYCa8FrbV IH6PPeskuSoPpE+sg4bB/Eu3g2rnvzjCqaI85eWKzgwOzjDlnh401JsQmnP597Odt1Z+ CIBDQa1L3xmyoKRKucL4CurLzwcXX7ga7KZE1xkLSEDEHRU5hV0Jnb2aDAUtkdMW5Trf yMGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=wQy3/F5joNergsR/ABXk05EEEem/roqnfLo8tHgTfa8=; b=HzbpzzCMYmnPdRg5CmKOC6EssmS6/yRYc6BdiY3tN3AX4H402SatGZZUgbKlL0hW0X zpKlfCVD0iOmhtqsqQKe42Xo3l2M4TXM9S8Bhev/VDweOcP4REuV0it92a8TAZ1uoa4C Ke5bkiyO1rYZ+yDyAb3Sq26RrTZJBQydk3oUJilhpscXxR+eot1F8BfPm6y5EVlu2SHx Y+/oBIVOu7Seh4OnbK1AASoXv/EOM0w8EnKxx+FErtEguq1i7qBfEOIPjUkC2KBDSWMF /TvIdgFVwk9aCyNFjV8XKcFc7wzKzdrpbPNOyuPOx24VIPyhccb6pKWWaBrxFbKEPskB rVEw== X-Gm-Message-State: APjAAAUKwdHROhON031pslrn8hRjW8skXbWtu2sXKPMebwyMijBdda6b Z5TZj78QhwLA8J+l9YWmNIG57fsUsdg= X-Google-Smtp-Source: APXvYqyCHAmIqOFxvd/ykkIeYJDB2r+CsqKeDCyY6UBlgdSkd0IuS5vOISQHUwxqk23b4J3FbOppag== X-Received: by 2002:a2e:9ada:: with SMTP id p26mr17592870ljj.167.1557866722717; Tue, 14 May 2019 13:45:22 -0700 (PDT) From: Max Filippov To: qemu-devel@nongnu.org Date: Tue, 14 May 2019 13:44:45 -0700 Message-Id: <20190514204447.17486-8-jcmvbkbc@gmail.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190514204447.17486-1-jcmvbkbc@gmail.com> References: <20190514204447.17486-1-jcmvbkbc@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::243 Subject: [Qemu-devel] [PATCH 7/9] target/xtensa: implement block prefetch option opcodes X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Max Filippov Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Block prefetch option adds a bunch of non-privileged opcodes that may be implemented as nops since QEMU doesn't model caches. Signed-off-by: Max Filippov Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/xtensa/translate.c | 42 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index 24eb70d619d5..356eb9948701 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -3078,6 +3078,9 @@ static const XtensaOpcodeOps core_ops[] =3D { .translate =3D translate_dcache, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { + .name =3D "dhi.b", + .translate =3D translate_nop, + }, { .name =3D "dhu", .translate =3D translate_dcache, .op_flags =3D XTENSA_OP_PRIVILEGED, @@ -3085,9 +3088,15 @@ static const XtensaOpcodeOps core_ops[] =3D { .name =3D "dhwb", .translate =3D translate_dcache, }, { + .name =3D "dhwb.b", + .translate =3D translate_nop, + }, { .name =3D "dhwbi", .translate =3D translate_dcache, }, { + .name =3D "dhwbi.b", + .translate =3D translate_nop, + }, { .name =3D "dii", .translate =3D translate_nop, .op_flags =3D XTENSA_OP_PRIVILEGED, @@ -3112,15 +3121,33 @@ static const XtensaOpcodeOps core_ops[] =3D { .translate =3D translate_dcache, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { + .name =3D "dpfm.b", + .translate =3D translate_nop, + }, { + .name =3D "dpfm.bf", + .translate =3D translate_nop, + }, { .name =3D "dpfr", .translate =3D translate_nop, }, { + .name =3D "dpfr.b", + .translate =3D translate_nop, + }, { + .name =3D "dpfr.bf", + .translate =3D translate_nop, + }, { .name =3D "dpfro", .translate =3D translate_nop, }, { .name =3D "dpfw", .translate =3D translate_nop, }, { + .name =3D "dpfw.b", + .translate =3D translate_nop, + }, { + .name =3D "dpfw.bf", + .translate =3D translate_nop, + }, { .name =3D "dpfwo", .translate =3D translate_nop, }, { @@ -3628,6 +3655,21 @@ static const XtensaOpcodeOps core_ops[] =3D { .par =3D (const uint32_t[]){true}, .op_flags =3D XTENSA_OP_PRIVILEGED, }, { + .name =3D "pfend.a", + .translate =3D translate_nop, + }, { + .name =3D "pfend.o", + .translate =3D translate_nop, + }, { + .name =3D "pfnxt.f", + .translate =3D translate_nop, + }, { + .name =3D "pfwait.a", + .translate =3D translate_nop, + }, { + .name =3D "pfwait.o", + .translate =3D translate_nop, + }, { .name =3D "pitlb", .translate =3D translate_ptlb, .par =3D (const uint32_t[]){false}, --=20 2.11.0 From nobody Thu Apr 25 07:57:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[2001:470:27:1fa::2]) by smtp.gmail.com with ESMTPSA id 78sm4011lje.81.2019.05.14.13.45.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 14 May 2019 13:45:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=jcFS5+jIJKosDV3MzdYV6crVIuBE3kgBVMwFRGOcg+I=; b=VHsT1I4dvW74OLvRw/avbw0DjE1VWDUevQKUqF7QRLQqInjBcwg/VH55fATvo5ivvg zzn/hfWoS950q8cV7b/EkOayV/qp4PdZBQCW9QJR5LLXIXmpE0Q1WDdgeT/R2eGUplSI 3OAG5A4Zw0Si6RxndTChCe7+MwxDvVjy2y6fHP7kEkPkjRCAe5wv36rCh5JO76W/V4nW q6h4J4SanGKiOshIPHj1+eY0tcqr7kbuz8GYaazFwEkj5EIsAZSWzFRLIWuXkbvv0oTo kMnMnUfuy1x8fN2/hX2Pqw4j1rbkPyqWkAQ/rtAY5tUUUK6nDDFtB28ZVhqs4Ko6To3r /B6g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=jcFS5+jIJKosDV3MzdYV6crVIuBE3kgBVMwFRGOcg+I=; b=AnGRh3m2pgROvS9qpVRSG9b8S69vnpWW4+Xt3Nx9R60vfgv8Crepjo4foCaHWun/y5 Snl5KLOnB2GplCedBuFk/K80BzXY+L50qjKwQnBy7FkaF9jVnHfb1ljsKVAEX4E02MLL vBZHoOwP3f9O4qVbmUI6kglk1YhXy+5m8gMoumVV1w12TDUJh5pGZs7z4BFQuSRUX67q OPzUfpASb5KWWgqNTzF+Z+qoQj2bsUFbszSrpOfp4B5k9QwomKhIpd22EEWuZKgwoezb EjPT6zUdabZqVHWN8VNWtzNeSx14dQQi2lbNAL89X5gFYswsllo6M10OKIvXjszwn+8H o4RA== X-Gm-Message-State: APjAAAVflMlJT4EE8a3rCcbW0MBMnkgFdH0FKBlsmCqyf4C9BxT2jPZc N5b9Eh6dG+1SKQ9cH7Q0vqv8DEpPl88= X-Google-Smtp-Source: APXvYqwgwgP1I4SXag4lM6DwwTU/YV+/9bqGZtJm5cWDJmqt9q30SfeG5X547Yw0MehgHuwK74KI+Q== X-Received: by 2002:a2e:9f41:: with SMTP id v1mr13805828ljk.66.1557866724525; Tue, 14 May 2019 13:45:24 -0700 (PDT) From: Max Filippov To: qemu-devel@nongnu.org Date: Tue, 14 May 2019 13:44:46 -0700 Message-Id: <20190514204447.17486-9-jcmvbkbc@gmail.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190514204447.17486-1-jcmvbkbc@gmail.com> References: <20190514204447.17486-1-jcmvbkbc@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::243 Subject: [Qemu-devel] [PATCH 8/9] target/xtensa: update list of exception causes X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Max Filippov Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add XEA2 exception cause codes defined in recent Xtensa ISA releases. Signed-off-by: Max Filippov --- target/xtensa/cpu.h | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index ba4ef2b6a729..8301923e4c4a 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -280,14 +280,15 @@ enum { LEVEL1_INTERRUPT_CAUSE, ALLOCA_CAUSE, INTEGER_DIVIDE_BY_ZERO_CAUSE, - PRIVILEGED_CAUSE =3D 8, + PC_VALUE_ERROR_CAUSE, + PRIVILEGED_CAUSE, LOAD_STORE_ALIGNMENT_CAUSE, - - INSTR_PIF_DATA_ERROR_CAUSE =3D 12, + EXTERNAL_REG_PRIVILEGE_CAUSE, + EXCLUSIVE_ERROR_CAUSE, + INSTR_PIF_DATA_ERROR_CAUSE, LOAD_STORE_PIF_DATA_ERROR_CAUSE, INSTR_PIF_ADDR_ERROR_CAUSE, LOAD_STORE_PIF_ADDR_ERROR_CAUSE, - INST_TLB_MISS_CAUSE, INST_TLB_MULTI_HIT_CAUSE, INST_FETCH_PRIVILEGE_CAUSE, --=20 2.11.0 From nobody Thu Apr 25 07:57:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1557868000; cv=none; d=zoho.com; s=zohoarc; b=BqHMB8VjA+fLW0XocyhhsjqAljeIGpChH/mfelxWBd5rg6vqPUQk+9lU3BOtNPh4tDIxrLkrFhY8D95qz0M6dccTreGpFsW4npEwp92CakFY//oBc3211xczGXp0Ct8Lctmc9TehTgHQqGCbGlWik/5wE8DVVEE9Um5m+jNGLsU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1557868000; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=FXb6aboJp5Icq+FwNf9gA5rmibu3GFrNef50fwTDTPg=; b=Ohrei6ltmCiiqUYMnKCCXy9CfOxnh6MfOIlPTqXMBg/JmB3fBixEezGStzZaykv0xwA6tOkZ6FLqsHiaGl59jDmNRBV6Jr0XudPK+bAdjPLRUabsmFbSvyg8sfZ6/+G9zGPG5FNcy5c91cn5Mkm4B9kHNj1bp7G/vMVvEDUJl/w= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1557868000242733.3819536933315; Tue, 14 May 2019 14:06:40 -0700 (PDT) Received: from localhost ([127.0.0.1]:54188 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hQedA-000582-4O for importer@patchew.org; Tue, 14 May 2019 17:06:36 -0400 Received: from eggs.gnu.org ([209.51.188.92]:39003) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hQeV2-0007lu-NN for qemu-devel@nongnu.org; Tue, 14 May 2019 16:58:14 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hQeIl-0007cB-2f for qemu-devel@nongnu.org; Tue, 14 May 2019 16:45:32 -0400 Received: from mail-lf1-x144.google.com ([2a00:1450:4864:20::144]:45619) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hQeIk-0007Vb-Nq for qemu-devel@nongnu.org; Tue, 14 May 2019 16:45:31 -0400 Received: by mail-lf1-x144.google.com with SMTP id n22so220195lfe.12 for ; Tue, 14 May 2019 13:45:27 -0700 (PDT) Received: from octofox.cadence.com (jcmvbkbc-1-pt.tunnel.tserv24.sto1.ipv6.he.net. [2001:470:27:1fa::2]) by smtp.gmail.com with ESMTPSA id 78sm4011lje.81.2019.05.14.13.45.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 14 May 2019 13:45:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=FXb6aboJp5Icq+FwNf9gA5rmibu3GFrNef50fwTDTPg=; b=KlkZZMZa+q+uA6Pkttf8tc6v+XK1gPv9hxxzCQCNeS1wq2HX5Nd/ARG6xPsy/jvSOs JMShqZxtLwB9cAuAaCbc/9426yH768oYn+5s/WVQzH3EoD9nq+f+L7zIGrxrN3TVPF+5 bs1tpm9lOfWGVQqP3z4rFOIJANKR1azDd2314Ys67WbWk5cedP9br/+sW9cdELEoSv35 jTfsTa/D312obWzPqzQ+mNBVPOZy3mOFpnS/JI+iXX92uGowYyzRfm/QJFuGzZaQjhQz pBYgeJJDps6Gk9ySId5pDNLwp+XFyMYkGIhRWu7/gqvi8meKoVyTv9em/17SDh2DqC6m pfvA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=FXb6aboJp5Icq+FwNf9gA5rmibu3GFrNef50fwTDTPg=; b=Vb4shJVnK6VqAUFxkMDFQ4KFn4/T7iQa8wmtN5zuKUY9AEYrdasXiv9BEPCxgO7Uwh AUNgxL8AmsAvDtmRGyUpFwToX1YQrSl7Ob0i3feiC6+rLUsFvX+7YqVwxdZrpZfcFncJ Qc5AKm5PKNJqXI98OqaQiuT7Y4mcJrPwd/OAlvgf35os2miMVg6ifEUIFuKm3/VyrPjI hvkut9BIVQTte5gflqkRn5Pa2CjNOLkAQFcSFuW02/rxo+eHYSPo44A8bv58CZiFLfoj YkarOo9ysI9ZS9Bif3YQgBZdqtv3i/LCnA3lOeth+BXNse5KiSeE8y2g4fKWQDaZtjo4 2oiw== X-Gm-Message-State: APjAAAXHuN4Gr9Q8a2SvVSSkGVI2YScSslCMvjK5Y0gzCB2CTriqtAC6 m/Ah7AxryFs5X/4fxJ/K8HNM55nNb5A= X-Google-Smtp-Source: APXvYqxSvg/4cQ1JhSl+358rAsvj4erFdhsGrsS/ACvQ3q0JhGTh2O9PNsETmwmcU+u4kqHGtWI6/g== X-Received: by 2002:a19:9c8f:: with SMTP id f137mr18065772lfe.94.1557866726555; Tue, 14 May 2019 13:45:26 -0700 (PDT) From: Max Filippov To: qemu-devel@nongnu.org Date: Tue, 14 May 2019 13:44:47 -0700 Message-Id: <20190514204447.17486-10-jcmvbkbc@gmail.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190514204447.17486-1-jcmvbkbc@gmail.com> References: <20190514204447.17486-1-jcmvbkbc@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::144 Subject: [Qemu-devel] [PATCH 9/9] target/xtensa: implement exclusive access option X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Max Filippov Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The Exclusive Instructions provide a general-purpose mechanism for atomic updates of memory-based synchronization variables that can be used for exclusion algorithms. Use cmpxchg-based implementation that is sufficient for the typical use of exclusive access in atomic operations. Signed-off-by: Max Filippov --- target/xtensa/cpu.c | 1 + target/xtensa/cpu.h | 2 + target/xtensa/helper.h | 1 + target/xtensa/op_helper.c | 42 ++++++++++++++++ target/xtensa/overlay_tool.h | 8 ++- target/xtensa/translate.c | 100 ++++++++++++++++++++++++++++++++++= ++++ tests/tcg/xtensa/test_exclusive.S | 48 ++++++++++++++++++ 7 files changed, 200 insertions(+), 2 deletions(-) create mode 100644 tests/tcg/xtensa/test_exclusive.S diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 4215a1881ec7..54c834228a91 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -82,6 +82,7 @@ static void xtensa_cpu_reset(CPUState *s) XTENSA_OPTION_ATOMCTL) ? 0x28 : 0x15; env->sregs[CONFIGID0] =3D env->config->configid[0]; env->sregs[CONFIGID1] =3D env->config->configid[1]; + env->exclusive_addr =3D -1; =20 #ifndef CONFIG_USER_ONLY reset_mmu(env); diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 8301923e4c4a..28a6fb4d796d 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -527,6 +527,8 @@ typedef struct CPUXtensaState { } fregs[16]; float_status fp_status; uint32_t windowbase_next; + uint32_t exclusive_addr; + uint32_t exclusive_val; =20 #ifndef CONFIG_USER_ONLY xtensa_tlb_entry itlb[7][MAX_TLB_WAY_SIZE]; diff --git a/target/xtensa/helper.h b/target/xtensa/helper.h index 9216bee57e9a..8532de0b35f5 100644 --- a/target/xtensa/helper.h +++ b/target/xtensa/helper.h @@ -24,6 +24,7 @@ DEF_HELPER_1(check_interrupts, void, env) DEF_HELPER_2(intset, void, env, i32) DEF_HELPER_2(intclear, void, env, i32) DEF_HELPER_3(check_atomctl, void, env, i32, i32) +DEF_HELPER_4(check_exclusive, void, env, i32, i32, i32) DEF_HELPER_2(wsr_memctl, void, env, i32) =20 DEF_HELPER_2(itlb_hit_test, void, env, i32) diff --git a/target/xtensa/op_helper.c b/target/xtensa/op_helper.c index 04971b044fac..09f4962d008a 100644 --- a/target/xtensa/op_helper.c +++ b/target/xtensa/op_helper.c @@ -130,6 +130,48 @@ void HELPER(check_atomctl)(CPUXtensaState *env, uint32= _t pc, uint32_t vaddr) } } =20 +void HELPER(check_exclusive)(CPUXtensaState *env, uint32_t pc, uint32_t va= ddr, + uint32_t is_write) +{ + uint32_t paddr, page_size, access; + uint32_t atomctl =3D env->sregs[ATOMCTL]; + int rc =3D xtensa_get_physical_addr(env, true, vaddr, is_write, + xtensa_get_cring(env), &paddr, + &page_size, &access); + + if (rc) { + HELPER(exception_cause_vaddr)(env, pc, rc, vaddr); + } + + /* When data cache is not configured use ATOMCTL bypass field. */ + if (!xtensa_option_enabled(env->config, XTENSA_OPTION_DCACHE)) { + access =3D PAGE_CACHE_BYPASS; + } + + switch (access & PAGE_CACHE_MASK) { + case PAGE_CACHE_WB: + atomctl >>=3D 2; + /* fall through */ + case PAGE_CACHE_WT: + atomctl >>=3D 2; + /* fall through */ + case PAGE_CACHE_BYPASS: + if ((atomctl & 0x3) =3D=3D 0) { + HELPER(exception_cause_vaddr)(env, pc, + EXCLUSIVE_ERROR_CAUSE, vaddr); + } + break; + + case PAGE_CACHE_ISOLATE: + HELPER(exception_cause_vaddr)(env, pc, + LOAD_STORE_ERROR_CAUSE, vaddr); + break; + + default: + break; + } +} + void HELPER(wsr_memctl)(CPUXtensaState *env, uint32_t v) { if (xtensa_option_enabled(env->config, XTENSA_OPTION_ICACHE)) { diff --git a/target/xtensa/overlay_tool.h b/target/xtensa/overlay_tool.h index 4925b21f0edf..f0cc33adfe05 100644 --- a/target/xtensa/overlay_tool.h +++ b/target/xtensa/overlay_tool.h @@ -76,6 +76,10 @@ #define XCHAL_HAVE_MPU 0 #endif =20 +#ifndef XCHAL_HAVE_EXCLUSIVE +#define XCHAL_HAVE_EXCLUSIVE 0 +#endif + #define XCHAL_OPTION(xchal, qemu) ((xchal) ? XTENSA_OPTION_BIT(qemu) : 0) =20 #define XTENSA_OPTIONS ( \ @@ -96,8 +100,8 @@ XCHAL_OPTION(XCHAL_HAVE_FP, XTENSA_OPTION_FP_COPROCESSOR) | \ XCHAL_OPTION(XCHAL_HAVE_RELEASE_SYNC, XTENSA_OPTION_MP_SYNCHRO) | \ XCHAL_OPTION(XCHAL_HAVE_S32C1I, XTENSA_OPTION_CONDITIONAL_STORE) | \ - XCHAL_OPTION(XCHAL_HAVE_S32C1I && XCHAL_HW_MIN_VERSION >=3D 230000, \ - XTENSA_OPTION_ATOMCTL) | \ + XCHAL_OPTION(((XCHAL_HAVE_S32C1I && XCHAL_HW_MIN_VERSION >=3D 230000) = || \ + XCHAL_HAVE_EXCLUSIVE), XTENSA_OPTION_ATOMCTL) | \ XCHAL_OPTION(XCHAL_HAVE_DEPBITS, XTENSA_OPTION_DEPBITS) | \ /* Interrupts and exceptions */ \ XCHAL_OPTION(XCHAL_HAVE_EXCEPTIONS, XTENSA_OPTION_EXCEPTION) | \ diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index 356eb9948701..158a600b4293 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -87,6 +87,8 @@ static TCGv_i32 cpu_BR8[2]; static TCGv_i32 cpu_SR[256]; static TCGv_i32 cpu_UR[256]; static TCGv_i32 cpu_windowbase_next; +static TCGv_i32 cpu_exclusive_addr; +static TCGv_i32 cpu_exclusive_val; =20 static GHashTable *xtensa_regfile_table; =20 @@ -216,6 +218,14 @@ void xtensa_translate_init(void) tcg_global_mem_new_i32(cpu_env, offsetof(CPUXtensaState, windowbase_next), "windowbase_next"); + cpu_exclusive_addr =3D + tcg_global_mem_new_i32(cpu_env, + offsetof(CPUXtensaState, exclusive_addr), + "exclusive_addr"); + cpu_exclusive_val =3D + tcg_global_mem_new_i32(cpu_env, + offsetof(CPUXtensaState, exclusive_val), + "exclusive_val"); } =20 void **xtensa_get_regfile_by_name(const char *name) @@ -1592,6 +1602,12 @@ static void translate_clrb_expstate(DisasContext *dc= , const OpcodeArg arg[], tcg_gen_andi_i32(cpu_UR[EXPSTATE], cpu_UR[EXPSTATE], ~(1u << arg[0].im= m)); } =20 +static void translate_clrex(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) +{ + tcg_gen_movi_i32(cpu_exclusive_addr, -1); +} + static void translate_const16(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { @@ -1667,6 +1683,17 @@ static void translate_extui(DisasContext *dc, const = OpcodeArg arg[], tcg_temp_free(tmp); } =20 +static void translate_getex(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) +{ + TCGv_i32 tmp =3D tcg_temp_new_i32(); + + tcg_gen_extract_i32(tmp, cpu_SR[ATOMCTL], 8, 1); + tcg_gen_deposit_i32(cpu_SR[ATOMCTL], cpu_SR[ATOMCTL], arg[0].in, 8, 1); + tcg_gen_mov_i32(arg[0].out, tmp); + tcg_temp_free(tmp); +} + static void translate_icache(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { @@ -1714,6 +1741,38 @@ static void translate_l32e(DisasContext *dc, const O= pcodeArg arg[], tcg_temp_free(addr); } =20 +#ifdef CONFIG_USER_ONLY +static void gen_check_exclusive(DisasContext *dc, TCGv_i32 addr, bool is_w= rite) +{ +} +#else +static void gen_check_exclusive(DisasContext *dc, TCGv_i32 addr, bool is_w= rite) +{ + if (!option_enabled(dc, XTENSA_OPTION_MPU)) { + TCGv_i32 tpc =3D tcg_const_i32(dc->pc); + TCGv_i32 write =3D tcg_const_i32(is_write); + + gen_helper_check_exclusive(cpu_env, tpc, addr, write); + tcg_temp_free(tpc); + tcg_temp_free(write); + } +} +#endif + +static void translate_l32ex(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) +{ + TCGv_i32 addr =3D tcg_temp_new_i32(); + + tcg_gen_mov_i32(addr, arg[1].in); + gen_load_store_alignment(dc, 2, addr, true); + gen_check_exclusive(dc, addr, false); + tcg_gen_qemu_ld_i32(arg[0].out, addr, dc->ring, MO_TEUL); + tcg_gen_mov_i32(cpu_exclusive_addr, addr); + tcg_gen_mov_i32(cpu_exclusive_val, arg[0].out); + tcg_temp_free(addr); +} + static void translate_ldst(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { @@ -2269,6 +2328,33 @@ static void translate_s32e(DisasContext *dc, const O= pcodeArg arg[], tcg_temp_free(addr); } =20 +static void translate_s32ex(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) +{ + TCGv_i32 prev =3D tcg_temp_new_i32(); + TCGv_i32 addr =3D tcg_temp_local_new_i32(); + TCGv_i32 res =3D tcg_temp_local_new_i32(); + TCGLabel *label =3D gen_new_label(); + + tcg_gen_movi_i32(res, 0); + tcg_gen_mov_i32(addr, arg[1].in); + gen_load_store_alignment(dc, 2, addr, true); + tcg_gen_brcond_i32(TCG_COND_NE, addr, cpu_exclusive_addr, label); + gen_check_exclusive(dc, addr, true); + tcg_gen_atomic_cmpxchg_i32(prev, cpu_exclusive_addr, cpu_exclusive_val, + arg[0].in, dc->cring, MO_TEUL); + tcg_gen_setcond_i32(TCG_COND_EQ, res, prev, cpu_exclusive_val); + tcg_gen_movcond_i32(TCG_COND_EQ, cpu_exclusive_val, + prev, cpu_exclusive_val, prev, cpu_exclusive_val); + tcg_gen_movi_i32(cpu_exclusive_addr, -1); + gen_set_label(label); + tcg_gen_extract_i32(arg[0].out, cpu_SR[ATOMCTL], 8, 1); + tcg_gen_deposit_i32(cpu_SR[ATOMCTL], cpu_SR[ATOMCTL], res, 8, 1); + tcg_temp_free(prev); + tcg_temp_free(addr); + tcg_temp_free(res); +} + static void translate_salt(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { @@ -3068,6 +3154,9 @@ static const XtensaOpcodeOps core_ops[] =3D { .name =3D "clrb_expstate", .translate =3D translate_clrb_expstate, }, { + .name =3D "clrex", + .translate =3D translate_clrex, + }, { .name =3D "const16", .translate =3D translate_const16, }, { @@ -3173,6 +3262,9 @@ static const XtensaOpcodeOps core_ops[] =3D { .name =3D "extw", .translate =3D translate_memw, }, { + .name =3D "getex", + .translate =3D translate_getex, + }, { .name =3D "hwwdtlba", .op_flags =3D XTENSA_OP_ILL, }, { @@ -3244,6 +3336,10 @@ static const XtensaOpcodeOps core_ops[] =3D { .translate =3D translate_l32e, .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_LOAD, }, { + .name =3D "l32ex", + .translate =3D translate_l32ex, + .op_flags =3D XTENSA_OP_LOAD, + }, { .name =3D (const char * const[]) { "l32i", "l32i.n", NULL, }, @@ -4557,6 +4653,10 @@ static const XtensaOpcodeOps core_ops[] =3D { .translate =3D translate_s32e, .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_STORE, }, { + .name =3D "s32ex", + .translate =3D translate_s32ex, + .op_flags =3D XTENSA_OP_LOAD | XTENSA_OP_STORE, + }, { .name =3D (const char * const[]) { "s32i", "s32i.n", "s32nb", NULL, }, diff --git a/tests/tcg/xtensa/test_exclusive.S b/tests/tcg/xtensa/test_excl= usive.S new file mode 100644 index 000000000000..7757a552ea00 --- /dev/null +++ b/tests/tcg/xtensa/test_exclusive.S @@ -0,0 +1,48 @@ +#include "macros.inc" + +test_suite exclusive + +#if XCHAL_HAVE_EXCLUSIVE + +test exclusive_nowrite + movi a2, 0x29 + wsr a2, atomctl + clrex + movi a2, 1f + movi a3, 1 + s32ex a3, a2 + getex a3 + assert eqi, a3, 0 + l32i a3, a2, 0 + assert eqi, a3, 3 + +.data +.align 4 +1: + .word 3 +.text +test_end + +test exclusive_write + movi a2, 0x29 + wsr a2, atomctl + movi a2, 1f + l32ex a3, a2 + assert eqi, a3, 3 + movi a3, 2 + s32ex a3, a2 + getex a3 + assert eqi, a3, 1 + l32i a3, a2, 0 + assert eqi, a3, 2 + +.data +.align 4 +1: + .word 3 +.text +test_end + +#endif + +test_suite_end --=20 2.11.0