From nobody Fri Apr 19 13:08:09 2024 Delivered-To: importer@patchew.org Received-SPF: temperror (zoho.com: Error in retrieving data from DNS) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1557814667; cv=none; d=zoho.com; s=zohoarc; b=gCPr130l3haIPD4B1Y5rHU5pN6vQ0EElWeLFpaAbufREagr593uXyPfpzk1A4v36cKBbJxQM1oHn6ddrzFH79BWJxxFpDuRLNAy4H2Ch5O3+zSNHSrm/lRhAo3e/RLiHG2PnOoXm2qdllYSqVdrwAt4DyD73bKasEzTHY6rOizs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1557814667; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=Z1U56j4LraiEu00XsHUWp+mKELyPgusoo03JAJvPE4Y=; b=XiVC22ZkS1eaXezSuuVXXtXphS/OVlVs2II77PhIhdqddEVrfQRO16g+LT7INjpRBPd5A0i9pi15Kc0nEZIBGqTe2nAfpiqZTC0gv18Jw2p02VfSCSRzjRjNQZBbayC31bWu6ECot6KbLA9JI1R5F4ltDk0QKZ5G881KTo7tczI= ARC-Authentication-Results: i=1; mx.zoho.com; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1557814667152532.9506682811646; Mon, 13 May 2019 23:17:47 -0700 (PDT) Received: from localhost ([127.0.0.1]:40086 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hQQkm-00054H-0J for importer@patchew.org; Tue, 14 May 2019 02:17:32 -0400 Received: from eggs.gnu.org ([209.51.188.92]:51877) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hQQig-0003Y0-QK for qemu-devel@nongnu.org; Tue, 14 May 2019 02:15:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hQQif-0007g7-BL for qemu-devel@nongnu.org; Tue, 14 May 2019 02:15:22 -0400 Received: from mail03.asahi-net.or.jp ([202.224.55.15]:45345) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hQQif-0007a5-0m for qemu-devel@nongnu.org; Tue, 14 May 2019 02:15:21 -0400 Received: from h61-195-96-97.vps.ablenet.jp (h61-195-96-97.vps.ablenet.jp [61.195.96.97]) (Authenticated sender: PQ4Y-STU) by mail03.asahi-net.or.jp (Postfix) with ESMTPA id 1A703423A8; Tue, 14 May 2019 15:15:17 +0900 (JST) Received: from ysato.dip.jp (ZM005235.ppp.dion.ne.jp [222.8.5.235]) by h61-195-96-97.vps.ablenet.jp (Postfix) with ESMTPSA id 73D2A240086; Tue, 14 May 2019 15:15:16 +0900 (JST) From: Yoshinori Sato To: qemu-devel@nongnu.org Date: Tue, 14 May 2019 15:14:56 +0900 Message-Id: <20190514061458.125225-11-ysato@users.sourceforge.jp> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190514061458.125225-1-ysato@users.sourceforge.jp> References: <20190514061458.125225-1-ysato@users.sourceforge.jp> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 202.224.55.15 Subject: [Qemu-devel] [PATCH v12 10/12] hw/registerfields.h: Add 8bit and 16bit register macros. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, richard.henderson@linaro.org, Yoshinori Sato , philmd@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Some RX peripheral using 8bit and 16bit registers. Added 8bit and 16bit APIs. Signed-off-by: Yoshinori Sato --- include/hw/registerfields.h | 32 +++++++++++++++++++++++++++++++- 1 file changed, 31 insertions(+), 1 deletion(-) diff --git a/include/hw/registerfields.h b/include/hw/registerfields.h index 2659a58737..a0bb0654d6 100644 --- a/include/hw/registerfields.h +++ b/include/hw/registerfields.h @@ -22,6 +22,14 @@ enum { A_ ## reg =3D (addr) }; = \ enum { R_ ## reg =3D (addr) / 4 }; =20 +#define REG8(reg, addr) \ + enum { A_ ## reg =3D (addr) }; = \ + enum { R_ ## reg =3D (addr) }; + +#define REG16(reg, addr) \ + enum { A_ ## reg =3D (addr) }; = \ + enum { R_ ## reg =3D (addr) / 2 }; + /* Define SHIFT, LENGTH and MASK constants for a field within a register */ =20 /* This macro will define R_FOO_BAR_MASK, R_FOO_BAR_SHIFT and R_FOO_BAR_LE= NGTH @@ -34,6 +42,12 @@ MAKE_64BIT_MASK(shift, length)}; =20 /* Extract a field from a register */ +#define FIELD_EX8(storage, reg, field) \ + extract8((storage), R_ ## reg ## _ ## field ## _SHIFT, \ + R_ ## reg ## _ ## field ## _LENGTH) +#define FIELD_EX16(storage, reg, field) \ + extract16((storage), R_ ## reg ## _ ## field ## _SHIFT, \ + R_ ## reg ## _ ## field ## _LENGTH) #define FIELD_EX32(storage, reg, field) \ extract32((storage), R_ ## reg ## _ ## field ## _SHIFT, \ R_ ## reg ## _ ## field ## _LENGTH) @@ -49,6 +63,22 @@ * Assigning values larger then the target field will result in * compilation warnings. */ +#define FIELD_DP8(storage, reg, field, val) ({ \ + struct { \ + unsigned int v:R_ ## reg ## _ ## field ## _LENGTH; \ + } v =3D { .v =3D val }; = \ + uint8_t d; \ + d =3D deposit32((storage), R_ ## reg ## _ ## field ## _SHIFT, = \ + R_ ## reg ## _ ## field ## _LENGTH, v.v); \ + d; }) +#define FIELD_DP16(storage, reg, field, val) ({ \ + struct { \ + unsigned int v:R_ ## reg ## _ ## field ## _LENGTH; \ + } v =3D { .v =3D val }; = \ + uint16_t d; \ + d =3D deposit32((storage), R_ ## reg ## _ ## field ## _SHIFT, = \ + R_ ## reg ## _ ## field ## _LENGTH, v.v); \ + d; }) #define FIELD_DP32(storage, reg, field, val) ({ \ struct { \ unsigned int v:R_ ## reg ## _ ## field ## _LENGTH; \ @@ -57,7 +87,7 @@ d =3D deposit32((storage), R_ ## reg ## _ ## field ## _SHIFT, = \ R_ ## reg ## _ ## field ## _LENGTH, v.v); \ d; }) -#define FIELD_DP64(storage, reg, field, val) ({ \ +#define FIELD_DP64(storage, reg, field, val) ({ \ struct { \ unsigned int v:R_ ## reg ## _ ## field ## _LENGTH; \ } v =3D { .v =3D val }; = \ --=20 2.11.0