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[97.113.13.231]) by smtp.gmail.com with ESMTPSA id u3sm238151pfn.29.2019.05.13.17.05.43 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 13 May 2019 17:05:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Apjrpc9r2vVqQ7yc2aMigKmKRzCXYxZj/bYKRWwstvE=; b=fISwRqojkaxngkWggVNvxGLn3q40QCb/55RLyJrc7Bl8Dc408nRTurUnSDSHtwiIjw df5gInGaEurHbF6rNeWrnBYSoWU5y1JhaG8zLLsie3vPWsE+Cru67ZtIHjGLFmOtZMKL EoGaidpbinGRm2V/LhEPu3WF1pwm/RNQ/UbOLczfswprMAjq1zvbEVA7Hn0wsuTpfuGF hF0GA+Uc0oddUzNXHkACpgdQQnepPce6jRQY2ewlmq3AspKl1+vJAW0diENrjAR8y0Rz 9DjZ3ARczRKd36nhObK8UGjWrLpKSFIKU1C5V8DQ8tNvTBGC0CVgdy6n46lVHZTPyzMn uZog== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Apjrpc9r2vVqQ7yc2aMigKmKRzCXYxZj/bYKRWwstvE=; b=LvC5USm1SRExGnrZyJAX5OlGN+Rcwr9LxWhQysV3lSj9sEJyYtUz+26sxzm47CWaSO A/WNq+q4YLqBxEG3GWe+zziYC/i3O2I5f50/NqmfAcOk30fVdj+KN+UFkdaRbz5hlAAF roBOVfZsm8h4tuHg2DYIUHZZYZZOfCd9K5SYFt/NJvo6g1PlFgJ1lA6eBPRHOBMOqHqI uzd7bKCknO3wFyLT16Ha3GmQAaVwcZ9JWnH5tKwqvfV4ZV+oqRacNexUo7W1WVLCqtAP NIu/f7Y3WHeylOjA+mmRYR/dhe9payGNGnOLAKfQ5C57I0ZPNJe9oNPSz1/eSoUm46YE 4mzw== X-Gm-Message-State: APjAAAUk55iIEul+Ihh0Tjccb62HeBHylpV8IJkxuH3KR8umGQg2mJUT twRsebL//2sDIdXvI6p4mPpQkEc+e1w= X-Google-Smtp-Source: APXvYqyU3YuZAzeq9yk9t17gi7CntWVt1AGmv7bkw2kIpHYK7NrSviENq6mSKP2ECXTpff+l37aKLA== X-Received: by 2002:a63:d10:: with SMTP id c16mr34108220pgl.156.1557792344190; Mon, 13 May 2019 17:05:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 13 May 2019 17:05:10 -0700 Message-Id: <20190514000540.4313-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190514000540.4313-1-richard.henderson@linaro.org> References: <20190514000540.4313-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PULL 01/31] tcg: Implement tcg_gen_gvec_3i() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linux.org, David Hildenbrand Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: David Hildenbrand Let's add tcg_gen_gvec_3i(), similar to tcg_gen_gvec_2i(), however without introducing "gen_helper_gvec_3i *fnoi", as it isn't needed for now. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: David Hildenbrand Message-Id: <20190416185301.25344-2-david@redhat.com> Signed-off-by: Richard Henderson --- tcg/tcg-op-gvec.h | 24 ++++++++ tcg/tcg-op-gvec.c | 139 ++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 163 insertions(+) diff --git a/tcg/tcg-op-gvec.h b/tcg/tcg-op-gvec.h index 850da32ded..c093243c4c 100644 --- a/tcg/tcg-op-gvec.h +++ b/tcg/tcg-op-gvec.h @@ -164,6 +164,27 @@ typedef struct { bool load_dest; } GVecGen3; =20 +typedef struct { + /* + * Expand inline as a 64-bit or 32-bit integer. Only one of these will= be + * non-NULL. + */ + void (*fni8)(TCGv_i64, TCGv_i64, TCGv_i64, int64_t); + void (*fni4)(TCGv_i32, TCGv_i32, TCGv_i32, int32_t); + /* Expand inline with a host vector type. */ + void (*fniv)(unsigned, TCGv_vec, TCGv_vec, TCGv_vec, int64_t); + /* Expand out-of-line helper w/descriptor, data in descriptor. */ + gen_helper_gvec_3 *fno; + /* The opcode, if any, to which this corresponds. */ + TCGOpcode opc; + /* The vector element size, if applicable. */ + uint8_t vece; + /* Prefer i64 to v64. */ + bool prefer_i64; + /* Load dest as a 3rd source operand. */ + bool load_dest; +} GVecGen3i; + typedef struct { /* Expand inline as a 64-bit or 32-bit integer. Only one of these will be non-NULL. */ @@ -193,6 +214,9 @@ void tcg_gen_gvec_2s(uint32_t dofs, uint32_t aofs, uint= 32_t oprsz, uint32_t maxsz, TCGv_i64 c, const GVecGen2s *); void tcg_gen_gvec_3(uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t oprsz, uint32_t maxsz, const GVecGen3 *); +void tcg_gen_gvec_3i(uint32_t dofs, uint32_t aofs, uint32_t bofs, + uint32_t oprsz, uint32_t maxsz, int64_t c, + const GVecGen3i *); void tcg_gen_gvec_4(uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t = cofs, uint32_t oprsz, uint32_t maxsz, const GVecGen4 *); =20 diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c index 0996ef0812..f831adb4e7 100644 --- a/tcg/tcg-op-gvec.c +++ b/tcg/tcg-op-gvec.c @@ -663,6 +663,29 @@ static void expand_3_i32(uint32_t dofs, uint32_t aofs, tcg_temp_free_i32(t0); } =20 +static void expand_3i_i32(uint32_t dofs, uint32_t aofs, uint32_t bofs, + uint32_t oprsz, int32_t c, bool load_dest, + void (*fni)(TCGv_i32, TCGv_i32, TCGv_i32, int32_= t)) +{ + TCGv_i32 t0 =3D tcg_temp_new_i32(); + TCGv_i32 t1 =3D tcg_temp_new_i32(); + TCGv_i32 t2 =3D tcg_temp_new_i32(); + uint32_t i; + + for (i =3D 0; i < oprsz; i +=3D 4) { + tcg_gen_ld_i32(t0, cpu_env, aofs + i); + tcg_gen_ld_i32(t1, cpu_env, bofs + i); + if (load_dest) { + tcg_gen_ld_i32(t2, cpu_env, dofs + i); + } + fni(t2, t0, t1, c); + tcg_gen_st_i32(t2, cpu_env, dofs + i); + } + tcg_temp_free_i32(t0); + tcg_temp_free_i32(t1); + tcg_temp_free_i32(t2); +} + /* Expand OPSZ bytes worth of three-operand operations using i32 elements.= */ static void expand_4_i32(uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t cofs, uint32_t oprsz, bool write_aofs, @@ -770,6 +793,29 @@ static void expand_3_i64(uint32_t dofs, uint32_t aofs, tcg_temp_free_i64(t0); } =20 +static void expand_3i_i64(uint32_t dofs, uint32_t aofs, uint32_t bofs, + uint32_t oprsz, int64_t c, bool load_dest, + void (*fni)(TCGv_i64, TCGv_i64, TCGv_i64, int64_= t)) +{ + TCGv_i64 t0 =3D tcg_temp_new_i64(); + TCGv_i64 t1 =3D tcg_temp_new_i64(); + TCGv_i64 t2 =3D tcg_temp_new_i64(); + uint32_t i; + + for (i =3D 0; i < oprsz; i +=3D 8) { + tcg_gen_ld_i64(t0, cpu_env, aofs + i); + tcg_gen_ld_i64(t1, cpu_env, bofs + i); + if (load_dest) { + tcg_gen_ld_i64(t2, cpu_env, dofs + i); + } + fni(t2, t0, t1, c); + tcg_gen_st_i64(t2, cpu_env, dofs + i); + } + tcg_temp_free_i64(t0); + tcg_temp_free_i64(t1); + tcg_temp_free_i64(t2); +} + /* Expand OPSZ bytes worth of three-operand operations using i64 elements.= */ static void expand_4_i64(uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t cofs, uint32_t oprsz, bool write_aofs, @@ -883,6 +929,35 @@ static void expand_3_vec(unsigned vece, uint32_t dofs,= uint32_t aofs, tcg_temp_free_vec(t0); } =20 +/* + * Expand OPSZ bytes worth of three-vector operands and an immediate opera= nd + * using host vectors. + */ +static void expand_3i_vec(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t tysz, + TCGType type, int64_t c, bool load_dest, + void (*fni)(unsigned, TCGv_vec, TCGv_vec, TCGv_v= ec, + int64_t)) +{ + TCGv_vec t0 =3D tcg_temp_new_vec(type); + TCGv_vec t1 =3D tcg_temp_new_vec(type); + TCGv_vec t2 =3D tcg_temp_new_vec(type); + uint32_t i; + + for (i =3D 0; i < oprsz; i +=3D tysz) { + tcg_gen_ld_vec(t0, cpu_env, aofs + i); + tcg_gen_ld_vec(t1, cpu_env, bofs + i); + if (load_dest) { + tcg_gen_ld_vec(t2, cpu_env, dofs + i); + } + fni(vece, t2, t0, t1, c); + tcg_gen_st_vec(t2, cpu_env, dofs + i); + } + tcg_temp_free_vec(t0); + tcg_temp_free_vec(t1); + tcg_temp_free_vec(t2); +} + /* Expand OPSZ bytes worth of four-operand operations using host vectors. = */ static void expand_4_vec(unsigned vece, uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t cofs, uint32_t oprsz, @@ -1174,6 +1249,70 @@ void tcg_gen_gvec_3(uint32_t dofs, uint32_t aofs, ui= nt32_t bofs, } } =20 +/* Expand a vector operation with three vectors and an immediate. */ +void tcg_gen_gvec_3i(uint32_t dofs, uint32_t aofs, uint32_t bofs, + uint32_t oprsz, uint32_t maxsz, int64_t c, + const GVecGen3i *g) +{ + TCGType type; + uint32_t some; + + check_size_align(oprsz, maxsz, dofs | aofs | bofs); + check_overlap_3(dofs, aofs, bofs, maxsz); + + type =3D 0; + if (g->fniv) { + type =3D choose_vector_type(g->opc, g->vece, oprsz, g->prefer_i64); + } + switch (type) { + case TCG_TYPE_V256: + /* + * Recall that ARM SVE allows vector sizes that are not a + * power of 2, but always a multiple of 16. The intent is + * that e.g. size =3D=3D 80 would be expanded with 2x32 + 1x16. + */ + some =3D QEMU_ALIGN_DOWN(oprsz, 32); + expand_3i_vec(g->vece, dofs, aofs, bofs, some, 32, TCG_TYPE_V256, + c, g->load_dest, g->fniv); + if (some =3D=3D oprsz) { + break; + } + dofs +=3D some; + aofs +=3D some; + bofs +=3D some; + oprsz -=3D some; + maxsz -=3D some; + /* fallthru */ + case TCG_TYPE_V128: + expand_3i_vec(g->vece, dofs, aofs, bofs, oprsz, 16, TCG_TYPE_V128, + c, g->load_dest, g->fniv); + break; + case TCG_TYPE_V64: + expand_3i_vec(g->vece, dofs, aofs, bofs, oprsz, 8, TCG_TYPE_V64, + c, g->load_dest, g->fniv); + break; + + case 0: + if (g->fni8 && check_size_impl(oprsz, 8)) { + expand_3i_i64(dofs, aofs, bofs, oprsz, c, g->load_dest, g->fni= 8); + } else if (g->fni4 && check_size_impl(oprsz, 4)) { + expand_3i_i32(dofs, aofs, bofs, oprsz, c, g->load_dest, g->fni= 4); + } else { + assert(g->fno !=3D NULL); + tcg_gen_gvec_3_ool(dofs, aofs, bofs, oprsz, maxsz, c, g->fno); + return; + } + break; + + default: + g_assert_not_reached(); + } + + if (oprsz < maxsz) { + expand_clr(dofs + oprsz, maxsz - oprsz); + } +} + /* Expand a vector four-operand operation. */ void tcg_gen_gvec_4(uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t = cofs, uint32_t oprsz, uint32_t maxsz, const GVecGen4 *g) --=20 2.17.1 From nobody Fri Apr 19 16:27:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1557792594; cv=none; d=zoho.com; s=zohoarc; b=nn09LjGWwovy1S5fvyqLV4pu5EMTHUQBeTKlg1dsvDcOrW6rE+4YdQ0B3LnR77zS2TzfQ37suYhNl5mVDoKdmUm2X1jR9Ci2j4xCZ9UA6vMWUysP2gZ07NpEItCaqDJymaA4mzg8Xj7jr6TbYJqKRqYXUqb4BDcN3y1DGHZUKV4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1557792594; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=I6td3WuBBk5Qpr2iJ7wAnroVlDoSyj0rbd0/PnMjxvM=; b=YjXORqwFY2x6rlpxHOz5PXbrfkispG/KRAnRks0jhEXCi+WhXxCqunUGPUEK6AuRR80VDz/SDilKhs/pj9UIiDnsArPEhDGCuoUXADCH5+gOGCHe5RoVtJ6tLPekK6yPGL94JKKARs7e3KQtvn00k+eSFAbGG/CX6CMk0OTFWcg= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 155779259454976.21485435797479; Mon, 13 May 2019 17:09:54 -0700 (PDT) Received: from localhost ([127.0.0.1]:36603 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hQL0x-000337-Go for importer@patchew.org; Mon, 13 May 2019 20:09:51 -0400 Received: from eggs.gnu.org ([209.51.188.92]:50780) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hQKxx-0001cr-E4 for qemu-devel@nongnu.org; Mon, 13 May 2019 20:07:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hQKx8-00035H-SK for qemu-devel@nongnu.org; Mon, 13 May 2019 20:06:45 -0400 Received: from mail-pl1-x634.google.com ([2607:f8b0:4864:20::634]:41400) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hQKx3-0002uf-3g for qemu-devel@nongnu.org; Mon, 13 May 2019 20:05:52 -0400 Received: by mail-pl1-x634.google.com with SMTP id f12so5249144plt.8 for ; Mon, 13 May 2019 17:05:47 -0700 (PDT) Received: from localhost.localdomain (97-113-13-231.tukw.qwest.net. [97.113.13.231]) by smtp.gmail.com with ESMTPSA id u3sm238151pfn.29.2019.05.13.17.05.44 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 13 May 2019 17:05:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=I6td3WuBBk5Qpr2iJ7wAnroVlDoSyj0rbd0/PnMjxvM=; b=sBXrfU3h7DR8iOmdcNVwa3erjb1ZKldKP6Cm7+2f/rnMLVzFlj6A5nGT9fWeQh7iob WqlZrJe+1lSiEbRNvw7K7uWJyRrRWc4xdB45wwPXImlIsgQd+kuSWLkWC5FY+y1PaPqs btYVefJG0d2qEJqf61xxCT4SPE9wM/fqPbzH7Mmba5d+5eWeayHUFwmLwfkA5iGE37uo 84uxp3ZBOs+y0LPl/5ThT0l29Q7YyoL+UomSkt9jTPBkBkuMoFJS2j5L30jLDBsu5OYW Hfg3Ljyed6HMncCMD3E8VJOQS02z+wgfeSpPFKrH8F1e1bCc1ugKfhtWTH+coBVlzNqS Qdng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=I6td3WuBBk5Qpr2iJ7wAnroVlDoSyj0rbd0/PnMjxvM=; b=Nsr+8hQ3uh762datARiizn6MNhQ8GeyjcuH0QwL8GwygVbQzwHaxPEki3V77ptkTlb yihwm0FsvDlLOhtB45CjKcfGjgCHPb+YkwS7DVlfWR9GV6JTISlT1N79BTQN2+WQeSF/ ifgt5ALEpFmF06nPIbNNoXRmYr0mMMo0cmtF2gOb8r1zXApGnD5AYTdRs2yxlcEDQwIt dxHDCn1CzROsuBqQtEkgYzmAejzUHqxDVOvSnneThIhft3mqfPNQsSKKRFrkEcCjIMzi qS7pzQHc3H5awwKpEaSZtEslaiGrPtIJJMhGHQY7nEGybIpnR8jwf443seoNzBprKC/a sQpQ== X-Gm-Message-State: APjAAAUskd5KcDe9YBR4NtGV1KBs+6nMvLI410GU0k96sk1ihM56Vp1L Dh/QSDMRmYfJpMRlZsJxuYADFqf4Bws= X-Google-Smtp-Source: APXvYqydDPHJ4tv5gigb7yfTDJn1bI2uQaOOScuhExGPscgY3WcmdeugmJZ874rvAm5tjidt9fSwXA== X-Received: by 2002:a17:902:8c82:: with SMTP id t2mr26391194plo.256.1557792345431; Mon, 13 May 2019 17:05:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 13 May 2019 17:05:11 -0700 Message-Id: <20190514000540.4313-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190514000540.4313-1-richard.henderson@linaro.org> References: <20190514000540.4313-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::634 Subject: [Qemu-devel] [PULL 02/31] tcg: Do not recreate INDEX_op_neg_vec unless supported X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linux.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Use tcg_can_emit_vec_op instead of just TCG_TARGET_HAS_neg_vec, so that we check the type and vece for the actual operation. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- tcg/optimize.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index 5150c38a25..24faa06260 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -734,9 +734,13 @@ void tcg_optimize(TCGContext *s) } else if (opc =3D=3D INDEX_op_sub_i64) { neg_op =3D INDEX_op_neg_i64; have_neg =3D TCG_TARGET_HAS_neg_i64; - } else { + } else if (TCG_TARGET_HAS_neg_vec) { + TCGType type =3D TCGOP_VECL(op) + TCG_TYPE_V64; + unsigned vece =3D TCGOP_VECE(op); neg_op =3D INDEX_op_neg_vec; - have_neg =3D TCG_TARGET_HAS_neg_vec; + have_neg =3D tcg_can_emit_vec_op(neg_op, type, vece) >= 0; + } else { + break; } if (!have_neg) { break; --=20 2.17.1 From nobody Fri Apr 19 16:27:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1557814197; cv=none; d=zoho.com; s=zohoarc; b=BBKtJrXUEWTt1C4UjePtDaLfJabCP3Omq3RuUNNIID49N74MZw2ULi/b3rRhLLkm/vklpinyt7FQYbfwskDKVDm88T1CWJkM2njEPphtf0WDkiX11pWXReVzKCw+t6CWejo0UznjfSeo7NbpZ/8quddSxNUbLR0UfVqHSMcPSi8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1557814197; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=JF2bKE9XmhoHbt9KR1NJ6aVBR5o9hUq7Nq5BVGZIG24=; b=g7PYYyMeXoq4RZeWE21EyxsCAjuxh9VVTe949AzyPDUX0dtwHhVGjL8RHZoWaqoUXOfO2UlO01rykFqnm6yWIyLoSdYkEUjLFnbZjoM+EnIndZYL00UeSluwikAbnAe9e50zqTz8F5R0nDSj0yaTfdC0VdsvUsKjfW2Vn7aExjk= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1557814197133492.28707570787424; Mon, 13 May 2019 23:09:57 -0700 (PDT) Received: from localhost ([127.0.0.1]:39967 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hQQcm-0001Zw-Ar for importer@patchew.org; Tue, 14 May 2019 02:09:16 -0400 Received: from eggs.gnu.org ([209.51.188.92]:47663) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hQQbt-0001IT-QY for qemu-devel@nongnu.org; Tue, 14 May 2019 02:08:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hQQbs-00061F-OA for qemu-devel@nongnu.org; Tue, 14 May 2019 02:08:21 -0400 Received: from mail-pl1-x633.google.com ([2607:f8b0:4864:20::633]:44557) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hQKx6-0002xw-RC for qemu-devel@nongnu.org; Mon, 13 May 2019 20:05:54 -0400 Received: by mail-pl1-x633.google.com with SMTP id d3so7261676plj.11 for ; Mon, 13 May 2019 17:05:48 -0700 (PDT) Received: from localhost.localdomain (97-113-13-231.tukw.qwest.net. [97.113.13.231]) by smtp.gmail.com with ESMTPSA id u3sm238151pfn.29.2019.05.13.17.05.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 13 May 2019 17:05:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=JF2bKE9XmhoHbt9KR1NJ6aVBR5o9hUq7Nq5BVGZIG24=; b=LcN1CWtejXlR4vPyIVND7D+/ad9xERF+38DPtvt1fWZ9u+6yhisaiq+OT9dfkUb7d0 P+5v23BgYWG1N57AWYPOr/A6yQxvFMQY9tVirHSHBPZe02nyAkyHamb0UUlHL7xZrHOo q9WWif05Q6upWGi84sAHzMkMeXkcEpJbAPhkaX08wMP+zey+f0nnHqPpDdKMJHg26Ua7 6VIa1ins50U4KpmUuoEYGhWpIZMERoxp8okUO3RkKgTtUdY+CuulqfOmdg6EVngKP3Gi 38/Pv+B3ntzaw/d8ZS5+XQklQGe/G7tnBIXOIc/D9qR7dyVzZumRA6hy0vbCODHMHMRk lkzA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=JF2bKE9XmhoHbt9KR1NJ6aVBR5o9hUq7Nq5BVGZIG24=; b=X6KNZnAQHducFE2RXsMFOhu6OvX0b5OafnUwx2PI/p85lbzl0d0fJEw12MZNyStf7f hI38hPN2gO99islSiyknYZeydNyFB1uBoJYdiO5YU64cA6HaAG9kAYX1P/Aie5G47AaI 0hING2fFupm+yJWn9rbsghFFYVELgRNncfIJt+CcRD+UvQ4uGOD/CA7RtzgvSVI6nVKu a0ENql1+ou3eel0X/JkKGpMydzP3Kr1XJ1Kn/abC8LqDNlKn7J31sX+bxO3AQ+cc51kY lWB31VL2UXMDIjX9FaS4BIVWA6zyNxTzo80uIMXuFQq/YtN48FHKdinoTMbou7MI4iYy UiHw== X-Gm-Message-State: APjAAAUlF1Kxh4NSFfF8VZoXb+1GCTSbc6wcp8TWg+cey7kzvOEpwFXJ PZZ9a7iWTTTtI4ADf1/HyIH/NE4f5Dg= X-Google-Smtp-Source: APXvYqw2rnB7qwBXw/6aYDbeeZtK5VszDP+Ks0t68+Dbpl6bp/PhADdzXOzn3OtQ51H3HunckOnjdA== X-Received: by 2002:a17:902:2f:: with SMTP id 44mr34503984pla.137.1557792346948; Mon, 13 May 2019 17:05:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 13 May 2019 17:05:12 -0700 Message-Id: <20190514000540.4313-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190514000540.4313-1-richard.henderson@linaro.org> References: <20190514000540.4313-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::633 Subject: [Qemu-devel] [PULL 03/31] tcg: Allow add_vec, sub_vec, neg_vec, not_vec to be expanded X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linux.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) PowerPC Altivec does not support add and subtract of 64-bit elements. Prepare for that configuration by not assuming the operation is universally supported. Reviewed-by: Alex Benn=C3=A9e Reviewed-by: David Hildenbrand Signed-off-by: Richard Henderson --- tcg/tcg-op-vec.c | 49 ++++++++++++++++++++++++++++++++---------------- 1 file changed, 33 insertions(+), 16 deletions(-) diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c index 27f65600c3..cfb18682b1 100644 --- a/tcg/tcg-op-vec.c +++ b/tcg/tcg-op-vec.c @@ -226,16 +226,6 @@ void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr b, TCGArg o,= TCGType low_type) vec_gen_3(INDEX_op_st_vec, low_type, 0, ri, bi, o); } =20 -void tcg_gen_add_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) -{ - vec_gen_op3(INDEX_op_add_vec, vece, r, a, b); -} - -void tcg_gen_sub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) -{ - vec_gen_op3(INDEX_op_sub_vec, vece, r, a, b); -} - void tcg_gen_and_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) { vec_gen_op3(INDEX_op_and_vec, 0, r, a, b); @@ -296,11 +286,30 @@ void tcg_gen_eqv_vec(unsigned vece, TCGv_vec r, TCGv_= vec a, TCGv_vec b) tcg_gen_not_vec(0, r, r); } =20 +static bool do_op2(unsigned vece, TCGv_vec r, TCGv_vec a, TCGOpcode opc) +{ + TCGTemp *rt =3D tcgv_vec_temp(r); + TCGTemp *at =3D tcgv_vec_temp(a); + TCGArg ri =3D temp_arg(rt); + TCGArg ai =3D temp_arg(at); + TCGType type =3D rt->base_type; + int can; + + tcg_debug_assert(at->base_type >=3D type); + can =3D tcg_can_emit_vec_op(opc, type, vece); + if (can > 0) { + vec_gen_2(opc, type, vece, ri, ai); + } else if (can < 0) { + tcg_expand_vec_op(opc, type, vece, ri, ai); + } else { + return false; + } + return true; +} + void tcg_gen_not_vec(unsigned vece, TCGv_vec r, TCGv_vec a) { - if (TCG_TARGET_HAS_not_vec) { - vec_gen_op2(INDEX_op_not_vec, 0, r, a); - } else { + if (!TCG_TARGET_HAS_not_vec || !do_op2(vece, r, a, INDEX_op_not_vec)) { TCGv_vec t =3D tcg_const_ones_vec_matching(r); tcg_gen_xor_vec(0, r, a, t); tcg_temp_free_vec(t); @@ -309,9 +318,7 @@ void tcg_gen_not_vec(unsigned vece, TCGv_vec r, TCGv_ve= c a) =20 void tcg_gen_neg_vec(unsigned vece, TCGv_vec r, TCGv_vec a) { - if (TCG_TARGET_HAS_neg_vec) { - vec_gen_op2(INDEX_op_neg_vec, vece, r, a); - } else { + if (!TCG_TARGET_HAS_neg_vec || !do_op2(vece, r, a, INDEX_op_neg_vec)) { TCGv_vec t =3D tcg_const_zeros_vec_matching(r); tcg_gen_sub_vec(vece, r, t, a); tcg_temp_free_vec(t); @@ -409,6 +416,16 @@ static void do_op3(unsigned vece, TCGv_vec r, TCGv_vec= a, } } =20 +void tcg_gen_add_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) +{ + do_op3(vece, r, a, b, INDEX_op_add_vec); +} + +void tcg_gen_sub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) +{ + do_op3(vece, r, a, b, INDEX_op_sub_vec); +} + void tcg_gen_mul_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) { do_op3(vece, r, a, b, INDEX_op_mul_vec); --=20 2.17.1 From nobody Fri Apr 19 16:27:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[97.113.13.231]) by smtp.gmail.com with ESMTPSA id u3sm238151pfn.29.2019.05.13.17.05.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 13 May 2019 17:05:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8xY7+p0pcQEl0h4weYpizn6VlNpB51y/q9GwD4ps2n4=; b=SRWKZsIYT56ZfBHcXojcFAKnOUKDdwDewXimaPxa7avemThUQ0zkN+dW58HEY/swlP jD31d3lGBvLGPgqfI1c1vsZsmwuSCo+8wIPErs8hp5BkKhrhfzxyGVDc5dPgWq8HVmHG Egj7yiKg+rTDLwDLhSa98pJsvoQkSr0uQS0yj81v9nR6vholCKIRqa71/ucYSCV4K8wG u/8lRAqNEwU/H8Gs573Jqnu0K0OS8NTHHcRYLFMnmqu8JaP7dGDs794tB7Yyg/34rMvb RJ0CKAhk7E4YWcT8Ot2gMVjb9XoZc4mcr2gFpfVd8H0vV+6W1zbFyoYv73DsKT0qJxre 0ECA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8xY7+p0pcQEl0h4weYpizn6VlNpB51y/q9GwD4ps2n4=; b=KbFuJZ9NYRF2AS9581hJJOFMJY6aHVl8ThVmyW10ex4J5vKQ/z1qv7AZAOmARsLQZC Epx6fnY5Rwl8I1hn4eWQXzhJwyzNfBezv/OSTlnwlIvHLQ3gvslGjeV8Q7XIWeQ3pyQa iasVAkC6yCsUozNZLUh4YfxuoCQu84opPptuEt4uY0N/iuLgLyIIX+rWIeqM5H00kI/n 1hTd7n7Up78b+C8XLcHWCeATqL7WN9zr+kIZQ2KGFYw0r21FDXvkAqzlYa/kvza+F50M Q8vADMKIzafCthg34bdxfQRZN9CNXMmCFE7ux8qgVlna4EnHeszlOJ6nPuRHlMJrOx1x XEJw== X-Gm-Message-State: APjAAAWvnonQ+5Ary118JKkPYJ14HREyXoKZxQJw2YdWnMIFoiOOo6Wi Nj01M3b0mHszQCQ1SlkPUiiMt2TO1O4= X-Google-Smtp-Source: APXvYqzc8EInVNx2096/bONsQe05vyondaKgnjoRM6zmej93yydd54ZJ7iR3xX/AaVO6xFUrwbDmaw== X-Received: by 2002:a65:608a:: with SMTP id t10mr34454404pgu.155.1557792348932; Mon, 13 May 2019 17:05:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 13 May 2019 17:05:13 -0700 Message-Id: <20190514000540.4313-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190514000540.4313-1-richard.henderson@linaro.org> References: <20190514000540.4313-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::430 Subject: [Qemu-devel] [PULL 04/31] tcg: Specify optional vector requirements with a list X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linux.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Replace the single opcode in .opc with a null-terminated array in .opt_opc. We still require that all opcodes be used with the same .vece. Validate the contents of this list with CONFIG_DEBUG_TCG. All tcg_gen_*_vec functions will check any list active during .fniv expansion. Swap the active list in and out as we expand other opcodes, or take control away from the front-end function. Convert all existing vector aware front ends. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- tcg/tcg-op-gvec.h | 24 +-- tcg/tcg.h | 20 +++ target/arm/translate-sve.c | 9 +- target/arm/translate.c | 123 +++++++++----- target/ppc/translate/vmx-impl.inc.c | 7 +- tcg/tcg-op-gvec.c | 249 ++++++++++++++++------------ tcg/tcg-op-vec.c | 102 ++++++++++++ 7 files changed, 372 insertions(+), 162 deletions(-) diff --git a/tcg/tcg-op-gvec.h b/tcg/tcg-op-gvec.h index c093243c4c..ac744ff7c9 100644 --- a/tcg/tcg-op-gvec.h +++ b/tcg/tcg-op-gvec.h @@ -91,8 +91,8 @@ typedef struct { void (*fniv)(unsigned, TCGv_vec, TCGv_vec); /* Expand out-of-line helper w/descriptor. */ gen_helper_gvec_2 *fno; - /* The opcode, if any, to which this corresponds. */ - TCGOpcode opc; + /* The optional opcodes, if any, utilized by .fniv. */ + const TCGOpcode *opt_opc; /* The data argument to the out-of-line helper. */ int32_t data; /* The vector element size, if applicable. */ @@ -112,8 +112,8 @@ typedef struct { gen_helper_gvec_2 *fno; /* Expand out-of-line helper w/descriptor, data as argument. */ gen_helper_gvec_2i *fnoi; - /* The opcode, if any, to which this corresponds. */ - TCGOpcode opc; + /* The optional opcodes, if any, utilized by .fniv. */ + const TCGOpcode *opt_opc; /* The vector element size, if applicable. */ uint8_t vece; /* Prefer i64 to v64. */ @@ -131,8 +131,8 @@ typedef struct { void (*fniv)(unsigned, TCGv_vec, TCGv_vec, TCGv_vec); /* Expand out-of-line helper w/descriptor. */ gen_helper_gvec_2i *fno; - /* The opcode, if any, to which this corresponds. */ - TCGOpcode opc; + /* The optional opcodes, if any, utilized by .fniv. */ + const TCGOpcode *opt_opc; /* The data argument to the out-of-line helper. */ uint32_t data; /* The vector element size, if applicable. */ @@ -152,8 +152,8 @@ typedef struct { void (*fniv)(unsigned, TCGv_vec, TCGv_vec, TCGv_vec); /* Expand out-of-line helper w/descriptor. */ gen_helper_gvec_3 *fno; - /* The opcode, if any, to which this corresponds. */ - TCGOpcode opc; + /* The optional opcodes, if any, utilized by .fniv. */ + const TCGOpcode *opt_opc; /* The data argument to the out-of-line helper. */ int32_t data; /* The vector element size, if applicable. */ @@ -175,8 +175,8 @@ typedef struct { void (*fniv)(unsigned, TCGv_vec, TCGv_vec, TCGv_vec, int64_t); /* Expand out-of-line helper w/descriptor, data in descriptor. */ gen_helper_gvec_3 *fno; - /* The opcode, if any, to which this corresponds. */ - TCGOpcode opc; + /* The optional opcodes, if any, utilized by .fniv. */ + const TCGOpcode *opt_opc; /* The vector element size, if applicable. */ uint8_t vece; /* Prefer i64 to v64. */ @@ -194,8 +194,8 @@ typedef struct { void (*fniv)(unsigned, TCGv_vec, TCGv_vec, TCGv_vec, TCGv_vec); /* Expand out-of-line helper w/descriptor. */ gen_helper_gvec_4 *fno; - /* The opcode, if any, to which this corresponds. */ - TCGOpcode opc; + /* The optional opcodes, if any, utilized by .fniv. */ + const TCGOpcode *opt_opc; /* The data argument to the out-of-line helper. */ int32_t data; /* The vector element size, if applicable. */ diff --git a/tcg/tcg.h b/tcg/tcg.h index cfc57110a1..2c7315da25 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -692,6 +692,7 @@ struct TCGContext { #ifdef CONFIG_DEBUG_TCG int temps_in_use; int goto_tb_issue_mask; + const TCGOpcode *vecop_list; #endif =20 /* Code generation. Note that we specifically do not use tcg_insn_unit @@ -1492,4 +1493,23 @@ void helper_atomic_sto_le_mmu(CPUArchState *env, tar= get_ulong addr, Int128 val, void helper_atomic_sto_be_mmu(CPUArchState *env, target_ulong addr, Int128= val, TCGMemOpIdx oi, uintptr_t retaddr); =20 +#ifdef CONFIG_DEBUG_TCG +void tcg_assert_listed_vecop(TCGOpcode); +#else +static inline void tcg_assert_listed_vecop(TCGOpcode op) { } +#endif + +static inline const TCGOpcode *tcg_swap_vecop_list(const TCGOpcode *n) +{ +#ifdef CONFIG_DEBUG_TCG + const TCGOpcode *o =3D tcg_ctx->vecop_list; + tcg_ctx->vecop_list =3D n; + return o; +#else + return NULL; +#endif +} + +bool tcg_can_emit_vecop_list(const TCGOpcode *, TCGType, unsigned); + #endif /* TCG_H */ diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 80645db508..fa068b0e47 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -3302,29 +3302,30 @@ static bool trans_SUB_zzi(DisasContext *s, arg_rri_= esz *a) =20 static bool trans_SUBR_zzi(DisasContext *s, arg_rri_esz *a) { + static const TCGOpcode vecop_list[] =3D { INDEX_op_sub_vec, 0 }; static const GVecGen2s op[4] =3D { { .fni8 =3D tcg_gen_vec_sub8_i64, .fniv =3D tcg_gen_sub_vec, .fno =3D gen_helper_sve_subri_b, - .opc =3D INDEX_op_sub_vec, + .opt_opc =3D vecop_list, .vece =3D MO_8, .scalar_first =3D true }, { .fni8 =3D tcg_gen_vec_sub16_i64, .fniv =3D tcg_gen_sub_vec, .fno =3D gen_helper_sve_subri_h, - .opc =3D INDEX_op_sub_vec, + .opt_opc =3D vecop_list, .vece =3D MO_16, .scalar_first =3D true }, { .fni4 =3D tcg_gen_sub_i32, .fniv =3D tcg_gen_sub_vec, .fno =3D gen_helper_sve_subri_s, - .opc =3D INDEX_op_sub_vec, + .opt_opc =3D vecop_list, .vece =3D MO_32, .scalar_first =3D true }, { .fni8 =3D tcg_gen_sub_i64, .fniv =3D tcg_gen_sub_vec, .fno =3D gen_helper_sve_subri_d, - .opc =3D INDEX_op_sub_vec, + .opt_opc =3D vecop_list, .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, .vece =3D MO_64, .scalar_first =3D true } diff --git a/target/arm/translate.c b/target/arm/translate.c index 10bc53f91c..35bd426a3d 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -5861,27 +5861,31 @@ static void gen_ssra_vec(unsigned vece, TCGv_vec d,= TCGv_vec a, int64_t sh) tcg_gen_add_vec(vece, d, d, a); } =20 +static const TCGOpcode vecop_list_ssra[] =3D { + INDEX_op_sari_vec, INDEX_op_add_vec, 0 +}; + const GVecGen2i ssra_op[4] =3D { { .fni8 =3D gen_ssra8_i64, .fniv =3D gen_ssra_vec, .load_dest =3D true, - .opc =3D INDEX_op_sari_vec, + .opt_opc =3D vecop_list_ssra, .vece =3D MO_8 }, { .fni8 =3D gen_ssra16_i64, .fniv =3D gen_ssra_vec, .load_dest =3D true, - .opc =3D INDEX_op_sari_vec, + .opt_opc =3D vecop_list_ssra, .vece =3D MO_16 }, { .fni4 =3D gen_ssra32_i32, .fniv =3D gen_ssra_vec, .load_dest =3D true, - .opc =3D INDEX_op_sari_vec, + .opt_opc =3D vecop_list_ssra, .vece =3D MO_32 }, { .fni8 =3D gen_ssra64_i64, .fniv =3D gen_ssra_vec, .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .opt_opc =3D vecop_list_ssra, .load_dest =3D true, - .opc =3D INDEX_op_sari_vec, .vece =3D MO_64 }, }; =20 @@ -5915,27 +5919,31 @@ static void gen_usra_vec(unsigned vece, TCGv_vec d,= TCGv_vec a, int64_t sh) tcg_gen_add_vec(vece, d, d, a); } =20 +static const TCGOpcode vecop_list_usra[] =3D { + INDEX_op_shri_vec, INDEX_op_add_vec, 0 +}; + const GVecGen2i usra_op[4] =3D { { .fni8 =3D gen_usra8_i64, .fniv =3D gen_usra_vec, .load_dest =3D true, - .opc =3D INDEX_op_shri_vec, + .opt_opc =3D vecop_list_usra, .vece =3D MO_8, }, { .fni8 =3D gen_usra16_i64, .fniv =3D gen_usra_vec, .load_dest =3D true, - .opc =3D INDEX_op_shri_vec, + .opt_opc =3D vecop_list_usra, .vece =3D MO_16, }, { .fni4 =3D gen_usra32_i32, .fniv =3D gen_usra_vec, .load_dest =3D true, - .opc =3D INDEX_op_shri_vec, + .opt_opc =3D vecop_list_usra, .vece =3D MO_32, }, { .fni8 =3D gen_usra64_i64, .fniv =3D gen_usra_vec, .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, .load_dest =3D true, - .opc =3D INDEX_op_shri_vec, + .opt_opc =3D vecop_list_usra, .vece =3D MO_64, }, }; =20 @@ -5993,27 +6001,29 @@ static void gen_shr_ins_vec(unsigned vece, TCGv_vec= d, TCGv_vec a, int64_t sh) } } =20 +static const TCGOpcode vecop_list_sri[] =3D { INDEX_op_shri_vec, 0 }; + const GVecGen2i sri_op[4] =3D { { .fni8 =3D gen_shr8_ins_i64, .fniv =3D gen_shr_ins_vec, .load_dest =3D true, - .opc =3D INDEX_op_shri_vec, + .opt_opc =3D vecop_list_sri, .vece =3D MO_8 }, { .fni8 =3D gen_shr16_ins_i64, .fniv =3D gen_shr_ins_vec, .load_dest =3D true, - .opc =3D INDEX_op_shri_vec, + .opt_opc =3D vecop_list_sri, .vece =3D MO_16 }, { .fni4 =3D gen_shr32_ins_i32, .fniv =3D gen_shr_ins_vec, .load_dest =3D true, - .opc =3D INDEX_op_shri_vec, + .opt_opc =3D vecop_list_sri, .vece =3D MO_32 }, { .fni8 =3D gen_shr64_ins_i64, .fniv =3D gen_shr_ins_vec, .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, .load_dest =3D true, - .opc =3D INDEX_op_shri_vec, + .opt_opc =3D vecop_list_sri, .vece =3D MO_64 }, }; =20 @@ -6069,27 +6079,29 @@ static void gen_shl_ins_vec(unsigned vece, TCGv_vec= d, TCGv_vec a, int64_t sh) } } =20 +static const TCGOpcode vecop_list_sli[] =3D { INDEX_op_shli_vec, 0 }; + const GVecGen2i sli_op[4] =3D { { .fni8 =3D gen_shl8_ins_i64, .fniv =3D gen_shl_ins_vec, .load_dest =3D true, - .opc =3D INDEX_op_shli_vec, + .opt_opc =3D vecop_list_sli, .vece =3D MO_8 }, { .fni8 =3D gen_shl16_ins_i64, .fniv =3D gen_shl_ins_vec, .load_dest =3D true, - .opc =3D INDEX_op_shli_vec, + .opt_opc =3D vecop_list_sli, .vece =3D MO_16 }, { .fni4 =3D gen_shl32_ins_i32, .fniv =3D gen_shl_ins_vec, .load_dest =3D true, - .opc =3D INDEX_op_shli_vec, + .opt_opc =3D vecop_list_sli, .vece =3D MO_32 }, { .fni8 =3D gen_shl64_ins_i64, .fniv =3D gen_shl_ins_vec, .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, .load_dest =3D true, - .opc =3D INDEX_op_shli_vec, + .opt_opc =3D vecop_list_sli, .vece =3D MO_64 }, }; =20 @@ -6156,51 +6168,60 @@ static void gen_mls_vec(unsigned vece, TCGv_vec d, = TCGv_vec a, TCGv_vec b) /* Note that while NEON does not support VMLA and VMLS as 64-bit ops, * these tables are shared with AArch64 which does support them. */ + +static const TCGOpcode vecop_list_mla[] =3D { + INDEX_op_mul_vec, INDEX_op_add_vec, 0 +}; + +static const TCGOpcode vecop_list_mls[] =3D { + INDEX_op_mul_vec, INDEX_op_sub_vec, 0 +}; + const GVecGen3 mla_op[4] =3D { { .fni4 =3D gen_mla8_i32, .fniv =3D gen_mla_vec, - .opc =3D INDEX_op_mul_vec, .load_dest =3D true, + .opt_opc =3D vecop_list_mla, .vece =3D MO_8 }, { .fni4 =3D gen_mla16_i32, .fniv =3D gen_mla_vec, - .opc =3D INDEX_op_mul_vec, .load_dest =3D true, + .opt_opc =3D vecop_list_mla, .vece =3D MO_16 }, { .fni4 =3D gen_mla32_i32, .fniv =3D gen_mla_vec, - .opc =3D INDEX_op_mul_vec, .load_dest =3D true, + .opt_opc =3D vecop_list_mla, .vece =3D MO_32 }, { .fni8 =3D gen_mla64_i64, .fniv =3D gen_mla_vec, - .opc =3D INDEX_op_mul_vec, .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, .load_dest =3D true, + .opt_opc =3D vecop_list_mla, .vece =3D MO_64 }, }; =20 const GVecGen3 mls_op[4] =3D { { .fni4 =3D gen_mls8_i32, .fniv =3D gen_mls_vec, - .opc =3D INDEX_op_mul_vec, .load_dest =3D true, + .opt_opc =3D vecop_list_mls, .vece =3D MO_8 }, { .fni4 =3D gen_mls16_i32, .fniv =3D gen_mls_vec, - .opc =3D INDEX_op_mul_vec, .load_dest =3D true, + .opt_opc =3D vecop_list_mls, .vece =3D MO_16 }, { .fni4 =3D gen_mls32_i32, .fniv =3D gen_mls_vec, - .opc =3D INDEX_op_mul_vec, .load_dest =3D true, + .opt_opc =3D vecop_list_mls, .vece =3D MO_32 }, { .fni8 =3D gen_mls64_i64, .fniv =3D gen_mls_vec, - .opc =3D INDEX_op_mul_vec, .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, .load_dest =3D true, + .opt_opc =3D vecop_list_mls, .vece =3D MO_64 }, }; =20 @@ -6226,19 +6247,25 @@ static void gen_cmtst_vec(unsigned vece, TCGv_vec d= , TCGv_vec a, TCGv_vec b) tcg_gen_cmp_vec(TCG_COND_NE, vece, d, d, a); } =20 +static const TCGOpcode vecop_list_cmtst[] =3D { INDEX_op_cmp_vec, 0 }; + const GVecGen3 cmtst_op[4] =3D { { .fni4 =3D gen_helper_neon_tst_u8, .fniv =3D gen_cmtst_vec, + .opt_opc =3D vecop_list_cmtst, .vece =3D MO_8 }, { .fni4 =3D gen_helper_neon_tst_u16, .fniv =3D gen_cmtst_vec, + .opt_opc =3D vecop_list_cmtst, .vece =3D MO_16 }, { .fni4 =3D gen_cmtst_i32, .fniv =3D gen_cmtst_vec, + .opt_opc =3D vecop_list_cmtst, .vece =3D MO_32 }, { .fni8 =3D gen_cmtst_i64, .fniv =3D gen_cmtst_vec, .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .opt_opc =3D vecop_list_cmtst, .vece =3D MO_64 }, }; =20 @@ -6253,26 +6280,30 @@ static void gen_uqadd_vec(unsigned vece, TCGv_vec t= , TCGv_vec sat, tcg_temp_free_vec(x); } =20 +static const TCGOpcode vecop_list_uqadd[] =3D { + INDEX_op_usadd_vec, INDEX_op_cmp_vec, INDEX_op_add_vec, 0 +}; + const GVecGen4 uqadd_op[4] =3D { { .fniv =3D gen_uqadd_vec, .fno =3D gen_helper_gvec_uqadd_b, - .opc =3D INDEX_op_usadd_vec, .write_aofs =3D true, + .opt_opc =3D vecop_list_uqadd, .vece =3D MO_8 }, { .fniv =3D gen_uqadd_vec, .fno =3D gen_helper_gvec_uqadd_h, - .opc =3D INDEX_op_usadd_vec, .write_aofs =3D true, + .opt_opc =3D vecop_list_uqadd, .vece =3D MO_16 }, { .fniv =3D gen_uqadd_vec, .fno =3D gen_helper_gvec_uqadd_s, - .opc =3D INDEX_op_usadd_vec, .write_aofs =3D true, + .opt_opc =3D vecop_list_uqadd, .vece =3D MO_32 }, { .fniv =3D gen_uqadd_vec, .fno =3D gen_helper_gvec_uqadd_d, - .opc =3D INDEX_op_usadd_vec, .write_aofs =3D true, + .opt_opc =3D vecop_list_uqadd, .vece =3D MO_64 }, }; =20 @@ -6287,25 +6318,29 @@ static void gen_sqadd_vec(unsigned vece, TCGv_vec t= , TCGv_vec sat, tcg_temp_free_vec(x); } =20 +static const TCGOpcode vecop_list_sqadd[] =3D { + INDEX_op_ssadd_vec, INDEX_op_cmp_vec, INDEX_op_add_vec, 0 +}; + const GVecGen4 sqadd_op[4] =3D { { .fniv =3D gen_sqadd_vec, .fno =3D gen_helper_gvec_sqadd_b, - .opc =3D INDEX_op_ssadd_vec, + .opt_opc =3D vecop_list_sqadd, .write_aofs =3D true, .vece =3D MO_8 }, { .fniv =3D gen_sqadd_vec, .fno =3D gen_helper_gvec_sqadd_h, - .opc =3D INDEX_op_ssadd_vec, + .opt_opc =3D vecop_list_sqadd, .write_aofs =3D true, .vece =3D MO_16 }, { .fniv =3D gen_sqadd_vec, .fno =3D gen_helper_gvec_sqadd_s, - .opc =3D INDEX_op_ssadd_vec, + .opt_opc =3D vecop_list_sqadd, .write_aofs =3D true, .vece =3D MO_32 }, { .fniv =3D gen_sqadd_vec, .fno =3D gen_helper_gvec_sqadd_d, - .opc =3D INDEX_op_ssadd_vec, + .opt_opc =3D vecop_list_sqadd, .write_aofs =3D true, .vece =3D MO_64 }, }; @@ -6321,25 +6356,29 @@ static void gen_uqsub_vec(unsigned vece, TCGv_vec t= , TCGv_vec sat, tcg_temp_free_vec(x); } =20 +static const TCGOpcode vecop_list_uqsub[] =3D { + INDEX_op_ussub_vec, INDEX_op_cmp_vec, INDEX_op_sub_vec, 0 +}; + const GVecGen4 uqsub_op[4] =3D { { .fniv =3D gen_uqsub_vec, .fno =3D gen_helper_gvec_uqsub_b, - .opc =3D INDEX_op_ussub_vec, + .opt_opc =3D vecop_list_uqsub, .write_aofs =3D true, .vece =3D MO_8 }, { .fniv =3D gen_uqsub_vec, .fno =3D gen_helper_gvec_uqsub_h, - .opc =3D INDEX_op_ussub_vec, + .opt_opc =3D vecop_list_uqsub, .write_aofs =3D true, .vece =3D MO_16 }, { .fniv =3D gen_uqsub_vec, .fno =3D gen_helper_gvec_uqsub_s, - .opc =3D INDEX_op_ussub_vec, + .opt_opc =3D vecop_list_uqsub, .write_aofs =3D true, .vece =3D MO_32 }, { .fniv =3D gen_uqsub_vec, .fno =3D gen_helper_gvec_uqsub_d, - .opc =3D INDEX_op_ussub_vec, + .opt_opc =3D vecop_list_uqsub, .write_aofs =3D true, .vece =3D MO_64 }, }; @@ -6355,25 +6394,29 @@ static void gen_sqsub_vec(unsigned vece, TCGv_vec t= , TCGv_vec sat, tcg_temp_free_vec(x); } =20 +static const TCGOpcode vecop_list_sqsub[] =3D { + INDEX_op_sssub_vec, INDEX_op_cmp_vec, INDEX_op_sub_vec, 0 +}; + const GVecGen4 sqsub_op[4] =3D { { .fniv =3D gen_sqsub_vec, .fno =3D gen_helper_gvec_sqsub_b, - .opc =3D INDEX_op_sssub_vec, + .opt_opc =3D vecop_list_sqsub, .write_aofs =3D true, .vece =3D MO_8 }, { .fniv =3D gen_sqsub_vec, .fno =3D gen_helper_gvec_sqsub_h, - .opc =3D INDEX_op_sssub_vec, + .opt_opc =3D vecop_list_sqsub, .write_aofs =3D true, .vece =3D MO_16 }, { .fniv =3D gen_sqsub_vec, .fno =3D gen_helper_gvec_sqsub_s, - .opc =3D INDEX_op_sssub_vec, + .opt_opc =3D vecop_list_sqsub, .write_aofs =3D true, .vece =3D MO_32 }, { .fniv =3D gen_sqsub_vec, .fno =3D gen_helper_gvec_sqsub_d, - .opc =3D INDEX_op_sssub_vec, + .opt_opc =3D vecop_list_sqsub, .write_aofs =3D true, .vece =3D MO_64 }, }; diff --git a/target/ppc/translate/vmx-impl.inc.c b/target/ppc/translate/vmx= -impl.inc.c index bd3ff40e68..6861f4c5b9 100644 --- a/target/ppc/translate/vmx-impl.inc.c +++ b/target/ppc/translate/vmx-impl.inc.c @@ -566,10 +566,15 @@ static void glue(glue(gen_, NAME), _vec)(unsigned vec= e, TCGv_vec t, \ } \ static void glue(gen_, NAME)(DisasContext *ctx) \ { \ + static const TCGOpcode vecop_list[] =3D { \ + glue(glue(INDEX_op_, NORM), _vec), \ + glue(glue(INDEX_op_, SAT), _vec), \ + INDEX_op_cmp_vec, 0 \ + }; \ static const GVecGen4 g =3D { \ .fniv =3D glue(glue(gen_, NAME), _vec), \ .fno =3D glue(gen_helper_, NAME), \ - .opc =3D glue(glue(INDEX_op_, SAT), _vec), \ + .opt_opc =3D vecop_list, \ .write_aofs =3D true, \ .vece =3D VECE, \ }; \ diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c index f831adb4e7..3fcb2352d9 100644 --- a/tcg/tcg-op-gvec.c +++ b/tcg/tcg-op-gvec.c @@ -26,6 +26,13 @@ =20 #define MAX_UNROLL 4 =20 +#ifdef CONFIG_DEBUG_TCG +static const TCGOpcode vecop_list_empty[1] =3D { 0 }; +#else +#define vecop_list_empty NULL +#endif + + /* Verify vector size and alignment rules. OFS should be the OR of all of the operand offsets so that we can check them all at once. */ static void check_size_align(uint32_t oprsz, uint32_t maxsz, uint32_t ofs) @@ -360,31 +367,29 @@ static void gen_dup_i64(unsigned vece, TCGv_i64 out, = TCGv_i64 in) * on elements of size VECE in the selected type. Do not select V64 if * PREFER_I64 is true. Return 0 if no vector type is selected. */ -static TCGType choose_vector_type(TCGOpcode op, unsigned vece, uint32_t si= ze, - bool prefer_i64) +static TCGType choose_vector_type(const TCGOpcode *list, unsigned vece, + uint32_t size, bool prefer_i64) { if (TCG_TARGET_HAS_v256 && check_size_impl(size, 32)) { - if (op =3D=3D 0) { - return TCG_TYPE_V256; - } - /* Recall that ARM SVE allows vector sizes that are not a + /* + * Recall that ARM SVE allows vector sizes that are not a * power of 2, but always a multiple of 16. The intent is * that e.g. size =3D=3D 80 would be expanded with 2x32 + 1x16. * It is hard to imagine a case in which v256 is supported * but v128 is not, but check anyway. */ - if (tcg_can_emit_vec_op(op, TCG_TYPE_V256, vece) + if (tcg_can_emit_vecop_list(list, TCG_TYPE_V256, vece) && (size % 32 =3D=3D 0 - || tcg_can_emit_vec_op(op, TCG_TYPE_V128, vece))) { + || tcg_can_emit_vecop_list(list, TCG_TYPE_V128, vece))) { return TCG_TYPE_V256; } } if (TCG_TARGET_HAS_v128 && check_size_impl(size, 16) - && (op =3D=3D 0 || tcg_can_emit_vec_op(op, TCG_TYPE_V128, vece))) { + && tcg_can_emit_vecop_list(list, TCG_TYPE_V128, vece)) { return TCG_TYPE_V128; } if (TCG_TARGET_HAS_v64 && !prefer_i64 && check_size_impl(size, 8) - && (op =3D=3D 0 || tcg_can_emit_vec_op(op, TCG_TYPE_V64, vece))) { + && tcg_can_emit_vecop_list(list, TCG_TYPE_V64, vece)) { return TCG_TYPE_V64; } return 0; @@ -418,7 +423,7 @@ static void do_dup(unsigned vece, uint32_t dofs, uint32= _t oprsz, /* Implement inline with a vector type, if possible. * Prefer integer when 64-bit host and no variable dup. */ - type =3D choose_vector_type(0, vece, oprsz, + type =3D choose_vector_type(NULL, vece, oprsz, (TCG_TARGET_REG_BITS =3D=3D 64 && in_32 =3D= =3D NULL && (in_64 =3D=3D NULL || vece =3D=3D MO_64)= )); if (type !=3D 0) { @@ -991,6 +996,8 @@ static void expand_4_vec(unsigned vece, uint32_t dofs, = uint32_t aofs, void tcg_gen_gvec_2(uint32_t dofs, uint32_t aofs, uint32_t oprsz, uint32_t maxsz, const GVecGen2 *g) { + const TCGOpcode *this_list =3D g->opt_opc ? : vecop_list_empty; + const TCGOpcode *hold_list =3D tcg_swap_vecop_list(this_list); TCGType type; uint32_t some; =20 @@ -999,7 +1006,7 @@ void tcg_gen_gvec_2(uint32_t dofs, uint32_t aofs, =20 type =3D 0; if (g->fniv) { - type =3D choose_vector_type(g->opc, g->vece, oprsz, g->prefer_i64); + type =3D choose_vector_type(g->opt_opc, g->vece, oprsz, g->prefer_= i64); } switch (type) { case TCG_TYPE_V256: @@ -1032,13 +1039,14 @@ void tcg_gen_gvec_2(uint32_t dofs, uint32_t aofs, } else { assert(g->fno !=3D NULL); tcg_gen_gvec_2_ool(dofs, aofs, oprsz, maxsz, g->data, g->fno); - return; + oprsz =3D maxsz; } break; =20 default: g_assert_not_reached(); } + tcg_swap_vecop_list(hold_list); =20 if (oprsz < maxsz) { expand_clr(dofs + oprsz, maxsz - oprsz); @@ -1049,6 +1057,8 @@ void tcg_gen_gvec_2(uint32_t dofs, uint32_t aofs, void tcg_gen_gvec_2i(uint32_t dofs, uint32_t aofs, uint32_t oprsz, uint32_t maxsz, int64_t c, const GVecGen2i *g) { + const TCGOpcode *this_list =3D g->opt_opc ? : vecop_list_empty; + const TCGOpcode *hold_list =3D tcg_swap_vecop_list(this_list); TCGType type; uint32_t some; =20 @@ -1057,7 +1067,7 @@ void tcg_gen_gvec_2i(uint32_t dofs, uint32_t aofs, ui= nt32_t oprsz, =20 type =3D 0; if (g->fniv) { - type =3D choose_vector_type(g->opc, g->vece, oprsz, g->prefer_i64); + type =3D choose_vector_type(g->opt_opc, g->vece, oprsz, g->prefer_= i64); } switch (type) { case TCG_TYPE_V256: @@ -1099,13 +1109,14 @@ void tcg_gen_gvec_2i(uint32_t dofs, uint32_t aofs, = uint32_t oprsz, maxsz, c, g->fnoi); tcg_temp_free_i64(tcg_c); } - return; + oprsz =3D maxsz; } break; =20 default: g_assert_not_reached(); } + tcg_swap_vecop_list(hold_list); =20 if (oprsz < maxsz) { expand_clr(dofs + oprsz, maxsz - oprsz); @@ -1123,9 +1134,11 @@ void tcg_gen_gvec_2s(uint32_t dofs, uint32_t aofs, u= int32_t oprsz, =20 type =3D 0; if (g->fniv) { - type =3D choose_vector_type(g->opc, g->vece, oprsz, g->prefer_i64); + type =3D choose_vector_type(g->opt_opc, g->vece, oprsz, g->prefer_= i64); } if (type !=3D 0) { + const TCGOpcode *this_list =3D g->opt_opc ? : vecop_list_empty; + const TCGOpcode *hold_list =3D tcg_swap_vecop_list(this_list); TCGv_vec t_vec =3D tcg_temp_new_vec(type); uint32_t some; =20 @@ -1163,6 +1176,7 @@ void tcg_gen_gvec_2s(uint32_t dofs, uint32_t aofs, ui= nt32_t oprsz, g_assert_not_reached(); } tcg_temp_free_vec(t_vec); + tcg_swap_vecop_list(hold_list); } else if (g->fni8 && check_size_impl(oprsz, 8)) { TCGv_i64 t64 =3D tcg_temp_new_i64(); =20 @@ -1190,6 +1204,8 @@ void tcg_gen_gvec_2s(uint32_t dofs, uint32_t aofs, ui= nt32_t oprsz, void tcg_gen_gvec_3(uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t oprsz, uint32_t maxsz, const GVecGen3 *g) { + const TCGOpcode *this_list =3D g->opt_opc ? : vecop_list_empty; + const TCGOpcode *hold_list =3D tcg_swap_vecop_list(this_list); TCGType type; uint32_t some; =20 @@ -1198,7 +1214,7 @@ void tcg_gen_gvec_3(uint32_t dofs, uint32_t aofs, uin= t32_t bofs, =20 type =3D 0; if (g->fniv) { - type =3D choose_vector_type(g->opc, g->vece, oprsz, g->prefer_i64); + type =3D choose_vector_type(g->opt_opc, g->vece, oprsz, g->prefer_= i64); } switch (type) { case TCG_TYPE_V256: @@ -1236,13 +1252,14 @@ void tcg_gen_gvec_3(uint32_t dofs, uint32_t aofs, u= int32_t bofs, assert(g->fno !=3D NULL); tcg_gen_gvec_3_ool(dofs, aofs, bofs, oprsz, maxsz, g->data, g->fno); - return; + oprsz =3D maxsz; } break; =20 default: g_assert_not_reached(); } + tcg_swap_vecop_list(hold_list); =20 if (oprsz < maxsz) { expand_clr(dofs + oprsz, maxsz - oprsz); @@ -1254,6 +1271,8 @@ void tcg_gen_gvec_3i(uint32_t dofs, uint32_t aofs, ui= nt32_t bofs, uint32_t oprsz, uint32_t maxsz, int64_t c, const GVecGen3i *g) { + const TCGOpcode *this_list =3D g->opt_opc ? : vecop_list_empty; + const TCGOpcode *hold_list =3D tcg_swap_vecop_list(this_list); TCGType type; uint32_t some; =20 @@ -1262,7 +1281,7 @@ void tcg_gen_gvec_3i(uint32_t dofs, uint32_t aofs, ui= nt32_t bofs, =20 type =3D 0; if (g->fniv) { - type =3D choose_vector_type(g->opc, g->vece, oprsz, g->prefer_i64); + type =3D choose_vector_type(g->opt_opc, g->vece, oprsz, g->prefer_= i64); } switch (type) { case TCG_TYPE_V256: @@ -1300,13 +1319,14 @@ void tcg_gen_gvec_3i(uint32_t dofs, uint32_t aofs, = uint32_t bofs, } else { assert(g->fno !=3D NULL); tcg_gen_gvec_3_ool(dofs, aofs, bofs, oprsz, maxsz, c, g->fno); - return; + oprsz =3D maxsz; } break; =20 default: g_assert_not_reached(); } + tcg_swap_vecop_list(hold_list); =20 if (oprsz < maxsz) { expand_clr(dofs + oprsz, maxsz - oprsz); @@ -1317,6 +1337,8 @@ void tcg_gen_gvec_3i(uint32_t dofs, uint32_t aofs, ui= nt32_t bofs, void tcg_gen_gvec_4(uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t = cofs, uint32_t oprsz, uint32_t maxsz, const GVecGen4 *g) { + const TCGOpcode *this_list =3D g->opt_opc ? : vecop_list_empty; + const TCGOpcode *hold_list =3D tcg_swap_vecop_list(this_list); TCGType type; uint32_t some; =20 @@ -1325,7 +1347,7 @@ void tcg_gen_gvec_4(uint32_t dofs, uint32_t aofs, uin= t32_t bofs, uint32_t cofs, =20 type =3D 0; if (g->fniv) { - type =3D choose_vector_type(g->opc, g->vece, oprsz, g->prefer_i64); + type =3D choose_vector_type(g->opt_opc, g->vece, oprsz, g->prefer_= i64); } switch (type) { case TCG_TYPE_V256: @@ -1366,13 +1388,14 @@ void tcg_gen_gvec_4(uint32_t dofs, uint32_t aofs, u= int32_t bofs, uint32_t cofs, assert(g->fno !=3D NULL); tcg_gen_gvec_4_ool(dofs, aofs, bofs, cofs, oprsz, maxsz, g->data, g->fno); - return; + oprsz =3D maxsz; } break; =20 default: g_assert_not_reached(); } + tcg_swap_vecop_list(hold_list); =20 if (oprsz < maxsz) { expand_clr(dofs + oprsz, maxsz - oprsz); @@ -1567,6 +1590,8 @@ void tcg_gen_vec_add32_i64(TCGv_i64 d, TCGv_i64 a, TC= Gv_i64 b) tcg_temp_free_i64(t2); } =20 +static const TCGOpcode vecop_list_add[] =3D { INDEX_op_add_vec, 0 }; + void tcg_gen_gvec_add(unsigned vece, uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t oprsz, uint32_t maxsz) { @@ -1574,22 +1599,22 @@ void tcg_gen_gvec_add(unsigned vece, uint32_t dofs,= uint32_t aofs, { .fni8 =3D tcg_gen_vec_add8_i64, .fniv =3D tcg_gen_add_vec, .fno =3D gen_helper_gvec_add8, - .opc =3D INDEX_op_add_vec, + .opt_opc =3D vecop_list_add, .vece =3D MO_8 }, { .fni8 =3D tcg_gen_vec_add16_i64, .fniv =3D tcg_gen_add_vec, .fno =3D gen_helper_gvec_add16, - .opc =3D INDEX_op_add_vec, + .opt_opc =3D vecop_list_add, .vece =3D MO_16 }, { .fni4 =3D tcg_gen_add_i32, .fniv =3D tcg_gen_add_vec, .fno =3D gen_helper_gvec_add32, - .opc =3D INDEX_op_add_vec, + .opt_opc =3D vecop_list_add, .vece =3D MO_32 }, { .fni8 =3D tcg_gen_add_i64, .fniv =3D tcg_gen_add_vec, .fno =3D gen_helper_gvec_add64, - .opc =3D INDEX_op_add_vec, + .opt_opc =3D vecop_list_add, .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, .vece =3D MO_64 }, }; @@ -1605,22 +1630,22 @@ void tcg_gen_gvec_adds(unsigned vece, uint32_t dofs= , uint32_t aofs, { .fni8 =3D tcg_gen_vec_add8_i64, .fniv =3D tcg_gen_add_vec, .fno =3D gen_helper_gvec_adds8, - .opc =3D INDEX_op_add_vec, + .opt_opc =3D vecop_list_add, .vece =3D MO_8 }, { .fni8 =3D tcg_gen_vec_add16_i64, .fniv =3D tcg_gen_add_vec, .fno =3D gen_helper_gvec_adds16, - .opc =3D INDEX_op_add_vec, + .opt_opc =3D vecop_list_add, .vece =3D MO_16 }, { .fni4 =3D tcg_gen_add_i32, .fniv =3D tcg_gen_add_vec, .fno =3D gen_helper_gvec_adds32, - .opc =3D INDEX_op_add_vec, + .opt_opc =3D vecop_list_add, .vece =3D MO_32 }, { .fni8 =3D tcg_gen_add_i64, .fniv =3D tcg_gen_add_vec, .fno =3D gen_helper_gvec_adds64, - .opc =3D INDEX_op_add_vec, + .opt_opc =3D vecop_list_add, .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, .vece =3D MO_64 }, }; @@ -1637,6 +1662,8 @@ void tcg_gen_gvec_addi(unsigned vece, uint32_t dofs, = uint32_t aofs, tcg_temp_free_i64(tmp); } =20 +static const TCGOpcode vecop_list_sub[] =3D { INDEX_op_sub_vec, 0 }; + void tcg_gen_gvec_subs(unsigned vece, uint32_t dofs, uint32_t aofs, TCGv_i64 c, uint32_t oprsz, uint32_t maxsz) { @@ -1644,22 +1671,22 @@ void tcg_gen_gvec_subs(unsigned vece, uint32_t dofs= , uint32_t aofs, { .fni8 =3D tcg_gen_vec_sub8_i64, .fniv =3D tcg_gen_sub_vec, .fno =3D gen_helper_gvec_subs8, - .opc =3D INDEX_op_sub_vec, + .opt_opc =3D vecop_list_sub, .vece =3D MO_8 }, { .fni8 =3D tcg_gen_vec_sub16_i64, .fniv =3D tcg_gen_sub_vec, .fno =3D gen_helper_gvec_subs16, - .opc =3D INDEX_op_sub_vec, + .opt_opc =3D vecop_list_sub, .vece =3D MO_16 }, { .fni4 =3D tcg_gen_sub_i32, .fniv =3D tcg_gen_sub_vec, .fno =3D gen_helper_gvec_subs32, - .opc =3D INDEX_op_sub_vec, + .opt_opc =3D vecop_list_sub, .vece =3D MO_32 }, { .fni8 =3D tcg_gen_sub_i64, .fniv =3D tcg_gen_sub_vec, .fno =3D gen_helper_gvec_subs64, - .opc =3D INDEX_op_sub_vec, + .opt_opc =3D vecop_list_sub, .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, .vece =3D MO_64 }, }; @@ -1723,22 +1750,22 @@ void tcg_gen_gvec_sub(unsigned vece, uint32_t dofs,= uint32_t aofs, { .fni8 =3D tcg_gen_vec_sub8_i64, .fniv =3D tcg_gen_sub_vec, .fno =3D gen_helper_gvec_sub8, - .opc =3D INDEX_op_sub_vec, + .opt_opc =3D vecop_list_sub, .vece =3D MO_8 }, { .fni8 =3D tcg_gen_vec_sub16_i64, .fniv =3D tcg_gen_sub_vec, .fno =3D gen_helper_gvec_sub16, - .opc =3D INDEX_op_sub_vec, + .opt_opc =3D vecop_list_sub, .vece =3D MO_16 }, { .fni4 =3D tcg_gen_sub_i32, .fniv =3D tcg_gen_sub_vec, .fno =3D gen_helper_gvec_sub32, - .opc =3D INDEX_op_sub_vec, + .opt_opc =3D vecop_list_sub, .vece =3D MO_32 }, { .fni8 =3D tcg_gen_sub_i64, .fniv =3D tcg_gen_sub_vec, .fno =3D gen_helper_gvec_sub64, - .opc =3D INDEX_op_sub_vec, + .opt_opc =3D vecop_list_sub, .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, .vece =3D MO_64 }, }; @@ -1747,27 +1774,29 @@ void tcg_gen_gvec_sub(unsigned vece, uint32_t dofs,= uint32_t aofs, tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]); } =20 +static const TCGOpcode vecop_list_mul[] =3D { INDEX_op_mul_vec, 0 }; + void tcg_gen_gvec_mul(unsigned vece, uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t oprsz, uint32_t maxsz) { static const GVecGen3 g[4] =3D { { .fniv =3D tcg_gen_mul_vec, .fno =3D gen_helper_gvec_mul8, - .opc =3D INDEX_op_mul_vec, + .opt_opc =3D vecop_list_mul, .vece =3D MO_8 }, { .fniv =3D tcg_gen_mul_vec, .fno =3D gen_helper_gvec_mul16, - .opc =3D INDEX_op_mul_vec, + .opt_opc =3D vecop_list_mul, .vece =3D MO_16 }, { .fni4 =3D tcg_gen_mul_i32, .fniv =3D tcg_gen_mul_vec, .fno =3D gen_helper_gvec_mul32, - .opc =3D INDEX_op_mul_vec, + .opt_opc =3D vecop_list_mul, .vece =3D MO_32 }, { .fni8 =3D tcg_gen_mul_i64, .fniv =3D tcg_gen_mul_vec, .fno =3D gen_helper_gvec_mul64, - .opc =3D INDEX_op_mul_vec, + .opt_opc =3D vecop_list_mul, .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, .vece =3D MO_64 }, }; @@ -1782,21 +1811,21 @@ void tcg_gen_gvec_muls(unsigned vece, uint32_t dofs= , uint32_t aofs, static const GVecGen2s g[4] =3D { { .fniv =3D tcg_gen_mul_vec, .fno =3D gen_helper_gvec_muls8, - .opc =3D INDEX_op_mul_vec, + .opt_opc =3D vecop_list_mul, .vece =3D MO_8 }, { .fniv =3D tcg_gen_mul_vec, .fno =3D gen_helper_gvec_muls16, - .opc =3D INDEX_op_mul_vec, + .opt_opc =3D vecop_list_mul, .vece =3D MO_16 }, { .fni4 =3D tcg_gen_mul_i32, .fniv =3D tcg_gen_mul_vec, .fno =3D gen_helper_gvec_muls32, - .opc =3D INDEX_op_mul_vec, + .opt_opc =3D vecop_list_mul, .vece =3D MO_32 }, { .fni8 =3D tcg_gen_mul_i64, .fniv =3D tcg_gen_mul_vec, .fno =3D gen_helper_gvec_muls64, - .opc =3D INDEX_op_mul_vec, + .opt_opc =3D vecop_list_mul, .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, .vece =3D MO_64 }, }; @@ -1816,22 +1845,23 @@ void tcg_gen_gvec_muli(unsigned vece, uint32_t dofs= , uint32_t aofs, void tcg_gen_gvec_ssadd(unsigned vece, uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t oprsz, uint32_t maxsz) { + static const TCGOpcode vecop_list[] =3D { INDEX_op_ssadd_vec, 0 }; static const GVecGen3 g[4] =3D { { .fniv =3D tcg_gen_ssadd_vec, .fno =3D gen_helper_gvec_ssadd8, - .opc =3D INDEX_op_ssadd_vec, + .opt_opc =3D vecop_list, .vece =3D MO_8 }, { .fniv =3D tcg_gen_ssadd_vec, .fno =3D gen_helper_gvec_ssadd16, - .opc =3D INDEX_op_ssadd_vec, + .opt_opc =3D vecop_list, .vece =3D MO_16 }, { .fniv =3D tcg_gen_ssadd_vec, .fno =3D gen_helper_gvec_ssadd32, - .opc =3D INDEX_op_ssadd_vec, + .opt_opc =3D vecop_list, .vece =3D MO_32 }, { .fniv =3D tcg_gen_ssadd_vec, .fno =3D gen_helper_gvec_ssadd64, - .opc =3D INDEX_op_ssadd_vec, + .opt_opc =3D vecop_list, .vece =3D MO_64 }, }; tcg_debug_assert(vece <=3D MO_64); @@ -1841,22 +1871,23 @@ void tcg_gen_gvec_ssadd(unsigned vece, uint32_t dof= s, uint32_t aofs, void tcg_gen_gvec_sssub(unsigned vece, uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t oprsz, uint32_t maxsz) { + static const TCGOpcode vecop_list[] =3D { INDEX_op_sssub_vec, 0 }; static const GVecGen3 g[4] =3D { { .fniv =3D tcg_gen_sssub_vec, .fno =3D gen_helper_gvec_sssub8, - .opc =3D INDEX_op_sssub_vec, + .opt_opc =3D vecop_list, .vece =3D MO_8 }, { .fniv =3D tcg_gen_sssub_vec, .fno =3D gen_helper_gvec_sssub16, - .opc =3D INDEX_op_sssub_vec, + .opt_opc =3D vecop_list, .vece =3D MO_16 }, { .fniv =3D tcg_gen_sssub_vec, .fno =3D gen_helper_gvec_sssub32, - .opc =3D INDEX_op_sssub_vec, + .opt_opc =3D vecop_list, .vece =3D MO_32 }, { .fniv =3D tcg_gen_sssub_vec, .fno =3D gen_helper_gvec_sssub64, - .opc =3D INDEX_op_sssub_vec, + .opt_opc =3D vecop_list, .vece =3D MO_64 }, }; tcg_debug_assert(vece <=3D MO_64); @@ -1882,24 +1913,25 @@ static void tcg_gen_usadd_i64(TCGv_i64 d, TCGv_i64 = a, TCGv_i64 b) void tcg_gen_gvec_usadd(unsigned vece, uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t oprsz, uint32_t maxsz) { + static const TCGOpcode vecop_list[] =3D { INDEX_op_usadd_vec, 0 }; static const GVecGen3 g[4] =3D { { .fniv =3D tcg_gen_usadd_vec, .fno =3D gen_helper_gvec_usadd8, - .opc =3D INDEX_op_usadd_vec, + .opt_opc =3D vecop_list, .vece =3D MO_8 }, { .fniv =3D tcg_gen_usadd_vec, .fno =3D gen_helper_gvec_usadd16, - .opc =3D INDEX_op_usadd_vec, + .opt_opc =3D vecop_list, .vece =3D MO_16 }, { .fni4 =3D tcg_gen_usadd_i32, .fniv =3D tcg_gen_usadd_vec, .fno =3D gen_helper_gvec_usadd32, - .opc =3D INDEX_op_usadd_vec, + .opt_opc =3D vecop_list, .vece =3D MO_32 }, { .fni8 =3D tcg_gen_usadd_i64, .fniv =3D tcg_gen_usadd_vec, .fno =3D gen_helper_gvec_usadd64, - .opc =3D INDEX_op_usadd_vec, + .opt_opc =3D vecop_list, .vece =3D MO_64 } }; tcg_debug_assert(vece <=3D MO_64); @@ -1925,24 +1957,25 @@ static void tcg_gen_ussub_i64(TCGv_i64 d, TCGv_i64 = a, TCGv_i64 b) void tcg_gen_gvec_ussub(unsigned vece, uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t oprsz, uint32_t maxsz) { + static const TCGOpcode vecop_list[] =3D { INDEX_op_ussub_vec, 0 }; static const GVecGen3 g[4] =3D { { .fniv =3D tcg_gen_ussub_vec, .fno =3D gen_helper_gvec_ussub8, - .opc =3D INDEX_op_ussub_vec, + .opt_opc =3D vecop_list, .vece =3D MO_8 }, { .fniv =3D tcg_gen_ussub_vec, .fno =3D gen_helper_gvec_ussub16, - .opc =3D INDEX_op_ussub_vec, + .opt_opc =3D vecop_list, .vece =3D MO_16 }, { .fni4 =3D tcg_gen_ussub_i32, .fniv =3D tcg_gen_ussub_vec, .fno =3D gen_helper_gvec_ussub32, - .opc =3D INDEX_op_ussub_vec, + .opt_opc =3D vecop_list, .vece =3D MO_32 }, { .fni8 =3D tcg_gen_ussub_i64, .fniv =3D tcg_gen_ussub_vec, .fno =3D gen_helper_gvec_ussub64, - .opc =3D INDEX_op_ussub_vec, + .opt_opc =3D vecop_list, .vece =3D MO_64 } }; tcg_debug_assert(vece <=3D MO_64); @@ -1952,24 +1985,25 @@ void tcg_gen_gvec_ussub(unsigned vece, uint32_t dof= s, uint32_t aofs, void tcg_gen_gvec_smin(unsigned vece, uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t oprsz, uint32_t maxsz) { + static const TCGOpcode vecop_list[] =3D { INDEX_op_smin_vec, 0 }; static const GVecGen3 g[4] =3D { { .fniv =3D tcg_gen_smin_vec, .fno =3D gen_helper_gvec_smin8, - .opc =3D INDEX_op_smin_vec, + .opt_opc =3D vecop_list, .vece =3D MO_8 }, { .fniv =3D tcg_gen_smin_vec, .fno =3D gen_helper_gvec_smin16, - .opc =3D INDEX_op_smin_vec, + .opt_opc =3D vecop_list, .vece =3D MO_16 }, { .fni4 =3D tcg_gen_smin_i32, .fniv =3D tcg_gen_smin_vec, .fno =3D gen_helper_gvec_smin32, - .opc =3D INDEX_op_smin_vec, + .opt_opc =3D vecop_list, .vece =3D MO_32 }, { .fni8 =3D tcg_gen_smin_i64, .fniv =3D tcg_gen_smin_vec, .fno =3D gen_helper_gvec_smin64, - .opc =3D INDEX_op_smin_vec, + .opt_opc =3D vecop_list, .vece =3D MO_64 } }; tcg_debug_assert(vece <=3D MO_64); @@ -1979,24 +2013,25 @@ void tcg_gen_gvec_smin(unsigned vece, uint32_t dofs= , uint32_t aofs, void tcg_gen_gvec_umin(unsigned vece, uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t oprsz, uint32_t maxsz) { + static const TCGOpcode vecop_list[] =3D { INDEX_op_umin_vec, 0 }; static const GVecGen3 g[4] =3D { { .fniv =3D tcg_gen_umin_vec, .fno =3D gen_helper_gvec_umin8, - .opc =3D INDEX_op_umin_vec, + .opt_opc =3D vecop_list, .vece =3D MO_8 }, { .fniv =3D tcg_gen_umin_vec, .fno =3D gen_helper_gvec_umin16, - .opc =3D INDEX_op_umin_vec, + .opt_opc =3D vecop_list, .vece =3D MO_16 }, { .fni4 =3D tcg_gen_umin_i32, .fniv =3D tcg_gen_umin_vec, .fno =3D gen_helper_gvec_umin32, - .opc =3D INDEX_op_umin_vec, + .opt_opc =3D vecop_list, .vece =3D MO_32 }, { .fni8 =3D tcg_gen_umin_i64, .fniv =3D tcg_gen_umin_vec, .fno =3D gen_helper_gvec_umin64, - .opc =3D INDEX_op_umin_vec, + .opt_opc =3D vecop_list, .vece =3D MO_64 } }; tcg_debug_assert(vece <=3D MO_64); @@ -2006,24 +2041,25 @@ void tcg_gen_gvec_umin(unsigned vece, uint32_t dofs= , uint32_t aofs, void tcg_gen_gvec_smax(unsigned vece, uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t oprsz, uint32_t maxsz) { + static const TCGOpcode vecop_list[] =3D { INDEX_op_smax_vec, 0 }; static const GVecGen3 g[4] =3D { { .fniv =3D tcg_gen_smax_vec, .fno =3D gen_helper_gvec_smax8, - .opc =3D INDEX_op_smax_vec, + .opt_opc =3D vecop_list, .vece =3D MO_8 }, { .fniv =3D tcg_gen_smax_vec, .fno =3D gen_helper_gvec_smax16, - .opc =3D INDEX_op_smax_vec, + .opt_opc =3D vecop_list, .vece =3D MO_16 }, { .fni4 =3D tcg_gen_smax_i32, .fniv =3D tcg_gen_smax_vec, .fno =3D gen_helper_gvec_smax32, - .opc =3D INDEX_op_smax_vec, + .opt_opc =3D vecop_list, .vece =3D MO_32 }, { .fni8 =3D tcg_gen_smax_i64, .fniv =3D tcg_gen_smax_vec, .fno =3D gen_helper_gvec_smax64, - .opc =3D INDEX_op_smax_vec, + .opt_opc =3D vecop_list, .vece =3D MO_64 } }; tcg_debug_assert(vece <=3D MO_64); @@ -2033,24 +2069,25 @@ void tcg_gen_gvec_smax(unsigned vece, uint32_t dofs= , uint32_t aofs, void tcg_gen_gvec_umax(unsigned vece, uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t oprsz, uint32_t maxsz) { + static const TCGOpcode vecop_list[] =3D { INDEX_op_umax_vec, 0 }; static const GVecGen3 g[4] =3D { { .fniv =3D tcg_gen_umax_vec, .fno =3D gen_helper_gvec_umax8, - .opc =3D INDEX_op_umax_vec, + .opt_opc =3D vecop_list, .vece =3D MO_8 }, { .fniv =3D tcg_gen_umax_vec, .fno =3D gen_helper_gvec_umax16, - .opc =3D INDEX_op_umax_vec, + .opt_opc =3D vecop_list, .vece =3D MO_16 }, { .fni4 =3D tcg_gen_umax_i32, .fniv =3D tcg_gen_umax_vec, .fno =3D gen_helper_gvec_umax32, - .opc =3D INDEX_op_umax_vec, + .opt_opc =3D vecop_list, .vece =3D MO_32 }, { .fni8 =3D tcg_gen_umax_i64, .fniv =3D tcg_gen_umax_vec, .fno =3D gen_helper_gvec_umax64, - .opc =3D INDEX_op_umax_vec, + .opt_opc =3D vecop_list, .vece =3D MO_64 } }; tcg_debug_assert(vece <=3D MO_64); @@ -2104,26 +2141,27 @@ void tcg_gen_vec_neg32_i64(TCGv_i64 d, TCGv_i64 b) void tcg_gen_gvec_neg(unsigned vece, uint32_t dofs, uint32_t aofs, uint32_t oprsz, uint32_t maxsz) { + static const TCGOpcode vecop_list[] =3D { INDEX_op_neg_vec, 0 }; static const GVecGen2 g[4] =3D { { .fni8 =3D tcg_gen_vec_neg8_i64, .fniv =3D tcg_gen_neg_vec, .fno =3D gen_helper_gvec_neg8, - .opc =3D INDEX_op_neg_vec, + .opt_opc =3D vecop_list, .vece =3D MO_8 }, { .fni8 =3D tcg_gen_vec_neg16_i64, .fniv =3D tcg_gen_neg_vec, .fno =3D gen_helper_gvec_neg16, - .opc =3D INDEX_op_neg_vec, + .opt_opc =3D vecop_list, .vece =3D MO_16 }, { .fni4 =3D tcg_gen_neg_i32, .fniv =3D tcg_gen_neg_vec, .fno =3D gen_helper_gvec_neg32, - .opc =3D INDEX_op_neg_vec, + .opt_opc =3D vecop_list, .vece =3D MO_32 }, { .fni8 =3D tcg_gen_neg_i64, .fniv =3D tcg_gen_neg_vec, .fno =3D gen_helper_gvec_neg64, - .opc =3D INDEX_op_neg_vec, + .opt_opc =3D vecop_list, .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, .vece =3D MO_64 }, }; @@ -2139,7 +2177,6 @@ void tcg_gen_gvec_and(unsigned vece, uint32_t dofs, u= int32_t aofs, .fni8 =3D tcg_gen_and_i64, .fniv =3D tcg_gen_and_vec, .fno =3D gen_helper_gvec_and, - .opc =3D INDEX_op_and_vec, .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, }; =20 @@ -2157,7 +2194,6 @@ void tcg_gen_gvec_or(unsigned vece, uint32_t dofs, ui= nt32_t aofs, .fni8 =3D tcg_gen_or_i64, .fniv =3D tcg_gen_or_vec, .fno =3D gen_helper_gvec_or, - .opc =3D INDEX_op_or_vec, .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, }; =20 @@ -2175,7 +2211,6 @@ void tcg_gen_gvec_xor(unsigned vece, uint32_t dofs, u= int32_t aofs, .fni8 =3D tcg_gen_xor_i64, .fniv =3D tcg_gen_xor_vec, .fno =3D gen_helper_gvec_xor, - .opc =3D INDEX_op_xor_vec, .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, }; =20 @@ -2193,7 +2228,6 @@ void tcg_gen_gvec_andc(unsigned vece, uint32_t dofs, = uint32_t aofs, .fni8 =3D tcg_gen_andc_i64, .fniv =3D tcg_gen_andc_vec, .fno =3D gen_helper_gvec_andc, - .opc =3D INDEX_op_andc_vec, .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, }; =20 @@ -2211,7 +2245,6 @@ void tcg_gen_gvec_orc(unsigned vece, uint32_t dofs, u= int32_t aofs, .fni8 =3D tcg_gen_orc_i64, .fniv =3D tcg_gen_orc_vec, .fno =3D gen_helper_gvec_orc, - .opc =3D INDEX_op_orc_vec, .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, }; =20 @@ -2277,7 +2310,6 @@ static const GVecGen2s gop_ands =3D { .fni8 =3D tcg_gen_and_i64, .fniv =3D tcg_gen_and_vec, .fno =3D gen_helper_gvec_ands, - .opc =3D INDEX_op_and_vec, .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, .vece =3D MO_64 }; @@ -2303,7 +2335,6 @@ static const GVecGen2s gop_xors =3D { .fni8 =3D tcg_gen_xor_i64, .fniv =3D tcg_gen_xor_vec, .fno =3D gen_helper_gvec_xors, - .opc =3D INDEX_op_xor_vec, .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, .vece =3D MO_64 }; @@ -2329,7 +2360,6 @@ static const GVecGen2s gop_ors =3D { .fni8 =3D tcg_gen_or_i64, .fniv =3D tcg_gen_or_vec, .fno =3D gen_helper_gvec_ors, - .opc =3D INDEX_op_or_vec, .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, .vece =3D MO_64 }; @@ -2368,26 +2398,27 @@ void tcg_gen_vec_shl16i_i64(TCGv_i64 d, TCGv_i64 a,= int64_t c) void tcg_gen_gvec_shli(unsigned vece, uint32_t dofs, uint32_t aofs, int64_t shift, uint32_t oprsz, uint32_t maxsz) { + static const TCGOpcode vecop_list[] =3D { INDEX_op_shli_vec, 0 }; static const GVecGen2i g[4] =3D { { .fni8 =3D tcg_gen_vec_shl8i_i64, .fniv =3D tcg_gen_shli_vec, .fno =3D gen_helper_gvec_shl8i, - .opc =3D INDEX_op_shli_vec, + .opt_opc =3D vecop_list, .vece =3D MO_8 }, { .fni8 =3D tcg_gen_vec_shl16i_i64, .fniv =3D tcg_gen_shli_vec, .fno =3D gen_helper_gvec_shl16i, - .opc =3D INDEX_op_shli_vec, + .opt_opc =3D vecop_list, .vece =3D MO_16 }, { .fni4 =3D tcg_gen_shli_i32, .fniv =3D tcg_gen_shli_vec, .fno =3D gen_helper_gvec_shl32i, - .opc =3D INDEX_op_shli_vec, + .opt_opc =3D vecop_list, .vece =3D MO_32 }, { .fni8 =3D tcg_gen_shli_i64, .fniv =3D tcg_gen_shli_vec, .fno =3D gen_helper_gvec_shl64i, - .opc =3D INDEX_op_shli_vec, + .opt_opc =3D vecop_list, .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, .vece =3D MO_64 }, }; @@ -2418,26 +2449,27 @@ void tcg_gen_vec_shr16i_i64(TCGv_i64 d, TCGv_i64 a,= int64_t c) void tcg_gen_gvec_shri(unsigned vece, uint32_t dofs, uint32_t aofs, int64_t shift, uint32_t oprsz, uint32_t maxsz) { + static const TCGOpcode vecop_list[] =3D { INDEX_op_shri_vec, 0 }; static const GVecGen2i g[4] =3D { { .fni8 =3D tcg_gen_vec_shr8i_i64, .fniv =3D tcg_gen_shri_vec, .fno =3D gen_helper_gvec_shr8i, - .opc =3D INDEX_op_shri_vec, + .opt_opc =3D vecop_list, .vece =3D MO_8 }, { .fni8 =3D tcg_gen_vec_shr16i_i64, .fniv =3D tcg_gen_shri_vec, .fno =3D gen_helper_gvec_shr16i, - .opc =3D INDEX_op_shri_vec, + .opt_opc =3D vecop_list, .vece =3D MO_16 }, { .fni4 =3D tcg_gen_shri_i32, .fniv =3D tcg_gen_shri_vec, .fno =3D gen_helper_gvec_shr32i, - .opc =3D INDEX_op_shri_vec, + .opt_opc =3D vecop_list, .vece =3D MO_32 }, { .fni8 =3D tcg_gen_shri_i64, .fniv =3D tcg_gen_shri_vec, .fno =3D gen_helper_gvec_shr64i, - .opc =3D INDEX_op_shri_vec, + .opt_opc =3D vecop_list, .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, .vece =3D MO_64 }, }; @@ -2482,26 +2514,27 @@ void tcg_gen_vec_sar16i_i64(TCGv_i64 d, TCGv_i64 a,= int64_t c) void tcg_gen_gvec_sari(unsigned vece, uint32_t dofs, uint32_t aofs, int64_t shift, uint32_t oprsz, uint32_t maxsz) { + static const TCGOpcode vecop_list[] =3D { INDEX_op_sari_vec, 0 }; static const GVecGen2i g[4] =3D { { .fni8 =3D tcg_gen_vec_sar8i_i64, .fniv =3D tcg_gen_sari_vec, .fno =3D gen_helper_gvec_sar8i, - .opc =3D INDEX_op_sari_vec, + .opt_opc =3D vecop_list, .vece =3D MO_8 }, { .fni8 =3D tcg_gen_vec_sar16i_i64, .fniv =3D tcg_gen_sari_vec, .fno =3D gen_helper_gvec_sar16i, - .opc =3D INDEX_op_sari_vec, + .opt_opc =3D vecop_list, .vece =3D MO_16 }, { .fni4 =3D tcg_gen_sari_i32, .fniv =3D tcg_gen_sari_vec, .fno =3D gen_helper_gvec_sar32i, - .opc =3D INDEX_op_sari_vec, + .opt_opc =3D vecop_list, .vece =3D MO_32 }, { .fni8 =3D tcg_gen_sari_i64, .fniv =3D tcg_gen_sari_vec, .fno =3D gen_helper_gvec_sar64i, - .opc =3D INDEX_op_sari_vec, + .opt_opc =3D vecop_list, .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, .vece =3D MO_64 }, }; @@ -2574,6 +2607,7 @@ void tcg_gen_gvec_cmp(TCGCond cond, unsigned vece, ui= nt32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t oprsz, uint32_t maxsz) { + static const TCGOpcode cmp_list[] =3D { INDEX_op_cmp_vec, 0 }; static gen_helper_gvec_3 * const eq_fn[4] =3D { gen_helper_gvec_eq8, gen_helper_gvec_eq16, gen_helper_gvec_eq32, gen_helper_gvec_eq64 @@ -2606,6 +2640,8 @@ void tcg_gen_gvec_cmp(TCGCond cond, unsigned vece, ui= nt32_t dofs, [TCG_COND_LTU] =3D ltu_fn, [TCG_COND_LEU] =3D leu_fn, }; + + const TCGOpcode *hold_list; TCGType type; uint32_t some; =20 @@ -2618,10 +2654,12 @@ void tcg_gen_gvec_cmp(TCGCond cond, unsigned vece, = uint32_t dofs, return; } =20 - /* Implement inline with a vector type, if possible. + /* + * Implement inline with a vector type, if possible. * Prefer integer when 64-bit host and 64-bit comparison. */ - type =3D choose_vector_type(INDEX_op_cmp_vec, vece, oprsz, + hold_list =3D tcg_swap_vecop_list(cmp_list); + type =3D choose_vector_type(cmp_list, vece, oprsz, TCG_TARGET_REG_BITS =3D=3D 64 && vece =3D=3D= MO_64); switch (type) { case TCG_TYPE_V256: @@ -2663,13 +2701,14 @@ void tcg_gen_gvec_cmp(TCGCond cond, unsigned vece, = uint32_t dofs, assert(fn !=3D NULL); } tcg_gen_gvec_3_ool(dofs, aofs, bofs, oprsz, maxsz, 0, fn[vece]= ); - return; + oprsz =3D maxsz; } break; =20 default: g_assert_not_reached(); } + tcg_swap_vecop_list(hold_list); =20 if (oprsz < maxsz) { expand_clr(dofs + oprsz, maxsz - oprsz); diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c index cfb18682b1..914fe42b1e 100644 --- a/tcg/tcg-op-vec.c +++ b/tcg/tcg-op-vec.c @@ -34,6 +34,90 @@ extern TCGv_i32 TCGV_HIGH_link_error(TCGv_i64); #define TCGV_HIGH TCGV_HIGH_link_error #endif =20 +/* + * Vector optional opcode tracking. + * Except for the basic logical operations (and, or, xor), and + * data movement (mov, ld, st, dupi), many vector opcodes are + * optional and may not be supported on the host. Thank Intel + * for the irregularity in their instruction set. + * + * The gvec expanders allow custom vector operations to be composed, + * generally via the .fniv callback in the GVecGen* structures. At + * the same time, in deciding whether to use this hook we need to + * know if the host supports the required operations. This is + * presented as an array of opcodes, terminated by 0. Each opcode + * is assumed to be expanded with the given VECE. + * + * For debugging, we want to validate this array. Therefore, when + * tcg_ctx->vec_opt_opc is non-NULL, the tcg_gen_*_vec expanders + * will validate that their opcode is present in the list. + */ +#ifdef CONFIG_DEBUG_TCG +void tcg_assert_listed_vecop(TCGOpcode op) +{ + const TCGOpcode *p =3D tcg_ctx->vecop_list; + if (p) { + for (; *p; ++p) { + if (*p =3D=3D op) { + return; + } + } + g_assert_not_reached(); + } +} +#endif + +bool tcg_can_emit_vecop_list(const TCGOpcode *list, + TCGType type, unsigned vece) +{ + if (list =3D=3D NULL) { + return true; + } + + for (; *list; ++list) { + TCGOpcode opc =3D *list; + +#ifdef CONFIG_DEBUG_TCG + switch (opc) { + case INDEX_op_and_vec: + case INDEX_op_or_vec: + case INDEX_op_xor_vec: + case INDEX_op_mov_vec: + case INDEX_op_dup_vec: + case INDEX_op_dupi_vec: + case INDEX_op_dup2_vec: + case INDEX_op_ld_vec: + case INDEX_op_st_vec: + /* These opcodes are mandatory and should not be listed. */ + g_assert_not_reached(); + default: + break; + } +#endif + + if (tcg_can_emit_vec_op(opc, type, vece)) { + continue; + } + + /* + * The opcode list is created by front ends based on what they + * actually invoke. We must mirror the logic in the routines + * below for generic expansions using other opcodes. + */ + switch (opc) { + case INDEX_op_neg_vec: + if (tcg_can_emit_vec_op(INDEX_op_sub_vec, type, vece)) { + continue; + } + break; + default: + break; + } + return false; + } + return true; +} + void vec_gen_2(TCGOpcode opc, TCGType type, unsigned vece, TCGArg r, TCGAr= g a) { TCGOp *op =3D tcg_emit_op(opc); @@ -296,11 +380,14 @@ static bool do_op2(unsigned vece, TCGv_vec r, TCGv_ve= c a, TCGOpcode opc) int can; =20 tcg_debug_assert(at->base_type >=3D type); + tcg_assert_listed_vecop(opc); can =3D tcg_can_emit_vec_op(opc, type, vece); if (can > 0) { vec_gen_2(opc, type, vece, ri, ai); } else if (can < 0) { + const TCGOpcode *hold_list =3D tcg_swap_vecop_list(NULL); tcg_expand_vec_op(opc, type, vece, ri, ai); + tcg_swap_vecop_list(hold_list); } else { return false; } @@ -318,11 +405,17 @@ void tcg_gen_not_vec(unsigned vece, TCGv_vec r, TCGv_= vec a) =20 void tcg_gen_neg_vec(unsigned vece, TCGv_vec r, TCGv_vec a) { + const TCGOpcode *hold_list; + + tcg_assert_listed_vecop(INDEX_op_neg_vec); + hold_list =3D tcg_swap_vecop_list(NULL); + if (!TCG_TARGET_HAS_neg_vec || !do_op2(vece, r, a, INDEX_op_neg_vec)) { TCGv_vec t =3D tcg_const_zeros_vec_matching(r); tcg_gen_sub_vec(vece, r, t, a); tcg_temp_free_vec(t); } + tcg_swap_vecop_list(hold_list); } =20 static void do_shifti(TCGOpcode opc, unsigned vece, @@ -337,6 +430,7 @@ static void do_shifti(TCGOpcode opc, unsigned vece, =20 tcg_debug_assert(at->base_type =3D=3D type); tcg_debug_assert(i >=3D 0 && i < (8 << vece)); + tcg_assert_listed_vecop(opc); =20 if (i =3D=3D 0) { tcg_gen_mov_vec(r, a); @@ -350,8 +444,10 @@ static void do_shifti(TCGOpcode opc, unsigned vece, /* We leave the choice of expansion via scalar or vector shift to the target. Often, but not always, dupi can feed a vector shift easier than a scalar. */ + const TCGOpcode *hold_list =3D tcg_swap_vecop_list(NULL); tcg_debug_assert(can < 0); tcg_expand_vec_op(opc, type, vece, ri, ai, i); + tcg_swap_vecop_list(hold_list); } } =20 @@ -384,12 +480,15 @@ void tcg_gen_cmp_vec(TCGCond cond, unsigned vece, =20 tcg_debug_assert(at->base_type >=3D type); tcg_debug_assert(bt->base_type >=3D type); + tcg_assert_listed_vecop(INDEX_op_cmp_vec); can =3D tcg_can_emit_vec_op(INDEX_op_cmp_vec, type, vece); if (can > 0) { vec_gen_4(INDEX_op_cmp_vec, type, vece, ri, ai, bi, cond); } else { + const TCGOpcode *hold_list =3D tcg_swap_vecop_list(NULL); tcg_debug_assert(can < 0); tcg_expand_vec_op(INDEX_op_cmp_vec, type, vece, ri, ai, bi, cond); + tcg_swap_vecop_list(hold_list); } } =20 @@ -407,12 +506,15 @@ static void do_op3(unsigned vece, TCGv_vec r, TCGv_ve= c a, =20 tcg_debug_assert(at->base_type >=3D type); tcg_debug_assert(bt->base_type >=3D type); + tcg_assert_listed_vecop(opc); can =3D tcg_can_emit_vec_op(opc, type, vece); if (can > 0) { vec_gen_3(opc, type, vece, ri, ai, bi); } else { + const TCGOpcode *hold_list =3D tcg_swap_vecop_list(NULL); tcg_debug_assert(can < 0); tcg_expand_vec_op(opc, type, vece, ri, ai, bi); + tcg_swap_vecop_list(hold_list); } } =20 --=20 2.17.1 From nobody Fri Apr 19 16:27:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1557793242; cv=none; d=zoho.com; s=zohoarc; b=VoUjBJt3dXNI3fdilDhqxDJneE3UpPFI1DRV9itCV7w2/vERuoAkqMBXpSPlNqx+wtIWC9dID/bJeu8Hhs6pusjDLZdtgVHODru2AtKyvfH/bL8tcz2Yw2Rc89vyz8qw00ZbVcBaH0LmGJ7a/KhwPxAVCQPgKdMQ6B3/hy9m4gE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1557793242; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=AEWllDC9QOtFQnoRVEZxCBNwIaVzx46hUstbb9Zao4Q=; b=KmPijwxhbKAYb+GhO179CJU6g/xocEEwGUh/Zm2+x+pKllU3eS+PeD8sfgOM8EgL9jA6t6VfaPe7CgGzKIX7A+p3WHQ49chzuE9E6gcRU2DVlvH/VfDfuI9zwf/Ob1J+fZbKsczATFTRsVQlmqoAxZsk24/PnkJ7mG8nQf6BXmE= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1557793242491403.6087063295564; Mon, 13 May 2019 17:20:42 -0700 (PDT) Received: from localhost ([127.0.0.1]:36771 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hQLBM-00050S-BA for importer@patchew.org; Mon, 13 May 2019 20:20:36 -0400 Received: from eggs.gnu.org ([209.51.188.92]:59366) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hQL1y-0004h8-LP for qemu-devel@nongnu.org; Mon, 13 May 2019 20:11:53 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hQKxB-00038Q-7K for qemu-devel@nongnu.org; Mon, 13 May 2019 20:10:54 -0400 Received: from mail-pg1-x544.google.com ([2607:f8b0:4864:20::544]:44496) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hQKx6-00031J-Tm for qemu-devel@nongnu.org; Mon, 13 May 2019 20:05:54 -0400 Received: by mail-pg1-x544.google.com with SMTP id z16so7585036pgv.11 for ; Mon, 13 May 2019 17:05:51 -0700 (PDT) Received: from localhost.localdomain (97-113-13-231.tukw.qwest.net. [97.113.13.231]) by smtp.gmail.com with ESMTPSA id u3sm238151pfn.29.2019.05.13.17.05.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 13 May 2019 17:05:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=AEWllDC9QOtFQnoRVEZxCBNwIaVzx46hUstbb9Zao4Q=; b=WaG4Tcz0PifdCR9WqNBKm4vpR6FCXO1PZsGdFXNeAI7otYI79ilijuObYWH6hj9dc+ nxwjfNt3iCs2mdi/im7S2z8bstp9G0XjUgX/W+tKxPzKXaH42kbEVExtvpgx99LYV2/1 EupqpCUEoVEV6+8Ujm49yDHHYrgINfF3Lc5hy8p2SlFnxhDDO27/VTaw3uyt9LJl69Ru zG9RleIxkr+VwZB/AEyy94C4RunGMCRtABk9jw7cCG/6glbaddrybl3BvHotdc0ph8vj gR9NpFSPgn9XtKHlRAqRuDaFvIcLydZDdZCTitGhIk1ew5Hh02o20gRMy1jTmTqpV4gN cMhw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=AEWllDC9QOtFQnoRVEZxCBNwIaVzx46hUstbb9Zao4Q=; b=gJcuSgFK0QH2nl1aKzSq0CZbd/YT/h+W+7yE1QtkO2ysSMwL1PuJpVL/+71Ztfc2P2 9SymOBHMeNbNMriJfqlPpYzfav11A181FpU3ORwBX1qzTsCsAEdhqnuOavAFy4kGWTpw lFM5iGIuZYMiVZs2XuQLS/muJcpwCYaZ21MLLxRXlG8TYkL/MHGXmeN+xt8iMIwfwsCx iw0YZQHQ/XIBhj/gI3jMtG1QMf7H1XPn7wcgnMGIuzxR8U4NgYBRanUEkpB6Jvm7zNo9 HEWpZQdRcHEJB0y4mCD3fMD9vsJtZIaW2bGHjeEJyjkzlpDhiqdQI2afOSzjIRL4f+kb CiPw== X-Gm-Message-State: APjAAAWddzncdbJ210mVszailiMmSQQ49VZceZIHVUDw/FjS4fAZLVzn F7rRjSUSOC9utEwz51dbckYmPnnDqw0= X-Google-Smtp-Source: APXvYqxzgymhRZeLTGd+uTDPLklKkVSdcN9v4CX05PWWnk6IT6Z5uVryFmn2XnQ172UOe98e99TZMw== X-Received: by 2002:a63:db10:: with SMTP id e16mr34890976pgg.142.1557792350421; Mon, 13 May 2019 17:05:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 13 May 2019 17:05:14 -0700 Message-Id: <20190514000540.4313-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190514000540.4313-1-richard.henderson@linaro.org> References: <20190514000540.4313-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::544 Subject: [Qemu-devel] [PULL 05/31] tcg: Assert fixed_reg is read-only X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linux.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) The only fixed_reg is cpu_env, and it should not be modified during any TB. Therefore code that tries to special-case moves into a fixed_reg is dead. Remove it. Reviewed-by: Alex Benn=C3=A9e Reviewed-by: David Hildenbrand Signed-off-by: Richard Henderson --- tcg/tcg.c | 87 +++++++++++++++++++++++++------------------------------ 1 file changed, 40 insertions(+), 47 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index f7bef51de8..70ca113c26 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -3274,11 +3274,8 @@ static void tcg_reg_alloc_do_movi(TCGContext *s, TCG= Temp *ots, tcg_target_ulong val, TCGLifeData arg_li= fe, TCGRegSet preferred_regs) { - if (ots->fixed_reg) { - /* For fixed registers, we do not do any constant propagation. */ - tcg_out_movi(s, ots->type, ots->reg, val); - return; - } + /* ENV should not be modified. */ + tcg_debug_assert(!ots->fixed_reg); =20 /* The movi is not explicitly generated here. */ if (ots->val_type =3D=3D TEMP_VAL_REG) { @@ -3314,6 +3311,9 @@ static void tcg_reg_alloc_mov(TCGContext *s, const TC= GOp *op) ots =3D arg_temp(op->args[0]); ts =3D arg_temp(op->args[1]); =20 + /* ENV should not be modified. */ + tcg_debug_assert(!ots->fixed_reg); + /* Note that otype !=3D itype for no-op truncation. */ otype =3D ots->type; itype =3D ts->type; @@ -3338,7 +3338,7 @@ static void tcg_reg_alloc_mov(TCGContext *s, const TC= GOp *op) } =20 tcg_debug_assert(ts->val_type =3D=3D TEMP_VAL_REG); - if (IS_DEAD_ARG(0) && !ots->fixed_reg) { + if (IS_DEAD_ARG(0)) { /* mov to a non-saved dead register makes no sense (even with liveness analysis disabled). */ tcg_debug_assert(NEED_SYNC_ARG(0)); @@ -3351,7 +3351,7 @@ static void tcg_reg_alloc_mov(TCGContext *s, const TC= GOp *op) } temp_dead(s, ots); } else { - if (IS_DEAD_ARG(1) && !ts->fixed_reg && !ots->fixed_reg) { + if (IS_DEAD_ARG(1) && !ts->fixed_reg) { /* the mov can be suppressed */ if (ots->val_type =3D=3D TEMP_VAL_REG) { s->reg_to_temp[ots->reg] =3D NULL; @@ -3504,6 +3504,10 @@ static void tcg_reg_alloc_op(TCGContext *s, const TC= GOp *op) arg =3D op->args[i]; arg_ct =3D &def->args_ct[i]; ts =3D arg_temp(arg); + + /* ENV should not be modified. */ + tcg_debug_assert(!ts->fixed_reg); + if ((arg_ct->ct & TCG_CT_ALIAS) && !const_args[arg_ct->alias_index]) { reg =3D new_args[arg_ct->alias_index]; @@ -3512,29 +3516,21 @@ static void tcg_reg_alloc_op(TCGContext *s, const T= CGOp *op) i_allocated_regs | o_allocated_regs, op->output_pref[k], ts->indirect_base); } else { - /* if fixed register, we try to use it */ - reg =3D ts->reg; - if (ts->fixed_reg && - tcg_regset_test_reg(arg_ct->u.regs, reg)) { - goto oarg_end; - } reg =3D tcg_reg_alloc(s, arg_ct->u.regs, o_allocated_regs, op->output_pref[k], ts->indirect_base); } tcg_regset_set_reg(o_allocated_regs, reg); - /* if a fixed register is used, then a move will be done after= wards */ - if (!ts->fixed_reg) { - if (ts->val_type =3D=3D TEMP_VAL_REG) { - s->reg_to_temp[ts->reg] =3D NULL; - } - ts->val_type =3D TEMP_VAL_REG; - ts->reg =3D reg; - /* temp value is modified, so the value kept in memory is - potentially not the same */ - ts->mem_coherent =3D 0; - s->reg_to_temp[reg] =3D ts; + if (ts->val_type =3D=3D TEMP_VAL_REG) { + s->reg_to_temp[ts->reg] =3D NULL; } - oarg_end: + ts->val_type =3D TEMP_VAL_REG; + ts->reg =3D reg; + /* + * Temp value is modified, so the value kept in memory is + * potentially not the same. + */ + ts->mem_coherent =3D 0; + s->reg_to_temp[reg] =3D ts; new_args[i] =3D reg; } } @@ -3550,10 +3546,10 @@ static void tcg_reg_alloc_op(TCGContext *s, const T= CGOp *op) /* move the outputs in the correct register if needed */ for(i =3D 0; i < nb_oargs; i++) { ts =3D arg_temp(op->args[i]); - reg =3D new_args[i]; - if (ts->fixed_reg && ts->reg !=3D reg) { - tcg_out_mov(s, ts->type, ts->reg, reg); - } + + /* ENV should not be modified. */ + tcg_debug_assert(!ts->fixed_reg); + if (NEED_SYNC_ARG(i)) { temp_sync(s, ts, o_allocated_regs, 0, IS_DEAD_ARG(i)); } else if (IS_DEAD_ARG(i)) { @@ -3674,26 +3670,23 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp= *op) for(i =3D 0; i < nb_oargs; i++) { arg =3D op->args[i]; ts =3D arg_temp(arg); + + /* ENV should not be modified. */ + tcg_debug_assert(!ts->fixed_reg); + reg =3D tcg_target_call_oarg_regs[i]; tcg_debug_assert(s->reg_to_temp[reg] =3D=3D NULL); - - if (ts->fixed_reg) { - if (ts->reg !=3D reg) { - tcg_out_mov(s, ts->type, ts->reg, reg); - } - } else { - if (ts->val_type =3D=3D TEMP_VAL_REG) { - s->reg_to_temp[ts->reg] =3D NULL; - } - ts->val_type =3D TEMP_VAL_REG; - ts->reg =3D reg; - ts->mem_coherent =3D 0; - s->reg_to_temp[reg] =3D ts; - if (NEED_SYNC_ARG(i)) { - temp_sync(s, ts, allocated_regs, 0, IS_DEAD_ARG(i)); - } else if (IS_DEAD_ARG(i)) { - temp_dead(s, ts); - } + if (ts->val_type =3D=3D TEMP_VAL_REG) { + s->reg_to_temp[ts->reg] =3D NULL; + } + ts->val_type =3D TEMP_VAL_REG; + ts->reg =3D reg; + ts->mem_coherent =3D 0; + s->reg_to_temp[reg] =3D ts; + if (NEED_SYNC_ARG(i)) { + temp_sync(s, ts, allocated_regs, 0, IS_DEAD_ARG(i)); + } else if (IS_DEAD_ARG(i)) { + temp_dead(s, ts); } } } --=20 2.17.1 From nobody Fri Apr 19 16:27:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[97.113.13.231]) by smtp.gmail.com with ESMTPSA id u3sm238151pfn.29.2019.05.13.17.05.50 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 13 May 2019 17:05:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=eQYUrWBgaVSTGc+XM8Y45frZ2xC0wqtFT2VlLB2AH5Q=; b=mH26fGaGPiHha/BXvai1qtLdlWeL8KkKkQdpv7U64LKNa6LMcKQiOw6k+yv3LN2fF/ RiL0JuwuO7O6yySkmSmLYKFm6zZf8Rt2tCIpj1vm8OTa4aoSKuOlQeoTcWlkz/2wwOAL 1PWNa3XPElL7RzVDbawZHNWe3QMTmd+Cs/jU3CgLdFWYfl/41AtqGMQ8ZEoQdsenC/kB sXspskInX1amn66CX5UEgLXtflYDMCQVasLuzxe0uPKFfCGNcuJXbJON8wvXEX0yU5jc fU4hRgS+XzzhIYDYyNTHJfHf3HfG4gNFHHxygmpVdn0GS0KAcGVoYzIa7FrIaGLURQ8f oFIw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=eQYUrWBgaVSTGc+XM8Y45frZ2xC0wqtFT2VlLB2AH5Q=; b=ApoegiCRnHFeib0yVS5+7At7QHBt+Lt86bCwhLo46PzCMY3MJQKLwnWaQ36D7KrAH9 EoVia/+giL5jppQ9QnBEyXSagLL3fdwlP9sx/KwO1MewVBuq1AB71Acke2Q0z6dJpEd0 H9itaMDI0MQRvcsZVZaC7TLBT88yNFlCYh4DI+6UXOeZT+S++AAgMiSJ7L+a3K48Szc7 N8OcZhMzu3msu8+rWVk+0ufQaTlHCGipNIzcaNRJB2wNbxU6JYaB6mi4fVPdQjSNpgQU Dn2xrxi4+3GhApri3VOQ/TRL8E1nyeSDtXknDqARTNmGQhoRsjnYBFyQrZ0HJ91rUvtY 4Vxw== X-Gm-Message-State: APjAAAUMp/lihf4XQGLJG5vmbnIeraMcazjxwzqqS3R/zj0qGeQXzPdd 3JJ9VEcomjytq+Fy0TmLmFBLq6fnr6g= X-Google-Smtp-Source: APXvYqwvEqC/fd3E1DMYVPCpU7jwfjjvtBLjK/Y6ui7gWFhu8YZmuerFMIS64F6bWW5YkVvBugzh0g== X-Received: by 2002:a17:902:e104:: with SMTP id cc4mr33070434plb.254.1557792351612; Mon, 13 May 2019 17:05:51 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 13 May 2019 17:05:15 -0700 Message-Id: <20190514000540.4313-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190514000540.4313-1-richard.henderson@linaro.org> References: <20190514000540.4313-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 Subject: [Qemu-devel] [PULL 06/31] tcg/arm: Use tcg_out_mov_reg in tcg_out_mov X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linux.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We have a function that takes an additional condition parameter over the standard backend interface. It already takes care of eliding no-op moves. Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.inc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c index abf0c444b4..130b6bef1e 100644 --- a/tcg/arm/tcg-target.inc.c +++ b/tcg/arm/tcg-target.inc.c @@ -2267,7 +2267,7 @@ static inline bool tcg_out_sti(TCGContext *s, TCGType= type, TCGArg val, static inline void tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) { - tcg_out_dat_reg(s, COND_AL, ARITH_MOV, ret, 0, arg, SHIFT_IMM_LSL(0)); + tcg_out_mov_reg(s, COND_AL, ret, arg); } =20 static inline void tcg_out_movi(TCGContext *s, TCGType type, --=20 2.17.1 From nobody Fri Apr 19 16:27:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1557792572; cv=none; d=zoho.com; s=zohoarc; b=Gt1SyqbxSzkke6GykBUtDxzoN4o/TdZgW1W0lc9+5Nh+TagAJB4bHnudsr1fTcoPZRsV5QPziLFPKbXCXiCNhladxtNXrfnUzjEY/zJTn6YPgoZ4WAaNXS23/dCuY6Oe/lehzMCMpW3A6+tlNtfvbkr6AbFYz3xVWLcVGo6IVQ4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1557792572; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=DVRqREBkCOgKbqofVojwT8Y9Ia/mxWbAuVeJ6nGotn0=; b=C9+oqzDMwhXz2Fmv7ZDx11eqKflMfY0xId6btWC+lked2N1MZyIEQwpVFl9L1cxd73/M1KoPKjqptokEaAyUNGpLtv/GoPp/1KIv9LDHv6oJ6CrkWoGZvcz+Z4DY61fgHv0vCD7oqfmvq3OYyEDnpXoxdfnVmaq7hBCnz2xOs8g= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1557792572563178.4288957720512; Mon, 13 May 2019 17:09:32 -0700 (PDT) Received: from localhost ([127.0.0.1]:36597 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hQL0T-0002e4-3t for importer@patchew.org; Mon, 13 May 2019 20:09:21 -0400 Received: from eggs.gnu.org ([209.51.188.92]:51008) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hQKy5-0001d5-AW for qemu-devel@nongnu.org; Mon, 13 May 2019 20:07:26 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hQKxH-0003FI-Fm for qemu-devel@nongnu.org; Mon, 13 May 2019 20:06:52 -0400 Received: from mail-pf1-x42b.google.com ([2607:f8b0:4864:20::42b]:38542) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hQKxA-00033v-Mw for qemu-devel@nongnu.org; Mon, 13 May 2019 20:05:58 -0400 Received: by mail-pf1-x42b.google.com with SMTP id y2so2609800pfg.5 for ; Mon, 13 May 2019 17:05:54 -0700 (PDT) Received: from localhost.localdomain (97-113-13-231.tukw.qwest.net. [97.113.13.231]) by smtp.gmail.com with ESMTPSA id u3sm238151pfn.29.2019.05.13.17.05.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 13 May 2019 17:05:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=DVRqREBkCOgKbqofVojwT8Y9Ia/mxWbAuVeJ6nGotn0=; b=K7yR9aaSlUwuvsGHVIQrFGX2LOshkScm97qK+6sVWa/aRxWul92/5pJh6ky3huHRLT hC0j5BLUYgwzToqJup4/W1BVgcasz5nLKBGNoeKE1dmVMAs4/Hml2tFWEWOrsDquSN4+ bWdTfq9UFXcia8j/M/2PDgOcOhn+j6sRkCvEgOKk2laniKo4ElL+N7eWuG6alQcqwcaS 797DJzlwhxKJjfsJZ/fMuHkaQfCKofyq5beDar3XwQKhW5MfKKiX9KHz9w/r7/d8D2xW PIDnmAjbzVn+uejcZ6zsgvLM/6dh14lKsVquy3Pk8X6ePkvuoDH8JUhJZlKeAz08J7x/ EkyQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=DVRqREBkCOgKbqofVojwT8Y9Ia/mxWbAuVeJ6nGotn0=; b=NWpsyKrsr+0blVgop9bKCgCFUBBdXgRVc3H4Pci8/RVqSLf8fEZ64q1rQBgGaF+Pjv bY2Jr1WAkZACFj7mkAOcuH27TgZK7OD+EbwOyVI0KoTZMR3GRpRVPCfTOse4kNzwiRg/ ozc7iHVV/vnsy+U9SlPo5WzHXwrQbl/+LLMWoUAfPSeuQH8n26hdsFNW4xjUykWPN0ht nWJDpZeXYQuforc3FVpYZ1NanbKhtyROvBYCCVZWM8EhqNDVXlj4taCkiZm6OU0F1Q/+ XnIkRqgqe3NsCikAUSyUr4B095QfiFcNH6mlwYnZU2JW3fhQ5SRcHLCq5bq46MifeP9D rMjQ== X-Gm-Message-State: APjAAAVmzR62wKDLhZXRFtBrkO6qGMi7chYHQT5takq8ypHUM3Mrl8K8 cPmnpj+io8HwTDQKx3w580b/svsuXyM= X-Google-Smtp-Source: APXvYqxzn2kuAQDh5oFF4xgaMeZpRbRQENHTc7qWZKJBpYOA2WgbKTmjBm1SAAjqaYvnhz9OPDP0Zg== X-Received: by 2002:a62:582:: with SMTP id 124mr37427958pff.209.1557792353090; Mon, 13 May 2019 17:05:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 13 May 2019 17:05:16 -0700 Message-Id: <20190514000540.4313-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190514000540.4313-1-richard.henderson@linaro.org> References: <20190514000540.4313-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::42b Subject: [Qemu-devel] [PULL 07/31] tcg: Return bool success from tcg_out_mov X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linux.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) This patch merely changes the interface, aborting on all failures, of which there are currently none. Reviewed-by: Alex Benn=C3=A9e Reviewed-by: David Hildenbrand Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: David Gibson Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.inc.c | 5 +++-- tcg/arm/tcg-target.inc.c | 3 ++- tcg/i386/tcg-target.inc.c | 5 +++-- tcg/mips/tcg-target.inc.c | 3 ++- tcg/ppc/tcg-target.inc.c | 3 ++- tcg/riscv/tcg-target.inc.c | 5 +++-- tcg/s390/tcg-target.inc.c | 3 ++- tcg/sparc/tcg-target.inc.c | 3 ++- tcg/tcg.c | 14 ++++++++++---- tcg/tci/tcg-target.inc.c | 3 ++- 10 files changed, 31 insertions(+), 16 deletions(-) diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c index eefa929948..ee89734318 100644 --- a/tcg/aarch64/tcg-target.inc.c +++ b/tcg/aarch64/tcg-target.inc.c @@ -938,10 +938,10 @@ static void tcg_out_ldst(TCGContext *s, AArch64Insn i= nsn, TCGReg rd, tcg_out_ldst_r(s, insn, rd, rn, TCG_TYPE_I64, TCG_REG_TMP); } =20 -static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg ar= g) +static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg ar= g) { if (ret =3D=3D arg) { - return; + return true; } switch (type) { case TCG_TYPE_I32: @@ -970,6 +970,7 @@ static void tcg_out_mov(TCGContext *s, TCGType type, TC= GReg ret, TCGReg arg) default: g_assert_not_reached(); } + return true; } =20 static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c index 130b6bef1e..7316504c9d 100644 --- a/tcg/arm/tcg-target.inc.c +++ b/tcg/arm/tcg-target.inc.c @@ -2264,10 +2264,11 @@ static inline bool tcg_out_sti(TCGContext *s, TCGTy= pe type, TCGArg val, return false; } =20 -static inline void tcg_out_mov(TCGContext *s, TCGType type, +static inline bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) { tcg_out_mov_reg(s, COND_AL, ret, arg); + return true; } =20 static inline void tcg_out_movi(TCGContext *s, TCGType type, diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index d5ed9f1ffd..1198c76392 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -809,12 +809,12 @@ static inline void tgen_arithr(TCGContext *s, int sub= op, int dest, int src) tcg_out_modrm(s, OPC_ARITH_GvEv + (subop << 3) + ext, dest, src); } =20 -static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg ar= g) +static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg ar= g) { int rexw =3D 0; =20 if (arg =3D=3D ret) { - return; + return true; } switch (type) { case TCG_TYPE_I64: @@ -852,6 +852,7 @@ static void tcg_out_mov(TCGContext *s, TCGType type, TC= GReg ret, TCGReg arg) default: g_assert_not_reached(); } + return true; } =20 static void tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c index 412cacdcb9..7cafd4a790 100644 --- a/tcg/mips/tcg-target.inc.c +++ b/tcg/mips/tcg-target.inc.c @@ -558,13 +558,14 @@ static inline void tcg_out_dsra(TCGContext *s, TCGReg= rd, TCGReg rt, TCGArg sa) tcg_out_opc_sa64(s, OPC_DSRA, OPC_DSRA32, rd, rt, sa); } =20 -static inline void tcg_out_mov(TCGContext *s, TCGType type, +static inline bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) { /* Simple reg-reg move, optimising out the 'do nothing' case */ if (ret !=3D arg) { tcg_out_opc_reg(s, OPC_OR, ret, arg, TCG_REG_ZERO); } + return true; } =20 static void tcg_out_movi(TCGContext *s, TCGType type, diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index 36b4791707..30c095d3d5 100644 --- a/tcg/ppc/tcg-target.inc.c +++ b/tcg/ppc/tcg-target.inc.c @@ -559,12 +559,13 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int = type, static void tcg_out_mem_long(TCGContext *s, int opi, int opx, TCGReg rt, TCGReg base, tcg_target_long offset); =20 -static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg ar= g) +static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg ar= g) { tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 64 || type =3D=3D TCG_TYPE= _I32); if (ret !=3D arg) { tcg_out32(s, OR | SAB(arg, ret, arg)); } + return true; } =20 static inline void tcg_out_rld(TCGContext *s, int op, TCGReg ra, TCGReg rs, diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c index 2932505094..6497a4dab2 100644 --- a/tcg/riscv/tcg-target.inc.c +++ b/tcg/riscv/tcg-target.inc.c @@ -515,10 +515,10 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int = type, * TCG intrinsics */ =20 -static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg ar= g) +static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg ar= g) { if (ret =3D=3D arg) { - return; + return true; } switch (type) { case TCG_TYPE_I32: @@ -528,6 +528,7 @@ static void tcg_out_mov(TCGContext *s, TCGType type, TC= GReg ret, TCGReg arg) default: g_assert_not_reached(); } + return true; } =20 static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd, diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c index 3d6150b10e..331d51852c 100644 --- a/tcg/s390/tcg-target.inc.c +++ b/tcg/s390/tcg-target.inc.c @@ -548,7 +548,7 @@ static void tcg_out_sh32(TCGContext* s, S390Opcode op, = TCGReg dest, tcg_out_insn_RS(s, op, dest, sh_reg, 0, sh_imm); } =20 -static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg dst, TCGReg sr= c) +static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg dst, TCGReg sr= c) { if (src !=3D dst) { if (type =3D=3D TCG_TYPE_I32) { @@ -557,6 +557,7 @@ static void tcg_out_mov(TCGContext *s, TCGType type, TC= GReg dst, TCGReg src) tcg_out_insn(s, RRE, LGR, dst, src); } } + return true; } =20 static const S390Opcode lli_insns[4] =3D { diff --git a/tcg/sparc/tcg-target.inc.c b/tcg/sparc/tcg-target.inc.c index 7a61839dc1..83295955a7 100644 --- a/tcg/sparc/tcg-target.inc.c +++ b/tcg/sparc/tcg-target.inc.c @@ -407,12 +407,13 @@ static void tcg_out_arithc(TCGContext *s, TCGReg rd, = TCGReg rs1, | (val2const ? INSN_IMM13(val2) : INSN_RS2(val2))); } =20 -static inline void tcg_out_mov(TCGContext *s, TCGType type, +static inline bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) { if (ret !=3D arg) { tcg_out_arith(s, ret, arg, TCG_REG_G0, ARITH_OR); } + return true; } =20 static inline void tcg_out_sethi(TCGContext *s, TCGReg ret, uint32_t arg) diff --git a/tcg/tcg.c b/tcg/tcg.c index 70ca113c26..8ed7cb8654 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -103,7 +103,7 @@ static const char *target_parse_constraint(TCGArgConstr= aint *ct, const char *ct_str, TCGType typ= e); static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg= 1, intptr_t arg2); -static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg ar= g); +static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg ar= g); static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg ret, tcg_target_long arg); static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, @@ -3367,7 +3367,9 @@ static void tcg_reg_alloc_mov(TCGContext *s, const TC= GOp *op) allocated_regs, preferred_regs, ots->indirect_base); } - tcg_out_mov(s, otype, ots->reg, ts->reg); + if (!tcg_out_mov(s, otype, ots->reg, ts->reg)) { + abort(); + } } ots->val_type =3D TEMP_VAL_REG; ots->mem_coherent =3D 0; @@ -3467,7 +3469,9 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCG= Op *op) i_allocated_regs, 0); reg =3D tcg_reg_alloc(s, arg_ct->u.regs, i_allocated_regs, o_preferred_regs, ts->indirect_base); - tcg_out_mov(s, ts->type, reg, ts->reg); + if (!tcg_out_mov(s, ts->type, reg, ts->reg)) { + abort(); + } } new_args[i] =3D reg; const_args[i] =3D 0; @@ -3626,7 +3630,9 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp *= op) if (ts->val_type =3D=3D TEMP_VAL_REG) { if (ts->reg !=3D reg) { tcg_reg_free(s, reg, allocated_regs); - tcg_out_mov(s, ts->type, reg, ts->reg); + if (!tcg_out_mov(s, ts->type, reg, ts->reg)) { + abort(); + } } } else { TCGRegSet arg_set =3D 0; diff --git a/tcg/tci/tcg-target.inc.c b/tcg/tci/tcg-target.inc.c index 0015a98485..992d50cb1e 100644 --- a/tcg/tci/tcg-target.inc.c +++ b/tcg/tci/tcg-target.inc.c @@ -509,7 +509,7 @@ static void tcg_out_ld(TCGContext *s, TCGType type, TCG= Reg ret, TCGReg arg1, old_code_ptr[1] =3D s->code_ptr - old_code_ptr; } =20 -static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg ar= g) +static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg ar= g) { uint8_t *old_code_ptr =3D s->code_ptr; tcg_debug_assert(ret !=3D arg); @@ -521,6 +521,7 @@ static void tcg_out_mov(TCGContext *s, TCGType type, TC= GReg ret, TCGReg arg) tcg_out_r(s, ret); tcg_out_r(s, arg); old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + return true; } =20 static void tcg_out_movi(TCGContext *s, TCGType type, --=20 2.17.1 From nobody Fri Apr 19 16:27:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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[97.113.13.231]) by smtp.gmail.com with ESMTPSA id u3sm238151pfn.29.2019.05.13.17.05.53 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 13 May 2019 17:05:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=jMr4oVpt08WI1vYqrX0gvWFc/UY/0FSsdcwMQYw/C7U=; b=qqlRZCs7JRToB5ZfRsgr96EGQPqxfTfXeXuyOuXqL+hxuTEch6+KRMPYH32OY2r12d z7hNC35yW28DBFczbreaGOrMKBSLpVDAuGex6Sts3FdLIqATvg1R/Ob6iztzUvCMxDGW 4u+pTEEYcMDl++yMcNj/cfB38ObrlX6EnuzVIp4DdEvzI7GYtxkuVWbW0DuD6jxK7kVN AzO5gRf+85yzLlODaPnt7JkcyvPbYykg+YLS4zZs99bL3ZnHg6Kx8ZlAM0+DCs98Jkxp GsVAF8rTBtzSw4FTGjayUBeenf+UWDHSYNu4Cvh4XHUI++9Pj5z397P7bA/8bSn8s0LV lzFw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=jMr4oVpt08WI1vYqrX0gvWFc/UY/0FSsdcwMQYw/C7U=; b=i7BQ0npdekWukyNtuiSe/e5EBbP4jgg/lYk5sk9du9tsqOz+x3c8kfdEIJPI92nf7i Rcmlk+VBBHQISNcAX9asIwwrJ9IAGgQ9pNUCp66/9kl2FdW7oWbuD/HQBy/8xHdLZda3 xW7IcQtq3a9OdOPDnqFTSffTMWbWeUn3jbTAPEcHgBi4M0mFyGg7ALeuaqpjh2wL+BZj i6jZfllePNYeLzWFU0IQK9kAozpMkV3GqgQxIzsawNQxXhfj8BdIEN/spjI97VOz0GiC 04TbkZGV+FN4N3jdtnho11gApCqeqXWS2x5k5XaAMxUilzpluIk6PPYnKpMzxE6qyNSo 71Zg== X-Gm-Message-State: APjAAAX2aDadAXQhLiErK+uwQ4Gzv82t/AjLu3qGzztt0dnQeZD3ajgf ZpG8XHsAkKpTvbfKGPpTiDfT+WLgkXE= X-Google-Smtp-Source: APXvYqxR2SakVOJ9wcAmsLSEZS1PNvQbBuf2apjdtKWvdkHjiCeCSmWLG5J+9xpKrV0Kzztn85wH9g== X-Received: by 2002:a62:5cc6:: with SMTP id q189mr6419457pfb.114.1557792354415; Mon, 13 May 2019 17:05:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 13 May 2019 17:05:17 -0700 Message-Id: <20190514000540.4313-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190514000540.4313-1-richard.henderson@linaro.org> References: <20190514000540.4313-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::532 Subject: [Qemu-devel] [PULL 08/31] tcg: Support cross-class moves without instruction support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linux.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" PowerPC Altivec does not support direct moves between vector registers and general registers. So when tcg_out_mov fails, we can use the backing memory for the temporary to perform the move. Acked-by: David Hildenbrand Signed-off-by: Richard Henderson --- tcg/tcg.c | 31 ++++++++++++++++++++++++++++--- 1 file changed, 28 insertions(+), 3 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index 8ed7cb8654..68d86361e2 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -3368,7 +3368,20 @@ static void tcg_reg_alloc_mov(TCGContext *s, const T= CGOp *op) ots->indirect_base); } if (!tcg_out_mov(s, otype, ots->reg, ts->reg)) { - abort(); + /* + * Cross register class move not supported. + * Store the source register into the destination slot + * and leave the destination temp as TEMP_VAL_MEM. + */ + assert(!ots->fixed_reg); + if (!ts->mem_allocated) { + temp_allocate_frame(s, ots); + } + tcg_out_st(s, ts->type, ts->reg, + ots->mem_base->reg, ots->mem_offset); + ots->mem_coherent =3D 1; + temp_free_or_dead(s, ots, -1); + return; } } ots->val_type =3D TEMP_VAL_REG; @@ -3470,7 +3483,13 @@ static void tcg_reg_alloc_op(TCGContext *s, const TC= GOp *op) reg =3D tcg_reg_alloc(s, arg_ct->u.regs, i_allocated_regs, o_preferred_regs, ts->indirect_base); if (!tcg_out_mov(s, ts->type, reg, ts->reg)) { - abort(); + /* + * Cross register class move not supported. Sync the + * temp back to its slot and load from there. + */ + temp_sync(s, ts, i_allocated_regs, 0, 0); + tcg_out_ld(s, ts->type, reg, + ts->mem_base->reg, ts->mem_offset); } } new_args[i] =3D reg; @@ -3631,7 +3650,13 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp = *op) if (ts->reg !=3D reg) { tcg_reg_free(s, reg, allocated_regs); if (!tcg_out_mov(s, ts->type, reg, ts->reg)) { - abort(); + /* + * Cross register class move not supported. Sync = the + * temp back to its slot and load from there. + */ + temp_sync(s, ts, allocated_regs, 0, 0); + tcg_out_ld(s, ts->type, reg, + ts->mem_base->reg, ts->mem_offset); } } } else { --=20 2.17.1 From nobody Fri Apr 19 16:27:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1557792739; cv=none; d=zoho.com; s=zohoarc; b=THFUBlzcY+B2aUw04JsCozQWAVHtufVqjuHx5u055hVevqw54+yNlZj1t9Px4jJGUjwliF3XmjpJj+ZOtxnO/IIEJxY8lySqdTYk6fg/oki62qlVl8IWbSmleRUtWHfZvGN19s2bDZLHmLtr2a7qaUijbfLRavVi1cMMeki34IE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1557792739; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=vlsz3mBJLHv925hZ117IYDgBd7E32bASu3EG/5gz9gQ=; b=KndP1OcmGoM3cx2hsy9ot+xZdV7a41N/XLJ1C4nSrfyLQHO/kpHcOd+4YLP365cVlZ4NEpTf0YVXY2WU9sgLHqmtWyRDMTlpLWZOq+3qWFToIbphVBppuTAfVDL/xaVMiIG+ASEyhyicjE5WCZF0S3VPmcuFnWrXMaRc4525osI= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1557792739097290.2711591196464; Mon, 13 May 2019 17:12:19 -0700 (PDT) Received: from localhost ([127.0.0.1]:36660 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hQL3E-0005QN-Vq for importer@patchew.org; Mon, 13 May 2019 20:12:13 -0400 Received: from eggs.gnu.org ([209.51.188.92]:53112) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hQKz6-00020x-JK for qemu-devel@nongnu.org; Mon, 13 May 2019 20:09:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hQKxL-0003NX-Np for qemu-devel@nongnu.org; Mon, 13 May 2019 20:07:56 -0400 Received: from mail-pg1-x530.google.com ([2607:f8b0:4864:20::530]:43858) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hQKxJ-00036P-7N for qemu-devel@nongnu.org; Mon, 13 May 2019 20:06:05 -0400 Received: by mail-pg1-x530.google.com with SMTP id t22so7591157pgi.10 for ; Mon, 13 May 2019 17:05:56 -0700 (PDT) Received: from localhost.localdomain (97-113-13-231.tukw.qwest.net. [97.113.13.231]) by smtp.gmail.com with ESMTPSA id u3sm238151pfn.29.2019.05.13.17.05.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 13 May 2019 17:05:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vlsz3mBJLHv925hZ117IYDgBd7E32bASu3EG/5gz9gQ=; b=U3lHCTYaWj6/bj3g9F9SoDzJWXOQY9zVP9wYQEU8umW2l7quU5KpaaRDg0iVtT4nLh 0D0FmS7AB343OVF/jCr5t5hembYiwNZGIWlHXamBFXSK6vRjPenG6BbZySeDJCQCJhtI bLTb013hxrB60ZmLVtj6iwwa8vOVLLPZXxEKFuHw3Tm0n6kOSXVvk/HKab18w2/Y2J23 q8Nv3Kqqtz/mW08MMp8M61ys3IAiGbtv/QcsmZWB60oNH0Rl4WtMsvpP1jNznHBNI2kw sV4oCu/CUb9XVeaLBdWplA+c9NMx/AnmDdFfzxUPOhQ86/Mg0kOixJ5kKMQpFbNeRL2m b8/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vlsz3mBJLHv925hZ117IYDgBd7E32bASu3EG/5gz9gQ=; b=FqaDLyIa36Y+lJxJv8wMdLMXvNof5MGWe1ykH5TLskrACxRE1xnTyt+Ze6xFsMSJk3 n4OO1RMPKt8AdW/yWX5SBkBLkrg/KasvtwMNFB9dFXqc2zhw0RBbaJiFzoIhPDlsWWsw egfi0AlgqTz0YVjUYHNPHlPAfTSqJ7JTObiFqvXcvZplevZDjXW4nh80AbjOHrD5/aa0 Q/p0ckolBd9GW7jGEP5+ewpX3mm7QWwwVQn82/HDGacekVmtnvJnyAv2QisplCJjNm+S khbgRVKN7Yx55yqK7BYo/6KDfdFvBrmkC0NryOhdxLLu5ex9GEyL8AOmmjMxQR49ov5z U85Q== X-Gm-Message-State: APjAAAVvk77+nE6BldQ5i7207Jx6gAs8jkkn+y8bZGn5jMscg6xi9Sdx TOk6w0PvSxYxcQtswYZhuCkOggdbbBk= X-Google-Smtp-Source: APXvYqzNXcfyWzJ+kjIUFZkknH+ShFtnbYvWGYG+7g5kFbuFEJLZjxq64gPB0AX4wAZk7qiy/w4DAw== X-Received: by 2002:aa7:8252:: with SMTP id e18mr37038185pfn.105.1557792355560; Mon, 13 May 2019 17:05:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 13 May 2019 17:05:18 -0700 Message-Id: <20190514000540.4313-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190514000540.4313-1-richard.henderson@linaro.org> References: <20190514000540.4313-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::530 Subject: [Qemu-devel] [PULL 09/31] tcg: Promote tcg_out_{dup, dupi}_vec to backend interface X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linux.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) The i386 backend already has these functions, and the aarch64 backend could easily split out one. Nothing is done with these functions yet, but this will aid register allocation of INDEX_op_dup_vec in a later patch. Adjust the aarch64 tcg_out_dupi_vec signature to match the new interface. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.inc.c | 12 ++++++++++-- tcg/i386/tcg-target.inc.c | 3 ++- tcg/tcg.c | 14 ++++++++++++++ 3 files changed, 26 insertions(+), 3 deletions(-) diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c index ee89734318..e443b5df23 100644 --- a/tcg/aarch64/tcg-target.inc.c +++ b/tcg/aarch64/tcg-target.inc.c @@ -799,7 +799,7 @@ static void tcg_out_logicali(TCGContext *s, AArch64Insn= insn, TCGType ext, } =20 static void tcg_out_dupi_vec(TCGContext *s, TCGType type, - TCGReg rd, uint64_t v64) + TCGReg rd, tcg_target_long v64) { int op, cmode, imm8; =20 @@ -814,6 +814,14 @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType ty= pe, } } =20 +static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, + TCGReg rd, TCGReg rs) +{ + int is_q =3D type - TCG_TYPE_V64; + tcg_out_insn(s, 3605, DUP, is_q, rd, rs, 1 << vece, 0); + return true; +} + static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd, tcg_target_long value) { @@ -2201,7 +2209,7 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode o= pc, tcg_out_insn(s, 3617, NOT, is_q, 0, a0, a1); break; case INDEX_op_dup_vec: - tcg_out_insn(s, 3605, DUP, is_q, a0, a1, 1 << vece, 0); + tcg_out_dup_vec(s, type, vece, a0, a1); break; case INDEX_op_shli_vec: tcg_out_insn(s, 3614, SHL, is_q, a0, a1, a2 + (8 << vece)); diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index 1198c76392..0d621670c7 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -855,7 +855,7 @@ static bool tcg_out_mov(TCGContext *s, TCGType type, TC= GReg ret, TCGReg arg) return true; } =20 -static void tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, +static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, TCGReg r, TCGReg a) { if (have_avx2) { @@ -888,6 +888,7 @@ static void tcg_out_dup_vec(TCGContext *s, TCGType type= , unsigned vece, g_assert_not_reached(); } } + return true; } =20 static void tcg_out_dupi_vec(TCGContext *s, TCGType type, diff --git a/tcg/tcg.c b/tcg/tcg.c index 68d86361e2..3ef4d3478d 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -109,10 +109,24 @@ static void tcg_out_movi(TCGContext *s, TCGType type, static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, const int *const_args); #if TCG_TARGET_MAYBE_vec +static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, + TCGReg dst, TCGReg src); +static void tcg_out_dupi_vec(TCGContext *s, TCGType type, + TCGReg dst, tcg_target_long arg); static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, unsigned vecl, unsigned vece, const TCGArg *args, const int *const_args); #else +static inline bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned v= ece, + TCGReg dst, TCGReg src) +{ + g_assert_not_reached(); +} +static inline void tcg_out_dupi_vec(TCGContext *s, TCGType type, + TCGReg dst, tcg_target_long arg) +{ + g_assert_not_reached(); +} static inline void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, unsigned v= ecl, unsigned vece, const TCGArg *args, const int *const_args) --=20 2.17.1 From nobody Fri Apr 19 16:27:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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X-Received-From: 2607:f8b0:4864:20::430 Subject: [Qemu-devel] [PULL 10/31] tcg: Manually expand INDEX_op_dup_vec X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linux.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This case is similar to INDEX_op_mov_* in that we need to do different things depending on the current location of the source. Signed-off-by: Richard Henderson --- v3: Added some commentary to the tcg_reg_alloc_* functions. --- tcg/aarch64/tcg-target.inc.c | 9 ++- tcg/i386/tcg-target.inc.c | 8 +-- tcg/tcg.c | 111 +++++++++++++++++++++++++++++++++++ 3 files changed, 118 insertions(+), 10 deletions(-) diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c index e443b5df23..3cefdd1e43 100644 --- a/tcg/aarch64/tcg-target.inc.c +++ b/tcg/aarch64/tcg-target.inc.c @@ -2108,10 +2108,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, =20 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ case INDEX_op_mov_i64: - case INDEX_op_mov_vec: case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */ case INDEX_op_movi_i64: - case INDEX_op_dupi_vec: case INDEX_op_call: /* Always emitted via tcg_out_call. */ default: g_assert_not_reached(); @@ -2208,9 +2206,6 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode o= pc, case INDEX_op_not_vec: tcg_out_insn(s, 3617, NOT, is_q, 0, a0, a1); break; - case INDEX_op_dup_vec: - tcg_out_dup_vec(s, type, vece, a0, a1); - break; case INDEX_op_shli_vec: tcg_out_insn(s, 3614, SHL, is_q, a0, a1, a2 + (8 << vece)); break; @@ -2254,6 +2249,10 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, } } break; + + case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */ + case INDEX_op_dupi_vec: /* Always emitted via tcg_out_movi. */ + case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */ default: g_assert_not_reached(); } diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index 0d621670c7..3c8229d413 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -2603,10 +2603,8 @@ static inline void tcg_out_op(TCGContext *s, TCGOpco= de opc, break; case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ case INDEX_op_mov_i64: - case INDEX_op_mov_vec: case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */ case INDEX_op_movi_i64: - case INDEX_op_dupi_vec: case INDEX_op_call: /* Always emitted via tcg_out_call. */ default: tcg_abort(); @@ -2795,9 +2793,6 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode o= pc, case INDEX_op_st_vec: tcg_out_st(s, type, a0, a1, a2); break; - case INDEX_op_dup_vec: - tcg_out_dup_vec(s, type, vece, a0, a1); - break; =20 case INDEX_op_x86_shufps_vec: insn =3D OPC_SHUFPS; @@ -2839,6 +2834,9 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode o= pc, tcg_out8(s, a2); break; =20 + case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */ + case INDEX_op_dupi_vec: /* Always emitted via tcg_out_movi. */ + case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */ default: g_assert_not_reached(); } diff --git a/tcg/tcg.c b/tcg/tcg.c index 3ef4d3478d..2b715bf099 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -3284,6 +3284,9 @@ static void tcg_reg_alloc_bb_end(TCGContext *s, TCGRe= gSet allocated_regs) save_globals(s, allocated_regs); } =20 +/* + * Specialized code generation for INDEX_op_movi_*. + */ static void tcg_reg_alloc_do_movi(TCGContext *s, TCGTemp *ots, tcg_target_ulong val, TCGLifeData arg_li= fe, TCGRegSet preferred_regs) @@ -3313,6 +3316,9 @@ static void tcg_reg_alloc_movi(TCGContext *s, const T= CGOp *op) tcg_reg_alloc_do_movi(s, ots, val, op->life, op->output_pref[0]); } =20 +/* + * Specialized code generation for INDEX_op_mov_*. + */ static void tcg_reg_alloc_mov(TCGContext *s, const TCGOp *op) { const TCGLifeData arg_life =3D op->life; @@ -3407,6 +3413,108 @@ static void tcg_reg_alloc_mov(TCGContext *s, const = TCGOp *op) } } =20 +/* + * Specialized code generation for INDEX_op_dup_vec. + */ +static void tcg_reg_alloc_dup(TCGContext *s, const TCGOp *op) +{ + const TCGLifeData arg_life =3D op->life; + TCGRegSet dup_out_regs, dup_in_regs; + TCGTemp *its, *ots; + TCGType itype, vtype; + unsigned vece; + bool ok; + + ots =3D arg_temp(op->args[0]); + its =3D arg_temp(op->args[1]); + + /* ENV should not be modified. */ + tcg_debug_assert(!ots->fixed_reg); + + itype =3D its->type; + vece =3D TCGOP_VECE(op); + vtype =3D TCGOP_VECL(op) + TCG_TYPE_V64; + + if (its->val_type =3D=3D TEMP_VAL_CONST) { + /* Propagate constant via movi -> dupi. */ + tcg_target_ulong val =3D its->val; + if (IS_DEAD_ARG(1)) { + temp_dead(s, its); + } + tcg_reg_alloc_do_movi(s, ots, val, arg_life, op->output_pref[0]); + return; + } + + dup_out_regs =3D tcg_op_defs[INDEX_op_dup_vec].args_ct[0].u.regs; + dup_in_regs =3D tcg_op_defs[INDEX_op_dup_vec].args_ct[1].u.regs; + + /* Allocate the output register now. */ + if (ots->val_type !=3D TEMP_VAL_REG) { + TCGRegSet allocated_regs =3D s->reserved_regs; + + if (!IS_DEAD_ARG(1) && its->val_type =3D=3D TEMP_VAL_REG) { + /* Make sure to not spill the input register. */ + tcg_regset_set_reg(allocated_regs, its->reg); + } + ots->reg =3D tcg_reg_alloc(s, dup_out_regs, allocated_regs, + op->output_pref[0], ots->indirect_base); + ots->val_type =3D TEMP_VAL_REG; + ots->mem_coherent =3D 0; + s->reg_to_temp[ots->reg] =3D ots; + } + + switch (its->val_type) { + case TEMP_VAL_REG: + /* + * The dup constriaints must be broad, covering all possible VECE. + * However, tcg_op_dup_vec() gets to see the VECE and we allow it + * to fail, indicating that extra moves are required for that case. + */ + if (tcg_regset_test_reg(dup_in_regs, its->reg)) { + if (tcg_out_dup_vec(s, vtype, vece, ots->reg, its->reg)) { + goto done; + } + /* Try again from memory or a vector input register. */ + } + if (!its->mem_coherent) { + /* + * The input register is not synced, and so an extra store + * would be required to use memory. Attempt an integer-vector + * register move first. We do not have a TCGRegSet for this. + */ + if (tcg_out_mov(s, itype, ots->reg, its->reg)) { + break; + } + /* Sync the temp back to its slot and load from there. */ + temp_sync(s, its, s->reserved_regs, 0, 0); + } + /* fall through */ + + case TEMP_VAL_MEM: + /* TODO: dup from memory */ + tcg_out_ld(s, itype, ots->reg, its->mem_base->reg, its->mem_offset= ); + break; + + default: + g_assert_not_reached(); + } + + /* We now have a vector input register, so dup must succeed. */ + ok =3D tcg_out_dup_vec(s, vtype, vece, ots->reg, ots->reg); + tcg_debug_assert(ok); + + done: + if (IS_DEAD_ARG(1)) { + temp_dead(s, its); + } + if (NEED_SYNC_ARG(0)) { + temp_sync(s, ots, s->reserved_regs, 0, 0); + } + if (IS_DEAD_ARG(0)) { + temp_dead(s, ots); + } +} + static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op) { const TCGLifeData arg_life =3D op->life; @@ -3981,6 +4089,9 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) case INDEX_op_dupi_vec: tcg_reg_alloc_movi(s, op); break; + case INDEX_op_dup_vec: + tcg_reg_alloc_dup(s, op); + break; case INDEX_op_insn_start: if (num_insns >=3D 0) { size_t off =3D tcg_current_code_size(s); --=20 2.17.1 From nobody Fri Apr 19 16:27:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1557806024; cv=none; d=zoho.com; s=zohoarc; b=hsq/yRlEX1umE/fjJWzgtKSPjv3rwdTCchd8wLL6r0MiiFsmRQZ7zYp3tzCIL74NXAgjcyN1OxRktWSHRpuD6ti/Aveqqk0s4sQCW/L11fpCbg3Ska1+Lc7vIvh1cirzH10mIxREBURWuORrDETvm97Jyhg0n7uxR/HIEXgQVC0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1557806024; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=yjaWcvw9UbJX/NgPrNoAKyN+ZZwbI4Jl9YPntsAKSX4=; b=ATeXsm3xhqUUjm8ZcP3O0ckRvONxzzOrhPzl2Y9nHx9qVHwOUsdy3X0uyLSAAQa99AHt3etx/RbNrjxW9O8kvnJmutBa4lA2n59mPA1nCY7OizpKFYGcgWa4j6OK5wXbHvhdpqph94VRc4TiF33uLoJS8l2BJnwNGi3Hxai4GjU= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1557806023974322.7841461957471; Mon, 13 May 2019 20:53:43 -0700 (PDT) Received: from localhost ([127.0.0.1]:38576 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hQOVV-0000qy-Kp for importer@patchew.org; Mon, 13 May 2019 23:53:37 -0400 Received: from eggs.gnu.org ([209.51.188.92]:56346) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hQOUU-0000BE-3T for qemu-devel@nongnu.org; Mon, 13 May 2019 23:52:35 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hQOUS-000355-Uk for qemu-devel@nongnu.org; Mon, 13 May 2019 23:52:34 -0400 Received: from mail-pf1-x42a.google.com ([2607:f8b0:4864:20::42a]:36943) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hQKxJ-0003Ay-9X for qemu-devel@nongnu.org; Mon, 13 May 2019 20:06:07 -0400 Received: by mail-pf1-x42a.google.com with SMTP id g3so8067283pfi.4 for ; Mon, 13 May 2019 17:05:59 -0700 (PDT) Received: from localhost.localdomain (97-113-13-231.tukw.qwest.net. [97.113.13.231]) by smtp.gmail.com with ESMTPSA id u3sm238151pfn.29.2019.05.13.17.05.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 13 May 2019 17:05:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=yjaWcvw9UbJX/NgPrNoAKyN+ZZwbI4Jl9YPntsAKSX4=; b=cI/k2fglzCzVv0W2UtPeSLi5Lo4mXGxJ9Uae728eJQPc2FXSW9n4qUv3tG0dKTNRua fI0eaDJ8V+0JNDwbtKovaO9gGa+OeDA0YnZEdQWDdOYJPLGhoSqJ+cySa6voAT/ay840 AE/STidMQbjqfkDERn+rVlRcIXBzwQDUSKU8+F5vDH/m9xtpVQSFyXc4IqG5lm+7KB/i Hu4imRsPpzXwnltiowpjIr1OhtuIuejwJLqF4gy427lgk3s4knHcFIv6eWI7Btojx1/S GCXLqly92L1BnKVh0baAvZ/4Pr0PE2EATks10BZxdqGde1y/WU0bXTtzR1IY3qyjlhm0 R0RQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=yjaWcvw9UbJX/NgPrNoAKyN+ZZwbI4Jl9YPntsAKSX4=; b=Lv5Ax1B95WYaMGNx9J/UlBswDWJ/Wft7X7vHeG2DT6RthXahDiNnfy+D8XX6r7lC9T m3IX0wDaptd/lmiUZVE9dkQIETIgJUyZtm2jbqlGUjcsqovREaHd0RQAayB5P6BlJwjn 7EFvpPgTZnXVCvpEbWl8CJtLJiWphfpr7LgOcJoYml8I64RWUbFOordsmFw1Yq4qaEDJ gWijQy6kmekPRNUvYMfJWH5dz9b+fd/kyHIAoPCRH9Suqr0Xu2aEcPHpWuf9EUoANdK8 YVOty5/xcKT5/zHhjr1eZpO65bQ8weL5UElSq+djoFfgEE36dApzGCRMOELGhUCPm7IE FUEg== X-Gm-Message-State: APjAAAUlgwY708Q7+FTcZCtTd5tUmkz7MzciWUVicl0N9JiiLThH6gDJ cxInp50ycwQL+R8owtz08c1xA7d+YT0= X-Google-Smtp-Source: APXvYqydk+4PGzlJS7rbgB1f+8+HV7dB6KptajTLSSdx4nJVwJssr0ryCVh/xmt11unpLa0+8EhZQw== X-Received: by 2002:a65:5241:: with SMTP id q1mr34254286pgp.298.1557792357975; Mon, 13 May 2019 17:05:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 13 May 2019 17:05:20 -0700 Message-Id: <20190514000540.4313-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190514000540.4313-1-richard.henderson@linaro.org> References: <20190514000540.4313-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::42a Subject: [Qemu-devel] [PULL 11/31] tcg: Add tcg_out_dupm_vec to the backend interface X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linux.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Currently stubbed out in all backends that support vectors. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.inc.c | 6 ++++++ tcg/i386/tcg-target.inc.c | 7 +++++++ tcg/tcg.c | 19 ++++++++++++++++++- 3 files changed, 31 insertions(+), 1 deletion(-) diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c index 3cefdd1e43..4a3cfa778a 100644 --- a/tcg/aarch64/tcg-target.inc.c +++ b/tcg/aarch64/tcg-target.inc.c @@ -822,6 +822,12 @@ static bool tcg_out_dup_vec(TCGContext *s, TCGType typ= e, unsigned vece, return true; } =20 +static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, + TCGReg r, TCGReg base, intptr_t offset) +{ + return false; +} + static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd, tcg_target_long value) { diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index 3c8229d413..f04933bc19 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -891,6 +891,13 @@ static bool tcg_out_dup_vec(TCGContext *s, TCGType typ= e, unsigned vece, return true; } =20 +static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, + TCGReg r, TCGReg base, intptr_t offset) +{ + return false; +} + + static void tcg_out_dupi_vec(TCGContext *s, TCGType type, TCGReg ret, tcg_target_long arg) { diff --git a/tcg/tcg.c b/tcg/tcg.c index 2b715bf099..b9945794c4 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -111,6 +111,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, co= nst TCGArg *args, #if TCG_TARGET_MAYBE_vec static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, TCGReg dst, TCGReg src); +static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, + TCGReg dst, TCGReg base, intptr_t offset); static void tcg_out_dupi_vec(TCGContext *s, TCGType type, TCGReg dst, tcg_target_long arg); static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, unsigned vecl, @@ -122,6 +124,11 @@ static inline bool tcg_out_dup_vec(TCGContext *s, TCGT= ype type, unsigned vece, { g_assert_not_reached(); } +static inline bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned = vece, + TCGReg dst, TCGReg base, intptr_t offs= et) +{ + g_assert_not_reached(); +} static inline void tcg_out_dupi_vec(TCGContext *s, TCGType type, TCGReg dst, tcg_target_long arg) { @@ -3422,6 +3429,7 @@ static void tcg_reg_alloc_dup(TCGContext *s, const TC= GOp *op) TCGRegSet dup_out_regs, dup_in_regs; TCGTemp *its, *ots; TCGType itype, vtype; + intptr_t endian_fixup; unsigned vece; bool ok; =20 @@ -3491,7 +3499,16 @@ static void tcg_reg_alloc_dup(TCGContext *s, const T= CGOp *op) /* fall through */ =20 case TEMP_VAL_MEM: - /* TODO: dup from memory */ +#ifdef HOST_WORDS_BIGENDIAN + endian_fixup =3D itype =3D=3D TCG_TYPE_I32 ? 4 : 8; + endian_fixup -=3D 1 << vece; +#else + endian_fixup =3D 0; +#endif + if (tcg_out_dupm_vec(s, vtype, vece, ots->reg, its->mem_base->reg, + its->mem_offset + endian_fixup)) { + goto done; + } tcg_out_ld(s, itype, ots->reg, its->mem_base->reg, its->mem_offset= ); break; =20 --=20 2.17.1 From nobody Fri Apr 19 16:27:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1557792580; cv=none; d=zoho.com; s=zohoarc; b=StT2u0Jglw/17Wh1lUROuW9jbSiizzOCIGwlvy+K+TTpZhTH4x0dH1aYtD55WJqNfeuyAOxG6WVbkX1+8svApBpIzcKElszKaol4kxdKFrbtIsH8gQ4NCITAQTJkJVHBMgizwrTQ7KYo7nVWaMJOjjW8oh7rjRGwaK9E4JocIBQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1557792580; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=4qREfMgDOvDIZnxD8mHxrlGbKtAgS56ZNj2GB4ImDXs=; b=VlQ0eUnTc0QVj+33sb5pOe4vkIDT7SWgROuG+ReeXJP6HommCvUk6HUPUS5HNuyexyn9Fw7qq+5uUu/rISSJMJu/HENmLC8Mm7mboyZ3d+J/zoiAWhlaHd21YY0F4SpFQ3ZrzN86NKT5k/JAAQcKX1k5t0cJ9z9eBevCbggJoXs= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1557792580144459.08984763191415; Mon, 13 May 2019 17:09:40 -0700 (PDT) Received: from localhost ([127.0.0.1]:36601 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hQL0g-0002pg-2V for importer@patchew.org; Mon, 13 May 2019 20:09:34 -0400 Received: from eggs.gnu.org ([209.51.188.92]:51131) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hQKy9-0001dC-2O for qemu-devel@nongnu.org; Mon, 13 May 2019 20:07:34 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hQKxJ-0003Jf-Fg for qemu-devel@nongnu.org; Mon, 13 May 2019 20:06:55 -0400 Received: from mail-pf1-x430.google.com ([2607:f8b0:4864:20::430]:42687) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hQKxJ-0003CA-0N for qemu-devel@nongnu.org; Mon, 13 May 2019 20:06:05 -0400 Received: by mail-pf1-x430.google.com with SMTP id 13so8063103pfw.9 for ; Mon, 13 May 2019 17:06:00 -0700 (PDT) Received: from localhost.localdomain (97-113-13-231.tukw.qwest.net. [97.113.13.231]) by smtp.gmail.com with ESMTPSA id u3sm238151pfn.29.2019.05.13.17.05.58 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 13 May 2019 17:05:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=4qREfMgDOvDIZnxD8mHxrlGbKtAgS56ZNj2GB4ImDXs=; b=VsbJxcyKmRyLl+PMeAvEhUPlSvDfB1Vflk6p0VJD9jxHAY+PWtzH9+/si5XvfI6vWI pwnMO2wY8weJ/Ov+lppwE2cp5PfIo1dR6IH1KImgmq6BFyzu+qN5Z7Uvgl5uWjkCtiyi 9dlJuAkrQRQwOZ9innjFLprn/XHgH0dhp3asvpaztEQXTKVNhpbItWmCc6ss9Hun6M7z pno5le59nwuDZDEmmGH45oCR0keVSza5JIi1AG/lXus48ZJgX6VsM3JOT3zaBFVX5p7M UUBYefKH47+j32PVdNEJx8JIXviD9ylMwlEYNES6y6mAwE6tpthsdVHS9hhH5d1ABNZ2 zPmw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=4qREfMgDOvDIZnxD8mHxrlGbKtAgS56ZNj2GB4ImDXs=; b=I8CQwGSwBXF0t/liE85FxzdS1kcUthe2LX4gnnzXXlPC7xwYeaKsozdcOsTzNbih2s jWriBNWCPeDf/uWmetCxehpIkJke4MgvE1kWyInp7iomhyYwG+86p2supDzNBSCkg1B1 YjPGDtIaj/zcDMLA0145V9yNGlJaTNPcycXl/PIC/CWdrajVkBgx0o7nlLeSr0vez8x6 fsbnAkgKhWDP76z5B1qN4qJhsdYdBe72Q3Ubf6o0EtqcjkPHrVY/sKxv2nMVpav4t9oR G+Jk/QOfBv7bf9aho3vyUGDVXBX0d877fD+LZfz732OF4AHzoIQHWFvGnxCMsXmDvxYl 5JzQ== X-Gm-Message-State: APjAAAUgh+HsPanW4a1B/I+3koebbmyo9VAPqp1DDgrFvI6xfO9lWfqR QV5gvU7CafGvDOLrUuSSvoTCmB0OHXE= X-Google-Smtp-Source: APXvYqyMNgvbBEYx+3uVNU7LYC4oavZefnMdaApUV+dOWDeL37xyNzuM9/Y0+lR8n70UFind+BLZkg== X-Received: by 2002:a63:1e5b:: with SMTP id p27mr33871719pgm.213.1557792359244; Mon, 13 May 2019 17:05:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 13 May 2019 17:05:21 -0700 Message-Id: <20190514000540.4313-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190514000540.4313-1-richard.henderson@linaro.org> References: <20190514000540.4313-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::430 Subject: [Qemu-devel] [PULL 12/31] tcg/i386: Implement tcg_out_dupm_vec X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linux.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" At the same time, improve tcg_out_dupi_vec wrt broadcast from the constant pool. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.inc.c | 57 +++++++++++++++++++++++++++++---------- 1 file changed, 43 insertions(+), 14 deletions(-) diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index f04933bc19..f4bd00e24f 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -358,7 +358,6 @@ static inline int tcg_target_const_match(tcg_target_lon= g val, TCGType type, #define OPC_MOVBE_MyGy (0xf1 | P_EXT38) #define OPC_MOVD_VyEy (0x6e | P_EXT | P_DATA16) #define OPC_MOVD_EyVy (0x7e | P_EXT | P_DATA16) -#define OPC_MOVDDUP (0x12 | P_EXT | P_SIMDF2) #define OPC_MOVDQA_VxWx (0x6f | P_EXT | P_DATA16) #define OPC_MOVDQA_WxVx (0x7f | P_EXT | P_DATA16) #define OPC_MOVDQU_VxWx (0x6f | P_EXT | P_SIMDF3) @@ -458,6 +457,10 @@ static inline int tcg_target_const_match(tcg_target_lo= ng val, TCGType type, #define OPC_UD2 (0x0b | P_EXT) #define OPC_VPBLENDD (0x02 | P_EXT3A | P_DATA16) #define OPC_VPBLENDVB (0x4c | P_EXT3A | P_DATA16) +#define OPC_VPINSRB (0x20 | P_EXT3A | P_DATA16) +#define OPC_VPINSRW (0xc4 | P_EXT | P_DATA16) +#define OPC_VBROADCASTSS (0x18 | P_EXT38 | P_DATA16) +#define OPC_VBROADCASTSD (0x19 | P_EXT38 | P_DATA16) #define OPC_VPBROADCASTB (0x78 | P_EXT38 | P_DATA16) #define OPC_VPBROADCASTW (0x79 | P_EXT38 | P_DATA16) #define OPC_VPBROADCASTD (0x58 | P_EXT38 | P_DATA16) @@ -855,16 +858,17 @@ static bool tcg_out_mov(TCGContext *s, TCGType type, = TCGReg ret, TCGReg arg) return true; } =20 +static const int avx2_dup_insn[4] =3D { + OPC_VPBROADCASTB, OPC_VPBROADCASTW, + OPC_VPBROADCASTD, OPC_VPBROADCASTQ, +}; + static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, TCGReg r, TCGReg a) { if (have_avx2) { - static const int dup_insn[4] =3D { - OPC_VPBROADCASTB, OPC_VPBROADCASTW, - OPC_VPBROADCASTD, OPC_VPBROADCASTQ, - }; int vex_l =3D (type =3D=3D TCG_TYPE_V256 ? P_VEXL : 0); - tcg_out_vex_modrm(s, dup_insn[vece] + vex_l, r, 0, a); + tcg_out_vex_modrm(s, avx2_dup_insn[vece] + vex_l, r, 0, a); } else { switch (vece) { case MO_8: @@ -894,10 +898,35 @@ static bool tcg_out_dup_vec(TCGContext *s, TCGType ty= pe, unsigned vece, static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, TCGReg r, TCGReg base, intptr_t offset) { - return false; + if (have_avx2) { + int vex_l =3D (type =3D=3D TCG_TYPE_V256 ? P_VEXL : 0); + tcg_out_vex_modrm_offset(s, avx2_dup_insn[vece] + vex_l, + r, 0, base, offset); + } else { + switch (vece) { + case MO_64: + tcg_out_vex_modrm_offset(s, OPC_VBROADCASTSD, r, 0, base, offs= et); + break; + case MO_32: + tcg_out_vex_modrm_offset(s, OPC_VBROADCASTSS, r, 0, base, offs= et); + break; + case MO_16: + tcg_out_vex_modrm_offset(s, OPC_VPINSRW, r, r, base, offset); + tcg_out8(s, 0); /* imm8 */ + tcg_out_dup_vec(s, type, vece, r, r); + break; + case MO_8: + tcg_out_vex_modrm_offset(s, OPC_VPINSRB, r, r, base, offset); + tcg_out8(s, 0); /* imm8 */ + tcg_out_dup_vec(s, type, vece, r, r); + break; + default: + g_assert_not_reached(); + } + } + return true; } =20 - static void tcg_out_dupi_vec(TCGContext *s, TCGType type, TCGReg ret, tcg_target_long arg) { @@ -918,16 +947,16 @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType t= ype, } else if (have_avx2) { tcg_out_vex_modrm_pool(s, OPC_VPBROADCASTQ + vex_l, ret); } else { - tcg_out_vex_modrm_pool(s, OPC_MOVDDUP, ret); + tcg_out_vex_modrm_pool(s, OPC_VBROADCASTSD, ret); } new_pool_label(s, arg, R_386_PC32, s->code_ptr - 4, -4); - } else if (have_avx2) { - tcg_out_vex_modrm_pool(s, OPC_VPBROADCASTD + vex_l, ret); - new_pool_label(s, arg, R_386_32, s->code_ptr - 4, 0); } else { - tcg_out_vex_modrm_pool(s, OPC_MOVD_VyEy, ret); + if (have_avx2) { + tcg_out_vex_modrm_pool(s, OPC_VBROADCASTSD + vex_l, ret); + } else { + tcg_out_vex_modrm_pool(s, OPC_VBROADCASTSS, ret); + } new_pool_label(s, arg, R_386_32, s->code_ptr - 4, 0); - tcg_out_dup_vec(s, type, MO_32, ret, ret); } } =20 --=20 2.17.1 From nobody Fri Apr 19 16:27:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1557792569; cv=none; d=zoho.com; s=zohoarc; b=joXK0y9MMBwaKZ8gzCC3OxAt13cOwCYG1hZPvJZU73znugbuNrb4v7b6qJLdxQG48zQLZW7EUXtCjM7rm5pmUMKoa9SRYSUJ0GO65CVMGVuZL8E7aAS28Hz2MKcUFZ2gdfexeGuIzjveEaRMGzyu/pBWil3JOIchRAen7zadK28= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1557792569; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=NDeQiI120O8qPLtGObyt0DUpB7btZP10JZcwXpqFkfc=; b=i/6wSCt6yGpKRrnye4YQsTV3TBqUZK0bCZmr38K5JbTy6d4BS9+xOuKQvdms/hVGylPN9wJTdvRnqkiXBQn/KEb8zh0z0xx3qyaNGhR83CEqGeDxGFeCqjpSrRk/8+Wf5BDRI2GeHLvGUAsf3MvPyyuWr0ud+RuitSYQgDuJwsA= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1557792569647281.73704704967065; Mon, 13 May 2019 17:09:29 -0700 (PDT) Received: from localhost ([127.0.0.1]:36599 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hQL0V-0002fr-Jk for importer@patchew.org; Mon, 13 May 2019 20:09:23 -0400 Received: from eggs.gnu.org ([209.51.188.92]:51033) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hQKy5-0001d8-L5 for qemu-devel@nongnu.org; Mon, 13 May 2019 20:07:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hQKxJ-0003JU-F3 for qemu-devel@nongnu.org; Mon, 13 May 2019 20:06:52 -0400 Received: from mail-pf1-x441.google.com ([2607:f8b0:4864:20::441]:33958) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hQKxH-0003Cy-4K for qemu-devel@nongnu.org; Mon, 13 May 2019 20:06:05 -0400 Received: by mail-pf1-x441.google.com with SMTP id n19so8073427pfa.1 for ; Mon, 13 May 2019 17:06:01 -0700 (PDT) Received: from localhost.localdomain (97-113-13-231.tukw.qwest.net. [97.113.13.231]) by smtp.gmail.com with ESMTPSA id u3sm238151pfn.29.2019.05.13.17.05.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 13 May 2019 17:05:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=NDeQiI120O8qPLtGObyt0DUpB7btZP10JZcwXpqFkfc=; b=uGgMSdBuP7yJnGqjk468tLkGVcdYB2nHjveFzgw1rNh0ivSnoV5R4lD23s9sfWva82 kea6pKiDOO0WB6K3hUIpVWip/OBkWel1jept3Iup0P/UPbnQcYaDx8b39CbI7BYBoNFu RR9cOuaqsNqJ4DcwRidvEo89xNchDVdRq9MO/BE1X32jDJlcRJ/fF9BqX1bxkjX9kBb9 gKVv0jH7FoUQUV7HhHV/XXpEojl20AqZ0yjE+V5Vwa2zYzb230l1kxc+pY2ePemnrU8C 546cMuIZum0ei3jjyCYorIzIJIPKW0GAvzwSkVt0yUawJ6r+3mNzHJirOh4KuTH1KWs1 ncRQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=NDeQiI120O8qPLtGObyt0DUpB7btZP10JZcwXpqFkfc=; b=niceH6m2TE9xkvjU3NLxWM6CgulOfLS3P5PNbVuzUSwQ8T7mfTLo8okdIhxQjZ6A8W 9qRQ5Uoo6DA+7ot914G++uh8gUyLwbhnWQxCU4lOCvfwOFhnV3SOT1ZzRmPx2nvPr+O9 IO0JNPPUkLmoJkjKgA0UozAs9lQJtz9fLKSXDuLrjXIuTPB2bLWh2WJi9R38QmfNJVN2 c77YEPmmMpUR8u4Ngnd370YJMxBeOQPmChKObV24Doc6nfolmMnVBeFxxtiUFRuJ+/gb LsucBQEGxWC/hvm6hzVddHiaWTapqTWcgvpGticHRFcbzLDRRekrliTyMj3X8yBlr2Md cX+w== X-Gm-Message-State: APjAAAXjezj83vrGBIhKED2GZo1LDCy3NHzfA50r0RicdtZmJxMmhsFZ 33C2nKJb4vtIJArfCS3t2IFeBYxKcaM= X-Google-Smtp-Source: APXvYqxI36PtdpwnOn5hl4hNmV1nlT91riTpfyV2zLayFoiEuXpYKVovxJbcp3KOgxwzwHvnNec7qg== X-Received: by 2002:a63:4a66:: with SMTP id j38mr15912424pgl.199.1557792360613; Mon, 13 May 2019 17:06:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 13 May 2019 17:05:22 -0700 Message-Id: <20190514000540.4313-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190514000540.4313-1-richard.henderson@linaro.org> References: <20190514000540.4313-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::441 Subject: [Qemu-devel] [PULL 13/31] tcg/aarch64: Implement tcg_out_dupm_vec X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linux.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The LD1R instruction does all the work. Note that the only useful addressing mode is a base register with no offset. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.inc.c | 37 ++++++++++++++++++++++++++++++++++-- 1 file changed, 35 insertions(+), 2 deletions(-) diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c index 4a3cfa778a..b4585724d3 100644 --- a/tcg/aarch64/tcg-target.inc.c +++ b/tcg/aarch64/tcg-target.inc.c @@ -381,6 +381,9 @@ typedef enum { I3207_BLR =3D 0xd63f0000, I3207_RET =3D 0xd65f0000, =20 + /* AdvSIMD load/store single structure. */ + I3303_LD1R =3D 0x0d40c000, + /* Load literal for loading the address at pc-relative offset */ I3305_LDR =3D 0x58000000, I3305_LDR_v64 =3D 0x5c000000, @@ -566,7 +569,14 @@ static inline uint32_t tcg_in32(TCGContext *s) #define tcg_out_insn(S, FMT, OP, ...) \ glue(tcg_out_insn_,FMT)(S, glue(glue(glue(I,FMT),_),OP), ## __VA_ARGS_= _) =20 -static void tcg_out_insn_3305(TCGContext *s, AArch64Insn insn, int imm19, = TCGReg rt) +static void tcg_out_insn_3303(TCGContext *s, AArch64Insn insn, bool q, + TCGReg rt, TCGReg rn, unsigned size) +{ + tcg_out32(s, insn | (rt & 0x1f) | (rn << 5) | (size << 10) | (q << 30)= ); +} + +static void tcg_out_insn_3305(TCGContext *s, AArch64Insn insn, + int imm19, TCGReg rt) { tcg_out32(s, insn | (imm19 & 0x7ffff) << 5 | rt); } @@ -825,7 +835,30 @@ static bool tcg_out_dup_vec(TCGContext *s, TCGType typ= e, unsigned vece, static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, TCGReg r, TCGReg base, intptr_t offset) { - return false; + TCGReg temp =3D TCG_REG_TMP; + + if (offset < -0xffffff || offset > 0xffffff) { + tcg_out_movi(s, TCG_TYPE_PTR, temp, offset); + tcg_out_insn(s, 3502, ADD, 1, temp, temp, base); + base =3D temp; + } else { + AArch64Insn add_insn =3D I3401_ADDI; + + if (offset < 0) { + add_insn =3D I3401_SUBI; + offset =3D -offset; + } + if (offset & 0xfff000) { + tcg_out_insn_3401(s, add_insn, 1, temp, base, offset & 0xfff00= 0); + base =3D temp; + } + if (offset & 0xfff) { + tcg_out_insn_3401(s, add_insn, 1, temp, base, offset & 0xfff); + base =3D temp; + } + } + tcg_out_insn(s, 3303, LD1R, type =3D=3D TCG_TYPE_V128, r, base, vece); + return true; } =20 static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd, --=20 2.17.1 From nobody Fri Apr 19 16:27:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1557793469; cv=none; d=zoho.com; s=zohoarc; b=B45Pqg2Fu1SInsZz0Py8vWgiWKrFyjCfGUNurF5Lg24y7kX9xR/g4zoKSkts98SreTDi8069t+0SYFk+PimUitvsStXASeT+WqLJne3wPCiyjwox6mocK2SqkhJLFfyC5O9SDcmz9fU6FB+jfVjBiiGCn89H1b6gM0ITawhaE9g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1557793469; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=iVwQGD3UgxRPzfaFzYVSbyOORaGGDvYg0K6GhJOxPgY=; b=T6U20aLUJ0Venkq0wIc2AvTBpg8Gy/DY7QqCVzWIf4e7ePN+OOTHNV6lMcOtpK4uY8nRx0uHHG7huTpXmt9y8FkFUBh7E6hG0GDUeW+sTidzKwNroP22wbP3OShcWkES+PyF6YP7zhKS/IM6idHx8EqH4Vwa4oygvjCcvh+wUGM= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1557793469211591.4087961376382; Mon, 13 May 2019 17:24:29 -0700 (PDT) Received: from localhost ([127.0.0.1]:36833 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hQLEx-0008RB-ET for importer@patchew.org; Mon, 13 May 2019 20:24:19 -0400 Received: from eggs.gnu.org ([209.51.188.92]:55553) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hQL0C-0002wt-NO for qemu-devel@nongnu.org; Mon, 13 May 2019 20:12:55 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hQKxL-0003M2-KC for qemu-devel@nongnu.org; Mon, 13 May 2019 20:08:59 -0400 Received: from mail-pg1-x534.google.com ([2607:f8b0:4864:20::534]:38014) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hQKxJ-0003EL-4t for qemu-devel@nongnu.org; Mon, 13 May 2019 20:06:05 -0400 Received: by mail-pg1-x534.google.com with SMTP id j26so7597971pgl.5 for ; Mon, 13 May 2019 17:06:03 -0700 (PDT) Received: from localhost.localdomain (97-113-13-231.tukw.qwest.net. [97.113.13.231]) by smtp.gmail.com with ESMTPSA id u3sm238151pfn.29.2019.05.13.17.06.00 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 13 May 2019 17:06:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=iVwQGD3UgxRPzfaFzYVSbyOORaGGDvYg0K6GhJOxPgY=; b=sG/WC0+r23m003fg0M4zp08hQy523okm2kmy+SrKoagnxuY/RDRlvzMrT7NvIbDCGn imEYoFNyApi40b5V60fOfN+jWhPi+U+cKy7SX+F8SqWl+1UOOJRV6H17JmPyuSkXGCcj inoDx75+j8Bj3KQIcCrrWzASUkd1BKyXxSYpzFdRx+/eYKTmda5nQnqvAunuVpHLLFY6 79re9c+fRxDOBw0uvOLRfeS6dzrKXmYWoDyRA5vKUItjprk0t6IuTZ01jVt5LeaQvo08 QGiv06oenRkfqLg+AkM5Drju+y+khnAbSkKikSErap4Un+XGVKjbufj62KQRoIr0J4/L ikeg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=iVwQGD3UgxRPzfaFzYVSbyOORaGGDvYg0K6GhJOxPgY=; b=WxFecX7aFA9iLlS7JlpMs2i/StwfdwRQPGfATKO4EaeTQqlQpD+qmAsKzxbigkf0Z5 Fm/kvRHfXCxJZ4ktTZTRmAYMnqqyjjg4/HtKqi1L3TqHRGY29vaqWmksyMD/aIMamI1K nCoQXPx2jalahwjfmL0vSXMGFdAsHDtgGtQJbyY6gCJzckpbrAyr3TKnRRJWMs8XvWz9 W/0xh8RntoQ6DN9DrwqmzjSGdHBbGcz2RbvZEUqaFfDoDfRIMT2fn+3FOVJvnfigSq+j IlHvP7BujGnceQA/V5VcRVhsRqtgIz7IRN4540XMO0gF4Eg053fgIu1lDT7aniS91oyq RCIA== X-Gm-Message-State: APjAAAWkAhKrS3bzbn3ukIzqXZOUfGitfaadjMdRPKDcGxISPNndgwlX 9YhoZaTRiEtsPoKLhcQ1JpPFy+eXGgs= X-Google-Smtp-Source: APXvYqxe2zVBDKdGoFQ7wfJLlPbwz0NbylidcxA6NobqEryPq9XjSo/wonKEbpHKybO64JnTOHTVyw== X-Received: by 2002:a65:42c3:: with SMTP id l3mr10681039pgp.372.1557792362192; Mon, 13 May 2019 17:06:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 13 May 2019 17:05:23 -0700 Message-Id: <20190514000540.4313-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190514000540.4313-1-richard.henderson@linaro.org> References: <20190514000540.4313-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::534 Subject: [Qemu-devel] [PULL 14/31] tcg: Add INDEX_op_dupm_vec X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linux.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Allow the backend to expand dup from memory directly, instead of forcing the value into a temp first. This is especially important if integer/vector register moves do not exist. Note that officially tcg_out_dupm_vec is allowed to fail. If it did, we could fix this up relatively easily: VECE =3D=3D 32/64: Load the value into a vector register, then dup. Both of these must work. VECE =3D=3D 8/16: If the value happens to be at an offset such that an aligned load would place the desired value in the least significant end of the register, go ahead and load w/garbage in high bits. Load the value w/INDEX_op_ld{8,16}_i32. Attempt a move directly to vector reg, which may fail. Store the value into the backing store for OTS. Load the value into the vector reg w/TCG_TYPE_I32, which must work. Duplicate from the vector reg into itself, which must work. All of which is well and good, except that all supported hosts can support dupm for all vece, so all of the failure paths would be dead code and untestable. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- tcg/tcg-op.h | 1 + tcg/tcg-opc.h | 1 + tcg/aarch64/tcg-target.inc.c | 4 ++ tcg/i386/tcg-target.inc.c | 4 ++ tcg/tcg-op-gvec.c | 89 +++++++++++++++++++----------------- tcg/tcg-op-vec.c | 11 +++++ tcg/tcg.c | 1 + 7 files changed, 70 insertions(+), 41 deletions(-) diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h index 1f1824c30a..9fff9864f6 100644 --- a/tcg/tcg-op.h +++ b/tcg/tcg-op.h @@ -954,6 +954,7 @@ void tcg_gen_atomic_umax_fetch_i64(TCGv_i64, TCGv, TCGv= _i64, TCGArg, TCGMemOp); void tcg_gen_mov_vec(TCGv_vec, TCGv_vec); void tcg_gen_dup_i32_vec(unsigned vece, TCGv_vec, TCGv_i32); void tcg_gen_dup_i64_vec(unsigned vece, TCGv_vec, TCGv_i64); +void tcg_gen_dup_mem_vec(unsigned vece, TCGv_vec, TCGv_ptr, tcg_target_lon= g); void tcg_gen_dup8i_vec(TCGv_vec, uint32_t); void tcg_gen_dup16i_vec(TCGv_vec, uint32_t); void tcg_gen_dup32i_vec(TCGv_vec, uint32_t); diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h index 1bad6e4208..4bf71f261f 100644 --- a/tcg/tcg-opc.h +++ b/tcg/tcg-opc.h @@ -219,6 +219,7 @@ DEF(dup2_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_REG_BI= TS =3D=3D 32)) =20 DEF(ld_vec, 1, 1, 1, IMPLVEC) DEF(st_vec, 0, 2, 1, IMPLVEC) +DEF(dupm_vec, 1, 1, 1, IMPLVEC) =20 DEF(add_vec, 1, 2, 0, IMPLVEC) DEF(sub_vec, 1, 2, 0, IMPLVEC) diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c index b4585724d3..3dda66e777 100644 --- a/tcg/aarch64/tcg-target.inc.c +++ b/tcg/aarch64/tcg-target.inc.c @@ -2191,6 +2191,9 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode o= pc, case INDEX_op_st_vec: tcg_out_st(s, type, a0, a1, a2); break; + case INDEX_op_dupm_vec: + tcg_out_dupm_vec(s, type, vece, a0, a1, a2); + break; case INDEX_op_add_vec: tcg_out_insn(s, 3616, ADD, is_q, vece, a0, a1, a2); break; @@ -2523,6 +2526,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) return &w_w; case INDEX_op_ld_vec: case INDEX_op_st_vec: + case INDEX_op_dupm_vec: return &w_r; case INDEX_op_dup_vec: return &w_wr; diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index f4bd00e24f..5b33bbd99b 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -2829,6 +2829,9 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode o= pc, case INDEX_op_st_vec: tcg_out_st(s, type, a0, a1, a2); break; + case INDEX_op_dupm_vec: + tcg_out_dupm_vec(s, type, vece, a0, a1, a2); + break; =20 case INDEX_op_x86_shufps_vec: insn =3D OPC_SHUFPS; @@ -3115,6 +3118,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) =20 case INDEX_op_ld_vec: case INDEX_op_st_vec: + case INDEX_op_dupm_vec: return &x_r; =20 case INDEX_op_add_vec: diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c index 3fcb2352d9..35ebc5a201 100644 --- a/tcg/tcg-op-gvec.c +++ b/tcg/tcg-op-gvec.c @@ -395,6 +395,41 @@ static TCGType choose_vector_type(const TCGOpcode *lis= t, unsigned vece, return 0; } =20 +static void do_dup_store(TCGType type, uint32_t dofs, uint32_t oprsz, + uint32_t maxsz, TCGv_vec t_vec) +{ + uint32_t i =3D 0; + + switch (type) { + case TCG_TYPE_V256: + /* + * Recall that ARM SVE allows vector sizes that are not a + * power of 2, but always a multiple of 16. The intent is + * that e.g. size =3D=3D 80 would be expanded with 2x32 + 1x16. + */ + for (; i + 32 <=3D oprsz; i +=3D 32) { + tcg_gen_stl_vec(t_vec, cpu_env, dofs + i, TCG_TYPE_V256); + } + /* fallthru */ + case TCG_TYPE_V128: + for (; i + 16 <=3D oprsz; i +=3D 16) { + tcg_gen_stl_vec(t_vec, cpu_env, dofs + i, TCG_TYPE_V128); + } + break; + case TCG_TYPE_V64: + for (; i < oprsz; i +=3D 8) { + tcg_gen_stl_vec(t_vec, cpu_env, dofs + i, TCG_TYPE_V64); + } + break; + default: + g_assert_not_reached(); + } + + if (oprsz < maxsz) { + expand_clr(dofs + oprsz, maxsz - oprsz); + } +} + /* Set OPRSZ bytes at DOFS to replications of IN_32, IN_64 or IN_C. * Only one of IN_32 or IN_64 may be set; * IN_C is used if IN_32 and IN_64 are unset. @@ -434,49 +469,11 @@ static void do_dup(unsigned vece, uint32_t dofs, uint= 32_t oprsz, } else if (in_64) { tcg_gen_dup_i64_vec(vece, t_vec, in_64); } else { - switch (vece) { - case MO_8: - tcg_gen_dup8i_vec(t_vec, in_c); - break; - case MO_16: - tcg_gen_dup16i_vec(t_vec, in_c); - break; - case MO_32: - tcg_gen_dup32i_vec(t_vec, in_c); - break; - default: - tcg_gen_dup64i_vec(t_vec, in_c); - break; - } + tcg_gen_dupi_vec(vece, t_vec, in_c); } - - i =3D 0; - switch (type) { - case TCG_TYPE_V256: - /* Recall that ARM SVE allows vector sizes that are not a - * power of 2, but always a multiple of 16. The intent is - * that e.g. size =3D=3D 80 would be expanded with 2x32 + 1x16. - */ - for (; i + 32 <=3D oprsz; i +=3D 32) { - tcg_gen_stl_vec(t_vec, cpu_env, dofs + i, TCG_TYPE_V256); - } - /* fallthru */ - case TCG_TYPE_V128: - for (; i + 16 <=3D oprsz; i +=3D 16) { - tcg_gen_stl_vec(t_vec, cpu_env, dofs + i, TCG_TYPE_V128); - } - break; - case TCG_TYPE_V64: - for (; i < oprsz; i +=3D 8) { - tcg_gen_stl_vec(t_vec, cpu_env, dofs + i, TCG_TYPE_V64); - } - break; - default: - g_assert_not_reached(); - } - + do_dup_store(type, dofs, oprsz, maxsz, t_vec); tcg_temp_free_vec(t_vec); - goto done; + return; } =20 /* Otherwise, inline with an integer type, unless "large". */ @@ -1449,6 +1446,16 @@ void tcg_gen_gvec_dup_i64(unsigned vece, uint32_t do= fs, uint32_t oprsz, void tcg_gen_gvec_dup_mem(unsigned vece, uint32_t dofs, uint32_t aofs, uint32_t oprsz, uint32_t maxsz) { + if (vece <=3D MO_64) { + TCGType type =3D choose_vector_type(0, vece, oprsz, 0); + if (type !=3D 0) { + TCGv_vec t_vec =3D tcg_temp_new_vec(type); + tcg_gen_dup_mem_vec(vece, t_vec, cpu_env, aofs); + do_dup_store(type, dofs, oprsz, maxsz, t_vec); + tcg_temp_free_vec(t_vec); + return; + } + } if (vece <=3D MO_32) { TCGv_i32 in =3D tcg_temp_new_i32(); switch (vece) { diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c index 914fe42b1e..213d2e22aa 100644 --- a/tcg/tcg-op-vec.c +++ b/tcg/tcg-op-vec.c @@ -278,6 +278,17 @@ void tcg_gen_dup_i32_vec(unsigned vece, TCGv_vec r, TC= Gv_i32 a) vec_gen_2(INDEX_op_dup_vec, type, vece, ri, ai); } =20 +void tcg_gen_dup_mem_vec(unsigned vece, TCGv_vec r, TCGv_ptr b, + tcg_target_long ofs) +{ + TCGArg ri =3D tcgv_vec_arg(r); + TCGArg bi =3D tcgv_ptr_arg(b); + TCGTemp *rt =3D arg_temp(ri); + TCGType type =3D rt->base_type; + + vec_gen_3(INDEX_op_dupm_vec, type, vece, ri, bi, ofs); +} + static void vec_gen_ldst(TCGOpcode opc, TCGv_vec r, TCGv_ptr b, TCGArg o) { TCGArg ri =3D tcgv_vec_arg(r); diff --git a/tcg/tcg.c b/tcg/tcg.c index b9945794c4..3b80feb344 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1600,6 +1600,7 @@ bool tcg_op_supported(TCGOpcode op) case INDEX_op_mov_vec: case INDEX_op_dup_vec: case INDEX_op_dupi_vec: + case INDEX_op_dupm_vec: case INDEX_op_ld_vec: case INDEX_op_st_vec: case INDEX_op_add_vec: --=20 2.17.1 From nobody Fri Apr 19 16:27:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1557793220; cv=none; d=zoho.com; s=zohoarc; b=b/IgsJ0U1DfDDA7E1RK87b7jRO6ncX4puoLPvPdS2csaa6pmxE0O8ID6rMNJBlEvM13KBkxknL0HtDARWc9xDYUlw0pFsayyTPhgImuqVvlSuhXazu2NbxvJC4oXGn+s9TU3/0+d54sSbti/HpYsvnxzpO5ROXamlOtdnXJX9mE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1557793220; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=a9OtYY/L3tjcYNcnftsoHy1MvDzVKoGmvUT84hy5Bno=; b=LzHXVOfoYDfyWECuVGBr/ZwoEPsmtsavRoSADVmld/l1f/7u69V5jzRohbR7rxhtgnAJigQKXQsOfQH8M+VZ3oKhIBEFAXhPcJzDPN041hn0R9nJnZwlWLRc5hrystikar47sZ8wu/g019GTUq4DQKB2s3FcfyU5gKjh78qQoZc= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1557793220848897.7589258458994; Mon, 13 May 2019 17:20:20 -0700 (PDT) Received: from localhost ([127.0.0.1]:36759 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hQLB1-0004kz-Eg for importer@patchew.org; Mon, 13 May 2019 20:20:15 -0400 Received: from eggs.gnu.org ([209.51.188.92]:56181) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hQL16-0003A9-7Z for qemu-devel@nongnu.org; Mon, 13 May 2019 20:10:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hQKxM-0003Nx-02 for qemu-devel@nongnu.org; Mon, 13 May 2019 20:09:55 -0400 Received: from mail-pg1-x529.google.com ([2607:f8b0:4864:20::529]:37153) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hQKxJ-0003I3-AT for qemu-devel@nongnu.org; Mon, 13 May 2019 20:06:07 -0400 Received: by mail-pg1-x529.google.com with SMTP id e6so7601068pgc.4 for ; Mon, 13 May 2019 17:06:05 -0700 (PDT) Received: from localhost.localdomain (97-113-13-231.tukw.qwest.net. [97.113.13.231]) by smtp.gmail.com with ESMTPSA id u3sm238151pfn.29.2019.05.13.17.06.02 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 13 May 2019 17:06:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=a9OtYY/L3tjcYNcnftsoHy1MvDzVKoGmvUT84hy5Bno=; b=bLQrywABJHDmt7ldD4Djzj51PiVrCHIxMTDaYKUa14FQHUbM5CIOGx2b1yJLOa7P/C GyscKxIFq6zn0C2fMkmdH1ofxAdYq7xBVsTQM/7i6E4gQVqIiaw4lbk6fGP0wfGS0DF0 pVMmmJxEUQDccLyn01vkxeIAhakmlAIilP5X9kj8N93Svey8ecNiPnyD6UzYlzgqy1vM 981sfqPV9lq6/X0UQQm76XpUsgabGflP9U474/rbYZnh2zvcX4FyPDVndsMItwoYsEKE ZNpZr/nq/OJOgshl1j6YFwldN2+R8R+8/v9oZSm5AOV65pcKmZKNC0qURHLXvLyaHwHv votA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=a9OtYY/L3tjcYNcnftsoHy1MvDzVKoGmvUT84hy5Bno=; b=Ud0SxlsUBwXWkRQA6NlyLmbbDRqOqSN+aHk6EnAjYu/Jx+3fLVICE9yRWo391tjd8R vBUBRyeJCqno4DxsNhGx4Y32Nvnypdpj4ZlLPSQ/vj76kLvUypEXhG479xzYOwZgLCxM LQyzpGm7glj+2aw+FMNYkfIay6WBTDCIGL6k5hWKTlt5niFUJl5Seu78XHn3nYA1dpGy F+TcOnDbndrw7YdsPh2q8dj11DQIBHBO5XR4837yAOPb5JzMuown4L2Ez1xSMNultPpo FhhlmamiD7aZAUiDXeDz6MxqegG0uck83YA4TuClsZA0XNFOfOUL8j6XfbIPKmdfF56j RmAA== X-Gm-Message-State: APjAAAVjNswjg5VHPuFMbjDPiuf/jGCgQ/WFU1SdVUAUujmESZD1xqyg r9RO6JXRyWYIAhFcW02PZvnDd4hZsaA= X-Google-Smtp-Source: APXvYqyDq5zd+bS5G83d5Q6VanoUi6A4q1Yb0TcB44W77Y1Hll3QQa9KDmiI5xwIycUBe3/bGstrjQ== X-Received: by 2002:a65:528b:: with SMTP id y11mr34672130pgp.341.1557792363444; Mon, 13 May 2019 17:06:03 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 13 May 2019 17:05:24 -0700 Message-Id: <20190514000540.4313-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190514000540.4313-1-richard.henderson@linaro.org> References: <20190514000540.4313-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::529 Subject: [Qemu-devel] [PULL 15/31] tcg: Add gvec expanders for variable shift X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linux.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) The gvec expanders perform a modulo on the shift count. If the target requires alternate behaviour, then it cannot use the generic gvec expanders anyway, and will have to have its own custom code. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- accel/tcg/tcg-runtime.h | 15 +++ tcg/tcg-op-gvec.h | 11 ++ tcg/tcg-op.h | 4 + accel/tcg/tcg-runtime-gvec.c | 144 ++++++++++++++++++++++++++ tcg/tcg-op-gvec.c | 195 +++++++++++++++++++++++++++++++++++ tcg/tcg-op-vec.c | 15 +++ 6 files changed, 384 insertions(+) diff --git a/accel/tcg/tcg-runtime.h b/accel/tcg/tcg-runtime.h index dfe325625c..ed3ce5fd91 100644 --- a/accel/tcg/tcg-runtime.h +++ b/accel/tcg/tcg-runtime.h @@ -254,6 +254,21 @@ DEF_HELPER_FLAGS_3(gvec_sar16i, TCG_CALL_NO_RWG, void,= ptr, ptr, i32) DEF_HELPER_FLAGS_3(gvec_sar32i, TCG_CALL_NO_RWG, void, ptr, ptr, i32) DEF_HELPER_FLAGS_3(gvec_sar64i, TCG_CALL_NO_RWG, void, ptr, ptr, i32) =20 +DEF_HELPER_FLAGS_4(gvec_shl8v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_shl16v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_shl32v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_shl64v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(gvec_shr8v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_shr16v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_shr32v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_shr64v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(gvec_sar8v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_sar16v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_sar32v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_sar64v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + DEF_HELPER_FLAGS_4(gvec_eq8, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_eq16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_eq32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) diff --git a/tcg/tcg-op-gvec.h b/tcg/tcg-op-gvec.h index ac744ff7c9..84a6247b16 100644 --- a/tcg/tcg-op-gvec.h +++ b/tcg/tcg-op-gvec.h @@ -318,6 +318,17 @@ void tcg_gen_gvec_shri(unsigned vece, uint32_t dofs, u= int32_t aofs, void tcg_gen_gvec_sari(unsigned vece, uint32_t dofs, uint32_t aofs, int64_t shift, uint32_t oprsz, uint32_t maxsz); =20 +/* + * Perform vector shift by vector element, modulo the element size. + * E.g. D[i] =3D A[i] << (B[i] % (8 << vece)). + */ +void tcg_gen_gvec_shlv(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_shrv(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_sarv(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz); + void tcg_gen_gvec_cmp(TCGCond cond, unsigned vece, uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t oprsz, uint32_t maxsz); diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h index 9fff9864f6..833c6330b5 100644 --- a/tcg/tcg-op.h +++ b/tcg/tcg-op.h @@ -986,6 +986,10 @@ void tcg_gen_shli_vec(unsigned vece, TCGv_vec r, TCGv_= vec a, int64_t i); void tcg_gen_shri_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i); void tcg_gen_sari_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i); =20 +void tcg_gen_shlv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s); +void tcg_gen_shrv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s); +void tcg_gen_sarv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s); + void tcg_gen_cmp_vec(TCGCond cond, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); =20 diff --git a/accel/tcg/tcg-runtime-gvec.c b/accel/tcg/tcg-runtime-gvec.c index e2c6f24262..2152fb6903 100644 --- a/accel/tcg/tcg-runtime-gvec.c +++ b/accel/tcg/tcg-runtime-gvec.c @@ -725,6 +725,150 @@ void HELPER(gvec_sar64i)(void *d, void *a, uint32_t d= esc) clear_high(d, oprsz, desc); } =20 +void HELPER(gvec_shl8v)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz =3D simd_oprsz(desc); + intptr_t i; + + for (i =3D 0; i < oprsz; i +=3D sizeof(uint8_t)) { + uint8_t sh =3D *(uint8_t *)(b + i) & 7; + *(uint8_t *)(d + i) =3D *(uint8_t *)(a + i) << sh; + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_shl16v)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz =3D simd_oprsz(desc); + intptr_t i; + + for (i =3D 0; i < oprsz; i +=3D sizeof(uint16_t)) { + uint8_t sh =3D *(uint16_t *)(b + i) & 15; + *(uint16_t *)(d + i) =3D *(uint16_t *)(a + i) << sh; + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_shl32v)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz =3D simd_oprsz(desc); + intptr_t i; + + for (i =3D 0; i < oprsz; i +=3D sizeof(uint32_t)) { + uint8_t sh =3D *(uint32_t *)(b + i) & 31; + *(uint32_t *)(d + i) =3D *(uint32_t *)(a + i) << sh; + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_shl64v)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz =3D simd_oprsz(desc); + intptr_t i; + + for (i =3D 0; i < oprsz; i +=3D sizeof(uint64_t)) { + uint8_t sh =3D *(uint64_t *)(b + i) & 63; + *(uint64_t *)(d + i) =3D *(uint64_t *)(a + i) << sh; + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_shr8v)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz =3D simd_oprsz(desc); + intptr_t i; + + for (i =3D 0; i < oprsz; i +=3D sizeof(uint8_t)) { + uint8_t sh =3D *(uint8_t *)(b + i) & 7; + *(uint8_t *)(d + i) =3D *(uint8_t *)(a + i) >> sh; + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_shr16v)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz =3D simd_oprsz(desc); + intptr_t i; + + for (i =3D 0; i < oprsz; i +=3D sizeof(uint16_t)) { + uint8_t sh =3D *(uint16_t *)(b + i) & 15; + *(uint16_t *)(d + i) =3D *(uint16_t *)(a + i) >> sh; + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_shr32v)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz =3D simd_oprsz(desc); + intptr_t i; + + for (i =3D 0; i < oprsz; i +=3D sizeof(uint32_t)) { + uint8_t sh =3D *(uint32_t *)(b + i) & 31; + *(uint32_t *)(d + i) =3D *(uint32_t *)(a + i) >> sh; + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_shr64v)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz =3D simd_oprsz(desc); + intptr_t i; + + for (i =3D 0; i < oprsz; i +=3D sizeof(uint64_t)) { + uint8_t sh =3D *(uint64_t *)(b + i) & 63; + *(uint64_t *)(d + i) =3D *(uint64_t *)(a + i) >> sh; + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_sar8v)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz =3D simd_oprsz(desc); + intptr_t i; + + for (i =3D 0; i < oprsz; i +=3D sizeof(vec8)) { + uint8_t sh =3D *(uint8_t *)(b + i) & 7; + *(int8_t *)(d + i) =3D *(int8_t *)(a + i) >> sh; + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_sar16v)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz =3D simd_oprsz(desc); + intptr_t i; + + for (i =3D 0; i < oprsz; i +=3D sizeof(int16_t)) { + uint8_t sh =3D *(uint16_t *)(b + i) & 15; + *(int16_t *)(d + i) =3D *(int16_t *)(a + i) >> sh; + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_sar32v)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz =3D simd_oprsz(desc); + intptr_t i; + + for (i =3D 0; i < oprsz; i +=3D sizeof(vec32)) { + uint8_t sh =3D *(uint32_t *)(b + i) & 31; + *(int32_t *)(d + i) =3D *(int32_t *)(a + i) >> sh; + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_sar64v)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz =3D simd_oprsz(desc); + intptr_t i; + + for (i =3D 0; i < oprsz; i +=3D sizeof(vec64)) { + uint8_t sh =3D *(uint64_t *)(b + i) & 63; + *(int64_t *)(d + i) =3D *(int64_t *)(a + i) >> sh; + } + clear_high(d, oprsz, desc); +} + /* If vectors are enabled, the compiler fills in -1 for true. Otherwise, we must take care of this by hand. */ #ifdef CONFIG_VECTOR16 diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c index 35ebc5a201..061ef329f1 100644 --- a/tcg/tcg-op-gvec.c +++ b/tcg/tcg-op-gvec.c @@ -2555,6 +2555,201 @@ void tcg_gen_gvec_sari(unsigned vece, uint32_t dofs= , uint32_t aofs, } } =20 +/* + * Expand D =3D A << (B % element bits) + * + * Unlike scalar shifts, where it is easy for the target front end + * to include the modulo as part of the expansion. If the target + * naturally includes the modulo as part of the operation, great! + * If the target has some other behaviour from out-of-range shifts, + * then it could not use this function anyway, and would need to + * do it's own expansion with custom functions. + */ +static void tcg_gen_shlv_mod_vec(unsigned vece, TCGv_vec d, + TCGv_vec a, TCGv_vec b) +{ + TCGv_vec t =3D tcg_temp_new_vec_matching(d); + + tcg_gen_dupi_vec(vece, t, (8 << vece) - 1); + tcg_gen_and_vec(vece, t, t, b); + tcg_gen_shlv_vec(vece, d, a, t); + tcg_temp_free_vec(t); +} + +static void tcg_gen_shl_mod_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) +{ + TCGv_i32 t =3D tcg_temp_new_i32(); + + tcg_gen_andi_i32(t, b, 31); + tcg_gen_shl_i32(d, a, t); + tcg_temp_free_i32(t); +} + +static void tcg_gen_shl_mod_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) +{ + TCGv_i64 t =3D tcg_temp_new_i64(); + + tcg_gen_andi_i64(t, b, 63); + tcg_gen_shl_i64(d, a, t); + tcg_temp_free_i64(t); +} + +void tcg_gen_gvec_shlv(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz) +{ + static const TCGOpcode vecop_list[] =3D { INDEX_op_shlv_vec, 0 }; + static const GVecGen3 g[4] =3D { + { .fniv =3D tcg_gen_shlv_mod_vec, + .fno =3D gen_helper_gvec_shl8v, + .opt_opc =3D vecop_list, + .vece =3D MO_8 }, + { .fniv =3D tcg_gen_shlv_mod_vec, + .fno =3D gen_helper_gvec_shl16v, + .opt_opc =3D vecop_list, + .vece =3D MO_16 }, + { .fni4 =3D tcg_gen_shl_mod_i32, + .fniv =3D tcg_gen_shlv_mod_vec, + .fno =3D gen_helper_gvec_shl32v, + .opt_opc =3D vecop_list, + .vece =3D MO_32 }, + { .fni8 =3D tcg_gen_shl_mod_i64, + .fniv =3D tcg_gen_shlv_mod_vec, + .fno =3D gen_helper_gvec_shl64v, + .opt_opc =3D vecop_list, + .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .vece =3D MO_64 }, + }; + + tcg_debug_assert(vece <=3D MO_64); + tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]); +} + +/* + * Similarly for logical right shifts. + */ + +static void tcg_gen_shrv_mod_vec(unsigned vece, TCGv_vec d, + TCGv_vec a, TCGv_vec b) +{ + TCGv_vec t =3D tcg_temp_new_vec_matching(d); + + tcg_gen_dupi_vec(vece, t, (8 << vece) - 1); + tcg_gen_and_vec(vece, t, t, b); + tcg_gen_shrv_vec(vece, d, a, t); + tcg_temp_free_vec(t); +} + +static void tcg_gen_shr_mod_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) +{ + TCGv_i32 t =3D tcg_temp_new_i32(); + + tcg_gen_andi_i32(t, b, 31); + tcg_gen_shr_i32(d, a, t); + tcg_temp_free_i32(t); +} + +static void tcg_gen_shr_mod_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) +{ + TCGv_i64 t =3D tcg_temp_new_i64(); + + tcg_gen_andi_i64(t, b, 63); + tcg_gen_shr_i64(d, a, t); + tcg_temp_free_i64(t); +} + +void tcg_gen_gvec_shrv(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz) +{ + static const TCGOpcode vecop_list[] =3D { INDEX_op_shrv_vec, 0 }; + static const GVecGen3 g[4] =3D { + { .fniv =3D tcg_gen_shrv_mod_vec, + .fno =3D gen_helper_gvec_shr8v, + .opt_opc =3D vecop_list, + .vece =3D MO_8 }, + { .fniv =3D tcg_gen_shrv_mod_vec, + .fno =3D gen_helper_gvec_shr16v, + .opt_opc =3D vecop_list, + .vece =3D MO_16 }, + { .fni4 =3D tcg_gen_shr_mod_i32, + .fniv =3D tcg_gen_shrv_mod_vec, + .fno =3D gen_helper_gvec_shr32v, + .opt_opc =3D vecop_list, + .vece =3D MO_32 }, + { .fni8 =3D tcg_gen_shr_mod_i64, + .fniv =3D tcg_gen_shrv_mod_vec, + .fno =3D gen_helper_gvec_shr64v, + .opt_opc =3D vecop_list, + .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .vece =3D MO_64 }, + }; + + tcg_debug_assert(vece <=3D MO_64); + tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]); +} + +/* + * Similarly for arithmetic right shifts. + */ + +static void tcg_gen_sarv_mod_vec(unsigned vece, TCGv_vec d, + TCGv_vec a, TCGv_vec b) +{ + TCGv_vec t =3D tcg_temp_new_vec_matching(d); + + tcg_gen_dupi_vec(vece, t, (8 << vece) - 1); + tcg_gen_and_vec(vece, t, t, b); + tcg_gen_sarv_vec(vece, d, a, t); + tcg_temp_free_vec(t); +} + +static void tcg_gen_sar_mod_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) +{ + TCGv_i32 t =3D tcg_temp_new_i32(); + + tcg_gen_andi_i32(t, b, 31); + tcg_gen_sar_i32(d, a, t); + tcg_temp_free_i32(t); +} + +static void tcg_gen_sar_mod_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) +{ + TCGv_i64 t =3D tcg_temp_new_i64(); + + tcg_gen_andi_i64(t, b, 63); + tcg_gen_sar_i64(d, a, t); + tcg_temp_free_i64(t); +} + +void tcg_gen_gvec_sarv(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz) +{ + static const TCGOpcode vecop_list[] =3D { INDEX_op_sarv_vec, 0 }; + static const GVecGen3 g[4] =3D { + { .fniv =3D tcg_gen_sarv_mod_vec, + .fno =3D gen_helper_gvec_sar8v, + .opt_opc =3D vecop_list, + .vece =3D MO_8 }, + { .fniv =3D tcg_gen_sarv_mod_vec, + .fno =3D gen_helper_gvec_sar16v, + .opt_opc =3D vecop_list, + .vece =3D MO_16 }, + { .fni4 =3D tcg_gen_sar_mod_i32, + .fniv =3D tcg_gen_sarv_mod_vec, + .fno =3D gen_helper_gvec_sar32v, + .opt_opc =3D vecop_list, + .vece =3D MO_32 }, + { .fni8 =3D tcg_gen_sar_mod_i64, + .fniv =3D tcg_gen_sarv_mod_vec, + .fno =3D gen_helper_gvec_sar64v, + .opt_opc =3D vecop_list, + .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .vece =3D MO_64 }, + }; + + tcg_debug_assert(vece <=3D MO_64); + tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]); +} + /* Expand OPSZ bytes worth of three-operand operations using i32 elements.= */ static void expand_cmp_i32(uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t oprsz, TCGCond cond) diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c index 213d2e22aa..96317dbd10 100644 --- a/tcg/tcg-op-vec.c +++ b/tcg/tcg-op-vec.c @@ -583,3 +583,18 @@ void tcg_gen_umax_vec(unsigned vece, TCGv_vec r, TCGv_= vec a, TCGv_vec b) { do_op3(vece, r, a, b, INDEX_op_umax_vec); } + +void tcg_gen_shlv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) +{ + do_op3(vece, r, a, b, INDEX_op_shlv_vec); +} + +void tcg_gen_shrv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) +{ + do_op3(vece, r, a, b, INDEX_op_shrv_vec); +} + +void tcg_gen_sarv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) +{ + do_op3(vece, r, a, b, INDEX_op_sarv_vec); +} --=20 2.17.1 From nobody Fri Apr 19 16:27:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1557815310; cv=none; d=zoho.com; s=zohoarc; b=EfbjnyTDPM7X4gM67nEmikTlnd+6hG9Ib/h0TgAxbpQcdvQkXVaI1xx5nqOwCiCSLfHPXdbmd593vj6sTqi9N6UM2KnNvDbHG+6rNBArfpPknvEuEXt5siyhqmsItGygpI6lunTnXSOJl+NYHwq2dbYJU8OuQ152g0uzdyt+RM0= ARC-Message-Signature: i=1; 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[97.113.13.231]) by smtp.gmail.com with ESMTPSA id u3sm238151pfn.29.2019.05.13.17.06.03 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 13 May 2019 17:06:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=+vy3D5n9NVcZ5Oj9MBgVyI+mUUxTaLSYcOmzMokmrqg=; b=mCQOHQ1HxRB1Chqk92LPRXqtYHOhcMtgWQUTpKtTDqD44VHJKY7uLHg9ZZEBAVGzp8 hOVoqPNzXz58Ig5EuBe4JBAU80yYdVjeP6dn6LxdhVhpXHOLtQgkf0KE+YemVFAz/cqz KB8iVoT3XPh/WoTd61Gn123svcORt2MDgCKWXeFO5wtxb8enHf5HLPOwvDk+07IlUuzY jl0T2eT7K5BpvZ6lBuJCducXe0loB2cGEnwyI5Nw0MARhk6ImVBeEy42uUE6kXLzH1p8 4ayXfF1wgU8ceVUouS7L7U4jIfIZ40b0AFOXOFASi5qfcCD5yNKSnT8oL0wQn4cIQJq2 WdXg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=+vy3D5n9NVcZ5Oj9MBgVyI+mUUxTaLSYcOmzMokmrqg=; b=CKc05/1Ywo/bVAhHKusTxufyMlgE810P7SKoGmbJJwdshW8Af5NbdoJL+VfTnCAgC+ g24OmqX/491JMM5SsVYuJEtuZhW07Ro/v/2WnY3KoMXTu+/5PTPWl+qh3sSdnCv8TEGn Uqch4NSGR7EfnIgsgNNdGOByM0KiDZJAWUThPjjUmOqnJgWsEOT+C1qbi478S/OGU3Mh EiU2slKhcFJ/tQoMkzS8eown31dTjnhVsifxVUng2DLGXYTsi4U+krFFlizRfOWwvBMK l9HM5HPeYzJH/dnoM6lh/cfRZyt77XYQwG8Q758H+bOrFRs9V45CsIOegiKg1813eMRv jnPQ== X-Gm-Message-State: APjAAAVDbwSC4GoactzMUpG5i0PVdFZSfKzwIbRKlH/OU2V6qkRFxEEd ao81p8Zm0gOILacbRHun3QJd/SOTQXM= X-Google-Smtp-Source: APXvYqz/U8jycTtHzNShUazkDAcqZLQBAN/HCPQUsziGlV/w4Eu1aQKDoHHvZ8NzhloXugcCZ1aeZA== X-Received: by 2002:a17:902:20e2:: with SMTP id v31mr34815656plg.138.1557792364786; Mon, 13 May 2019 17:06:04 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 13 May 2019 17:05:25 -0700 Message-Id: <20190514000540.4313-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190514000540.4313-1-richard.henderson@linaro.org> References: <20190514000540.4313-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::635 Subject: [Qemu-devel] [PULL 16/31] tcg/i386: Support vector variable shift opcodes X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linux.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.h | 2 +- tcg/i386/tcg-target.inc.c | 35 +++++++++++++++++++++++++++++++++++ 2 files changed, 36 insertions(+), 1 deletion(-) diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 241bf19413..b240633455 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -184,7 +184,7 @@ extern bool have_avx2; #define TCG_TARGET_HAS_neg_vec 0 #define TCG_TARGET_HAS_shi_vec 1 #define TCG_TARGET_HAS_shs_vec 0 -#define TCG_TARGET_HAS_shv_vec 0 +#define TCG_TARGET_HAS_shv_vec have_avx2 #define TCG_TARGET_HAS_cmp_vec 1 #define TCG_TARGET_HAS_mul_vec 1 #define TCG_TARGET_HAS_sat_vec 1 diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index 5b33bbd99b..c9448b6d84 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -467,6 +467,11 @@ static inline int tcg_target_const_match(tcg_target_lo= ng val, TCGType type, #define OPC_VPBROADCASTQ (0x59 | P_EXT38 | P_DATA16) #define OPC_VPERMQ (0x00 | P_EXT3A | P_DATA16 | P_REXW) #define OPC_VPERM2I128 (0x46 | P_EXT3A | P_DATA16 | P_VEXL) +#define OPC_VPSLLVD (0x47 | P_EXT38 | P_DATA16) +#define OPC_VPSLLVQ (0x47 | P_EXT38 | P_DATA16 | P_REXW) +#define OPC_VPSRAVD (0x46 | P_EXT38 | P_DATA16) +#define OPC_VPSRLVD (0x45 | P_EXT38 | P_DATA16) +#define OPC_VPSRLVQ (0x45 | P_EXT38 | P_DATA16 | P_REXW) #define OPC_VZEROUPPER (0x77 | P_EXT) #define OPC_XCHG_ax_r32 (0x90) =20 @@ -2707,6 +2712,18 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, static int const umax_insn[4] =3D { OPC_PMAXUB, OPC_PMAXUW, OPC_PMAXUD, OPC_UD2 }; + static int const shlv_insn[4] =3D { + /* TODO: AVX512 adds support for MO_16. */ + OPC_UD2, OPC_UD2, OPC_VPSLLVD, OPC_VPSLLVQ + }; + static int const shrv_insn[4] =3D { + /* TODO: AVX512 adds support for MO_16. */ + OPC_UD2, OPC_UD2, OPC_VPSRLVD, OPC_VPSRLVQ + }; + static int const sarv_insn[4] =3D { + /* TODO: AVX512 adds support for MO_16, MO_64. */ + OPC_UD2, OPC_UD2, OPC_VPSRAVD, OPC_UD2 + }; =20 TCGType type =3D vecl + TCG_TYPE_V64; int insn, sub; @@ -2759,6 +2776,15 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, case INDEX_op_umax_vec: insn =3D umax_insn[vece]; goto gen_simd; + case INDEX_op_shlv_vec: + insn =3D shlv_insn[vece]; + goto gen_simd; + case INDEX_op_shrv_vec: + insn =3D shrv_insn[vece]; + goto gen_simd; + case INDEX_op_sarv_vec: + insn =3D sarv_insn[vece]; + goto gen_simd; case INDEX_op_x86_punpckl_vec: insn =3D punpckl_insn[vece]; goto gen_simd; @@ -3136,6 +3162,9 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) case INDEX_op_umin_vec: case INDEX_op_smax_vec: case INDEX_op_umax_vec: + case INDEX_op_shlv_vec: + case INDEX_op_shrv_vec: + case INDEX_op_sarv_vec: case INDEX_op_cmp_vec: case INDEX_op_x86_shufps_vec: case INDEX_op_x86_blend_vec: @@ -3193,6 +3222,12 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type,= unsigned vece) } return 1; =20 + case INDEX_op_shlv_vec: + case INDEX_op_shrv_vec: + return have_avx2 && vece >=3D MO_32; + case INDEX_op_sarv_vec: + return have_avx2 && vece =3D=3D MO_32; + case INDEX_op_mul_vec: if (vece =3D=3D MO_8) { /* We can expand the operation for MO_8. */ --=20 2.17.1 From nobody Fri Apr 19 16:27:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1557809494; cv=none; d=zoho.com; s=zohoarc; b=OOvXrep3nnFPSRChTPgE23z2sZ0U90wNFJ8bGNMk5p38GYHMVtcB6O2UzscN+0HL06NFwHsGJPr5ps1oj+ycwuvEgZcWWOcIh35qXyTOhjNjr+LVdn70geT8wJ1otn4lAUF9oo9oJuuC3HSDfFn/93uVWJqqwWlmd1FYoqzRTTk= ARC-Message-Signature: i=1; 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X-Received-From: 2607:f8b0:4864:20::62d Subject: [Qemu-devel] [PULL 17/31] tcg/aarch64: Support vector variable shift opcodes X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linux.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.h | 2 +- tcg/aarch64/tcg-target.opc.h | 2 ++ tcg/aarch64/tcg-target.inc.c | 42 ++++++++++++++++++++++++++++++++++++ 3 files changed, 45 insertions(+), 1 deletion(-) diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index ce2bb1f90b..f5640a229b 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -134,7 +134,7 @@ typedef enum { #define TCG_TARGET_HAS_neg_vec 1 #define TCG_TARGET_HAS_shi_vec 1 #define TCG_TARGET_HAS_shs_vec 0 -#define TCG_TARGET_HAS_shv_vec 0 +#define TCG_TARGET_HAS_shv_vec 1 #define TCG_TARGET_HAS_cmp_vec 1 #define TCG_TARGET_HAS_mul_vec 1 #define TCG_TARGET_HAS_sat_vec 1 diff --git a/tcg/aarch64/tcg-target.opc.h b/tcg/aarch64/tcg-target.opc.h index 4816a6c3d4..59e1d3f7f7 100644 --- a/tcg/aarch64/tcg-target.opc.h +++ b/tcg/aarch64/tcg-target.opc.h @@ -1,3 +1,5 @@ /* Target-specific opcodes for host vector expansion. These will be emitted by tcg_expand_vec_op. For those familiar with GCC internals, consider these to be UNSPEC with names. */ + +DEF(aa64_sshl_vec, 1, 2, 0, IMPLVEC) diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c index 3dda66e777..df123c07f1 100644 --- a/tcg/aarch64/tcg-target.inc.c +++ b/tcg/aarch64/tcg-target.inc.c @@ -536,12 +536,14 @@ typedef enum { I3616_CMEQ =3D 0x2e208c00, I3616_SMAX =3D 0x0e206400, I3616_SMIN =3D 0x0e206c00, + I3616_SSHL =3D 0x0e204400, I3616_SQADD =3D 0x0e200c00, I3616_SQSUB =3D 0x0e202c00, I3616_UMAX =3D 0x2e206400, I3616_UMIN =3D 0x2e206c00, I3616_UQADD =3D 0x2e200c00, I3616_UQSUB =3D 0x2e202c00, + I3616_USHL =3D 0x2e204400, =20 /* AdvSIMD two-reg misc. */ I3617_CMGT0 =3D 0x0e208800, @@ -2257,6 +2259,12 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, case INDEX_op_sari_vec: tcg_out_insn(s, 3614, SSHR, is_q, a0, a1, (16 << vece) - a2); break; + case INDEX_op_shlv_vec: + tcg_out_insn(s, 3616, USHL, is_q, vece, a0, a1, a2); + break; + case INDEX_op_aa64_sshl_vec: + tcg_out_insn(s, 3616, SSHL, is_q, vece, a0, a1, a2); + break; case INDEX_op_cmp_vec: { TCGCond cond =3D args[3]; @@ -2324,7 +2332,11 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type,= unsigned vece) case INDEX_op_smin_vec: case INDEX_op_umax_vec: case INDEX_op_umin_vec: + case INDEX_op_shlv_vec: return 1; + case INDEX_op_shrv_vec: + case INDEX_op_sarv_vec: + return -1; case INDEX_op_mul_vec: return vece < MO_64; =20 @@ -2336,6 +2348,32 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type,= unsigned vece) void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, TCGArg a0, ...) { + va_list va; + TCGv_vec v0, v1, v2, t1; + + va_start(va, a0); + v0 =3D temp_tcgv_vec(arg_temp(a0)); + v1 =3D temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); + v2 =3D temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); + + switch (opc) { + case INDEX_op_shrv_vec: + case INDEX_op_sarv_vec: + /* Right shifts are negative left shifts for AArch64. */ + t1 =3D tcg_temp_new_vec(type); + tcg_gen_neg_vec(vece, t1, v2); + opc =3D (opc =3D=3D INDEX_op_shrv_vec + ? INDEX_op_shlv_vec : INDEX_op_aa64_sshl_vec); + vec_gen_3(opc, type, vece, tcgv_vec_arg(v0), + tcgv_vec_arg(v1), tcgv_vec_arg(t1)); + tcg_temp_free_vec(t1); + break; + + default: + g_assert_not_reached(); + } + + va_end(va); } =20 static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) @@ -2517,6 +2555,10 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOp= code op) case INDEX_op_smin_vec: case INDEX_op_umax_vec: case INDEX_op_umin_vec: + case INDEX_op_shlv_vec: + case INDEX_op_shrv_vec: + case INDEX_op_sarv_vec: + case INDEX_op_aa64_sshl_vec: return &w_w_w; case INDEX_op_not_vec: case INDEX_op_neg_vec: --=20 2.17.1 From nobody Fri Apr 19 16:27:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1557808642; cv=none; d=zoho.com; s=zohoarc; b=dPss3S3sgPMvtD6t58dvMHcoXzSnyx5rQF/wkBdJPaKYUsezQzQnZbkMnRGJPUCfdCunX2lLIW1yV7PqgMZOjHGKSk3O5A46busSnf04Zt4LcGFz42+8HczA1Qb+iUdoh1GxCdTA6zam31AXkFx84k8GokoTwUSAtK1hSOFRZro= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1557808642; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=qw9asg7SRqxlX27WylYo/55gkKhhqIWBrKFJgQwUqqc=; b=SgyB1on/xWiDrVQ7eDSCWis9jYqUFybsmJ4SNg1t41mBGBrqbUxGOGKlxG+0/NbTfyjakbMIrnKxy+jBRrwbem/GOd0+LKai7ufk9vYwFiIAgFmP7hHh7CfG9ZbtZ1f7HpEObMTfESOHZc5Elk7bj4OKZbD9SfPXSM1SxDK4Ddc= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1557808642864177.43649632019606; Mon, 13 May 2019 21:37:22 -0700 (PDT) Received: from localhost ([127.0.0.1]:39002 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hQPBA-0003IF-6m for importer@patchew.org; Tue, 14 May 2019 00:36:40 -0400 Received: from eggs.gnu.org ([209.51.188.92]:58419) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hQPAF-0002xl-5W for qemu-devel@nongnu.org; Tue, 14 May 2019 00:35:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hQPAD-000576-Eh for qemu-devel@nongnu.org; Tue, 14 May 2019 00:35:43 -0400 Received: from mail-pl1-x629.google.com ([2607:f8b0:4864:20::629]:45077) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hQKxN-0003PZ-Js for qemu-devel@nongnu.org; Mon, 13 May 2019 20:06:11 -0400 Received: by mail-pl1-x629.google.com with SMTP id a5so7254609pls.12 for ; Mon, 13 May 2019 17:06:08 -0700 (PDT) Received: from localhost.localdomain (97-113-13-231.tukw.qwest.net. [97.113.13.231]) by smtp.gmail.com with ESMTPSA id u3sm238151pfn.29.2019.05.13.17.06.06 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 13 May 2019 17:06:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=qw9asg7SRqxlX27WylYo/55gkKhhqIWBrKFJgQwUqqc=; b=lkG/QmzTW/zZONINuJOr2zZe9lZC/dbWUUqmnAWhOfiqiys/vYzZ1t+C78K/1MoI+C JJ5bIW/M6upkIWDdXXDyRlh9/jIggv8RFYIfWP42UaBe1+TXM9ia8MY6KMHpTx8Iy4Gr 6fEppWA7/nGPoGg68L4qZQ8z2VVE9MFbjSZSKhCMZoHrdgWwq+3n+jAV+3Zf7ompXsR8 Jr+WXccVDoo/5LMDobbzKBYvupsKVT6AUmde7KIfhl/CWRvxXPSQ52e7TFMpD5b1IVvg kZWQm+R8YbtvubJh7YrKFc398SJ4nY/lHoOEhxOzTHgbqU0ajNYpOoMW5fUGBYwtjEIE whIw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=qw9asg7SRqxlX27WylYo/55gkKhhqIWBrKFJgQwUqqc=; b=RLn2parAmCEnzl6+OQygRwjo9gW3sPWYK74kiV+pAASZQ017BigTS0wqi86Vn1rN64 FMY0bTErnxAJn8/DwqzvKBDJny6ceQ3U2og/JJJdlmzFAfQbMGoeIXB4TuKgVn7XYQTL /wSSoq7QUW6zXLJbKOt2L5RgTq4ugXAGAcVdvimGomZeWCG9ib3G4NQ88zTgLa+dYNJC cSI6EeIpqDUKiK+Ui5lVMnXM2YwDDAFRvuG30aa7gB8Z96cKIbktMzJccCKyxGddPxjo w3DEF1+ciKP6qaoIIxO9y7qvlc30ha0NSrwqCrD7sveFbhPPtuvDPhE568smRgrzcGvj l4tQ== X-Gm-Message-State: APjAAAVd1LpUIL9RohS0SgXgLO2L+ijlK6DM0nyJLm0KUlTh9Iqw0PcA FeIgvaTbv4SrCFv9iAa64S3O9oy1/9c= X-Google-Smtp-Source: APXvYqxhZUdaov2z+wJEK0+Ry6AsiSsqnyU3q0sNB3hdvt2JitreIKr/X7+uJsW9DsEBDnPbqZ2UjA== X-Received: by 2002:a17:902:b202:: with SMTP id t2mr33525755plr.69.1557792367215; Mon, 13 May 2019 17:06:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 13 May 2019 17:05:27 -0700 Message-Id: <20190514000540.4313-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190514000540.4313-1-richard.henderson@linaro.org> References: <20190514000540.4313-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::629 Subject: [Qemu-devel] [PULL 18/31] tcg: Add gvec expanders for vector shift by scalar X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linux.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Allow expansion either via shift by scalar or by replicating the scalar for shift by vector. Signed-off-by: Richard Henderson --- v3: Use a private structure for do_gvec_shifts. --- tcg/tcg-op-gvec.h | 7 ++ tcg/tcg-op.h | 4 + tcg/tcg-op-gvec.c | 214 ++++++++++++++++++++++++++++++++++++++++++++++ tcg/tcg-op-vec.c | 54 ++++++++++++ 4 files changed, 279 insertions(+) diff --git a/tcg/tcg-op-gvec.h b/tcg/tcg-op-gvec.h index 84a6247b16..6ee98f3378 100644 --- a/tcg/tcg-op-gvec.h +++ b/tcg/tcg-op-gvec.h @@ -318,6 +318,13 @@ void tcg_gen_gvec_shri(unsigned vece, uint32_t dofs, u= int32_t aofs, void tcg_gen_gvec_sari(unsigned vece, uint32_t dofs, uint32_t aofs, int64_t shift, uint32_t oprsz, uint32_t maxsz); =20 +void tcg_gen_gvec_shls(unsigned vece, uint32_t dofs, uint32_t aofs, + TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_shrs(unsigned vece, uint32_t dofs, uint32_t aofs, + TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_sars(unsigned vece, uint32_t dofs, uint32_t aofs, + TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz); + /* * Perform vector shift by vector element, modulo the element size. * E.g. D[i] =3D A[i] << (B[i] % (8 << vece)). diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h index 833c6330b5..472b73cb38 100644 --- a/tcg/tcg-op.h +++ b/tcg/tcg-op.h @@ -986,6 +986,10 @@ void tcg_gen_shli_vec(unsigned vece, TCGv_vec r, TCGv_= vec a, int64_t i); void tcg_gen_shri_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i); void tcg_gen_sari_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i); =20 +void tcg_gen_shls_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s); +void tcg_gen_shrs_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s); +void tcg_gen_sars_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s); + void tcg_gen_shlv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s); void tcg_gen_shrv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s); void tcg_gen_sarv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s); diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c index 061ef329f1..c69c7960b8 100644 --- a/tcg/tcg-op-gvec.c +++ b/tcg/tcg-op-gvec.c @@ -2555,6 +2555,220 @@ void tcg_gen_gvec_sari(unsigned vece, uint32_t dofs= , uint32_t aofs, } } =20 +/* + * Specialized generation vector shifts by a non-constant scalar. + */ + +typedef struct { + void (*fni4)(TCGv_i32, TCGv_i32, TCGv_i32); + void (*fni8)(TCGv_i64, TCGv_i64, TCGv_i64); + void (*fniv_s)(unsigned, TCGv_vec, TCGv_vec, TCGv_i32); + void (*fniv_v)(unsigned, TCGv_vec, TCGv_vec, TCGv_vec); + gen_helper_gvec_2 *fno[4]; + TCGOpcode s_list[2]; + TCGOpcode v_list[2]; +} GVecGen2sh; + +static void expand_2sh_vec(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t oprsz, uint32_t tysz, TCGType type, + TCGv_i32 shift, + void (*fni)(unsigned, TCGv_vec, TCGv_vec, TCGv_= i32)) +{ + TCGv_vec t0 =3D tcg_temp_new_vec(type); + uint32_t i; + + for (i =3D 0; i < oprsz; i +=3D tysz) { + tcg_gen_ld_vec(t0, cpu_env, aofs + i); + fni(vece, t0, t0, shift); + tcg_gen_st_vec(t0, cpu_env, dofs + i); + } + tcg_temp_free_vec(t0); +} + +static void +do_gvec_shifts(unsigned vece, uint32_t dofs, uint32_t aofs, TCGv_i32 shift, + uint32_t oprsz, uint32_t maxsz, const GVecGen2sh *g) +{ + TCGType type; + uint32_t some; + + check_size_align(oprsz, maxsz, dofs | aofs); + check_overlap_2(dofs, aofs, maxsz); + + /* If the backend has a scalar expansion, great. */ + type =3D choose_vector_type(g->s_list, vece, oprsz, vece =3D=3D MO_64); + if (type) { + const TCGOpcode *hold_list =3D tcg_swap_vecop_list(NULL); + switch (type) { + case TCG_TYPE_V256: + some =3D QEMU_ALIGN_DOWN(oprsz, 32); + expand_2sh_vec(vece, dofs, aofs, some, 32, + TCG_TYPE_V256, shift, g->fniv_s); + if (some =3D=3D oprsz) { + break; + } + dofs +=3D some; + aofs +=3D some; + oprsz -=3D some; + maxsz -=3D some; + /* fallthru */ + case TCG_TYPE_V128: + expand_2sh_vec(vece, dofs, aofs, oprsz, 16, + TCG_TYPE_V128, shift, g->fniv_s); + break; + case TCG_TYPE_V64: + expand_2sh_vec(vece, dofs, aofs, oprsz, 8, + TCG_TYPE_V64, shift, g->fniv_s); + break; + default: + g_assert_not_reached(); + } + tcg_swap_vecop_list(hold_list); + goto clear_tail; + } + + /* If the backend supports variable vector shifts, also cool. */ + type =3D choose_vector_type(g->v_list, vece, oprsz, vece =3D=3D MO_64); + if (type) { + const TCGOpcode *hold_list =3D tcg_swap_vecop_list(NULL); + TCGv_vec v_shift =3D tcg_temp_new_vec(type); + + if (vece =3D=3D MO_64) { + TCGv_i64 sh64 =3D tcg_temp_new_i64(); + tcg_gen_extu_i32_i64(sh64, shift); + tcg_gen_dup_i64_vec(MO_64, v_shift, sh64); + tcg_temp_free_i64(sh64); + } else { + tcg_gen_dup_i32_vec(vece, v_shift, shift); + } + + switch (type) { + case TCG_TYPE_V256: + some =3D QEMU_ALIGN_DOWN(oprsz, 32); + expand_2s_vec(vece, dofs, aofs, some, 32, TCG_TYPE_V256, + v_shift, false, g->fniv_v); + if (some =3D=3D oprsz) { + break; + } + dofs +=3D some; + aofs +=3D some; + oprsz -=3D some; + maxsz -=3D some; + /* fallthru */ + case TCG_TYPE_V128: + expand_2s_vec(vece, dofs, aofs, oprsz, 16, TCG_TYPE_V128, + v_shift, false, g->fniv_v); + break; + case TCG_TYPE_V64: + expand_2s_vec(vece, dofs, aofs, oprsz, 8, TCG_TYPE_V64, + v_shift, false, g->fniv_v); + break; + default: + g_assert_not_reached(); + } + tcg_temp_free_vec(v_shift); + tcg_swap_vecop_list(hold_list); + goto clear_tail; + } + + /* Otherwise fall back to integral... */ + if (vece =3D=3D MO_32 && check_size_impl(oprsz, 4)) { + expand_2s_i32(dofs, aofs, oprsz, shift, false, g->fni4); + } else if (vece =3D=3D MO_64 && check_size_impl(oprsz, 8)) { + TCGv_i64 sh64 =3D tcg_temp_new_i64(); + tcg_gen_extu_i32_i64(sh64, shift); + expand_2s_i64(dofs, aofs, oprsz, sh64, false, g->fni8); + tcg_temp_free_i64(sh64); + } else { + TCGv_ptr a0 =3D tcg_temp_new_ptr(); + TCGv_ptr a1 =3D tcg_temp_new_ptr(); + TCGv_i32 desc =3D tcg_temp_new_i32(); + + tcg_gen_shli_i32(desc, shift, SIMD_DATA_SHIFT); + tcg_gen_ori_i32(desc, desc, simd_desc(oprsz, maxsz, 0)); + tcg_gen_addi_ptr(a0, cpu_env, dofs); + tcg_gen_addi_ptr(a1, cpu_env, aofs); + + g->fno[vece](a0, a1, desc); + + tcg_temp_free_ptr(a0); + tcg_temp_free_ptr(a1); + tcg_temp_free_i32(desc); + return; + } + + clear_tail: + if (oprsz < maxsz) { + expand_clr(dofs + oprsz, maxsz - oprsz); + } +} + +void tcg_gen_gvec_shls(unsigned vece, uint32_t dofs, uint32_t aofs, + TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz) +{ + static const GVecGen2sh g =3D { + .fni4 =3D tcg_gen_shl_i32, + .fni8 =3D tcg_gen_shl_i64, + .fniv_s =3D tcg_gen_shls_vec, + .fniv_v =3D tcg_gen_shlv_vec, + .fno =3D { + gen_helper_gvec_shl8i, + gen_helper_gvec_shl16i, + gen_helper_gvec_shl32i, + gen_helper_gvec_shl64i, + }, + .s_list =3D { INDEX_op_shls_vec, 0 }, + .v_list =3D { INDEX_op_shlv_vec, 0 }, + }; + + tcg_debug_assert(vece <=3D MO_64); + do_gvec_shifts(vece, dofs, aofs, shift, oprsz, maxsz, &g); +} + +void tcg_gen_gvec_shrs(unsigned vece, uint32_t dofs, uint32_t aofs, + TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz) +{ + static const GVecGen2sh g =3D { + .fni4 =3D tcg_gen_shr_i32, + .fni8 =3D tcg_gen_shr_i64, + .fniv_s =3D tcg_gen_shrs_vec, + .fniv_v =3D tcg_gen_shrv_vec, + .fno =3D { + gen_helper_gvec_shr8i, + gen_helper_gvec_shr16i, + gen_helper_gvec_shr32i, + gen_helper_gvec_shr64i, + }, + .s_list =3D { INDEX_op_shrs_vec, 0 }, + .v_list =3D { INDEX_op_shrv_vec, 0 }, + }; + + tcg_debug_assert(vece <=3D MO_64); + do_gvec_shifts(vece, dofs, aofs, shift, oprsz, maxsz, &g); +} + +void tcg_gen_gvec_sars(unsigned vece, uint32_t dofs, uint32_t aofs, + TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz) +{ + static const GVecGen2sh g =3D { + .fni4 =3D tcg_gen_sar_i32, + .fni8 =3D tcg_gen_sar_i64, + .fniv_s =3D tcg_gen_sars_vec, + .fniv_v =3D tcg_gen_sarv_vec, + .fno =3D { + gen_helper_gvec_sar8i, + gen_helper_gvec_sar16i, + gen_helper_gvec_sar32i, + gen_helper_gvec_sar64i, + }, + .s_list =3D { INDEX_op_sars_vec, 0 }, + .v_list =3D { INDEX_op_sarv_vec, 0 }, + }; + + tcg_debug_assert(vece <=3D MO_64); + do_gvec_shifts(vece, dofs, aofs, shift, oprsz, maxsz, &g); +} + /* * Expand D =3D A << (B % element bits) * diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c index 96317dbd10..16062f5995 100644 --- a/tcg/tcg-op-vec.c +++ b/tcg/tcg-op-vec.c @@ -598,3 +598,57 @@ void tcg_gen_sarv_vec(unsigned vece, TCGv_vec r, TCGv_= vec a, TCGv_vec b) { do_op3(vece, r, a, b, INDEX_op_sarv_vec); } + +static void do_shifts(unsigned vece, TCGv_vec r, TCGv_vec a, + TCGv_i32 s, TCGOpcode opc_s, TCGOpcode opc_v) +{ + TCGTemp *rt =3D tcgv_vec_temp(r); + TCGTemp *at =3D tcgv_vec_temp(a); + TCGTemp *st =3D tcgv_i32_temp(s); + TCGArg ri =3D temp_arg(rt); + TCGArg ai =3D temp_arg(at); + TCGArg si =3D temp_arg(st); + TCGType type =3D rt->base_type; + const TCGOpcode *hold_list; + int can; + + tcg_debug_assert(at->base_type >=3D type); + tcg_assert_listed_vecop(opc_s); + hold_list =3D tcg_swap_vecop_list(NULL); + + can =3D tcg_can_emit_vec_op(opc_s, type, vece); + if (can > 0) { + vec_gen_3(opc_s, type, vece, ri, ai, si); + } else if (can < 0) { + tcg_expand_vec_op(opc_s, type, vece, ri, ai, si); + } else { + TCGv_vec vec_s =3D tcg_temp_new_vec(type); + + if (vece =3D=3D MO_64) { + TCGv_i64 s64 =3D tcg_temp_new_i64(); + tcg_gen_extu_i32_i64(s64, s); + tcg_gen_dup_i64_vec(MO_64, vec_s, s64); + tcg_temp_free_i64(s64); + } else { + tcg_gen_dup_i32_vec(vece, vec_s, s); + } + do_op3(vece, r, a, vec_s, opc_v); + tcg_temp_free_vec(vec_s); + } + tcg_swap_vecop_list(hold_list); +} + +void tcg_gen_shls_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 b) +{ + do_shifts(vece, r, a, b, INDEX_op_shls_vec, INDEX_op_shlv_vec); +} + +void tcg_gen_shrs_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 b) +{ + do_shifts(vece, r, a, b, INDEX_op_shrs_vec, INDEX_op_shrv_vec); +} + +void tcg_gen_sars_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 b) +{ + do_shifts(vece, r, a, b, INDEX_op_sars_vec, INDEX_op_sarv_vec); +} --=20 2.17.1 From nobody Fri Apr 19 16:27:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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X-Received-From: 2607:f8b0:4864:20::535 Subject: [Qemu-devel] [PULL 19/31] tcg/i386: Support vector scalar shift opcodes X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linux.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.h | 2 +- tcg/i386/tcg-target.inc.c | 35 +++++++++++++++++++++++++++++++++++ 2 files changed, 36 insertions(+), 1 deletion(-) diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index b240633455..618aa520d2 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -183,7 +183,7 @@ extern bool have_avx2; #define TCG_TARGET_HAS_not_vec 0 #define TCG_TARGET_HAS_neg_vec 0 #define TCG_TARGET_HAS_shi_vec 1 -#define TCG_TARGET_HAS_shs_vec 0 +#define TCG_TARGET_HAS_shs_vec 1 #define TCG_TARGET_HAS_shv_vec have_avx2 #define TCG_TARGET_HAS_cmp_vec 1 #define TCG_TARGET_HAS_mul_vec 1 diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index c9448b6d84..0ba1587da4 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -420,6 +420,14 @@ static inline int tcg_target_const_match(tcg_target_lo= ng val, TCGType type, #define OPC_PSHIFTW_Ib (0x71 | P_EXT | P_DATA16) /* /2 /6 /4 */ #define OPC_PSHIFTD_Ib (0x72 | P_EXT | P_DATA16) /* /2 /6 /4 */ #define OPC_PSHIFTQ_Ib (0x73 | P_EXT | P_DATA16) /* /2 /6 /4 */ +#define OPC_PSLLW (0xf1 | P_EXT | P_DATA16) +#define OPC_PSLLD (0xf2 | P_EXT | P_DATA16) +#define OPC_PSLLQ (0xf3 | P_EXT | P_DATA16) +#define OPC_PSRAW (0xe1 | P_EXT | P_DATA16) +#define OPC_PSRAD (0xe2 | P_EXT | P_DATA16) +#define OPC_PSRLW (0xd1 | P_EXT | P_DATA16) +#define OPC_PSRLD (0xd2 | P_EXT | P_DATA16) +#define OPC_PSRLQ (0xd3 | P_EXT | P_DATA16) #define OPC_PSUBB (0xf8 | P_EXT | P_DATA16) #define OPC_PSUBW (0xf9 | P_EXT | P_DATA16) #define OPC_PSUBD (0xfa | P_EXT | P_DATA16) @@ -2724,6 +2732,15 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, /* TODO: AVX512 adds support for MO_16, MO_64. */ OPC_UD2, OPC_UD2, OPC_VPSRAVD, OPC_UD2 }; + static int const shls_insn[4] =3D { + OPC_UD2, OPC_PSLLW, OPC_PSLLD, OPC_PSLLQ + }; + static int const shrs_insn[4] =3D { + OPC_UD2, OPC_PSRLW, OPC_PSRLD, OPC_PSRLQ + }; + static int const sars_insn[4] =3D { + OPC_UD2, OPC_PSRAW, OPC_PSRAD, OPC_UD2 + }; =20 TCGType type =3D vecl + TCG_TYPE_V64; int insn, sub; @@ -2785,6 +2802,15 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, case INDEX_op_sarv_vec: insn =3D sarv_insn[vece]; goto gen_simd; + case INDEX_op_shls_vec: + insn =3D shls_insn[vece]; + goto gen_simd; + case INDEX_op_shrs_vec: + insn =3D shrs_insn[vece]; + goto gen_simd; + case INDEX_op_sars_vec: + insn =3D sars_insn[vece]; + goto gen_simd; case INDEX_op_x86_punpckl_vec: insn =3D punpckl_insn[vece]; goto gen_simd; @@ -3165,6 +3191,9 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) case INDEX_op_shlv_vec: case INDEX_op_shrv_vec: case INDEX_op_sarv_vec: + case INDEX_op_shls_vec: + case INDEX_op_shrs_vec: + case INDEX_op_sars_vec: case INDEX_op_cmp_vec: case INDEX_op_x86_shufps_vec: case INDEX_op_x86_blend_vec: @@ -3222,6 +3251,12 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type,= unsigned vece) } return 1; =20 + case INDEX_op_shls_vec: + case INDEX_op_shrs_vec: + return vece >=3D MO_16; + case INDEX_op_sars_vec: + return vece >=3D MO_16 && vece <=3D MO_32; + case INDEX_op_shlv_vec: case INDEX_op_shrv_vec: return have_avx2 && vece >=3D MO_32; --=20 2.17.1 From nobody Fri Apr 19 16:27:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1557811477; cv=none; d=zoho.com; s=zohoarc; b=ZmA2/qnP7mIcazRk7X9xSzFr6SxbChKzp/wMxZT4K9YG+LiawBI7xYnaZJ2ej103bcmvX08hijA6OjGZyJOAMGhTjjKoyx7229pN0kuNJ8F//wPyZJS8F11VlGuH5GWYIURJWrEQ97ICQCTjJ/ds5nIFhyJF6aO/0zwqMdmQbGg= ARC-Message-Signature: i=1; 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[97.113.13.231]) by smtp.gmail.com with ESMTPSA id u3sm238151pfn.29.2019.05.13.17.06.08 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 13 May 2019 17:06:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=oB7VP5ATUZChOLMjOlpdWPN1IctJhwYBQQIlaCDVjkw=; b=leTqu8/DI8MzpUWoAYnCi1Qr4rR0BtDqbXChthla/WcLLjap3YjbdF7QbYqfwoH8mf OCpU21DvuZ4xwPpdaQ/828EJApuw5wCc24hYWqBVyGt7CzTIs1j+aexFQw1mi7zSzrrJ WrkBSpMNrEtXHbKRVwZvxHJ/QpvKSJazzGrMd9yTHNUQMaA6e+5oc1/3C63NaGY99z6s Gy1zHDznTt+2ZUwE6s047lMidadP5Ub1DEMwK/hFLfzmXIk14YEYhRlXTtHXqVsh6lML gBKZjeEIfbL4tc3yiwk6WiSJtcqkJShKrdLrwa2giPTtetY6W8S4DAfowveoF3cjXMZV U+nw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=oB7VP5ATUZChOLMjOlpdWPN1IctJhwYBQQIlaCDVjkw=; b=LmNfyC63gaR117mb/xxd1goLICmA92PJE/zLK+/Oo9hqir8nRjq3oL9gp4XFeQl0u/ GGm/jAwIcRPIu5eB4wfdmEhwnTZ9C6gXlIkHiJEuerdLMWsBxxYCrS5+HX8vwbJ89t55 5/2uGYLEvew2Ly+itK+KO7y9fZB76zrmk7BSptfRorMQyyEiIcbLrxmSrw6WDOl6w/Lj iCn/F8mUw4TpYLGK2uElCHZSDPEh/T4vHQ83vuYb3SQNORiZH7ua9lgbXa4/gpRxxyXF 8+9TxLnOQ4tNRa5kWD0PnfhaJPKYLHDDwmagKjhddJH4D49OP+cqjQmxrl9xPw2S5o6Y 4vgg== X-Gm-Message-State: APjAAAUPxFz/G+80Q8T4uZwu1IpzSe4+RI7bOhe57a+6ProCuA6gkRWb ZLdwBk1orz1wFPRdju1dU3pmip0iqak= X-Google-Smtp-Source: APXvYqwDQhebWUDaVLM/bY2S9m8bNX2yc9Lj/TMZ5v9ekYGQuugEPq6EKvE9zy/bYNE0MEfenAzV7w== X-Received: by 2002:a17:902:e785:: with SMTP id cp5mr15743115plb.167.1557792369502; Mon, 13 May 2019 17:06:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 13 May 2019 17:05:29 -0700 Message-Id: <20190514000540.4313-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190514000540.4313-1-richard.henderson@linaro.org> References: <20190514000540.4313-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::62a Subject: [Qemu-devel] [PULL 20/31] tcg: Add support for integer absolute value X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linux.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Remove a function of the same name from target/arm/. Use a branchless implementation of abs gleaned from gcc. Reviewed-by: Alex Benn=C3=A9e Reviewed-by: David Hildenbrand Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/tcg-op.h | 5 +++++ target/arm/translate.c | 10 ---------- tcg/tcg-op.c | 20 ++++++++++++++++++++ 3 files changed, 25 insertions(+), 10 deletions(-) diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h index 472b73cb38..660fe205d0 100644 --- a/tcg/tcg-op.h +++ b/tcg/tcg-op.h @@ -335,6 +335,7 @@ void tcg_gen_smin_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32= arg2); void tcg_gen_smax_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_umin_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_umax_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2); +void tcg_gen_abs_i32(TCGv_i32, TCGv_i32); =20 static inline void tcg_gen_discard_i32(TCGv_i32 arg) { @@ -534,6 +535,7 @@ void tcg_gen_smin_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64= arg2); void tcg_gen_smax_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_umin_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_umax_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2); +void tcg_gen_abs_i64(TCGv_i64, TCGv_i64); =20 #if TCG_TARGET_REG_BITS =3D=3D 64 static inline void tcg_gen_discard_i64(TCGv_i64 arg) @@ -973,6 +975,7 @@ void tcg_gen_nor_vec(unsigned vece, TCGv_vec r, TCGv_ve= c a, TCGv_vec b); void tcg_gen_eqv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); void tcg_gen_not_vec(unsigned vece, TCGv_vec r, TCGv_vec a); void tcg_gen_neg_vec(unsigned vece, TCGv_vec r, TCGv_vec a); +void tcg_gen_abs_vec(unsigned vece, TCGv_vec r, TCGv_vec a); void tcg_gen_ssadd_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); void tcg_gen_usadd_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); void tcg_gen_sssub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); @@ -1019,6 +1022,7 @@ void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr base, TCGAr= g offset, TCGType t); #define tcg_gen_addi_tl tcg_gen_addi_i64 #define tcg_gen_sub_tl tcg_gen_sub_i64 #define tcg_gen_neg_tl tcg_gen_neg_i64 +#define tcg_gen_abs_tl tcg_gen_abs_i64 #define tcg_gen_subfi_tl tcg_gen_subfi_i64 #define tcg_gen_subi_tl tcg_gen_subi_i64 #define tcg_gen_and_tl tcg_gen_and_i64 @@ -1131,6 +1135,7 @@ void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr base, TCGAr= g offset, TCGType t); #define tcg_gen_addi_tl tcg_gen_addi_i32 #define tcg_gen_sub_tl tcg_gen_sub_i32 #define tcg_gen_neg_tl tcg_gen_neg_i32 +#define tcg_gen_abs_tl tcg_gen_abs_i32 #define tcg_gen_subfi_tl tcg_gen_subfi_i32 #define tcg_gen_subi_tl tcg_gen_subi_i32 #define tcg_gen_and_tl tcg_gen_and_i32 diff --git a/target/arm/translate.c b/target/arm/translate.c index 35bd426a3d..b25781554f 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -604,16 +604,6 @@ static void gen_sar(TCGv_i32 dest, TCGv_i32 t0, TCGv_i= 32 t1) tcg_temp_free_i32(tmp1); } =20 -static void tcg_gen_abs_i32(TCGv_i32 dest, TCGv_i32 src) -{ - TCGv_i32 c0 =3D tcg_const_i32(0); - TCGv_i32 tmp =3D tcg_temp_new_i32(); - tcg_gen_neg_i32(tmp, src); - tcg_gen_movcond_i32(TCG_COND_GT, dest, src, c0, src, tmp); - tcg_temp_free_i32(c0); - tcg_temp_free_i32(tmp); -} - static void shifter_out_im(TCGv_i32 var, int shift) { if (shift =3D=3D 0) { diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index a00d1df37e..0ac291f1c4 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -1091,6 +1091,16 @@ void tcg_gen_umax_i32(TCGv_i32 ret, TCGv_i32 a, TCGv= _i32 b) tcg_gen_movcond_i32(TCG_COND_LTU, ret, a, b, b, a); } =20 +void tcg_gen_abs_i32(TCGv_i32 ret, TCGv_i32 a) +{ + TCGv_i32 t =3D tcg_temp_new_i32(); + + tcg_gen_sari_i32(t, a, 31); + tcg_gen_xor_i32(ret, a, t); + tcg_gen_sub_i32(ret, ret, t); + tcg_temp_free_i32(t); +} + /* 64-bit ops */ =20 #if TCG_TARGET_REG_BITS =3D=3D 32 @@ -2548,6 +2558,16 @@ void tcg_gen_umax_i64(TCGv_i64 ret, TCGv_i64 a, TCGv= _i64 b) tcg_gen_movcond_i64(TCG_COND_LTU, ret, a, b, b, a); } =20 +void tcg_gen_abs_i64(TCGv_i64 ret, TCGv_i64 a) +{ + TCGv_i64 t =3D tcg_temp_new_i64(); + + tcg_gen_sari_i64(t, a, 63); + tcg_gen_xor_i64(ret, a, t); + tcg_gen_sub_i64(ret, ret, t); + tcg_temp_free_i64(t); +} + /* Size changing operations. */ =20 void tcg_gen_extrl_i64_i32(TCGv_i32 ret, TCGv_i64 arg) --=20 2.17.1 From nobody Fri Apr 19 16:27:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; 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X-Received-From: 2607:f8b0:4864:20::433 Subject: [Qemu-devel] [PULL 21/31] tcg: Add support for vector absolute value X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linux.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- accel/tcg/tcg-runtime.h | 5 +++ tcg/aarch64/tcg-target.h | 1 + tcg/i386/tcg-target.h | 1 + tcg/tcg-op-gvec.h | 2 ++ tcg/tcg-opc.h | 1 + tcg/tcg.h | 1 + accel/tcg/tcg-runtime-gvec.c | 48 +++++++++++++++++++++++++++ tcg/tcg-op-gvec.c | 63 ++++++++++++++++++++++++++++++++++++ tcg/tcg-op-vec.c | 39 ++++++++++++++++++++++ tcg/tcg.c | 2 ++ tcg/README | 4 +++ 11 files changed, 167 insertions(+) diff --git a/accel/tcg/tcg-runtime.h b/accel/tcg/tcg-runtime.h index ed3ce5fd91..6d73dc2d65 100644 --- a/accel/tcg/tcg-runtime.h +++ b/accel/tcg/tcg-runtime.h @@ -225,6 +225,11 @@ DEF_HELPER_FLAGS_3(gvec_neg16, TCG_CALL_NO_RWG, void, = ptr, ptr, i32) DEF_HELPER_FLAGS_3(gvec_neg32, TCG_CALL_NO_RWG, void, ptr, ptr, i32) DEF_HELPER_FLAGS_3(gvec_neg64, TCG_CALL_NO_RWG, void, ptr, ptr, i32) =20 +DEF_HELPER_FLAGS_3(gvec_abs8, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(gvec_abs16, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(gvec_abs32, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(gvec_abs64, TCG_CALL_NO_RWG, void, ptr, ptr, i32) + DEF_HELPER_FLAGS_3(gvec_not, TCG_CALL_NO_RWG, void, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_and, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_or, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index f5640a229b..21d06d928c 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -132,6 +132,7 @@ typedef enum { #define TCG_TARGET_HAS_orc_vec 1 #define TCG_TARGET_HAS_not_vec 1 #define TCG_TARGET_HAS_neg_vec 1 +#define TCG_TARGET_HAS_abs_vec 0 #define TCG_TARGET_HAS_shi_vec 1 #define TCG_TARGET_HAS_shs_vec 0 #define TCG_TARGET_HAS_shv_vec 1 diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 618aa520d2..7445f05885 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -182,6 +182,7 @@ extern bool have_avx2; #define TCG_TARGET_HAS_orc_vec 0 #define TCG_TARGET_HAS_not_vec 0 #define TCG_TARGET_HAS_neg_vec 0 +#define TCG_TARGET_HAS_abs_vec 0 #define TCG_TARGET_HAS_shi_vec 1 #define TCG_TARGET_HAS_shs_vec 1 #define TCG_TARGET_HAS_shv_vec have_avx2 diff --git a/tcg/tcg-op-gvec.h b/tcg/tcg-op-gvec.h index 6ee98f3378..52a398c190 100644 --- a/tcg/tcg-op-gvec.h +++ b/tcg/tcg-op-gvec.h @@ -228,6 +228,8 @@ void tcg_gen_gvec_not(unsigned vece, uint32_t dofs, uin= t32_t aofs, uint32_t oprsz, uint32_t maxsz); void tcg_gen_gvec_neg(unsigned vece, uint32_t dofs, uint32_t aofs, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_abs(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t oprsz, uint32_t maxsz); =20 void tcg_gen_gvec_add(unsigned vece, uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t oprsz, uint32_t maxsz); diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h index 4bf71f261f..4a2dd116eb 100644 --- a/tcg/tcg-opc.h +++ b/tcg/tcg-opc.h @@ -225,6 +225,7 @@ DEF(add_vec, 1, 2, 0, IMPLVEC) DEF(sub_vec, 1, 2, 0, IMPLVEC) DEF(mul_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_mul_vec)) DEF(neg_vec, 1, 1, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_neg_vec)) +DEF(abs_vec, 1, 1, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_abs_vec)) DEF(ssadd_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_sat_vec)) DEF(usadd_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_sat_vec)) DEF(sssub_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_sat_vec)) diff --git a/tcg/tcg.h b/tcg/tcg.h index 2c7315da25..0e01a70d66 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -176,6 +176,7 @@ typedef uint64_t TCGRegSet; && !defined(TCG_TARGET_HAS_v128) \ && !defined(TCG_TARGET_HAS_v256) #define TCG_TARGET_MAYBE_vec 0 +#define TCG_TARGET_HAS_abs_vec 0 #define TCG_TARGET_HAS_neg_vec 0 #define TCG_TARGET_HAS_not_vec 0 #define TCG_TARGET_HAS_andc_vec 0 diff --git a/accel/tcg/tcg-runtime-gvec.c b/accel/tcg/tcg-runtime-gvec.c index 2152fb6903..0f09e0ef38 100644 --- a/accel/tcg/tcg-runtime-gvec.c +++ b/accel/tcg/tcg-runtime-gvec.c @@ -398,6 +398,54 @@ void HELPER(gvec_neg64)(void *d, void *a, uint32_t des= c) clear_high(d, oprsz, desc); } =20 +void HELPER(gvec_abs8)(void *d, void *a, uint32_t desc) +{ + intptr_t oprsz =3D simd_oprsz(desc); + intptr_t i; + + for (i =3D 0; i < oprsz; i +=3D sizeof(int8_t)) { + int8_t aa =3D *(int8_t *)(a + i); + *(int8_t *)(d + i) =3D aa < 0 ? -aa : aa; + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_abs16)(void *d, void *a, uint32_t desc) +{ + intptr_t oprsz =3D simd_oprsz(desc); + intptr_t i; + + for (i =3D 0; i < oprsz; i +=3D sizeof(int16_t)) { + int16_t aa =3D *(int16_t *)(a + i); + *(int16_t *)(d + i) =3D aa < 0 ? -aa : aa; + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_abs32)(void *d, void *a, uint32_t desc) +{ + intptr_t oprsz =3D simd_oprsz(desc); + intptr_t i; + + for (i =3D 0; i < oprsz; i +=3D sizeof(int32_t)) { + int32_t aa =3D *(int32_t *)(a + i); + *(int32_t *)(d + i) =3D aa < 0 ? -aa : aa; + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_abs64)(void *d, void *a, uint32_t desc) +{ + intptr_t oprsz =3D simd_oprsz(desc); + intptr_t i; + + for (i =3D 0; i < oprsz; i +=3D sizeof(int64_t)) { + int64_t aa =3D *(int64_t *)(a + i); + *(int64_t *)(d + i) =3D aa < 0 ? -aa : aa; + } + clear_high(d, oprsz, desc); +} + void HELPER(gvec_mov)(void *d, void *a, uint32_t desc) { intptr_t oprsz =3D simd_oprsz(desc); diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c index c69c7960b8..338ddd9d9e 100644 --- a/tcg/tcg-op-gvec.c +++ b/tcg/tcg-op-gvec.c @@ -2177,6 +2177,69 @@ void tcg_gen_gvec_neg(unsigned vece, uint32_t dofs, = uint32_t aofs, tcg_gen_gvec_2(dofs, aofs, oprsz, maxsz, &g[vece]); } =20 +static void gen_absv_mask(TCGv_i64 d, TCGv_i64 b, unsigned vece) +{ + TCGv_i64 t =3D tcg_temp_new_i64(); + int nbit =3D 8 << vece; + + /* Create -1 for each negative element. */ + tcg_gen_shri_i64(t, b, nbit - 1); + tcg_gen_andi_i64(t, t, dup_const(vece, 1)); + tcg_gen_muli_i64(t, t, (1 << nbit) - 1); + + /* + * Invert (via xor -1) and add one (via sub -1). + * Because of the ordering the msb is cleared, + * so we never have carry into the next element. + */ + tcg_gen_xor_i64(d, b, t); + tcg_gen_sub_i64(d, d, t); + + tcg_temp_free_i64(t); +} + +static void tcg_gen_vec_abs8_i64(TCGv_i64 d, TCGv_i64 b) +{ + gen_absv_mask(d, b, MO_8); +} + +static void tcg_gen_vec_abs16_i64(TCGv_i64 d, TCGv_i64 b) +{ + gen_absv_mask(d, b, MO_16); +} + +void tcg_gen_gvec_abs(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t oprsz, uint32_t maxsz) +{ + static const TCGOpcode vecop_list[] =3D { INDEX_op_abs_vec, 0 }; + static const GVecGen2 g[4] =3D { + { .fni8 =3D tcg_gen_vec_abs8_i64, + .fniv =3D tcg_gen_abs_vec, + .fno =3D gen_helper_gvec_abs8, + .opt_opc =3D vecop_list, + .vece =3D MO_8 }, + { .fni8 =3D tcg_gen_vec_abs16_i64, + .fniv =3D tcg_gen_abs_vec, + .fno =3D gen_helper_gvec_abs16, + .opt_opc =3D vecop_list, + .vece =3D MO_16 }, + { .fni4 =3D tcg_gen_abs_i32, + .fniv =3D tcg_gen_abs_vec, + .fno =3D gen_helper_gvec_abs32, + .opt_opc =3D vecop_list, + .vece =3D MO_32 }, + { .fni8 =3D tcg_gen_abs_i64, + .fniv =3D tcg_gen_abs_vec, + .fno =3D gen_helper_gvec_abs64, + .opt_opc =3D vecop_list, + .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .vece =3D MO_64 }, + }; + + tcg_debug_assert(vece <=3D MO_64); + tcg_gen_gvec_2(dofs, aofs, oprsz, maxsz, &g[vece]); +} + void tcg_gen_gvec_and(unsigned vece, uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t oprsz, uint32_t maxsz) { diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c index 16062f5995..543508d545 100644 --- a/tcg/tcg-op-vec.c +++ b/tcg/tcg-op-vec.c @@ -110,6 +110,14 @@ bool tcg_can_emit_vecop_list(const TCGOpcode *list, continue; } break; + case INDEX_op_abs_vec: + if (tcg_can_emit_vec_op(INDEX_op_sub_vec, type, vece) + && (tcg_can_emit_vec_op(INDEX_op_smax_vec, type, vece) > 0 + || tcg_can_emit_vec_op(INDEX_op_sari_vec, type, vece) = > 0 + || tcg_can_emit_vec_op(INDEX_op_cmp_vec, type, vece)))= { + continue; + } + break; default: break; } @@ -429,6 +437,37 @@ void tcg_gen_neg_vec(unsigned vece, TCGv_vec r, TCGv_v= ec a) tcg_swap_vecop_list(hold_list); } =20 +void tcg_gen_abs_vec(unsigned vece, TCGv_vec r, TCGv_vec a) +{ + const TCGOpcode *hold_list; + + tcg_assert_listed_vecop(INDEX_op_abs_vec); + hold_list =3D tcg_swap_vecop_list(NULL); + + if (!do_op2(vece, r, a, INDEX_op_abs_vec)) { + TCGType type =3D tcgv_vec_temp(r)->base_type; + TCGv_vec t =3D tcg_temp_new_vec(type); + + tcg_debug_assert(tcg_can_emit_vec_op(INDEX_op_sub_vec, type, vece)= ); + if (tcg_can_emit_vec_op(INDEX_op_smax_vec, type, vece) > 0) { + tcg_gen_neg_vec(vece, t, a); + tcg_gen_smax_vec(vece, r, a, t); + } else { + if (tcg_can_emit_vec_op(INDEX_op_sari_vec, type, vece) > 0) { + tcg_gen_sari_vec(vece, t, a, (8 << vece) - 1); + } else { + do_dupi_vec(t, MO_REG, 0); + tcg_gen_cmp_vec(TCG_COND_LT, vece, t, a, t); + } + tcg_gen_xor_vec(vece, r, a, t); + tcg_gen_sub_vec(vece, r, r, t); + } + + tcg_temp_free_vec(t); + } + tcg_swap_vecop_list(hold_list); +} + static void do_shifti(TCGOpcode opc, unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i) { diff --git a/tcg/tcg.c b/tcg/tcg.c index 3b80feb344..24083b8c00 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1616,6 +1616,8 @@ bool tcg_op_supported(TCGOpcode op) return have_vec && TCG_TARGET_HAS_not_vec; case INDEX_op_neg_vec: return have_vec && TCG_TARGET_HAS_neg_vec; + case INDEX_op_abs_vec: + return have_vec && TCG_TARGET_HAS_abs_vec; case INDEX_op_andc_vec: return have_vec && TCG_TARGET_HAS_andc_vec; case INDEX_op_orc_vec: diff --git a/tcg/README b/tcg/README index c30e5418a6..cbdfd3b6bc 100644 --- a/tcg/README +++ b/tcg/README @@ -561,6 +561,10 @@ E.g. VECL=3D1 -> 64 << 1 -> v128, and VECE=3D2 -> 1 <<= 2 -> i32. =20 Similarly, v0 =3D -v1. =20 +* abs_vec v0, v1 + + Similarly, v0 =3D v1 < 0 ? -v1 : v1, in elements across the vector. + * smin_vec: * umin_vec: =20 --=20 2.17.1 From nobody Fri Apr 19 16:27:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1557793097; cv=none; d=zoho.com; s=zohoarc; b=I/1/QMKiFh0WZGc6KhqBmoULzkoL14wnDMyPQyGq1f2nKZTAcwyMU9xU+2SygXngskbIWbjb53N1ECR3pnsE9r4IddKIL8MkoT1fLm9b36M49bdJGSDQm32ETfhSJ1jnY1oUdLow7ijwehIo56GDSXIOnC+J/T7ZzCVyH5YXI2E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1557793097; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=4RamRVLS6CpSQqwq41FPx2oK0CgrkzF+uLuaNa5g2S4=; b=UpZnVqMB1sdIj2oKgRQYe9/rX/KQZbQr2l6WuGQo6VSEnNQX+oklE+pGzY/r25VifOZOFY0BKSlV5T2NmrUfBJz37JJvH68inxD+wUgX3+EmWhDG2pYQGwy91LI6vdQH1Sk0sXZWPOvttd+boCPxF7yofnzKDmXVnzrg4vebnCs= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 155779309757228.621972190160363; Mon, 13 May 2019 17:18:17 -0700 (PDT) Received: from localhost ([127.0.0.1]:36739 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hQL8z-0003Jy-GR for importer@patchew.org; Mon, 13 May 2019 20:18:09 -0400 Received: from eggs.gnu.org ([209.51.188.92]:55539) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hQL0C-0002ws-KY for qemu-devel@nongnu.org; Mon, 13 May 2019 20:09:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hQKxX-0003j0-VJ for qemu-devel@nongnu.org; Mon, 13 May 2019 20:08:58 -0400 Received: from mail-pl1-x62b.google.com ([2607:f8b0:4864:20::62b]:42240) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hQKxS-0003cm-1u for qemu-devel@nongnu.org; Mon, 13 May 2019 20:06:15 -0400 Received: by mail-pl1-x62b.google.com with SMTP id x15so7260079pln.9 for ; Mon, 13 May 2019 17:06:13 -0700 (PDT) Received: from localhost.localdomain (97-113-13-231.tukw.qwest.net. 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X-Received-From: 2607:f8b0:4864:20::62b Subject: [Qemu-devel] [PULL 22/31] tcg/i386: Support vector absolute value X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linux.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.h | 2 +- tcg/i386/tcg-target.inc.c | 15 +++++++++++++++ 2 files changed, 16 insertions(+), 1 deletion(-) diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 7445f05885..66f16fbe3c 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -182,7 +182,7 @@ extern bool have_avx2; #define TCG_TARGET_HAS_orc_vec 0 #define TCG_TARGET_HAS_not_vec 0 #define TCG_TARGET_HAS_neg_vec 0 -#define TCG_TARGET_HAS_abs_vec 0 +#define TCG_TARGET_HAS_abs_vec 1 #define TCG_TARGET_HAS_shi_vec 1 #define TCG_TARGET_HAS_shs_vec 1 #define TCG_TARGET_HAS_shv_vec have_avx2 diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index 0ba1587da4..aafd01cb49 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -369,6 +369,9 @@ static inline int tcg_target_const_match(tcg_target_lon= g val, TCGType type, #define OPC_MOVSLQ (0x63 | P_REXW) #define OPC_MOVZBL (0xb6 | P_EXT) #define OPC_MOVZWL (0xb7 | P_EXT) +#define OPC_PABSB (0x1c | P_EXT38 | P_DATA16) +#define OPC_PABSW (0x1d | P_EXT38 | P_DATA16) +#define OPC_PABSD (0x1e | P_EXT38 | P_DATA16) #define OPC_PACKSSDW (0x6b | P_EXT | P_DATA16) #define OPC_PACKSSWB (0x63 | P_EXT | P_DATA16) #define OPC_PACKUSDW (0x2b | P_EXT38 | P_DATA16) @@ -2741,6 +2744,10 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, static int const sars_insn[4] =3D { OPC_UD2, OPC_PSRAW, OPC_PSRAD, OPC_UD2 }; + static int const abs_insn[4] =3D { + /* TODO: AVX512 adds support for MO_64. */ + OPC_PABSB, OPC_PABSW, OPC_PABSD, OPC_UD2 + }; =20 TCGType type =3D vecl + TCG_TYPE_V64; int insn, sub; @@ -2829,6 +2836,11 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, insn =3D OPC_PUNPCKLDQ; goto gen_simd; #endif + case INDEX_op_abs_vec: + insn =3D abs_insn[vece]; + a2 =3D a1; + a1 =3D 0; + goto gen_simd; gen_simd: tcg_debug_assert(insn !=3D OPC_UD2); if (type =3D=3D TCG_TYPE_V256) { @@ -3206,6 +3218,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) case INDEX_op_dup2_vec: #endif return &x_x_x; + case INDEX_op_abs_vec: case INDEX_op_dup_vec: case INDEX_op_shli_vec: case INDEX_op_shri_vec: @@ -3283,6 +3296,8 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, = unsigned vece) case INDEX_op_umin_vec: case INDEX_op_umax_vec: return vece <=3D MO_32 ? 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X-Received-From: 2607:f8b0:4864:20::42e Subject: [Qemu-devel] [PULL 23/31] tcg/aarch64: Support vector absolute value X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linux.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.h | 2 +- tcg/aarch64/tcg-target.inc.c | 6 ++++++ 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index 21d06d928c..e43554c3c7 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -132,7 +132,7 @@ typedef enum { #define TCG_TARGET_HAS_orc_vec 1 #define TCG_TARGET_HAS_not_vec 1 #define TCG_TARGET_HAS_neg_vec 1 -#define TCG_TARGET_HAS_abs_vec 0 +#define TCG_TARGET_HAS_abs_vec 1 #define TCG_TARGET_HAS_shi_vec 1 #define TCG_TARGET_HAS_shs_vec 0 #define TCG_TARGET_HAS_shv_vec 1 diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c index df123c07f1..1248dfd04c 100644 --- a/tcg/aarch64/tcg-target.inc.c +++ b/tcg/aarch64/tcg-target.inc.c @@ -552,6 +552,7 @@ typedef enum { I3617_CMGE0 =3D 0x2e208800, I3617_CMLE0 =3D 0x2e20a800, I3617_NOT =3D 0x2e205800, + I3617_ABS =3D 0x0e20b800, I3617_NEG =3D 0x2e20b800, =20 /* System instructions. */ @@ -2208,6 +2209,9 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode o= pc, case INDEX_op_neg_vec: tcg_out_insn(s, 3617, NEG, is_q, vece, a0, a1); break; + case INDEX_op_abs_vec: + tcg_out_insn(s, 3617, ABS, is_q, vece, a0, a1); + break; case INDEX_op_and_vec: tcg_out_insn(s, 3616, AND, is_q, 0, a0, a1, a2); break; @@ -2319,6 +2323,7 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, = unsigned vece) case INDEX_op_andc_vec: case INDEX_op_orc_vec: case INDEX_op_neg_vec: + case INDEX_op_abs_vec: case INDEX_op_not_vec: case INDEX_op_cmp_vec: case INDEX_op_shli_vec: @@ -2562,6 +2567,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) return &w_w_w; case INDEX_op_not_vec: case INDEX_op_neg_vec: + case INDEX_op_abs_vec: case INDEX_op_shli_vec: case INDEX_op_shri_vec: case INDEX_op_sari_vec: --=20 2.17.1 From nobody Fri Apr 19 16:27:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; 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X-Received-From: 2607:f8b0:4864:20::533 Subject: [Qemu-devel] [PULL 24/31] target/arm: Use tcg_gen_abs_i64 and tcg_gen_gvec_abs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linux.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- target/arm/helper.h | 2 -- target/arm/neon_helper.c | 5 ----- target/arm/translate-a64.c | 41 +++++--------------------------------- target/arm/translate.c | 11 +++------- 4 files changed, 8 insertions(+), 51 deletions(-) diff --git a/target/arm/helper.h b/target/arm/helper.h index 50cb036378..132aa1682e 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -352,8 +352,6 @@ DEF_HELPER_2(neon_ceq_u8, i32, i32, i32) DEF_HELPER_2(neon_ceq_u16, i32, i32, i32) DEF_HELPER_2(neon_ceq_u32, i32, i32, i32) =20 -DEF_HELPER_1(neon_abs_s8, i32, i32) -DEF_HELPER_1(neon_abs_s16, i32, i32) DEF_HELPER_1(neon_clz_u8, i32, i32) DEF_HELPER_1(neon_clz_u16, i32, i32) DEF_HELPER_1(neon_cls_s8, i32, i32) diff --git a/target/arm/neon_helper.c b/target/arm/neon_helper.c index ed1c6fc41c..4259056723 100644 --- a/target/arm/neon_helper.c +++ b/target/arm/neon_helper.c @@ -1228,11 +1228,6 @@ NEON_VOP(ceq_u16, neon_u16, 2) NEON_VOP(ceq_u32, neon_u32, 1) #undef NEON_FN =20 -#define NEON_FN(dest, src, dummy) dest =3D (src < 0) ? -src : src -NEON_VOP1(abs_s8, neon_s8, 4) -NEON_VOP1(abs_s16, neon_s16, 2) -#undef NEON_FN - /* Count Leading Sign/Zero Bits. */ static inline int do_clz8(uint8_t x) { diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 9dcc5ff3a3..b7c5a928b4 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -9468,11 +9468,7 @@ static void handle_2misc_64(DisasContext *s, int opc= ode, bool u, if (u) { tcg_gen_neg_i64(tcg_rd, tcg_rn); } else { - TCGv_i64 tcg_zero =3D tcg_const_i64(0); - tcg_gen_neg_i64(tcg_rd, tcg_rn); - tcg_gen_movcond_i64(TCG_COND_GT, tcg_rd, tcg_rn, tcg_zero, - tcg_rn, tcg_rd); - tcg_temp_free_i64(tcg_zero); + tcg_gen_abs_i64(tcg_rd, tcg_rn); } break; case 0x2f: /* FABS */ @@ -12366,11 +12362,12 @@ static void disas_simd_two_reg_misc(DisasContext = *s, uint32_t insn) } break; case 0xb: - if (u) { /* NEG */ + if (u) { /* ABS, NEG */ gen_gvec_fn2(s, is_q, rd, rn, tcg_gen_gvec_neg, size); - return; + } else { + gen_gvec_fn2(s, is_q, rd, rn, tcg_gen_gvec_abs, size); } - break; + return; } =20 if (size =3D=3D 3) { @@ -12438,17 +12435,6 @@ static void disas_simd_two_reg_misc(DisasContext *= s, uint32_t insn) gen_helper_neon_qabs_s32(tcg_res, cpu_env, tcg_op); } break; - case 0xb: /* ABS, NEG */ - if (u) { - tcg_gen_neg_i32(tcg_res, tcg_op); - } else { - TCGv_i32 tcg_zero =3D tcg_const_i32(0); - tcg_gen_neg_i32(tcg_res, tcg_op); - tcg_gen_movcond_i32(TCG_COND_GT, tcg_res, tcg_op, - tcg_zero, tcg_op, tcg_res); - tcg_temp_free_i32(tcg_zero); - } - break; case 0x2f: /* FABS */ gen_helper_vfp_abss(tcg_res, tcg_op); break; @@ -12561,23 +12547,6 @@ static void disas_simd_two_reg_misc(DisasContext *= s, uint32_t insn) tcg_temp_free_i32(tcg_zero); break; } - case 0xb: /* ABS, NEG */ - if (u) { - TCGv_i32 tcg_zero =3D tcg_const_i32(0); - if (size) { - gen_helper_neon_sub_u16(tcg_res, tcg_zero, tcg= _op); - } else { - gen_helper_neon_sub_u8(tcg_res, tcg_zero, tcg_= op); - } - tcg_temp_free_i32(tcg_zero); - } else { - if (size) { - gen_helper_neon_abs_s16(tcg_res, tcg_op); - } else { - gen_helper_neon_abs_s8(tcg_res, tcg_op); - } - } - break; case 0x4: /* CLS, CLZ */ if (u) { if (size =3D=3D 0) { diff --git a/target/arm/translate.c b/target/arm/translate.c index b25781554f..dd053c80d6 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8120,6 +8120,9 @@ static int disas_neon_data_insn(DisasContext *s, uint= 32_t insn) case NEON_2RM_VNEG: tcg_gen_gvec_neg(size, rd_ofs, rm_ofs, vec_size, vec_s= ize); break; + case NEON_2RM_VABS: + tcg_gen_gvec_abs(size, rd_ofs, rm_ofs, vec_size, vec_s= ize); + break; =20 default: elementwise: @@ -8225,14 +8228,6 @@ static int disas_neon_data_insn(DisasContext *s, uin= t32_t insn) } tcg_temp_free_i32(tmp2); break; - case NEON_2RM_VABS: - switch(size) { - case 0: gen_helper_neon_abs_s8(tmp, tmp); brea= k; - case 1: gen_helper_neon_abs_s16(tmp, tmp); bre= ak; - case 2: tcg_gen_abs_i32(tmp, tmp); break; - default: abort(); - } - break; case NEON_2RM_VCGT0_F: { TCGv_ptr fpstatus =3D get_fpstatus_ptr(1); --=20 2.17.1 From nobody Fri Apr 19 16:27:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[97.113.13.231]) by smtp.gmail.com with ESMTPSA id u3sm238151pfn.29.2019.05.13.17.06.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 13 May 2019 17:06:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=YokYl3JyovfmDfQXuf+lxigUFluEl1v9bGn/sssho6E=; b=eakOqkHpFvRoos90HDt/mJSzWzOkf6TeNWGb6U+t7AYbYhpBGpznvBLcJllDjgWgo4 suqLrP6NRLM6WluiwQBpsRh4JQ+B6iHUBtucBnS9PtIJxOQsUTfDeAHbELsqEykvH66j QFoY2K9olf0LgpvLArkkoyVvKmUOXQtESfDmYtX1oCCuPInvXe6wga92DBCr8SmFVfqx CLaq4jEDt4LeZUoZndpgyCkGh/h/nqYcTHCuHqH/UAVJ9j8DpmmiITwgfOyRS7otBuyr 1rZNLDS6tGCZfZnzZ9+i81Pt9O4skgYFYykfk3Y4Jo/l8EcRVvLolb/H9x4NbEA2z67y yKBQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=YokYl3JyovfmDfQXuf+lxigUFluEl1v9bGn/sssho6E=; b=X0VVEusuDrieKCrGbiLIxHv19cG8lQ+AbuWRvugHs+fCSAKPvbME4MYZDGr+l3/X2Y Ma4DoMN+gYCtyAHdE4jnk3pg5+J9MWzOJVf+MM++H8wh8M9dqojg2cHNmOtYwXLqRaq0 Zxq7/9cUGCHTC/8KOtGVzFDnwuYT+d60ZktxXbzq60xsDBt0tWP4pnVs9+w9nWpNhqGZ NqO1oKdrc9wnKIjTetJVQgRtUAniTJeVY+N4Bp5n8sP9kVEkv5UCSooI3EE79MNfijw/ YCJ3RAs5h3GA9EKaswWJVNyJa/gQ4qwplHxngu1eDGhXBXOjzv6iQhuxvqEvyi6uDsHR j7UQ== X-Gm-Message-State: APjAAAXJkRtrwh+e93LqLBA5lAaNirsREt6s8w2gGV9l2FSWI3U3ke4V k56sMu34QlM5TGyhTRq7YtA4fMvGjrw= X-Google-Smtp-Source: APXvYqziIRn8Vfim1I3ObfdUdgFfe+nhT+6KP6TCJJ5i6cu9EQFrjcz59aN92fdfPRsYUPdipakmQg== X-Received: by 2002:a63:a84c:: with SMTP id i12mr35515549pgp.115.1557792375444; Mon, 13 May 2019 17:06:15 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 13 May 2019 17:05:34 -0700 Message-Id: <20190514000540.4313-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190514000540.4313-1-richard.henderson@linaro.org> References: <20190514000540.4313-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 Subject: [Qemu-devel] [PULL 25/31] target/cris: Use tcg_gen_abs_tl X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linux.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: David Hildenbrand Signed-off-by: Richard Henderson --- target/cris/translate.c | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/target/cris/translate.c b/target/cris/translate.c index b005a5c20e..31b40a57f9 100644 --- a/target/cris/translate.c +++ b/target/cris/translate.c @@ -1686,18 +1686,11 @@ static int dec_cmp_r(CPUCRISState *env, DisasContex= t *dc) =20 static int dec_abs_r(CPUCRISState *env, DisasContext *dc) { - TCGv t0; - LOG_DIS("abs $r%u, $r%u\n", dc->op1, dc->op2); cris_cc_mask(dc, CC_MASK_NZ); =20 - t0 =3D tcg_temp_new(); - tcg_gen_sari_tl(t0, cpu_R[dc->op1], 31); - tcg_gen_xor_tl(cpu_R[dc->op2], cpu_R[dc->op1], t0); - tcg_gen_sub_tl(cpu_R[dc->op2], cpu_R[dc->op2], t0); - tcg_temp_free(t0); - + tcg_gen_abs_tl(cpu_R[dc->op2], cpu_R[dc->op1]); cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op2], 4); return 2; --=20 2.17.1 From nobody Fri Apr 19 16:27:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1557806410; cv=none; d=zoho.com; s=zohoarc; b=F1p/GC9fobPmTyoS3jYb4F7IX8TSzbM9hnb1JfIIytVxHRi8p4Ei05dcSDHw2TAm6kyiqRSbzvXkV0fwbhrhaFba9CXkaPAoqY7cKe9B9HkCoTEeMxz5FxvfT36kAIFZW3VbMYiHO40x/gpWndMAYqkSWAe4hOsiH/i4Q5vjGwY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1557806410; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=FH8HIUisgKxx/wO5rpgn7QNUU9WJqnDYvJ4xHC9+spw=; b=KJTir+85wFZ9xU3H5iH82b8cSnJuF6rsy6xsnUznV8Kr2RxgAQYaRlY33Veh8DO2ZQq5ETfuZvm0n6OeQgOQmtUfU0uXQkjyOLuN4eASlFgPg545lmGyfjGuNs9Q+OKEBaiRJ1O3Cb15T4vOkFURV4MvF1j2zqhGfRtdDb8yklM= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1557806410809146.41468591388127; Mon, 13 May 2019 21:00:10 -0700 (PDT) Received: from localhost ([127.0.0.1]:38630 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hQObk-0002nt-E5 for importer@patchew.org; Tue, 14 May 2019 00:00:04 -0400 Received: from eggs.gnu.org ([209.51.188.92]:36751) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hQOar-0002W6-SB for qemu-devel@nongnu.org; Mon, 13 May 2019 23:59:10 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hQOaq-0003f8-Qu for qemu-devel@nongnu.org; Mon, 13 May 2019 23:59:09 -0400 Received: from mail-pg1-x52e.google.com ([2607:f8b0:4864:20::52e]:38009) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hQKxg-0003hH-0C for qemu-devel@nongnu.org; Mon, 13 May 2019 20:06:28 -0400 Received: by mail-pg1-x52e.google.com with SMTP id j26so7598243pgl.5 for ; Mon, 13 May 2019 17:06:17 -0700 (PDT) Received: from localhost.localdomain (97-113-13-231.tukw.qwest.net. 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X-Received-From: 2607:f8b0:4864:20::52e Subject: [Qemu-devel] [PULL 26/31] target/ppc: Use tcg_gen_abs_i32 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linux.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20190423102145.14812-2-f4bug@amsat.org> Signed-off-by: Richard Henderson --- target/ppc/translate/spe-impl.inc.c | 14 +------------- 1 file changed, 1 insertion(+), 13 deletions(-) diff --git a/target/ppc/translate/spe-impl.inc.c b/target/ppc/translate/spe= -impl.inc.c index 7ab0a29b5f..36b4d5654d 100644 --- a/target/ppc/translate/spe-impl.inc.c +++ b/target/ppc/translate/spe-impl.inc.c @@ -126,19 +126,7 @@ static inline void gen_##name(DisasContext *ctx) = \ tcg_temp_free_i32(t0); = \ } =20 -static inline void gen_op_evabs(TCGv_i32 ret, TCGv_i32 arg1) -{ - TCGLabel *l1 =3D gen_new_label(); - TCGLabel *l2 =3D gen_new_label(); - - tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1); - tcg_gen_neg_i32(ret, arg1); - tcg_gen_br(l2); - gen_set_label(l1); - tcg_gen_mov_i32(ret, arg1); - gen_set_label(l2); -} -GEN_SPEOP_ARITH1(evabs, gen_op_evabs); +GEN_SPEOP_ARITH1(evabs, tcg_gen_abs_i32); GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32); GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32); GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32); --=20 2.17.1 From nobody Fri Apr 19 16:27:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1557792907; cv=none; d=zoho.com; s=zohoarc; b=RAtCfvXnfPTo9/WyInhExCegNGmVJR5Ah+HBebZllY0iF83P694ymRtU0HTYLtlQQ+3r0H7xcRTPGR2Z3WfxhHwdi8VapsIJerLTPFD+6MG0fvvv0io+CqtzzP/6T3h1fYpIraQzh+bzB235gUUuUlFEiOi6IP10/3qIqUuyUVs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1557792907; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=sLhzMGGDR1ZhuOEjkMPl9rWAydAxNvaV/cqSFAgz/Lc=; b=HWvdIQjR/IJSoNzkJ5EEqAfoj9UiwimTMYGffeDT0LdqIxxQOoW4CRoYkscLjhIvNep3+YkelmqihPHFAMe54iMvdXZXzYsx8mAl0LDI634nQyF0y6XzWAWfc5v4xJSk5GdDrXwUtj2D2vqqYIiveoWubZo4voVeLPmcsqWGZK8= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1557792907681779.2392847525712; Mon, 13 May 2019 17:15:07 -0700 (PDT) Received: from localhost ([127.0.0.1]:36683 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hQL5x-0000YM-O1 for importer@patchew.org; Mon, 13 May 2019 20:15:01 -0400 Received: from eggs.gnu.org ([209.51.188.92]:56181) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hQL0V-0003A9-Ui for qemu-devel@nongnu.org; Mon, 13 May 2019 20:09:58 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hQKxd-0003pb-VA for qemu-devel@nongnu.org; Mon, 13 May 2019 20:09:20 -0400 Received: from mail-pl1-x62e.google.com ([2607:f8b0:4864:20::62e]:45082) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hQKxb-0003hs-Nu for qemu-devel@nongnu.org; Mon, 13 May 2019 20:06:24 -0400 Received: by mail-pl1-x62e.google.com with SMTP id a5so7254778pls.12 for ; Mon, 13 May 2019 17:06:19 -0700 (PDT) Received: from localhost.localdomain (97-113-13-231.tukw.qwest.net. [97.113.13.231]) by smtp.gmail.com with ESMTPSA id u3sm238151pfn.29.2019.05.13.17.06.16 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 13 May 2019 17:06:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=sLhzMGGDR1ZhuOEjkMPl9rWAydAxNvaV/cqSFAgz/Lc=; b=mWeOPVw8BrPnhBNWTkiLQ4QHDd/KJRJ5qCgIfVsi37jD5J5U3vuE79UEXwyZ6T+CoW RxJ1sBLV/1y02v+Nlq3RHjRBGGFPL8Y6Nx1RBLx+pOQG2tZacXwdspI9M1ghCNFN6dsM 5DD8hswVfPbLjVdUW5b6YDs2hu5vDWEhYyG7GP65FKh3nryHl1VaVRc571zk8Ok+ljbB a+M3Q8tBHsUOGpSDg0Xf4AVYjdR1bL89vScHyxvLL5exxNb9EbBmU1qbH4cbfuG1qbYx kqDw1q+T5FoUnxdGuqtlY/0jYtVYrU6ApV8hlgNF2i7+Dnz1q0W4zwz/659P9bF0nVi2 Pdcw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=sLhzMGGDR1ZhuOEjkMPl9rWAydAxNvaV/cqSFAgz/Lc=; b=mhWF3yw8hEihGNYKMRTaeW1wrlvcZ9oqffYI1O/LBXjGU3SZnJ3tgkd62OucXKcD3G sRIVFyQaqnpTknv29L6KXuWvuDzUA0vPX1Q6Z1352WwxtnJVbnonq8eFYNkwb+Iz3LzC ufhcSw12J6Pzv0sFnqegv+clWWldbbNAMnYptblFoCtCSIEOQtEvqZJhHqLiPW7E3uwk jZj6WxsyUbswoMhI+K7UJpfsbjcSB0NaDVesPNBWYwARGEcS776oZ+1fuHVg65ttmt59 MVUuN20gAJdQKIGNWMgDVpUHuZVpdE6SUZwCUNMWKd87KmQN+zDpQS7FF6G+zpACDK42 EBGg== X-Gm-Message-State: APjAAAVvhq8Tqv95a6M8XRVUz2jwIl+UuHNhSOgMnJoND5Jori6dUra5 pWMTgzafzxb6Y1T+lAFj2jEcR6B0vpY= X-Google-Smtp-Source: APXvYqzjdt0flkZOcTz+my76vGdwIgoxiVAOgpFdVQjyQHvwcPv31f+5TxRjJRzMO4VMQl3J/wWvZw== X-Received: by 2002:a17:902:a405:: with SMTP id p5mr29556378plq.51.1557792377818; Mon, 13 May 2019 17:06:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 13 May 2019 17:05:36 -0700 Message-Id: <20190514000540.4313-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190514000540.4313-1-richard.henderson@linaro.org> References: <20190514000540.4313-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::62e Subject: [Qemu-devel] [PULL 27/31] target/ppc: Use tcg_gen_abs_tl X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linux.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/ppc/translate.c | 68 +++++++++++++++--------------------------- 1 file changed, 24 insertions(+), 44 deletions(-) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 8d08625c33..b5217f632f 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -5075,40 +5075,26 @@ static void gen_ecowx(DisasContext *ctx) /* abs - abs. */ static void gen_abs(DisasContext *ctx) { - TCGLabel *l1 =3D gen_new_label(); - TCGLabel *l2 =3D gen_new_label(); - tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1); - tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); - tcg_gen_br(l2); - gen_set_label(l1); - tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); - gen_set_label(l2); + TCGv d =3D cpu_gpr[rD(ctx->opcode)]; + TCGv a =3D cpu_gpr[rA(ctx->opcode)]; + + tcg_gen_abs_tl(d, a); if (unlikely(Rc(ctx->opcode) !=3D 0)) { - gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); + gen_set_Rc0(ctx, d); } } =20 /* abso - abso. */ static void gen_abso(DisasContext *ctx) { - TCGLabel *l1 =3D gen_new_label(); - TCGLabel *l2 =3D gen_new_label(); - TCGLabel *l3 =3D gen_new_label(); - /* Start with XER OV disabled, the most likely case */ - tcg_gen_movi_tl(cpu_ov, 0); - tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2); - tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, = l1); - tcg_gen_movi_tl(cpu_ov, 1); - tcg_gen_movi_tl(cpu_so, 1); - tcg_gen_br(l2); - gen_set_label(l1); - tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); - tcg_gen_br(l3); - gen_set_label(l2); - tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); - gen_set_label(l3); + TCGv d =3D cpu_gpr[rD(ctx->opcode)]; + TCGv a =3D cpu_gpr[rA(ctx->opcode)]; + + tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_ov, a, 0x80000000); + tcg_gen_abs_tl(d, a); + tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); if (unlikely(Rc(ctx->opcode) !=3D 0)) { - gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); + gen_set_Rc0(ctx, d); } } =20 @@ -5344,34 +5330,28 @@ static void gen_mulo(DisasContext *ctx) /* nabs - nabs. */ static void gen_nabs(DisasContext *ctx) { - TCGLabel *l1 =3D gen_new_label(); - TCGLabel *l2 =3D gen_new_label(); - tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1); - tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); - tcg_gen_br(l2); - gen_set_label(l1); - tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); - gen_set_label(l2); + TCGv d =3D cpu_gpr[rD(ctx->opcode)]; + TCGv a =3D cpu_gpr[rA(ctx->opcode)]; + + tcg_gen_abs_tl(d, a); + tcg_gen_neg_tl(d, d); if (unlikely(Rc(ctx->opcode) !=3D 0)) { - gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); + gen_set_Rc0(ctx, d); } } =20 /* nabso - nabso. */ static void gen_nabso(DisasContext *ctx) { - TCGLabel *l1 =3D gen_new_label(); - TCGLabel *l2 =3D gen_new_label(); - tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1); - tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); - tcg_gen_br(l2); - gen_set_label(l1); - tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); - gen_set_label(l2); + TCGv d =3D cpu_gpr[rD(ctx->opcode)]; + TCGv a =3D cpu_gpr[rA(ctx->opcode)]; + + tcg_gen_abs_tl(d, a); + tcg_gen_neg_tl(d, d); /* nabs never overflows */ tcg_gen_movi_tl(cpu_ov, 0); if (unlikely(Rc(ctx->opcode) !=3D 0)) { - gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); + gen_set_Rc0(ctx, d); } } =20 --=20 2.17.1 From nobody Fri Apr 19 16:27:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[97.113.13.231]) by smtp.gmail.com with ESMTPSA id u3sm238151pfn.29.2019.05.13.17.06.17 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 13 May 2019 17:06:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ceuwSjt3kxNVh2jVmVheMvD/TRbf+fHQnKrqah+IplI=; b=YM3lIN7ecRVVN96Zqwn3iTt3ZilJW4YCEcNw5L5LEGAKSF5X+pauae51nAl5dcRL8E BjwMplzL5TxfrmjPO5jP15Zx23/Dja9ESWt5syivIbsNp9q6BipXveJAkLNmyWEgpfYZ 4+3x9R72QAhSaNZgmUTnofXdkw+YPCnVSQ/tsjWbegNCHWJrgi9BC3TtfYG5DLoXrnjD i8V6HKagriz2SjyW8tx4Wql41bez/4I8hCBKQz/1SX/hvckrK7ffhoZBFbxqg61hRf/Q ehD1ZUQq/YTMgoYCR/00gxPSpFK9pdl7sxdrrXafCJFqJycW3U898CjUxO0mE2XnhBut Sz8Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ceuwSjt3kxNVh2jVmVheMvD/TRbf+fHQnKrqah+IplI=; b=mk2Nsa2Y91dC21LjLDKL8gMPC6hotPhkI3/wh0SIt+HHReuKYsL4XdquPQjlP/xXtC O/Jgim1Lbu0kEi5AHL+UIRtXhFsghDp7bmYbYQRtTyiIXkKqwpauLglVnM4OEZF7o+qA 3VmZK6XoWKIl1bYZezV6VaoJ5HTeFTF+WzzzJVG66RSEHxctZPjgGNcse/tMRrF63IXy g9vMmpiAyEWT9IQyXHxPdoOs0WDiAxIyWPA2fBW+gHtM2quf2zL+umkNDePU9vvAi55o +X/ZnbbjIuYiI+n+lMaQKIHaaMgo/a4RNCEEtLv1QLHAmTtbO5ROf0HrjpJNcyB5oxIH Tehw== X-Gm-Message-State: APjAAAWwvSQjP6HcAn6lN/cqfuirDFjrQvuBVU5lAefZrNYHTHQ6wVJS O5bS0XfUWHEtQ5whZEFwkfq9M+hTSkk= X-Google-Smtp-Source: APXvYqxwyA2VgIdG3t+IEyO3fyrwwSCFxhpJPX7G73pAcqF216VCMDK0WlYlCtNv9fjCFzdFBhdnFw== X-Received: by 2002:a63:7c55:: with SMTP id l21mr10588783pgn.121.1557792378991; Mon, 13 May 2019 17:06:18 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 13 May 2019 17:05:37 -0700 Message-Id: <20190514000540.4313-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190514000540.4313-1-richard.henderson@linaro.org> References: <20190514000540.4313-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::544 Subject: [Qemu-devel] [PULL 28/31] target/s390x: Use tcg_gen_abs_i64 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linux.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: David Hildenbrand Signed-off-by: Richard Henderson --- target/s390x/translate.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/target/s390x/translate.c b/target/s390x/translate.c index d4951836ad..e8e8a79b7d 100644 --- a/target/s390x/translate.c +++ b/target/s390x/translate.c @@ -1407,13 +1407,7 @@ static DisasJumpType help_branch(DisasContext *s, Di= sasCompare *c, =20 static DisasJumpType op_abs(DisasContext *s, DisasOps *o) { - TCGv_i64 z, n; - z =3D tcg_const_i64(0); - n =3D tcg_temp_new_i64(); - tcg_gen_neg_i64(n, o->in2); - tcg_gen_movcond_i64(TCG_COND_LT, o->out, o->in2, z, n, o->in2); - tcg_temp_free_i64(n); - tcg_temp_free_i64(z); + tcg_gen_abs_i64(o->out, o->in2); return DISAS_NEXT; } =20 --=20 2.17.1 From nobody Fri Apr 19 16:27:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1557792766; cv=none; d=zoho.com; s=zohoarc; b=ELtyjQLjeo3dbvucT8Zz4A3F7LskKWvZkUAC4SIdcAbIOdyou4i+w4Kikyd3pzpFikIWj2dP0Jn5b8VXi5WzMzoRxvpaNNjxC01ti2VG3G/vQAtnsc5Dl1Uxr5CKPaRGhvH21+2RcNhZmDK+pJN9p+rpWtZcXFq/zhG0oajw20U= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1557792766; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=NPRvgVGg8Y/3Ni/kBR6Hw8ovXKBKiDD4+leXLS3F/ik=; b=VrNP2C0HGKzPRz6SbyRPVWhpRUJegHSS4y2YT20QIHZl6YrldXkkyUWHSFLLoTkoO7VzpVsvxFjrHlkNKJKzYHTd1GFHMyvdhDoh4GUAOrrR4UTNZR3vP+gpjCAXOOLtGEYpfkm9NnXX6vhF7YL01C2rwWyWqkPew5lLrQtfpI4= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1557792766327510.44457271130705; Mon, 13 May 2019 17:12:46 -0700 (PDT) Received: from localhost ([127.0.0.1]:36664 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hQL3j-0005qz-7y for importer@patchew.org; Mon, 13 May 2019 20:12:43 -0400 Received: from eggs.gnu.org ([209.51.188.92]:53358) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hQKzB-00025X-K6 for qemu-devel@nongnu.org; Mon, 13 May 2019 20:08:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hQKxg-0003sY-5l for qemu-devel@nongnu.org; Mon, 13 May 2019 20:08:01 -0400 Received: from mail-pf1-x42a.google.com ([2607:f8b0:4864:20::42a]:41105) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hQKxd-0003jf-UX for qemu-devel@nongnu.org; Mon, 13 May 2019 20:06:27 -0400 Received: by mail-pf1-x42a.google.com with SMTP id l132so8057206pfc.8 for ; Mon, 13 May 2019 17:06:21 -0700 (PDT) Received: from localhost.localdomain (97-113-13-231.tukw.qwest.net. [97.113.13.231]) by smtp.gmail.com with ESMTPSA id u3sm238151pfn.29.2019.05.13.17.06.19 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 13 May 2019 17:06:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=NPRvgVGg8Y/3Ni/kBR6Hw8ovXKBKiDD4+leXLS3F/ik=; b=JteRtTLDNIM8JHMEuRdmyIaBMSBrjp3H1hDPFGeoMKXyzyrYDTdqNt7o9GpCY0Rsz5 jC4wgCkZjwyHRInK0fyz5DT+mSwxrVNv+WVWIyHcrzE1iKYImaHEUY4rbV6TIm+LTLyu nFOHwwbEKubcPUkujDc1g0m4ZW6RwlS02TyI2ldPs/SgR5T8O/OLd1Eao6mWGp06cPCH TIq5SkhXfNUNamtaqws8e7DMA+DTBVM1NDupSCWJlw+7/ntdVFuF/VWWiCcGgbVlu+co Ooiswa0KnCNPb2bWOZuuKTzccnw/oEAz1HYc2Y/XY6xvMhy5bZZSnQ2sV2rZJwq6djMi q12w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NPRvgVGg8Y/3Ni/kBR6Hw8ovXKBKiDD4+leXLS3F/ik=; b=latT8BI/vM2ctSUpiyKsHpFVuPzPp5Om+4TBHVtTGhcihprPwF/0Npro4ATwtqZVlE 6MnHR936KBsAECD39JNk1IUUXx94hV+SkokFWjcb8Iuot/NpI85WgWsD2l0cl6cYPnk5 SGMCp09VjL7hmrGvraEFNTlpXQ45aTy10cVNr2vmRSFMGUkm4+UL5JH/ZVbm8jCg8p5X z/gxyjELlQDMpHeV3fU/QTYsBfmlyxX9+RIJeiBEjywKJUYm3/VOK6zxaw0ZPdxDwY+y ewhkp9CytZk2FMpRjdnmwUXGcF+BFra7xNbSIH7A3cOR8e5ls249Qp2yc27Y5xysWagR m2gw== X-Gm-Message-State: APjAAAX6lBhnMYeqKolUu6DT7Y0UedeX+7uF7sumGnTMdtY3+yz8HZS2 H8leAUvkxGk+MJhtSCKId1xcr6BUUOo= X-Google-Smtp-Source: APXvYqzHv+6a6a8mTJ7a45JMOAU+PT2jrdlIsftYUpt9mh+26H41yeM6kQT3EcvxRdKy7IdmA6rztA== X-Received: by 2002:a62:5801:: with SMTP id m1mr495543pfb.32.1557792380158; Mon, 13 May 2019 17:06:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 13 May 2019 17:05:38 -0700 Message-Id: <20190514000540.4313-30-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190514000540.4313-1-richard.henderson@linaro.org> References: <20190514000540.4313-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::42a Subject: [Qemu-devel] [PULL 29/31] target/tricore: Use tcg_gen_abs_tl X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linux.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Bastian Koppelmann Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20190423102145.14812-3-f4bug@amsat.org> Signed-off-by: Richard Henderson --- target/tricore/translate.c | 27 +++++---------------------- 1 file changed, 5 insertions(+), 22 deletions(-) diff --git a/target/tricore/translate.c b/target/tricore/translate.c index 8f6416144e..06c4485e55 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -2415,11 +2415,7 @@ gen_msubadr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3= , uint32_t n, uint32_t mode) =20 static inline void gen_abs(TCGv ret, TCGv r1) { - TCGv temp =3D tcg_temp_new(); - TCGv t0 =3D tcg_const_i32(0); - - tcg_gen_neg_tl(temp, r1); - tcg_gen_movcond_tl(TCG_COND_GE, ret, r1, t0, r1, temp); + tcg_gen_abs_tl(ret, r1); /* overflow can only happen, if r1 =3D 0x80000000 */ tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, r1, 0x80000000); tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); @@ -2430,9 +2426,6 @@ static inline void gen_abs(TCGv ret, TCGv r1) tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV); /* calc SAV bit */ tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); - - tcg_temp_free(temp); - tcg_temp_free(t0); } =20 static inline void gen_absdif(TCGv ret, TCGv r1, TCGv r2) @@ -6617,13 +6610,8 @@ static void decode_rr_divide(CPUTriCoreState *env, D= isasContext *ctx) tcg_gen_movi_tl(cpu_PSW_AV, 0); if (!tricore_feature(env, TRICORE_FEATURE_131)) { /* overflow =3D (abs(D[r3+1]) >=3D abs(D[r2])) */ - tcg_gen_neg_tl(temp, temp3); - /* use cpu_PSW_AV to compare against 0 */ - tcg_gen_movcond_tl(TCG_COND_LT, temp, temp3, cpu_PSW_AV, - temp, temp3); - tcg_gen_neg_tl(temp2, cpu_gpr_d[r2]); - tcg_gen_movcond_tl(TCG_COND_LT, temp2, cpu_gpr_d[r2], cpu_PSW_= AV, - temp2, cpu_gpr_d[r2]); + tcg_gen_abs_tl(temp, temp3); + tcg_gen_abs_tl(temp2, cpu_gpr_d[r2]); tcg_gen_setcond_tl(TCG_COND_GE, cpu_PSW_V, temp, temp2); } else { /* overflow =3D (D[b] =3D=3D 0) */ @@ -6655,13 +6643,8 @@ static void decode_rr_divide(CPUTriCoreState *env, D= isasContext *ctx) tcg_gen_movi_tl(cpu_PSW_AV, 0); if (!tricore_feature(env, TRICORE_FEATURE_131)) { /* overflow =3D (abs(D[r3+1]) >=3D abs(D[r2])) */ - tcg_gen_neg_tl(temp, temp3); - /* use cpu_PSW_AV to compare against 0 */ - tcg_gen_movcond_tl(TCG_COND_LT, temp, temp3, cpu_PSW_AV, - temp, temp3); - tcg_gen_neg_tl(temp2, cpu_gpr_d[r2]); - tcg_gen_movcond_tl(TCG_COND_LT, temp2, cpu_gpr_d[r2], cpu_PSW_= AV, - temp2, cpu_gpr_d[r2]); + tcg_gen_abs_tl(temp, temp3); + tcg_gen_abs_tl(temp2, cpu_gpr_d[r2]); tcg_gen_setcond_tl(TCG_COND_GE, cpu_PSW_V, temp, temp2); } else { /* overflow =3D (D[b] =3D=3D 0) */ --=20 2.17.1 From nobody Fri Apr 19 16:27:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[97.113.13.231]) by smtp.gmail.com with ESMTPSA id u3sm238151pfn.29.2019.05.13.17.06.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 13 May 2019 17:06:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=noj71OX2nBmtjQYQqqpKzc/I+BY/kKSngSA5N+1PwXo=; b=jtcz28yA526udG4B48oNCqm7yEW54j8bRtwkhwSvWd4tkdYt5//ZF4sPwNhEzdSD0F ClPCon1esoPYq5sw65/d5kjS0fL4HG7iH61x7bW5UnG4+hZ+DTNisXutkBE/uWrO6IRp 5InJx9aVIvvDePzPpjjzcIvUg1BberPxpW5X40e6RmdQKOlLOTpTi+CIYaaXL0ZE523C XHXXIwgub9LdFrExuTd+N6OfyUziQTYS37cAdlUdH0oyMtqs+XL28ZlKNJ4Uj6HS9xFF CiB1tTRqbLC8eHq2Hwe+OHhWxOYqtlYncPjqWASORNdZLvHAA4bgAEmJ8m9y+AkcRwWp PuAw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=noj71OX2nBmtjQYQqqpKzc/I+BY/kKSngSA5N+1PwXo=; b=FB9VysfiXTVv73I+ZejP3NnDSb3wK8zzspuusZIYMm89EGdc3Ietlbc3zWnP5IvukB yWxibT5ywFC3HKQvUT/FM3O7Lqq+dBN7KtLU2yUYVoRrlCkYvehTMOZlVjmp0jTNhewR Fi1Q3dxNdAGw6gbdY6FsgLET/P5WKpf4CntL9ugUEtLBAq8PLcv436FSHhnZF5GIFKzg 5AlkXeNtuq5yM0Q2eG37Y03lR3s4ScVOSybDFqwi4CHqPT5SaoPO2ZluF1w84AzxI06Q eY1FhEXdT2LxUcspYGfSlSG6+u2fcuXdaTPYaegkJ4DFyqNWUzadD/kGX0Ts6XL0SGyJ sV1A== X-Gm-Message-State: APjAAAW9rRHSSZQvJaNv0c88HazbyZsfk0FY93jucHZTYcRPwBFTEO/B kvMMh8biyTHsLaYw4iEwCKhGFvFIIoA= X-Google-Smtp-Source: APXvYqxkffx8y4YWWZhr+m8Fv5rObCSnQYSj+/CiU50YCd0YlGoRlBFC1WGrknena8v8XHa3S5CtoA== X-Received: by 2002:a17:902:868c:: with SMTP id g12mr17201396plo.323.1557792381317; Mon, 13 May 2019 17:06:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 13 May 2019 17:05:39 -0700 Message-Id: <20190514000540.4313-31-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190514000540.4313-1-richard.henderson@linaro.org> References: <20190514000540.4313-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::644 Subject: [Qemu-devel] [PULL 30/31] target/xtensa: Use tcg_gen_abs_i32 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linux.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Acked-by: Max Filippov Signed-off-by: Richard Henderson --- target/xtensa/translate.c | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index 301c8e3161..b063fa85f2 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -1709,14 +1709,7 @@ void restore_state_to_opc(CPUXtensaState *env, Trans= lationBlock *tb, static void translate_abs(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - TCGv_i32 zero =3D tcg_const_i32(0); - TCGv_i32 neg =3D tcg_temp_new_i32(); - - tcg_gen_neg_i32(neg, arg[1].in); - tcg_gen_movcond_i32(TCG_COND_GE, arg[0].out, - arg[1].in, zero, arg[1].in, neg); - tcg_temp_free(neg); - tcg_temp_free(zero); + tcg_gen_abs_i32(arg[0].out, arg[1].in); } =20 static void translate_add(DisasContext *dc, const OpcodeArg arg[], --=20 2.17.1 From nobody Fri Apr 19 16:27:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1557792810; cv=none; d=zoho.com; s=zohoarc; b=Kmgq9xaruUXOGzOFGXShUyEnu93uPvwDIHLMsyexpU6AMqvBwC15BQClGbw98pHwMDPLKlfZRv3T5p80FAcgFQScVqu9x9EUp3zdsrGUJ2KFMEB4ay0uUdaFqVd7BKi5kXCErzgT+v3UTWki2TLZA6gVVsUQi0GMLLSgZUxlO5I= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1557792810; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=1kgfuF1MVun7P1d0mNatwqAFUCrmFPWnRVb1dwFf54w=; b=jqpQSHQWj8TA9AWYJ/1lGp0lPbyDN4FV/ew21wps1BE65q/pWL41NLQQO4s8kPLTfhH8xGq6bY01lQWzGUsMoTpknNb5fv0lUMnow0bf2jFd8GKiAk93ou+qyuOQud4F6Qy52NoGjC2insOQE7GdoQrInMUT3iXKnkDVnkQ4dqE= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1557792810040468.7472845728705; Mon, 13 May 2019 17:13:30 -0700 (PDT) Received: from localhost ([127.0.0.1]:36666 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hQL4O-0006Lm-Ua for importer@patchew.org; Mon, 13 May 2019 20:13:25 -0400 Received: from eggs.gnu.org ([209.51.188.92]:52473) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hQKyp-0001pI-FA for qemu-devel@nongnu.org; Mon, 13 May 2019 20:09:47 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hQKxg-0003s9-65 for qemu-devel@nongnu.org; Mon, 13 May 2019 20:07:31 -0400 Received: from mail-pf1-x433.google.com ([2607:f8b0:4864:20::433]:35783) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hQKxd-0003lk-UZ for qemu-devel@nongnu.org; Mon, 13 May 2019 20:06:27 -0400 Received: by mail-pf1-x433.google.com with SMTP id t87so8077720pfa.2 for ; Mon, 13 May 2019 17:06:23 -0700 (PDT) Received: from localhost.localdomain (97-113-13-231.tukw.qwest.net. [97.113.13.231]) by smtp.gmail.com with ESMTPSA id u3sm238151pfn.29.2019.05.13.17.06.21 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 13 May 2019 17:06:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=1kgfuF1MVun7P1d0mNatwqAFUCrmFPWnRVb1dwFf54w=; b=CNs0bde5VHPTPuHdyT+g0uPXyOQVWb/md047xu6VtaJrB1MEpkLQb9pFDedkQpKvgT HAx5OUCQF8d5avFy6SjnVSyF6yUlNDcZKeqTaxGCVDQjNP+EIFBVUTlxqijTLEiKimVR iLiPo3QWo9cad0mhwMCbwtYM0f4LLWQr1R/80vXKURUm0GO7j3Xc8GnF9leyiarDJkG7 hSzgCkiAfDVf5rSR9kNtqIJtNwQ6Z+2Wbfc/3FQDTsz7fQzlEZHxnGbLj2KD6nbtzAXt sCq/bdfcJ+7tra0yM4Zzf9rjPF2UKl7BzmX9turuqwEsSw+gWTcUefGb932Uh+rCFcTv vj+A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=1kgfuF1MVun7P1d0mNatwqAFUCrmFPWnRVb1dwFf54w=; b=A6aXkmQZVxaiKMTQOrdpVj4eSG5GGU0nB2qZzJvhe3yYgAe0Z3GeGughAGqiuLXLg7 lP68nCF19BMzOPne+NQY5Au2ell3JdPNEfdYKQcfBu4HBm7yekX5tl8HlCAYR6rz63tW tUhnlCgQFJlPkUSN7FRIER37ykDlJ0Uvd1SG7D2y25QeJFjbSQ1KKofh4A7JbjPqTsTQ K4KpCC6H3gcKQWg2NF2BL32RXGwz9nsS6TbbGxIbijhtozVhvUnXmm9uKcL99gsBj1Wc auYVy4REFfGDc0XsRg0DibTCjXYLH6jr69yqfwqDygXujq2Wr09ZJ/FyYA6LS99Lk4Bn 8A9w== X-Gm-Message-State: APjAAAUmXEDAhpq4qIdF1GhBGnC4BQJ6fxd1DE+LtT3AvSBNYBQ9uUwa QyKlaWgCgLhBW+e3/ijjqlylA9+verY= X-Google-Smtp-Source: APXvYqwv0l1e7tiu3eE0I1xoJdaY3G+U7DWY1QrkmTdlWQxufDYZI7UFLdq7NoY3HU/6ANwFICgWhw== X-Received: by 2002:a63:754b:: with SMTP id f11mr35176034pgn.32.1557792382497; Mon, 13 May 2019 17:06:22 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 13 May 2019 17:05:40 -0700 Message-Id: <20190514000540.4313-32-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190514000540.4313-1-richard.henderson@linaro.org> References: <20190514000540.4313-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::433 Subject: [Qemu-devel] [PULL 31/31] tcg/aarch64: Do not advertise minmax for MO_64 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linux.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The min/max instructions are not available for 64-bit elements. Fixes: 93f332a50371 Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.inc.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c index 1248dfd04c..40bf35079a 100644 --- a/tcg/aarch64/tcg-target.inc.c +++ b/tcg/aarch64/tcg-target.inc.c @@ -2333,16 +2333,16 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type= , unsigned vece) case INDEX_op_sssub_vec: case INDEX_op_usadd_vec: case INDEX_op_ussub_vec: - case INDEX_op_smax_vec: - case INDEX_op_smin_vec: - case INDEX_op_umax_vec: - case INDEX_op_umin_vec: case INDEX_op_shlv_vec: return 1; case INDEX_op_shrv_vec: case INDEX_op_sarv_vec: return -1; case INDEX_op_mul_vec: + case INDEX_op_smax_vec: + case INDEX_op_smin_vec: + case INDEX_op_umax_vec: + case INDEX_op_umin_vec: return vece < MO_64; =20 default: --=20 2.17.1