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[97.113.13.231]) by smtp.gmail.com with ESMTPSA id 19sm5920517pgz.24.2019.05.10.08.19.46 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 10 May 2019 08:19:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=7ZAIu4sKS6YB4WebUUhTxA56tE0hF5se6ULN034aZNQ=; b=WzX5/Kg3wXGGAAVo4Q5/PLRYl3vm580BE/g9KL3k/ouTDQOpiKB6T9XBcmZeFCy/1X WcLldaII9Gyjk1PcYLTKMKKSKZTe8+1xo0gaxyobfTrF2fLDI7xalsVOLeJEP2ewcaYA n/CYwb2ltPliqWgFePK4/Cr5u4CHXaMe2B79eRMfkBIz5ZBsOdgmfKxCmQ5ofrB8QG9t n+C3LYTzZLwv9Ku96lJ13FT0VGp2IR+CYTudPQxrJ2YFw5pEP0IBzLgzzk/iwRzDY2+h LX581NsUX1zvQUyL5S1EXb0LD1kFBwEGFk+eyXZWH7M4pFPcYdaXurt4y+1Ti0iK2NG3 O0pw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7ZAIu4sKS6YB4WebUUhTxA56tE0hF5se6ULN034aZNQ=; b=fHfQxcNYUdyNdu5we/GtcVYoMuQpa8BMO4xSj16TAWpUV1anqBq3kMwLDBo6cSjTbI UWxa4OU5fMiOqNmjjbSrK9mndiaECojWn2hzzolKLYSVQQCKrJd6371BN8tGI0rYAWOM 7hPWgBOMin6JVB1Zv5U/JYhky3js09OP9M9Tj3obulnmFBGUSTJj75CplSQuDlanlyJK 8xBDpWAjFNc4RDNIIpwt1G49pC5OO66PfjBiw5T3kGwq1c2MXPcfMoGWPi7+LRXh1Qua 0xen6+cSbZShSycUPG57KygE4QyzzAaKctOHuhFQzs6W1G9UfFu3ubYEChlGHHEMMMmq WtSQ== X-Gm-Message-State: APjAAAVd0jWLzi5Alx3kdccVj+oyz2fw2YXKD0iF/6QPzspORuUi93Wk XlhMzHsDWgvQvHyGh1phxc/Oic+YHnY= X-Google-Smtp-Source: APXvYqzlyhy5QN67Ew0xUp9Kk/YdZKdPyyvDDLWOAwaCuTSUuq3kJY/rCilVhfCjfz8eHcMT/LHNrA== X-Received: by 2002:a62:2703:: with SMTP id n3mr14915651pfn.199.1557501587657; Fri, 10 May 2019 08:19:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 10 May 2019 08:19:18 -0700 Message-Id: <20190510151944.22981-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190510151944.22981-1-richard.henderson@linaro.org> References: <20190510151944.22981-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::42b Subject: [Qemu-devel] [PULL 01/27] tcg: Add CPUClass::tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) This hook will replace the (user-only mode specific) handle_mmu_fault hook, and the (system mode specific) tlb_fill function. The handle_mmu_fault hook was written as if there was a valid way to recover from an mmu fault, and had 3 possible return states. In reality, the only valid action is to raise an exception, return to the main loop, and deliver the SIGSEGV to the guest. Note that all of the current implementations of handle_mmu_fault for guests which support linux-user do in fact only ever return 1, which is the signal to return to the main loop. Using the hook for system mode requires that all targets be converted, so for now the hook is (optionally) used only from user-only mode. Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- include/qom/cpu.h | 9 +++++++++ accel/tcg/user-exec.c | 39 ++++++++++++++------------------------- 2 files changed, 23 insertions(+), 25 deletions(-) diff --git a/include/qom/cpu.h b/include/qom/cpu.h index 08abcbd3fe..c1f267b4e0 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -118,6 +118,12 @@ struct TranslationBlock; * will need to do more. If this hook is not implemented then the * default is to call @set_pc(tb->pc). * @handle_mmu_fault: Callback for handling an MMU fault. + * @tlb_fill: Callback for handling a softmmu tlb miss or user-only + * address fault. For system mode, if the access is valid, call + * tlb_set_page and return true; if the access is invalid, and + * probe is true, return false; otherwise raise an exception and + * do not return. For user-only mode, always raise an exception + * and do not return. * @get_phys_page_debug: Callback for obtaining a physical address. * @get_phys_page_attrs_debug: Callback for obtaining a physical address a= nd the * associated memory transaction attributes to use for the access. @@ -191,6 +197,9 @@ typedef struct CPUClass { void (*synchronize_from_tb)(CPUState *cpu, struct TranslationBlock *tb= ); int (*handle_mmu_fault)(CPUState *cpu, vaddr address, int size, int rw, int mmu_index); + bool (*tlb_fill)(CPUState *cpu, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr); hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr, MemTxAttrs *attrs); diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 0789984fe6..199f88c826 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -65,6 +65,7 @@ static inline int handle_cpu_signal(uintptr_t pc, siginfo= _t *info, CPUClass *cc; int ret; unsigned long address =3D (unsigned long)info->si_addr; + MMUAccessType access_type; =20 /* We must handle PC addresses from two different sources: * a call return address and a signal frame address. @@ -147,35 +148,23 @@ static inline int handle_cpu_signal(uintptr_t pc, sig= info_t *info, are still valid segv ones */ address =3D h2g_nocheck(address); =20 - cc =3D CPU_GET_CLASS(cpu); - /* see if it is an MMU fault */ - g_assert(cc->handle_mmu_fault); - ret =3D cc->handle_mmu_fault(cpu, address, 0, is_write, MMU_USER_IDX); - - if (ret =3D=3D 0) { - /* The MMU fault was handled without causing real CPU fault. - * Retain helper_retaddr for a possible second fault. - */ - return 1; - } - - /* All other paths lead to cpu_exit; clear helper_retaddr - * for next execution. + /* + * There is no way the target can handle this other than raising + * an exception. Undo signal and retaddr state prior to longjmp. */ + sigprocmask(SIG_SETMASK, old_set, NULL); helper_retaddr =3D 0; =20 - if (ret < 0) { - return 0; /* not an MMU fault */ + cc =3D CPU_GET_CLASS(cpu); + if (cc->tlb_fill) { + access_type =3D is_write ? MMU_DATA_STORE : MMU_DATA_LOAD; + cc->tlb_fill(cpu, address, 0, access_type, MMU_USER_IDX, false, pc= ); + g_assert_not_reached(); + } else { + ret =3D cc->handle_mmu_fault(cpu, address, 0, is_write, MMU_USER_I= DX); + g_assert(ret > 0); + cpu_loop_exit_restore(cpu, pc); } - - /* Now we have a real cpu fault. */ - cpu_restore_state(cpu, pc, true); - - sigprocmask(SIG_SETMASK, old_set, NULL); - cpu_loop_exit(cpu); - - /* never comes here */ - return 1; } =20 #if defined(__i386__) --=20 2.17.1 From nobody Tue Apr 30 04:47:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1557501726; cv=none; d=zoho.com; s=zohoarc; b=I+0uD8CB88Z6nS62xY4oilfGxJFkFKTPVzUW7shKMV5BIFsYDHbfMqOpRXREQs4BKITz2VtM8C8FbxE1ftCTQQwapkFyoNfUbKwrYJISftB6xFxSLgIL7BvhJGWhyuIeyME1/2XFa+crPQV99Hxfjm7k92IVmKNv/+W85W8ZKbo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1557501726; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=FfWuCh2mm65OwVmLvUKciMMvVsrbj00IXvSAZ0jgt/k=; b=Wf62Z+OZDLuhSZOMCJ+LZl9Y72NfJu74ICw8DpTkW4tWAXeXK2SC+KXhjvFr1UW8fVfuo3Xi163vxegePSQms7HXZCWJeWvkuIvxAVy5pdzzFGKq6A8cofP7zu5mlkn39puEcWzJ2vg95sp90UT0MHnCXXjsqp35r4XDtMEN1os= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1557501726492464.5084331565423; Fri, 10 May 2019 08:22:06 -0700 (PDT) Received: from localhost ([127.0.0.1]:44999 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hP7LX-0000NG-CO for importer@patchew.org; Fri, 10 May 2019 11:22:03 -0400 Received: from eggs.gnu.org ([209.51.188.92]:55935) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hP7JP-0007Ok-I7 for qemu-devel@nongnu.org; Fri, 10 May 2019 11:19:52 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hP7JO-0008Dc-DJ for qemu-devel@nongnu.org; Fri, 10 May 2019 11:19:51 -0400 Received: from mail-pf1-x442.google.com ([2607:f8b0:4864:20::442]:39794) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hP7JO-0008Cz-6t for qemu-devel@nongnu.org; Fri, 10 May 2019 11:19:50 -0400 Received: by mail-pf1-x442.google.com with SMTP id z26so3404116pfg.6 for ; Fri, 10 May 2019 08:19:50 -0700 (PDT) Received: from localhost.localdomain (97-113-13-231.tukw.qwest.net. [97.113.13.231]) by smtp.gmail.com with ESMTPSA id 19sm5920517pgz.24.2019.05.10.08.19.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 10 May 2019 08:19:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=FfWuCh2mm65OwVmLvUKciMMvVsrbj00IXvSAZ0jgt/k=; b=mJxTkwtnFtTM8f1S3KTzL1i+xwO9CxFOhV+gQYZsGyu5pneF2S8rat/EXgfRkIRjmx S89IClaCSzCpTKnXlfRiQZkA/1GNnNjnXvps7cFbWyKRmHMFdT36k/y7IVrxcwBD5wto zWlPMkX01Ph+D6LkZgl6k6B6VizLggnub7HilUZu2sm7amDQ7Ux8VYzWiS8sIG94B1bS +QJ0DwG/yQG/s+D0p6MINqek7KGk8VGOrjj74ish+aWACLsWqTW9Gt7triFC3sSHEB3w 6137ZfTJ1YeluBcoqJB3bMZzUo4RKY/nJhfxnK5/nL5SMJ3mjr/tEwBAMh8x7BYlgKLE piuQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=FfWuCh2mm65OwVmLvUKciMMvVsrbj00IXvSAZ0jgt/k=; b=UFghDdVr71WY2cm7F9Gb0W57nKVf1O+CR0HZhhLhDFHv1BK08+BkiZyuO1EGFj8o68 S6OsPz572evzgorcq9um0RhD3zfw4ct+DvQaH+DQm5613BF8aKpQOwFYktsX0F4HKf1d OQw/dlpsCIcol99iuQ4xt+m5/GDZ+YAR1erleAPJnSpq83+OAlRFIglB3nkO6parNcoJ ezuBEyW1oU2DakJMwZlFpy50NUmhAVK3o3viWFyzsyKFU/EmzK6rdiOkxwlE6JsOizDn FGgcsf11wHfPSuLF29VMUcUIQ0iGrQhLTWvg97/InoOIe/S5zIofvTDd5NzuJGG0/2TJ fh2Q== X-Gm-Message-State: APjAAAU+0S5sofKNFxlLU9xzQsoa+mIbieXDgPcGKhn+mTfP1fPH+xcc +MeOX9BiOBBrKlDvCcBm6ewP43EDn6k= X-Google-Smtp-Source: APXvYqyCN7fniTFLhkQ7SJSXIk/FQ6odBkYzRYI1Bq5rUImuaIyNe5mIlLBcYJ9XNbaOR78vF86ZnA== X-Received: by 2002:aa7:9a99:: with SMTP id w25mr14683056pfi.249.1557501588824; Fri, 10 May 2019 08:19:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 10 May 2019 08:19:19 -0700 Message-Id: <20190510151944.22981-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190510151944.22981-1-richard.henderson@linaro.org> References: <20190510151944.22981-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PULL 02/27] target/alpha: Convert to CPUClass::tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/alpha/cpu.h | 5 +++-- target/alpha/cpu.c | 5 ++--- target/alpha/helper.c | 30 +++++++++++++++++++++--------- target/alpha/mem_helper.c | 16 ---------------- 4 files changed, 26 insertions(+), 30 deletions(-) diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index 63bf3618ff..cf09112b6a 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -475,8 +475,9 @@ void alpha_cpu_list(void); is returned if the signal was handled by the virtual CPU. */ int cpu_alpha_signal_handler(int host_signum, void *pinfo, void *puc); -int alpha_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int= rw, - int mmu_idx); +bool alpha_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); void QEMU_NORETURN dynamic_excp(CPUAlphaState *, uintptr_t, int, int); void QEMU_NORETURN arith_excp(CPUAlphaState *, uintptr_t, int, uint64_t); =20 diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index ad3588a44a..7c81be4111 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -225,9 +225,8 @@ static void alpha_cpu_class_init(ObjectClass *oc, void = *data) cc->set_pc =3D alpha_cpu_set_pc; cc->gdb_read_register =3D alpha_cpu_gdb_read_register; cc->gdb_write_register =3D alpha_cpu_gdb_write_register; -#ifdef CONFIG_USER_ONLY - cc->handle_mmu_fault =3D alpha_cpu_handle_mmu_fault; -#else + cc->tlb_fill =3D alpha_cpu_tlb_fill; +#ifndef CONFIG_USER_ONLY cc->do_transaction_failed =3D alpha_cpu_do_transaction_failed; cc->do_unaligned_access =3D alpha_cpu_do_unaligned_access; cc->get_phys_page_debug =3D alpha_cpu_get_phys_page_debug; diff --git a/target/alpha/helper.c b/target/alpha/helper.c index 7201576aae..929a217455 100644 --- a/target/alpha/helper.c +++ b/target/alpha/helper.c @@ -104,14 +104,15 @@ void cpu_alpha_store_gr(CPUAlphaState *env, unsigned = reg, uint64_t val) } =20 #if defined(CONFIG_USER_ONLY) -int alpha_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, - int rw, int mmu_idx) +bool alpha_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) { AlphaCPU *cpu =3D ALPHA_CPU(cs); =20 cs->exception_index =3D EXCP_MMFAULT; cpu->env.trap_arg0 =3D address; - return 1; + cpu_loop_exit_restore(cs, retaddr); } #else /* Returns the OSF/1 entMM failure indication, or -1 on success. */ @@ -248,26 +249,37 @@ hwaddr alpha_cpu_get_phys_page_debug(CPUState *cs, va= ddr addr) return (fail >=3D 0 ? -1 : phys); } =20 -int alpha_cpu_handle_mmu_fault(CPUState *cs, vaddr addr, int size, int rw, - int mmu_idx) +bool alpha_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) { AlphaCPU *cpu =3D ALPHA_CPU(cs); CPUAlphaState *env =3D &cpu->env; target_ulong phys; int prot, fail; =20 - fail =3D get_physical_address(env, addr, 1 << rw, mmu_idx, &phys, &pro= t); + fail =3D get_physical_address(env, addr, 1 << access_type, + mmu_idx, &phys, &prot); if (unlikely(fail >=3D 0)) { + if (probe) { + return false; + } cs->exception_index =3D EXCP_MMFAULT; env->trap_arg0 =3D addr; env->trap_arg1 =3D fail; - env->trap_arg2 =3D (rw =3D=3D 2 ? -1 : rw); - return 1; + env->trap_arg2 =3D (access_type =3D=3D MMU_INST_FETCH ? -1 : acces= s_type); + cpu_loop_exit_restore(cs, retaddr); } =20 tlb_set_page(cs, addr & TARGET_PAGE_MASK, phys & TARGET_PAGE_MASK, prot, mmu_idx, TARGET_PAGE_SIZE); - return 0; + return true; +} + +void tlb_fill(CPUState *cs, target_ulong addr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) +{ + alpha_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retadd= r); } #endif /* USER_ONLY */ =20 diff --git a/target/alpha/mem_helper.c b/target/alpha/mem_helper.c index 011bc73dca..934faa1d6f 100644 --- a/target/alpha/mem_helper.c +++ b/target/alpha/mem_helper.c @@ -62,20 +62,4 @@ void alpha_cpu_do_transaction_failed(CPUState *cs, hwadd= r physaddr, env->error_code =3D 0; cpu_loop_exit_restore(cs, retaddr); } - -/* try to fill the TLB and return an exception if error. If retaddr is - NULL, it means that the function was called in C code (i.e. not - from generated code or from helper.c) */ -/* XXX: fix it to restore all registers */ -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - int ret; - - ret =3D alpha_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu_id= x); - if (unlikely(ret !=3D 0)) { - /* Exception index and error code are already set */ - cpu_loop_exit_restore(cs, retaddr); - } -} #endif /* CONFIG_USER_ONLY */ --=20 2.17.1 From nobody Tue Apr 30 04:47:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1557502269; cv=none; d=zoho.com; s=zohoarc; b=IuLYGHIbpf4nJfT+lMnm+ofHJSXT4+Jp0OHLIgjVtQ06CYVhVvVr/JFecqc0797zpiY837x6yqZyIq0YEIw9ix+VbWK1CdjjTouTOHSIU7enPsbSHPXttsw1UuK4F2tfxmhQMjrgoRQH8S4eQ+tPOQfiutIOT8zHrb+wwIzhfQw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1557502269; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=arkTudclBbivAZzWnq6ClicZUzHEE3qicGPLMaqemkE=; b=gvXU4mSFA7rWXOa4hnA8V33anVxdytyiwYAZuUvaBAMGLe0TBtw97jO9V3pgsW7h+iiWu4fxsJJA4vmzSjrctATOjXq3oKVFakAfr9/nrB5aGML/vJlT55isiD6BTKELWeOmUUPQZAsgeMAfkgB8aYq7TPKVboo06ZAy6FQlBSA= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1557502269046625.663534807421; Fri, 10 May 2019 08:31:09 -0700 (PDT) Received: from localhost ([127.0.0.1]:45146 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hP7UH-00010S-TG for importer@patchew.org; Fri, 10 May 2019 11:31:05 -0400 Received: from eggs.gnu.org ([209.51.188.92]:55983) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hP7JR-0007Pb-IJ for qemu-devel@nongnu.org; Fri, 10 May 2019 11:19:55 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hP7JP-0008Er-VV for qemu-devel@nongnu.org; Fri, 10 May 2019 11:19:53 -0400 Received: from mail-pg1-x543.google.com ([2607:f8b0:4864:20::543]:36208) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hP7JP-0008ED-NP for qemu-devel@nongnu.org; Fri, 10 May 2019 11:19:51 -0400 Received: by mail-pg1-x543.google.com with SMTP id a3so3181989pgb.3 for ; Fri, 10 May 2019 08:19:51 -0700 (PDT) Received: from localhost.localdomain (97-113-13-231.tukw.qwest.net. [97.113.13.231]) by smtp.gmail.com with ESMTPSA id 19sm5920517pgz.24.2019.05.10.08.19.48 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 10 May 2019 08:19:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=arkTudclBbivAZzWnq6ClicZUzHEE3qicGPLMaqemkE=; b=o1bcK7Y/KLk+oCtZu68b5QuVTg94gZkj8VRibWyLTLLXRmh2ll/RD0yD7QGWhtmkg9 o8p/SB4r4veWG6WsRvAYRyZDBh+/cR9eG8k2vvALN5Z/YAOpq4l828/Kbd1zxsT8qiDv dz9B0CIhtb1/paoaNDmBes0moxLeLHHDDr/4z91lNfJIqC1fbpd4iXHxBb5QCqzDHMFx EDRSY5P9dlu/k35/xBTcH7wYQ49/1s+Hakmx0r2/de4Uq8zXZVx4DAYGYP8lTq1XzF/i bh2rpmTZ9oeknwUK93SeAJfVnFB8lpZoUp1MaT8SnC2pVsUzGepNUjbnC0v0NXdYTytr +q9A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=arkTudclBbivAZzWnq6ClicZUzHEE3qicGPLMaqemkE=; b=NqBsHDG+eTQPF1URMX9GXuthWLe2C2y8XV6W2lCseuXPr03vh6pbOIVsLdJOs2RFef ZpCgVEW/VocXU8Uare/vhcXkU/Ybv5VnK/IyQ/IY4BflTyMJ7YWopFTF82ZoWqVQ8gF0 iNQElaP7ZOAfM9ecoG6X7UpIFEEmLW1tpBcfsf4hPn/NieC8GV651l2PI3ONijHEFT7X x1iag6cXk2DufziCM0tOJlLeVHG9O9vtQ1wtdDluADVJjOns8haOQv1A1+vixKNzTJCg ZljsRdlRTr4ZtyZ/ZUyzESNk1gTMZe+sD4o3iMp1Xn/n4HLJK+yYl6gBr8IfYg+zEf/D WePQ== X-Gm-Message-State: APjAAAXfGPschEsAn/QIS0v7Kb8iLPrzyKGg9l6xhuYy+Qfmp+LTqlNP mQb4hKlAV8mWeHADiiQl1PpMSPUl7Ys= X-Google-Smtp-Source: APXvYqwYVQG34tWCFXteJJrjyWJ0r1zB9A7+1ksmkjkKVROsy41z97PLauy4tQOFyHWkj8onilYvWw== X-Received: by 2002:a63:af45:: with SMTP id s5mr14259077pgo.420.1557501590462; Fri, 10 May 2019 08:19:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 10 May 2019 08:19:20 -0700 Message-Id: <20190510151944.22981-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190510151944.22981-1-richard.henderson@linaro.org> References: <20190510151944.22981-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 Subject: [Qemu-devel] [PULL 03/27] target/arm: Convert to CPUClass::tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Cc: qemu-arm@nongnu.org Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/internals.h | 10 +++-- target/arm/cpu.c | 22 +--------- target/arm/helper.c | 98 ++++++++++++++++++++++++++---------------- target/arm/op_helper.c | 29 ++----------- 4 files changed, 73 insertions(+), 86 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 587a1ddf58..5a02f458f3 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -761,10 +761,12 @@ static inline bool arm_extabort_type(MemTxResult resu= lt) return result !=3D MEMTX_DECODE_ERROR; } =20 -/* Do a page table walk and add page to TLB if possible */ -bool arm_tlb_fill(CPUState *cpu, vaddr address, - MMUAccessType access_type, int mmu_idx, - ARMMMUFaultInfo *fi); +bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); + +void arm_deliver_fault(ARMCPU *cpu, vaddr addr, MMUAccessType access_type, + int mmu_idx, ARMMMUFaultInfo *fi) QEMU_NORETURN; =20 /* Return true if the stage 1 translation regime is using LPAE format page * tables */ diff --git a/target/arm/cpu.c b/target/arm/cpu.c index a181fa8dc1..bb8e824c3e 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2133,23 +2133,6 @@ static Property arm_cpu_properties[] =3D { DEFINE_PROP_END_OF_LIST() }; =20 -#ifdef CONFIG_USER_ONLY -static int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, - int rw, int mmu_idx) -{ - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; - - env->exception.vaddress =3D address; - if (rw =3D=3D 2) { - cs->exception_index =3D EXCP_PREFETCH_ABORT; - } else { - cs->exception_index =3D EXCP_DATA_ABORT; - } - return 1; -} -#endif - static gchar *arm_gdb_arch_name(CPUState *cs) { ARMCPU *cpu =3D ARM_CPU(cs); @@ -2182,9 +2165,8 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) cc->synchronize_from_tb =3D arm_cpu_synchronize_from_tb; cc->gdb_read_register =3D arm_cpu_gdb_read_register; cc->gdb_write_register =3D arm_cpu_gdb_write_register; -#ifdef CONFIG_USER_ONLY - cc->handle_mmu_fault =3D arm_cpu_handle_mmu_fault; -#else + cc->tlb_fill =3D arm_cpu_tlb_fill; +#ifndef CONFIG_USER_ONLY cc->do_interrupt =3D arm_cpu_do_interrupt; cc->do_unaligned_access =3D arm_cpu_do_unaligned_access; cc->do_transaction_failed =3D arm_cpu_do_transaction_failed; diff --git a/target/arm/helper.c b/target/arm/helper.c index 1e6eb0d0f3..f1a2b94ddb 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -12596,43 +12596,6 @@ static bool get_phys_addr(CPUARMState *env, target= _ulong address, } } =20 -/* Walk the page table and (if the mapping exists) add the page - * to the TLB. Return false on success, or true on failure. Populate - * fsr with ARM DFSR/IFSR fault register format value on failure. - */ -bool arm_tlb_fill(CPUState *cs, vaddr address, - MMUAccessType access_type, int mmu_idx, - ARMMMUFaultInfo *fi) -{ - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; - hwaddr phys_addr; - target_ulong page_size; - int prot; - int ret; - MemTxAttrs attrs =3D {}; - - ret =3D get_phys_addr(env, address, access_type, - core_to_arm_mmu_idx(env, mmu_idx), &phys_addr, - &attrs, &prot, &page_size, fi, NULL); - if (!ret) { - /* - * Map a single [sub]page. Regions smaller than our declared - * target page size are handled specially, so for those we - * pass in the exact addresses. - */ - if (page_size >=3D TARGET_PAGE_SIZE) { - phys_addr &=3D TARGET_PAGE_MASK; - address &=3D TARGET_PAGE_MASK; - } - tlb_set_page_with_attrs(cs, address, phys_addr, attrs, - prot, mmu_idx, page_size); - return 0; - } - - return ret; -} - hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, MemTxAttrs *attrs) { @@ -13111,6 +13074,67 @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t= addr, uint32_t op) =20 #endif =20 +bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + +#ifdef CONFIG_USER_ONLY + cpu->env.exception.vaddress =3D address; + if (access_type =3D=3D MMU_INST_FETCH) { + cs->exception_index =3D EXCP_PREFETCH_ABORT; + } else { + cs->exception_index =3D EXCP_DATA_ABORT; + } + cpu_loop_exit_restore(cs, retaddr); +#else + hwaddr phys_addr; + target_ulong page_size; + int prot, ret; + MemTxAttrs attrs =3D {}; + ARMMMUFaultInfo fi =3D {}; + + /* + * Walk the page table and (if the mapping exists) add the page + * to the TLB. On success, return true. Otherwise, if probing, + * return false. Otherwise populate fsr with ARM DFSR/IFSR fault + * register format, and signal the fault. + */ + ret =3D get_phys_addr(&cpu->env, address, access_type, + core_to_arm_mmu_idx(&cpu->env, mmu_idx), + &phys_addr, &attrs, &prot, &page_size, &fi, NULL); + if (likely(!ret)) { + /* + * Map a single [sub]page. Regions smaller than our declared + * target page size are handled specially, so for those we + * pass in the exact addresses. + */ + if (page_size >=3D TARGET_PAGE_SIZE) { + phys_addr &=3D TARGET_PAGE_MASK; + address &=3D TARGET_PAGE_MASK; + } + tlb_set_page_with_attrs(cs, address, phys_addr, attrs, + prot, mmu_idx, page_size); + return true; + } else if (probe) { + return false; + } else { + /* now we have a real cpu fault */ + cpu_restore_state(cs, retaddr, true); + arm_deliver_fault(cpu, address, access_type, mmu_idx, &fi); + } +#endif +} + +#ifndef CONFIG_USER_ONLY +void tlb_fill(CPUState *cs, target_ulong addr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) +{ + arm_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); +} +#endif + void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in) { /* Implement DC ZVA, which zeroes a fixed-length block of memory. diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 8698b4dc83..8ee15a4bd4 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -126,8 +126,8 @@ static inline uint32_t merge_syn_data_abort(uint32_t te= mplate_syn, return syn; } =20 -static void deliver_fault(ARMCPU *cpu, vaddr addr, MMUAccessType access_ty= pe, - int mmu_idx, ARMMMUFaultInfo *fi) +void arm_deliver_fault(ARMCPU *cpu, vaddr addr, MMUAccessType access_type, + int mmu_idx, ARMMMUFaultInfo *fi) { CPUARMState *env =3D &cpu->env; int target_el; @@ -179,27 +179,6 @@ static void deliver_fault(ARMCPU *cpu, vaddr addr, MMU= AccessType access_type, raise_exception(env, exc, syn, target_el); } =20 -/* try to fill the TLB and return an exception if error. If retaddr is - * NULL, it means that the function was called in C code (i.e. not - * from generated code or from helper.c) - */ -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - bool ret; - ARMMMUFaultInfo fi =3D {}; - - ret =3D arm_tlb_fill(cs, addr, access_type, mmu_idx, &fi); - if (unlikely(ret)) { - ARMCPU *cpu =3D ARM_CPU(cs); - - /* now we have a real cpu fault */ - cpu_restore_state(cs, retaddr, true); - - deliver_fault(cpu, addr, access_type, mmu_idx, &fi); - } -} - /* Raise a data fault alignment exception for the specified virtual addres= s */ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, MMUAccessType access_type, @@ -212,7 +191,7 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr va= ddr, cpu_restore_state(cs, retaddr, true); =20 fi.type =3D ARMFault_Alignment; - deliver_fault(cpu, vaddr, access_type, mmu_idx, &fi); + arm_deliver_fault(cpu, vaddr, access_type, mmu_idx, &fi); } =20 /* arm_cpu_do_transaction_failed: handle a memory system error response @@ -233,7 +212,7 @@ void arm_cpu_do_transaction_failed(CPUState *cs, hwaddr= physaddr, =20 fi.ea =3D arm_extabort_type(response); fi.type =3D ARMFault_SyncExternal; - deliver_fault(cpu, addr, access_type, mmu_idx, &fi); + arm_deliver_fault(cpu, addr, access_type, mmu_idx, &fi); } =20 #endif /* !defined(CONFIG_USER_ONLY) */ --=20 2.17.1 From nobody Tue Apr 30 04:47:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1557501965; cv=none; d=zoho.com; s=zohoarc; b=efXLhk/8z0ld30Czs3DC1sV8c1Ao5lo/9u6pwk7d0SfxhDIsWyx+oDYPu4CE/A6R4mMsZx0rOn5y0StxXMAGtnAyG7jy/tpn0r8e+N9Nc3sJStL+noUSjVolj74u9e9Br2PrpL14fMJ0xUEl78FZjAmmT/fVkT8g/95nrtChW6U= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1557501965; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=PI6csDpWdG6t7BSfq5z2Q2G3DWQrj5ohp4MLYzjDA0s=; b=Cy0cQXCfyb67wBUq+pGwfEhYBH6Rq1pMw7yjlffPRG6nrghy9OwfgWwfAn3N8K1APWsv7IwyIlYabkM2O+gQiw2wtVyJcXMRfX3ojZq/O2I7owvYqwZoTKt5pkKY0/lqhMKM1YfQqFgmshJkmjeaYk4pGa/RZgUr83/NgnYMrPk= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1557501965127700.513550244689; Fri, 10 May 2019 08:26:05 -0700 (PDT) Received: from localhost ([127.0.0.1]:45058 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hP7PG-0004NM-FJ for importer@patchew.org; Fri, 10 May 2019 11:25:54 -0400 Received: from eggs.gnu.org ([209.51.188.92]:56003) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hP7JS-0007Qm-Qe for qemu-devel@nongnu.org; Fri, 10 May 2019 11:19:56 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hP7JR-0008HQ-DL for qemu-devel@nongnu.org; Fri, 10 May 2019 11:19:54 -0400 Received: from mail-pl1-x642.google.com ([2607:f8b0:4864:20::642]:36186) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hP7JR-0008FO-6W for qemu-devel@nongnu.org; Fri, 10 May 2019 11:19:53 -0400 Received: by mail-pl1-x642.google.com with SMTP id d21so3002693plr.3 for ; Fri, 10 May 2019 08:19:53 -0700 (PDT) Received: from localhost.localdomain (97-113-13-231.tukw.qwest.net. [97.113.13.231]) by smtp.gmail.com with ESMTPSA id 19sm5920517pgz.24.2019.05.10.08.19.50 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 10 May 2019 08:19:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=PI6csDpWdG6t7BSfq5z2Q2G3DWQrj5ohp4MLYzjDA0s=; b=X2FIHoUjkw7zfz+AnL3JyxdcsX6GMlDetKkTRm7XuOExyDl0igsfiy+OGRdP4rMAQv FQnUB8RMpr5vr5590bFsw7BbtQzR2fKC+XYoj6mFfhkBBIY87liZ9eZPXv/ebx4CqEBS t8KTTjP2imx6MoqboDFayszVhnVmln8Vid47nM/P6UBt5Jw4PZlPMVVZ4eQBaw2TWEE7 9hwC2ZFyWmQcIXkjyXlbXd3T+z/jCkuzmngi2vd57jVLEfrkc9C3O2I54JifZBdoIe7X kDHkQcoHAXdOiucwBifnbHqfUza0qOu1eVqVQSqe2KQ+gzWtSIWDt98xvRXsPq7jxiAX Lm7Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=PI6csDpWdG6t7BSfq5z2Q2G3DWQrj5ohp4MLYzjDA0s=; b=co8NhdqCnCXaGLMa6OPNJoS3MIXz5udUZ9nMzXS1TgvvPdj11OFKEC/F79orJ5I6gM Bx26I2gAlAWX60PFQvGjF8fHaNocrLcDlpsFdJQaNSWwni93iUVscVRJFsloP6OdQ9R9 myEADcjSToVxDcJ1CNxCQFstoSeQ0nzz8ZFg4iWAitC4J0mUzh1dmGgHPsdh7focMf/3 z4wBuH51fdpwmi8+vKVIg4tHtbSmMzuS1MELwwKm/Rx2TNrumYf2IHQQ756/SpE/522C PvLOmIDR8oI1cAsVIcdmx9rCdvJ8SWw3NQHkk22WbyByUiMOIf5YsGqP7uxX2HonyJ3p ZlBA== X-Gm-Message-State: APjAAAW5+NZzFxLdICgTDqFr+e//b1ewhtZCn4vL7hOi1inbUdodzoPF M6ln7F9oJSYiYKzGW5zWUHlMNqOGK/k= X-Google-Smtp-Source: APXvYqwXiqXneT+c+lisy0Huzj68VA04fpohjXunMMGN5r8DXwgEdTaAZxNXDkwmXDbDzfI970J79w== X-Received: by 2002:a17:902:12d:: with SMTP id 42mr7423220plb.4.1557501591865; Fri, 10 May 2019 08:19:51 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 10 May 2019 08:19:21 -0700 Message-Id: <20190510151944.22981-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190510151944.22981-1-richard.henderson@linaro.org> References: <20190510151944.22981-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::642 Subject: [Qemu-devel] [PULL 04/27] target/cris: Convert to CPUClass::tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, "Edgar E . Iglesias" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Remove dumping of cpu state. Remove logging of PC, as that value is garbage until cpu_restore_state. Cc: Edgar E. Iglesias Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/cris/cpu.h | 5 +-- target/cris/cpu.c | 5 ++- target/cris/helper.c | 67 +++++++++++++++++++++++------------------ target/cris/op_helper.c | 28 ----------------- 4 files changed, 42 insertions(+), 63 deletions(-) diff --git a/target/cris/cpu.h b/target/cris/cpu.h index 0fbe771639..857de79e24 100644 --- a/target/cris/cpu.h +++ b/target/cris/cpu.h @@ -281,8 +281,9 @@ static inline int cpu_mmu_index (CPUCRISState *env, boo= l ifetch) return !!(env->pregs[PR_CCS] & U_FLAG); } =20 -int cris_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int = rw, - int mmu_idx); +bool cris_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); =20 /* Support function regs. */ #define SFR_RW_GC_CFG 0][0 diff --git a/target/cris/cpu.c b/target/cris/cpu.c index 75729bfdd5..4e5288ae80 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -269,9 +269,8 @@ static void cris_cpu_class_init(ObjectClass *oc, void *= data) cc->set_pc =3D cris_cpu_set_pc; cc->gdb_read_register =3D cris_cpu_gdb_read_register; cc->gdb_write_register =3D cris_cpu_gdb_write_register; -#ifdef CONFIG_USER_ONLY - cc->handle_mmu_fault =3D cris_cpu_handle_mmu_fault; -#else + cc->tlb_fill =3D cris_cpu_tlb_fill; +#ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D cris_cpu_get_phys_page_debug; dc->vmsd =3D &vmstate_cris_cpu; #endif diff --git a/target/cris/helper.c b/target/cris/helper.c index 3939603c73..69464837c8 100644 --- a/target/cris/helper.c +++ b/target/cris/helper.c @@ -24,6 +24,7 @@ #include "qemu/host-utils.h" #include "exec/exec-all.h" #include "exec/cpu_ldst.h" +#include "exec/helper-proto.h" =20 =20 //#define CRIS_HELPER_DEBUG @@ -53,15 +54,15 @@ void crisv10_cpu_do_interrupt(CPUState *cs) cris_cpu_do_interrupt(cs); } =20 -int cris_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int r= w, - int mmu_idx) +bool cris_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) { CRISCPU *cpu =3D CRIS_CPU(cs); =20 cs->exception_index =3D 0xaa; cpu->env.pregs[PR_EDA] =3D address; - cpu_dump_state(cs, stderr, 0); - return 1; + cpu_loop_exit_restore(cs, retaddr); } =20 #else /* !CONFIG_USER_ONLY */ @@ -76,33 +77,19 @@ static void cris_shift_ccs(CPUCRISState *env) env->pregs[PR_CCS] =3D ccs; } =20 -int cris_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int r= w, - int mmu_idx) +bool cris_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) { CRISCPU *cpu =3D CRIS_CPU(cs); CPUCRISState *env =3D &cpu->env; struct cris_mmu_result res; int prot, miss; - int r =3D -1; target_ulong phy; =20 - qemu_log_mask(CPU_LOG_MMU, "%s addr=3D%" VADDR_PRIx " pc=3D%x rw=3D%x\= n", - __func__, address, env->pc, rw); miss =3D cris_mmu_translate(&res, env, address & TARGET_PAGE_MASK, - rw, mmu_idx, 0); - if (miss) { - if (cs->exception_index =3D=3D EXCP_BUSFAULT) { - cpu_abort(cs, - "CRIS: Illegal recursive bus fault." - "addr=3D%" VADDR_PRIx " rw=3D%d\n", - address, rw); - } - - env->pregs[PR_EDA] =3D address; - cs->exception_index =3D EXCP_BUSFAULT; - env->fault_vector =3D res.bf_vec; - r =3D 1; - } else { + access_type, mmu_idx, 0); + if (likely(!miss)) { /* * Mask off the cache selection bit. The ETRAX busses do not * see the top bit. @@ -111,15 +98,35 @@ int cris_cpu_handle_mmu_fault(CPUState *cs, vaddr addr= ess, int size, int rw, prot =3D res.prot; tlb_set_page(cs, address & TARGET_PAGE_MASK, phy, prot, mmu_idx, TARGET_PAGE_SIZE); - r =3D 0; + return true; } - if (r > 0) { - qemu_log_mask(CPU_LOG_MMU, - "%s returns %d irqreq=3D%x addr=3D%" VADDR_PRIx " phy=3D%x= vec=3D%x" - " pc=3D%x\n", __func__, r, cs->interrupt_request, address, - res.phy, res.bf_vec, env->pc); + + if (probe) { + return false; } - return r; + + if (cs->exception_index =3D=3D EXCP_BUSFAULT) { + cpu_abort(cs, "CRIS: Illegal recursive bus fault." + "addr=3D%" VADDR_PRIx " access_type=3D%d\n", + address, access_type); + } + + env->pregs[PR_EDA] =3D address; + cs->exception_index =3D EXCP_BUSFAULT; + env->fault_vector =3D res.bf_vec; + if (retaddr) { + if (cpu_restore_state(cs, retaddr, true)) { + /* Evaluate flags after retranslation. */ + helper_top_evaluate_flags(env); + } + } + cpu_loop_exit(cs); +} + +void tlb_fill(CPUState *cs, target_ulong addr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) +{ + cris_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr= ); } =20 void crisv10_cpu_do_interrupt(CPUState *cs) diff --git a/target/cris/op_helper.c b/target/cris/op_helper.c index 0ee3a3117b..26a395b413 100644 --- a/target/cris/op_helper.c +++ b/target/cris/op_helper.c @@ -37,34 +37,6 @@ #define D_LOG(...) do { } while (0) #endif =20 -#if !defined(CONFIG_USER_ONLY) -/* Try to fill the TLB and return an exception if error. If retaddr is - NULL, it means that the function was called in C code (i.e. not - from generated code or from helper.c) */ -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - CRISCPU *cpu =3D CRIS_CPU(cs); - CPUCRISState *env =3D &cpu->env; - int ret; - - D_LOG("%s pc=3D%x tpc=3D%x ra=3D%p\n", __func__, - env->pc, env->pregs[PR_EDA], (void *)retaddr); - ret =3D cris_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu_idx= ); - if (unlikely(ret)) { - if (retaddr) { - /* now we have a real cpu fault */ - if (cpu_restore_state(cs, retaddr, true)) { - /* Evaluate flags after retranslation. */ - helper_top_evaluate_flags(env); - } - } - cpu_loop_exit(cs); - } -} - -#endif - void helper_raise_exception(CPUCRISState *env, uint32_t index) { CPUState *cs =3D CPU(cris_env_get_cpu(env)); --=20 2.17.1 From nobody Tue Apr 30 04:47:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1557502495; cv=none; d=zoho.com; s=zohoarc; b=S0D1noI/QtPbAWpyP8sNHMJ7Cb6gZ9B8ZYrcTqqoP34JKidyUiVGQxn1jbmSvcy6SCiapcUbqgNMDmK/JqES/TEBRZcvNTl+8yvsIwbUJoa8iFh57WJhIb6lBIpdM6kSVy1HdKqZwPBztDJCGUPI7xx1XChkcYwAUYGkVc7z7oA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1557502495; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=w7l/Pbs/dkuyE6y60mYyZzngNGSZYjs+O6jEPehbb2U=; b=VQkkUVFsTcWr76HGqNEvQwYF5OH+FbH9uwJvxFrIzLshDN9mOFzQtWMg0682Cm6YHqZ3g77JFUgFp9BNG2Lmx/uBsTFqU2c8DSKQ1d9kvYsnI8u4rCekUqkuBPfzWcGHtNKhJiW6sC6qAhEUKbRXps6sF4UN8pYsv4dXrb5qW5I= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1557502495578729.9519807653148; Fri, 10 May 2019 08:34:55 -0700 (PDT) Received: from localhost ([127.0.0.1]:45174 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hP7Xw-0004RP-Fh for importer@patchew.org; Fri, 10 May 2019 11:34:52 -0400 Received: from eggs.gnu.org ([209.51.188.92]:56036) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hP7JU-0007Rq-6u for qemu-devel@nongnu.org; Fri, 10 May 2019 11:19:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hP7JS-0008Lg-Vv for qemu-devel@nongnu.org; Fri, 10 May 2019 11:19:56 -0400 Received: from mail-pg1-x542.google.com ([2607:f8b0:4864:20::542]:41797) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hP7JS-0008JL-P1 for qemu-devel@nongnu.org; Fri, 10 May 2019 11:19:54 -0400 Received: by mail-pg1-x542.google.com with SMTP id z3so3174853pgp.8 for ; Fri, 10 May 2019 08:19:54 -0700 (PDT) Received: from localhost.localdomain (97-113-13-231.tukw.qwest.net. [97.113.13.231]) by smtp.gmail.com with ESMTPSA id 19sm5920517pgz.24.2019.05.10.08.19.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 10 May 2019 08:19:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=w7l/Pbs/dkuyE6y60mYyZzngNGSZYjs+O6jEPehbb2U=; b=NDxtRjIT9OwOwhQuz62GbKxNx3/1UWV99hQDQbrbUl+wF85WhiunFo3gRQe5HTaM2z yaEKk8KC6PV2P/UGYI2RSFDhDZq75/roQ6mZuJJNRZc/XosJQzWWuuB0Wug6gKqc2mV0 8sJ8SM83s2wKVm1JrUy11/3lyp/0SdU+9XqUnoj+Hgn7EtwXAIexBd6m4pbyj/6TJ7tJ uovo/1e0mRAd3KOb8ZcG73XEE09pohPxEbE6HsRwnpPrGFRKOkf9cH9YIIXTRUQfdtyT ZR/q0DVxrRwMouujnEU7+bivGIx+lQfnYRq08TAKACRX9AWZ3JGqVxdQuparR3GUtozD ehzg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=w7l/Pbs/dkuyE6y60mYyZzngNGSZYjs+O6jEPehbb2U=; b=q09N78clsZDPD0PRmY7m5RgtdUJ2f5Fkwihl9+2wHU3HH7YS5Or21CoJ+WsdD7a5eb Ljp9XIS4rEXWGJtBPrYlX8XDUKUo3/gY7LN7gXGk4yq0I3/TbEsDX57f7K2xuYi6eTg7 6J8m/PzNsXFpBegQnYgB6drFVoivA/cVt9eA3NS2Ol94J6ZgDPdmj65lp8+q2NevxX4u cnjtU7ocqkOxQ1T2Bv6WExPzYrsao1L53s7XwrlNhX0cN9GF+dhxCxyqWhsxYKrwq+xl 8mwzP0uOUaIrX4W8FJTiLpYYn2u2qjbSJ682UenWeiXHyI6xoic+qVB2iT+IsjphMGSo 9JTA== X-Gm-Message-State: APjAAAXmJqtjHqtOAKk63EaBXokM/N9v5doALf622BlIOANavrJUPNmq GemwRpr7mNUkb7IDQ6yVep1L3xTq8qM= X-Google-Smtp-Source: APXvYqzWafCd/DDsaPUDKIDQn0EvgAPR3qNeP+mUCy5aDGehTHZ8ALdsIw9n+rKSszC7hnTCFlSL9Q== X-Received: by 2002:a63:4852:: with SMTP id x18mr980020pgk.14.1557501593469; Fri, 10 May 2019 08:19:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 10 May 2019 08:19:22 -0700 Message-Id: <20190510151944.22981-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190510151944.22981-1-richard.henderson@linaro.org> References: <20190510151944.22981-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::542 Subject: [Qemu-devel] [PULL 05/27] target/hppa: Convert to CPUClass::tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 8 ++++---- target/hppa/cpu.c | 5 ++--- target/hppa/mem_helper.c | 22 +++++++++++++++++----- 3 files changed, 23 insertions(+), 12 deletions(-) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 923346adb6..c1e0215e66 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -360,10 +360,10 @@ int hppa_cpu_gdb_write_register(CPUState *cpu, uint8_= t *buf, int reg); void hppa_cpu_do_interrupt(CPUState *cpu); bool hppa_cpu_exec_interrupt(CPUState *cpu, int int_req); void hppa_cpu_dump_state(CPUState *cs, FILE *f, int); -#ifdef CONFIG_USER_ONLY -int hppa_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, - int rw, int midx); -#else +bool hppa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); +#ifndef CONFIG_USER_ONLY int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, int type, hwaddr *pphys, int *pprot); extern const MemoryRegionOps hppa_io_eir_ops; diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index e64f48581e..9717ea1798 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -163,9 +163,8 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *= data) cc->synchronize_from_tb =3D hppa_cpu_synchronize_from_tb; cc->gdb_read_register =3D hppa_cpu_gdb_read_register; cc->gdb_write_register =3D hppa_cpu_gdb_write_register; -#ifdef CONFIG_USER_ONLY - cc->handle_mmu_fault =3D hppa_cpu_handle_mmu_fault; -#else + cc->tlb_fill =3D hppa_cpu_tlb_fill; +#ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D hppa_cpu_get_phys_page_debug; dc->vmsd =3D &vmstate_hppa_cpu; #endif diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index 77fb544838..5cee0c19b1 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -25,8 +25,9 @@ #include "trace.h" =20 #ifdef CONFIG_USER_ONLY -int hppa_cpu_handle_mmu_fault(CPUState *cs, vaddr address, - int size, int rw, int mmu_idx) +bool hppa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) { HPPACPU *cpu =3D HPPA_CPU(cs); =20 @@ -34,7 +35,7 @@ int hppa_cpu_handle_mmu_fault(CPUState *cs, vaddr address, which would affect si_code. */ cs->exception_index =3D EXCP_DMP; cpu->env.cr[CR_IOR] =3D address; - return 1; + cpu_loop_exit_restore(cs, retaddr); } #else static hppa_tlb_entry *hppa_find_tlb(CPUHPPAState *env, vaddr addr) @@ -213,8 +214,9 @@ hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr= addr) return excp =3D=3D EXCP_DTLB_MISS ? -1 : phys; } =20 -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType type, int mmu_idx, uintptr_t retaddr) +bool hppa_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, + MMUAccessType type, int mmu_idx, + bool probe, uintptr_t retaddr) { HPPACPU *cpu =3D HPPA_CPU(cs); CPUHPPAState *env =3D &cpu->env; @@ -236,6 +238,9 @@ void tlb_fill(CPUState *cs, target_ulong addr, int size, excp =3D hppa_get_physical_address(env, addr, mmu_idx, a_prot, &phys, &prot); if (unlikely(excp >=3D 0)) { + if (probe) { + return false; + } trace_hppa_tlb_fill_excp(env, addr, size, type, mmu_idx); /* Failure. Raise the indicated exception. */ cs->exception_index =3D excp; @@ -252,6 +257,13 @@ void tlb_fill(CPUState *cs, target_ulong addr, int siz= e, /* Success! Store the translation into the QEMU TLB. */ tlb_set_page(cs, addr & TARGET_PAGE_MASK, phys & TARGET_PAGE_MASK, prot, mmu_idx, TARGET_PAGE_SIZE); + return true; +} + +void tlb_fill(CPUState *cs, target_ulong addr, int size, + MMUAccessType type, int mmu_idx, uintptr_t retaddr) +{ + hppa_cpu_tlb_fill(cs, addr, size, type, mmu_idx, false, retaddr); } =20 /* Insert (Insn/Data) TLB Address. Note this is PA 1.1 only. */ --=20 2.17.1 From nobody Tue Apr 30 04:47:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1557501890; cv=none; d=zoho.com; s=zohoarc; b=ahHTaV0UQdOaXewZprUtbheDXkR7l/Hq6LmlTzCetqpkRK/pXCcBds8ec+FF3hFAA+VkQwvdaO/nHqqhcAydeSB/6HtZEktomQ3wQA8lTr/8LaJKpC6IHlrHQfzbbS6d2jQ8NnsI5/bxCGhvtwhUC3qpj71Ml1TGkBCCRjzLGDE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1557501890; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=s87CuOmfhyfGLXIPM91Iv48ElcI94bqoXpVc6e0DK1o=; b=Pvnr+h6gWlO+JR1tebqz/1RjbSh43izcQQz2zDbgr+EsialdKg6KI1Tq4NLfWTAu4D6VDu9WVaK4EwtZJ1ct5jhyCIlycbvYakyvuFr+LiZbVlNh0hv1LezV4Id3H0w4zzhNSgBW8yDJQp8iz7BGo7448eNU3KFH7771x5VegEA= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1557501890801439.93642577125695; Fri, 10 May 2019 08:24:50 -0700 (PDT) Received: from localhost ([127.0.0.1]:45026 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hP7OB-0003RD-KG for importer@patchew.org; Fri, 10 May 2019 11:24:47 -0400 Received: from eggs.gnu.org ([209.51.188.92]:56059) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hP7JV-0007St-Ca for qemu-devel@nongnu.org; Fri, 10 May 2019 11:19:58 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hP7JU-0008Oh-2Q for qemu-devel@nongnu.org; Fri, 10 May 2019 11:19:57 -0400 Received: from mail-pl1-x632.google.com ([2607:f8b0:4864:20::632]:35855) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hP7JT-0008My-SK for qemu-devel@nongnu.org; Fri, 10 May 2019 11:19:56 -0400 Received: by mail-pl1-x632.google.com with SMTP id d21so3002737plr.3 for ; Fri, 10 May 2019 08:19:55 -0700 (PDT) Received: from localhost.localdomain (97-113-13-231.tukw.qwest.net. [97.113.13.231]) by smtp.gmail.com with ESMTPSA id 19sm5920517pgz.24.2019.05.10.08.19.53 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 10 May 2019 08:19:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=s87CuOmfhyfGLXIPM91Iv48ElcI94bqoXpVc6e0DK1o=; b=wRHDNs9M8gJ4f3SIGelLWIcpVo0JF7TP9xoi97E4O+rS4EdcreMwqicJKIK/KUZz1w Bh51hKNPKPPzUzX70dTM6bAOOlymFTNS6dpndAM/UhKdlaEQ+MRKrtLzA5UvvUBAesXQ qfgi7ML1Y4lSUDcVJC6hQXS731VOgEUkc0zuMHG3X9JjvUZuN0Rf4xYDtdZmlZ9cFd/y ndwYXzytYLp6tmtwMF8bAP6u0WOUGpkmaWc66m0rOffQQMy5HMp0+knmpfISo85JH1xz JKJxZFKbVTo8ctCj19s7OzzYO4WPDahWINAi/dcN/L3qbR1aaqhLn/SAszzAoHuoazS1 6QXw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=s87CuOmfhyfGLXIPM91Iv48ElcI94bqoXpVc6e0DK1o=; b=Hzw1dBHjOO0XC9pM0mx4zXQb3a8+3Xkdf//1p8PCY68iv3JORFhhiqNefpeSk8S+N/ kYddEMRcn1ee0uq8BZKQwzZ5YEid2gAhDYHapdt/5FJl1KNKT2TtK2d+Cz9GDcjG80eN +r1TROAiUlrGd3QKX6SRsJFRqnc3mWnKOSbJ3wIIuPfhpWdCzpVuhPgSI5PObxV98VEM qdL8aawh7ItxSMw/glD7IM3RIosAfd/MhvjYduvuYn2RQDUJ3bgcU/5OI4FYhMJdcHh3 4yAgQyNzI+q/HMbdKE2RD5UMYWUKQKT8kWh5FupOBqwo3eWW/F6ZluRmXWqTzEgunE8f H7mw== X-Gm-Message-State: APjAAAVPnWohhL4Tcf3+wdauzkEboS719aww+8CCbL1bjhGA0IYwb7gP LJDVQTR6mzER0sqLc16Kjce2ygMivUk= X-Google-Smtp-Source: APXvYqzYDf6vEGvZWPBEx4IKu2Qln7cuP4OSey/yPIUVPVBjFwbETpUH7kVNTfNIpYb8gRpwyxXZ6A== X-Received: by 2002:a17:902:8698:: with SMTP id g24mr14293071plo.151.1557501594578; Fri, 10 May 2019 08:19:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 10 May 2019 08:19:23 -0700 Message-Id: <20190510151944.22981-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190510151944.22981-1-richard.henderson@linaro.org> References: <20190510151944.22981-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::632 Subject: [Qemu-devel] [PULL 06/27] target/i386: Convert to CPUClass::tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Eduardo Habkost , Paolo Bonzini Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We do not support probing, but we do not need it yet either. Cc: Paolo Bonzini Cc: Eduardo Habkost Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/i386/cpu.h | 5 ++-- target/i386/cpu.c | 5 ++-- target/i386/excp_helper.c | 61 +++++++++++++++++++++++++-------------- target/i386/mem_helper.c | 21 -------------- 4 files changed, 44 insertions(+), 48 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 0128910661..fce6660bac 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1656,8 +1656,9 @@ void host_cpuid(uint32_t function, uint32_t count, void host_vendor_fms(char *vendor, int *family, int *model, int *stepping); =20 /* helper.c */ -int x86_cpu_handle_mmu_fault(CPUState *cpu, vaddr addr, int size, - int is_write, int mmu_idx); +bool x86_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); void x86_cpu_set_a20(X86CPU *cpu, int a20_state); =20 #ifndef CONFIG_USER_ONLY diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 722c5514d4..3c98869577 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -5915,9 +5915,8 @@ static void x86_cpu_common_class_init(ObjectClass *oc= , void *data) cc->gdb_write_register =3D x86_cpu_gdb_write_register; cc->get_arch_id =3D x86_cpu_get_arch_id; cc->get_paging_enabled =3D x86_cpu_get_paging_enabled; -#ifdef CONFIG_USER_ONLY - cc->handle_mmu_fault =3D x86_cpu_handle_mmu_fault; -#else + cc->tlb_fill =3D x86_cpu_tlb_fill; +#ifndef CONFIG_USER_ONLY cc->asidx_from_attrs =3D x86_asidx_from_attrs; cc->get_memory_mapping =3D x86_cpu_get_memory_mapping; cc->get_phys_page_debug =3D x86_cpu_get_phys_page_debug; diff --git a/target/i386/excp_helper.c b/target/i386/excp_helper.c index 49231f6b69..68bf8e3f7c 100644 --- a/target/i386/excp_helper.c +++ b/target/i386/excp_helper.c @@ -137,26 +137,7 @@ void raise_exception_ra(CPUX86State *env, int exceptio= n_index, uintptr_t retaddr raise_interrupt2(env, exception_index, 0, 0, 0, retaddr); } =20 -#if defined(CONFIG_USER_ONLY) -int x86_cpu_handle_mmu_fault(CPUState *cs, vaddr addr, int size, - int is_write, int mmu_idx) -{ - X86CPU *cpu =3D X86_CPU(cs); - CPUX86State *env =3D &cpu->env; - - /* user mode only emulation */ - is_write &=3D 1; - env->cr[2] =3D addr; - env->error_code =3D (is_write << PG_ERROR_W_BIT); - env->error_code |=3D PG_ERROR_U_MASK; - cs->exception_index =3D EXCP0E_PAGE; - env->exception_is_int =3D 0; - env->exception_next_eip =3D -1; - return 1; -} - -#else - +#if !defined(CONFIG_USER_ONLY) static hwaddr get_hphys(CPUState *cs, hwaddr gphys, MMUAccessType access_t= ype, int *prot) { @@ -365,8 +346,8 @@ static hwaddr get_hphys(CPUState *cs, hwaddr gphys, MMU= AccessType access_type, * 0 =3D nothing more to do * 1 =3D generate PF fault */ -int x86_cpu_handle_mmu_fault(CPUState *cs, vaddr addr, int size, - int is_write1, int mmu_idx) +static int handle_mmu_fault(CPUState *cs, vaddr addr, int size, + int is_write1, int mmu_idx) { X86CPU *cpu =3D X86_CPU(cs); CPUX86State *env =3D &cpu->env; @@ -691,3 +672,39 @@ do_check_protect_pse36: return 1; } #endif + +bool x86_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) +{ + X86CPU *cpu =3D X86_CPU(cs); + CPUX86State *env =3D &cpu->env; + +#ifdef CONFIG_USER_ONLY + /* user mode only emulation */ + env->cr[2] =3D addr; + env->error_code =3D (access_type =3D=3D MMU_DATA_STORE) << PG_ERROR_W_= BIT; + env->error_code |=3D PG_ERROR_U_MASK; + cs->exception_index =3D EXCP0E_PAGE; + env->exception_is_int =3D 0; + env->exception_next_eip =3D -1; + cpu_loop_exit_restore(cs, retaddr); +#else + env->retaddr =3D retaddr; + if (handle_mmu_fault(cs, addr, size, access_type, mmu_idx)) { + /* FIXME: On error in get_hphys we have already jumped out. */ + g_assert(!probe); + raise_exception_err_ra(env, cs->exception_index, + env->error_code, retaddr); + } + return true; +#endif +} + +#if !defined(CONFIG_USER_ONLY) +void tlb_fill(CPUState *cs, target_ulong addr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) +{ + x86_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); +} +#endif diff --git a/target/i386/mem_helper.c b/target/i386/mem_helper.c index 6cc53bcb40..1885df29d2 100644 --- a/target/i386/mem_helper.c +++ b/target/i386/mem_helper.c @@ -191,24 +191,3 @@ void helper_boundl(CPUX86State *env, target_ulong a0, = int v) raise_exception_ra(env, EXCP05_BOUND, GETPC()); } } - -#if !defined(CONFIG_USER_ONLY) -/* try to fill the TLB and return an exception if error. If retaddr is - * NULL, it means that the function was called in C code (i.e. not - * from generated code or from helper.c) - */ -/* XXX: fix it to restore all registers */ -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - X86CPU *cpu =3D X86_CPU(cs); - CPUX86State *env =3D &cpu->env; - int ret; - - env->retaddr =3D retaddr; - ret =3D x86_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu_idx); - if (ret) { - raise_exception_err_ra(env, cs->exception_index, env->error_code, = retaddr); - } -} -#endif --=20 2.17.1 From nobody Tue Apr 30 04:47:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1557502138; cv=none; d=zoho.com; s=zohoarc; b=ZVbC4pK8pySQZ7FZ5zUCyYKqjuXoGBmdxlgxjHfOKS+cE9GCJsKUVQI63h/yRObLLmaBshL73tIiL/fq1o7puMeQWKbxZi0Wwp29aYNlwLoS7GDNZ2VP8DFxJM/H86xexo8jZ8IvPUqcbfIcqmwVeDBr9Hy2Im5fO+nIPHwmuq8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1557502138; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=KDWMmeXDxeYaDrbtpgauY6pAF7pSEhxca7JLZhrlUgE=; b=XohbhlGkliHKfshxbbIUoNcDeHOtXdqUpBJbrIAZ1o/XVRkfZwfBlQh6lkeisWzbLgAYgBIwnJ0KUNM5DjuqACCaOLtQ2KEZJUZiC0TY8fA4J7nvLw9a45zZvXJFSWx6iiPbSWjxBqgBWUa6exyyGPOEfRFQJmD4+TN54/2PwHs= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1557502138625354.1354596715621; Fri, 10 May 2019 08:28:58 -0700 (PDT) Received: from localhost ([127.0.0.1]:45087 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hP7Rr-00073S-57 for importer@patchew.org; Fri, 10 May 2019 11:28:35 -0400 Received: from eggs.gnu.org ([209.51.188.92]:56085) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hP7JX-0007Uw-5z for qemu-devel@nongnu.org; Fri, 10 May 2019 11:20:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hP7JV-0008Pr-CE for qemu-devel@nongnu.org; Fri, 10 May 2019 11:19:59 -0400 Received: from mail-pg1-x541.google.com ([2607:f8b0:4864:20::541]:34396) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hP7JV-0008P5-51 for qemu-devel@nongnu.org; Fri, 10 May 2019 11:19:57 -0400 Received: by mail-pg1-x541.google.com with SMTP id c13so3193942pgt.1 for ; Fri, 10 May 2019 08:19:57 -0700 (PDT) Received: from localhost.localdomain (97-113-13-231.tukw.qwest.net. [97.113.13.231]) by smtp.gmail.com with ESMTPSA id 19sm5920517pgz.24.2019.05.10.08.19.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 10 May 2019 08:19:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=KDWMmeXDxeYaDrbtpgauY6pAF7pSEhxca7JLZhrlUgE=; b=cwWa+SIwBw5dOd9/wbWsoKFwNFkrAtqi60EkVXvqjl+VKTTmnabBZj22+flfUQL0a+ YnpDT0RGjNxamlEOigRg8FJTE2qD4PSBd4HJB/Mi/PXHD/RndmFp3PokXfJOTeVQTvY9 xerrI0E2L7gQ8OM3dUtMOGuvm0o1VBEqasw70TQoK/+JIZ1WPmL6kC+3WWHbnA920h9z BkCcCycyo5/IgalVQHi7ljn9zdUe2QywL0zvEr52BduCd1aozjR2CaVIVdo2PjW8SxjH YsLlrFw0uiMLjEDLOtKxQqxUfh+JQH17XxsWq7/8uOleKbwKJBwJgnaXS33dQv+4JMHd PccQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=KDWMmeXDxeYaDrbtpgauY6pAF7pSEhxca7JLZhrlUgE=; b=isEF2AEfzIY4YlL2SFGC89Q/lFQtUvWe6S3QzV+amHKd2Iv4GjhjCjeoIuIFvJT6ok epd5hfntUIp73t4RQNfS0r0bExEMsRImKVoC855lQHQweL8cKnH0BM3PKKnwobbe43QI xkt+4v39LwQzroGIsoi3uwgojr9apg92+tp4h7LHzkeNUN3cq4ObtLgTfpSixS7HvHww nJDfPs9d9cuLbJixP4CNEpu8AeqkVTojh+bWpUwRfboKRVBvymgpgQ6Tm1f7Q3AlMyGg uddW88fcJGkloKbHqeaUp6Lrg4ATsO4N5UWNT/Ovs6JeV0cEZ7bFRZewazh8Fb94ISi4 5OHQ== X-Gm-Message-State: APjAAAV4n8R4VxRUKWm5j4ba2XChWBTfTbVxY8GQsRf5RWOYuzZkkrAo fIJtJiyjjlo5czp1+BIYn0suL6EEPEo= X-Google-Smtp-Source: APXvYqyhwn9RCuyz0s3DamSGJ13n8Rv5Swh0WxgZKo2TK4JDTfSQ4XvrD9nTHTzgPstZh2GtL3fiBQ== X-Received: by 2002:a62:5653:: with SMTP id k80mr14676038pfb.144.1557501595860; Fri, 10 May 2019 08:19:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 10 May 2019 08:19:24 -0700 Message-Id: <20190510151944.22981-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190510151944.22981-1-richard.henderson@linaro.org> References: <20190510151944.22981-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PULL 07/27] target/lm32: Convert to CPUClass::tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Michael Walle Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Cc: Michael Walle Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/lm32/cpu.h | 5 +++-- target/lm32/cpu.c | 5 ++--- target/lm32/helper.c | 12 +++++++++--- target/lm32/op_helper.c | 16 ---------------- 4 files changed, 14 insertions(+), 24 deletions(-) diff --git a/target/lm32/cpu.h b/target/lm32/cpu.h index 9b1e6c2d58..d224d4426e 100644 --- a/target/lm32/cpu.h +++ b/target/lm32/cpu.h @@ -261,8 +261,9 @@ bool lm32_cpu_do_semihosting(CPUState *cs); #define cpu_list lm32_cpu_list #define cpu_signal_handler cpu_lm32_signal_handler =20 -int lm32_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int = rw, - int mmu_idx); +bool lm32_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); =20 #include "exec/cpu-all.h" =20 diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c index 282da19994..57c50c1578 100644 --- a/target/lm32/cpu.c +++ b/target/lm32/cpu.c @@ -231,9 +231,8 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *= data) cc->set_pc =3D lm32_cpu_set_pc; cc->gdb_read_register =3D lm32_cpu_gdb_read_register; cc->gdb_write_register =3D lm32_cpu_gdb_write_register; -#ifdef CONFIG_USER_ONLY - cc->handle_mmu_fault =3D lm32_cpu_handle_mmu_fault; -#else + cc->tlb_fill =3D lm32_cpu_tlb_fill; +#ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D lm32_cpu_get_phys_page_debug; cc->vmsd =3D &vmstate_lm32_cpu; #endif diff --git a/target/lm32/helper.c b/target/lm32/helper.c index a039a993ff..1db9a5562e 100644 --- a/target/lm32/helper.c +++ b/target/lm32/helper.c @@ -25,8 +25,9 @@ #include "exec/semihost.h" #include "exec/log.h" =20 -int lm32_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int r= w, - int mmu_idx) +bool lm32_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) { LM32CPU *cpu =3D LM32_CPU(cs); CPULM32State *env =3D &cpu->env; @@ -40,8 +41,13 @@ int lm32_cpu_handle_mmu_fault(CPUState *cs, vaddr addres= s, int size, int rw, } else { tlb_set_page(cs, address, address, prot, mmu_idx, TARGET_PAGE_SIZE= ); } + return true; +} =20 - return 0; +void tlb_fill(CPUState *cs, target_ulong addr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) +{ + lm32_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr= ); } =20 hwaddr lm32_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) diff --git a/target/lm32/op_helper.c b/target/lm32/op_helper.c index 234d55e056..be12b11b02 100644 --- a/target/lm32/op_helper.c +++ b/target/lm32/op_helper.c @@ -143,21 +143,5 @@ uint32_t HELPER(rcsr_jrx)(CPULM32State *env) { return lm32_juart_get_jrx(env->juart_state); } - -/* Try to fill the TLB and return an exception if error. If retaddr is - * NULL, it means that the function was called in C code (i.e. not - * from generated code or from helper.c) - */ -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - int ret; - - ret =3D lm32_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu_idx= ); - if (unlikely(ret)) { - /* now we have a real cpu fault */ - cpu_loop_exit_restore(cs, retaddr); - } -} #endif =20 --=20 2.17.1 From nobody Tue Apr 30 04:47:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1557502488; cv=none; d=zoho.com; s=zohoarc; b=kj5t37knHkDNB6GA1LBQ4B/JS1LldFVtylIGjv8boF+ucRvYjWRA9eejwieueTYD/klrunRyQvpc9kaiFt0RjKTtVn+QUSzs270BSu86ppAAE6bs0XcqSpkthjTzDtKeIIp1VJbAVA+LoqSMzynxRWENKPowbgy3UvcsQ/rsIVM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1557502488; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=epdYlBTiLaV9VQx6jCDpGmNhfjLLlYzffabxUVX4RgQ=; b=m+uhG+vuvHW/IFoc/Al+A2crhiToxu0oWkp4scdKzX366gxlYCG1NgXux03AA4qu8X6GQHGAqo+MDG6hcSWMj5/ZIZUai4WgiftnoCT/23lF3uP7L6SRmOV5MOnuaov83RqRsdF76FVvGbRv0/e2A0lCW+cYPPrQPn32cSNe5Hg= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1557502488044451.2001604500697; Fri, 10 May 2019 08:34:48 -0700 (PDT) Received: from localhost ([127.0.0.1]:45172 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hP7Xm-0004KB-Vb for importer@patchew.org; Fri, 10 May 2019 11:34:43 -0400 Received: from eggs.gnu.org ([209.51.188.92]:56151) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hP7Jb-0007a7-LO for qemu-devel@nongnu.org; Fri, 10 May 2019 11:20:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hP7JW-0008Qr-GT for qemu-devel@nongnu.org; Fri, 10 May 2019 11:20:03 -0400 Received: from mail-pl1-x643.google.com ([2607:f8b0:4864:20::643]:39497) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hP7JW-0008QD-AH for qemu-devel@nongnu.org; Fri, 10 May 2019 11:19:58 -0400 Received: by mail-pl1-x643.google.com with SMTP id g9so2996119plm.6 for ; Fri, 10 May 2019 08:19:58 -0700 (PDT) Received: from localhost.localdomain (97-113-13-231.tukw.qwest.net. [97.113.13.231]) by smtp.gmail.com with ESMTPSA id 19sm5920517pgz.24.2019.05.10.08.19.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 10 May 2019 08:19:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=epdYlBTiLaV9VQx6jCDpGmNhfjLLlYzffabxUVX4RgQ=; b=QW0okPleQujLTUlxcqDQUK0x+NfYr1wLiEpXpUc95jvPzeKAmnCfFWeEiGzJ17qXO9 XkivkzLWsVeloBcgsnow1dBVhpJOiF69V5+QJSRs1ZLeDMZYDJKUhvx8Gsw4bxlu0McG 5xRplWCO+S2AL1ehbKIYM2ge/R7oSkPPdldZ0XkZ74+IPt2GWRg4m4YEghfH8JqqovVx lRUCOpCzWVPuMNpb82P9J+Rv/dtKRQDnQwTwd/566O1wkUAt6N4NPOJIsMToAkiD+YGI Mpyb+BQeHv4GLRaYiuJuHt6vOlGOLtRFczmnpnj7yGrQT+TQT+r0T9qE6jrjjLEUjYIQ EFFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=epdYlBTiLaV9VQx6jCDpGmNhfjLLlYzffabxUVX4RgQ=; b=UVoHpM1iFrnC0HJ3DVk3qUUcLhDdVz/cg7Uq9WW8MCutYnHcCLkT7whhiBXFHjEgUf A33lv0vh79stk/vt0vDamXMiyAIK6OdKdNGNEBiBQyVLyGy72TcB5I9Zihx9uv0fldog rGuVwiiKx18CEXBfCdQCvBMYNuR9qZOXGdENav2fomSL+FFzq6fnbREfVEhaZRSmNMY0 ZS483CFnBRUH3ifTgeK6TdmH5XJZGe0rnTrXsfcBYLkHjlXFp++3tsnr55YPT+WulQFF onjI2ffWUFyJpDnXG7EKKfltOZ8YxPdGuuH2mt1CeJTsVBjDROWkPWDR9w4Rj1sOnF1H Sr3g== X-Gm-Message-State: APjAAAWGOE+vnIpYpmEyB5wf/JjeTrYw4YAxZP5bnmaQ9XYxTOwBjYpZ ZbeljjPEc+uAKjfakri2aFYyFC9J+q0= X-Google-Smtp-Source: APXvYqwJEQayE/urDGFQ3krsMl0yjOXhIVIzbFcEoUVaidbOPXR0bgH8bVjclRdi+vn/ndWR+Fldgg== X-Received: by 2002:a17:902:f24:: with SMTP id 33mr13743282ply.33.1557501596967; Fri, 10 May 2019 08:19:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 10 May 2019 08:19:25 -0700 Message-Id: <20190510151944.22981-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190510151944.22981-1-richard.henderson@linaro.org> References: <20190510151944.22981-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 Subject: [Qemu-devel] [PULL 08/27] target/m68k: Convert to CPUClass::tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Laurent Vivier Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Cc: Laurent Vivier Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/m68k/cpu.h | 5 ++- target/m68k/cpu.c | 2 +- target/m68k/helper.c | 87 ++++++++++++++++++++++------------------- target/m68k/op_helper.c | 15 ------- 4 files changed, 50 insertions(+), 59 deletions(-) diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index ad41608341..683d3e2f79 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -542,8 +542,9 @@ static inline int cpu_mmu_index (CPUM68KState *env, boo= l ifetch) return (env->sr & SR_S) =3D=3D 0 ? 1 : 0; } =20 -int m68k_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int = rw, - int mmu_idx); +bool m68k_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); void m68k_cpu_unassigned_access(CPUState *cs, hwaddr addr, bool is_write, bool is_exec, int is_asi, unsigned size); diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 582e3a73b3..6f441bc973 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -269,7 +269,7 @@ static void m68k_cpu_class_init(ObjectClass *c, void *d= ata) cc->set_pc =3D m68k_cpu_set_pc; cc->gdb_read_register =3D m68k_cpu_gdb_read_register; cc->gdb_write_register =3D m68k_cpu_gdb_write_register; - cc->handle_mmu_fault =3D m68k_cpu_handle_mmu_fault; + cc->tlb_fill =3D m68k_cpu_tlb_fill; #if defined(CONFIG_SOFTMMU) cc->do_unassigned_access =3D m68k_cpu_unassigned_access; cc->get_phys_page_debug =3D m68k_cpu_get_phys_page_debug; diff --git a/target/m68k/helper.c b/target/m68k/helper.c index d958a34959..862f955f7b 100644 --- a/target/m68k/helper.c +++ b/target/m68k/helper.c @@ -353,20 +353,7 @@ void m68k_switch_sp(CPUM68KState *env) env->current_sp =3D new_sp; } =20 -#if defined(CONFIG_USER_ONLY) - -int m68k_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int r= w, - int mmu_idx) -{ - M68kCPU *cpu =3D M68K_CPU(cs); - - cs->exception_index =3D EXCP_ACCESS; - cpu->env.mmu.ar =3D address; - return 1; -} - -#else - +#if !defined(CONFIG_USER_ONLY) /* MMU: 68040 only */ =20 static void print_address_zone(uint32_t logical, uint32_t physical, @@ -795,11 +782,36 @@ hwaddr m68k_cpu_get_phys_page_debug(CPUState *cs, vad= dr addr) return phys_addr; } =20 -int m68k_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int r= w, - int mmu_idx) +/* + * Notify CPU of a pending interrupt. Prioritization and vectoring should + * be handled by the interrupt controller. Real hardware only requests + * the vector when the interrupt is acknowledged by the CPU. For + * simplicity we calculate it when the interrupt is signalled. + */ +void m68k_set_irq_level(M68kCPU *cpu, int level, uint8_t vector) +{ + CPUState *cs =3D CPU(cpu); + CPUM68KState *env =3D &cpu->env; + + env->pending_level =3D level; + env->pending_vector =3D vector; + if (level) { + cpu_interrupt(cs, CPU_INTERRUPT_HARD); + } else { + cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); + } +} + +#endif + +bool m68k_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType qemu_access_type, int mmu_idx, + bool probe, uintptr_t retaddr) { M68kCPU *cpu =3D M68K_CPU(cs); CPUM68KState *env =3D &cpu->env; + +#ifndef CONFIG_USER_ONLY hwaddr physical; int prot; int access_type; @@ -812,32 +824,35 @@ int m68k_cpu_handle_mmu_fault(CPUState *cs, vaddr add= ress, int size, int rw, address & TARGET_PAGE_MASK, PAGE_READ | PAGE_WRITE | PAGE_EXEC, mmu_idx, TARGET_PAGE_SIZE); - return 0; + return true; } =20 - if (rw =3D=3D 2) { + if (qemu_access_type =3D=3D MMU_INST_FETCH) { access_type =3D ACCESS_CODE; - rw =3D 0; } else { access_type =3D ACCESS_DATA; - if (rw) { + if (qemu_access_type =3D=3D MMU_DATA_STORE) { access_type |=3D ACCESS_STORE; } } - if (mmu_idx !=3D MMU_USER_IDX) { access_type |=3D ACCESS_SUPER; } =20 ret =3D get_physical_address(&cpu->env, &physical, &prot, address, access_type, &page_size); - if (ret =3D=3D 0) { + if (likely(ret =3D=3D 0)) { address &=3D TARGET_PAGE_MASK; physical +=3D address & (page_size - 1); tlb_set_page(cs, address, physical, prot, mmu_idx, TARGET_PAGE_SIZE); - return 0; + return true; } + + if (probe) { + return false; + } + /* page fault */ env->mmu.ssw =3D M68K_ATC_040; switch (size) { @@ -862,29 +877,19 @@ int m68k_cpu_handle_mmu_fault(CPUState *cs, vaddr add= ress, int size, int rw, if (!(access_type & ACCESS_STORE)) { env->mmu.ssw |=3D M68K_RW_040; } - env->mmu.ar =3D address; +#endif + cs->exception_index =3D EXCP_ACCESS; - return 1; + env->mmu.ar =3D address; + cpu_loop_exit_restore(cs, retaddr); } =20 -/* Notify CPU of a pending interrupt. Prioritization and vectoring should - be handled by the interrupt controller. Real hardware only requests - the vector when the interrupt is acknowledged by the CPU. For - simplicitly we calculate it when the interrupt is signalled. */ -void m68k_set_irq_level(M68kCPU *cpu, int level, uint8_t vector) +#ifndef CONFIG_USER_ONLY +void tlb_fill(CPUState *cs, target_ulong addr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) { - CPUState *cs =3D CPU(cpu); - CPUM68KState *env =3D &cpu->env; - - env->pending_level =3D level; - env->pending_vector =3D vector; - if (level) { - cpu_interrupt(cs, CPU_INTERRUPT_HARD); - } else { - cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); - } + m68k_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr= ); } - #endif =20 uint32_t HELPER(bitrev)(uint32_t x) diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c index 76f439985a..d421614727 100644 --- a/target/m68k/op_helper.c +++ b/target/m68k/op_helper.c @@ -36,21 +36,6 @@ static inline void do_interrupt_m68k_hardirq(CPUM68KStat= e *env) =20 #else =20 -/* Try to fill the TLB and return an exception if error. If retaddr is - NULL, it means that the function was called in C code (i.e. not - from generated code or from helper.c) */ -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - int ret; - - ret =3D m68k_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu_idx= ); - if (unlikely(ret)) { - /* now we have a real cpu fault */ - cpu_loop_exit_restore(cs, retaddr); - } -} - static void cf_rte(CPUM68KState *env) { uint32_t sp; --=20 2.17.1 From nobody Tue Apr 30 04:47:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1557502684; cv=none; d=zoho.com; s=zohoarc; b=FsmQ0DJ5ICoCG2afL4SLRsha5EvSUb7KnDTa3EExX0vKnHBmLMwRJcXdIsji9QuF3AfNNDhF4+oICJ7Wfecw9mU9/FbmMn+D0o76JbYhxTQx1bpfTMEDOuOnM2SmV0OtEXjAqGF5cpKQamAZm8uwp2oGhGz/T1DyBy3LVzmrgpw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1557502684; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=+7y06FOuP0C5aG2mOuHskCnd9OAXBDISnnNJ70hVpew=; b=fe8F35Uju13PQiGKdmYuYWmJjGjlF1BucblZWeC0S+CHYNgMpTsPhjnxuT5LvV2a2K9PxemYxV3brZvOum9xtQ6cNIl38lOV24TpYZo4hCetMi92KFifQUVLn9zf2AymH5wFqepCqARvosPkmw2hUouWf2ywea/yGyOTbJMUcEY= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1557502684114639.3707407626604; Fri, 10 May 2019 08:38:04 -0700 (PDT) Received: from localhost ([127.0.0.1]:45232 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hP7az-00084M-2B for importer@patchew.org; Fri, 10 May 2019 11:38:01 -0400 Received: from eggs.gnu.org ([209.51.188.92]:56111) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hP7JZ-0007Wl-2z for qemu-devel@nongnu.org; Fri, 10 May 2019 11:20:02 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hP7JX-0008Rr-QJ for qemu-devel@nongnu.org; Fri, 10 May 2019 11:20:01 -0400 Received: from mail-pg1-x543.google.com ([2607:f8b0:4864:20::543]:34398) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hP7JX-0008RI-Id for qemu-devel@nongnu.org; Fri, 10 May 2019 11:19:59 -0400 Received: by mail-pg1-x543.google.com with SMTP id c13so3193993pgt.1 for ; Fri, 10 May 2019 08:19:59 -0700 (PDT) Received: from localhost.localdomain (97-113-13-231.tukw.qwest.net. [97.113.13.231]) by smtp.gmail.com with ESMTPSA id 19sm5920517pgz.24.2019.05.10.08.19.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 10 May 2019 08:19:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=+7y06FOuP0C5aG2mOuHskCnd9OAXBDISnnNJ70hVpew=; b=E72R3Yj6L0iATHOIucHI0+wjwGaoWYGUrNwMcXXPNSfClCB2moQ6KZDoLfHsE4CdVV vQOf0yqiG3KB6R3+uABaT6aSTxM40NF6Jt5mtvCvfcLwPcjK9p6DLJa0HaO0dWS5zbKQ Lbm6EysukqLqcXV2Nm89MCtCBerMMtxkv5/bKiqiHh5OQ4yYTMp+8wuMUv9uWlH/4M++ CC7SZQZt8z/3NWreg4k56aL7JFiWcxBsQUMWUDVNSrPmkbuHE4effcsVWnYs7vHZbZro r/G80eL/L8W6q4Ko94at055OEtMdp7ZXXc7CSEH4tYN6yj+sFjbbZum4vOgQ3EkLKZ8N RCGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=+7y06FOuP0C5aG2mOuHskCnd9OAXBDISnnNJ70hVpew=; b=YkS6UYb8915lBDqpINd628XEeOSFmQxqiqnk7ZAgCoxEwURyjjKOmsUUrcxl6XKLdX jNqGGKcwCXWOn00FS4nbi90EmeOurP7mp6O22bzEAXIknqjfIbGvUG4BpBLpgE6HBcw6 Adp0JAqrO9weABZqymMx1z4yQatt/fHEE/tM48VBUrUvSAnzd+7CrzXyM/D3RVCeOTy5 XldNIv1y6rw68JFrTRWAOJYnET8RaZl5J4bphxDmYnCaZRSI3+ja3y9X4S9piSIi+iR5 Ok+iiRHy4I8TpdwTM/ZON7VG9U0NjLPvsaTKt95nmSVodKIka4jNPhySqiXdVpIGc7Pl pYkQ== X-Gm-Message-State: APjAAAWIcQtVXF1mqCnyBvoenrnDZWDnB7gFWgDg+EJTJu7IAyGclQcW 5TPg828Pu2PjI0SCoKk8vcZsuG5foTI= X-Google-Smtp-Source: APXvYqwkLAKs07ynckfyAybJNT4TyouwMrR2le66x2vrTYD9gCFSMN/KBae/gHSv7aNN55OKQhOWMg== X-Received: by 2002:a62:6444:: with SMTP id y65mr15063612pfb.148.1557501598314; Fri, 10 May 2019 08:19:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 10 May 2019 08:19:26 -0700 Message-Id: <20190510151944.22981-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190510151944.22981-1-richard.henderson@linaro.org> References: <20190510151944.22981-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 Subject: [Qemu-devel] [PULL 09/27] target/microblaze: Convert to CPUClass::tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, "Edgar E . Iglesias" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Cc: Edgar E. Iglesias Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 5 +- target/microblaze/cpu.c | 5 +- target/microblaze/helper.c | 107 ++++++++++++++++++---------------- target/microblaze/op_helper.c | 19 ------ 4 files changed, 62 insertions(+), 74 deletions(-) diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index f20e796865..7a9fb8f4aa 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -374,8 +374,9 @@ static inline int cpu_mmu_index (CPUMBState *env, bool = ifetch) return MMU_KERNEL_IDX; } =20 -int mb_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int rw, - int mmu_idx); +bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); =20 #include "exec/cpu-all.h" =20 diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 5596cd5485..0ea549910b 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -304,9 +304,8 @@ static void mb_cpu_class_init(ObjectClass *oc, void *da= ta) cc->set_pc =3D mb_cpu_set_pc; cc->gdb_read_register =3D mb_cpu_gdb_read_register; cc->gdb_write_register =3D mb_cpu_gdb_write_register; -#ifdef CONFIG_USER_ONLY - cc->handle_mmu_fault =3D mb_cpu_handle_mmu_fault; -#else + cc->tlb_fill =3D mb_cpu_tlb_fill; +#ifndef CONFIG_USER_ONLY cc->do_transaction_failed =3D mb_cpu_transaction_failed; cc->get_phys_page_debug =3D mb_cpu_get_phys_page_debug; #endif diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index 9848e31d7f..a523c77959 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -38,73 +38,80 @@ void mb_cpu_do_interrupt(CPUState *cs) env->regs[14] =3D env->sregs[SR_PC]; } =20 -int mb_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw, - int mmu_idx) +bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) { cs->exception_index =3D 0xaa; - cpu_dump_state(cs, stderr, 0); - return 1; + cpu_loop_exit_restore(cs, retaddr); } =20 #else /* !CONFIG_USER_ONLY */ =20 -int mb_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw, - int mmu_idx) +bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) { MicroBlazeCPU *cpu =3D MICROBLAZE_CPU(cs); CPUMBState *env =3D &cpu->env; + struct microblaze_mmu_lookup lu; unsigned int hit; - int r =3D 1; int prot; =20 - /* Translate if the MMU is available and enabled. */ - if (mmu_idx !=3D MMU_NOMMU_IDX) { - uint32_t vaddr, paddr; - struct microblaze_mmu_lookup lu; - - hit =3D mmu_translate(&env->mmu, &lu, address, rw, mmu_idx); - if (hit) { - vaddr =3D address & TARGET_PAGE_MASK; - paddr =3D lu.paddr + vaddr - lu.vaddr; - - qemu_log_mask(CPU_LOG_MMU, "MMU map mmu=3D%d v=3D%x p=3D%x pro= t=3D%x\n", - mmu_idx, vaddr, paddr, lu.prot); - tlb_set_page(cs, vaddr, paddr, lu.prot, mmu_idx, TARGET_PAGE_S= IZE); - r =3D 0; - } else { - env->sregs[SR_EAR] =3D address; - qemu_log_mask(CPU_LOG_MMU, "mmu=3D%d miss v=3D%" VADDR_PRIx "\= n", - mmu_idx, address); - - switch (lu.err) { - case ERR_PROT: - env->sregs[SR_ESR] =3D rw =3D=3D 2 ? 17 : 16; - env->sregs[SR_ESR] |=3D (rw =3D=3D 1) << 10; - break; - case ERR_MISS: - env->sregs[SR_ESR] =3D rw =3D=3D 2 ? 19 : 18; - env->sregs[SR_ESR] |=3D (rw =3D=3D 1) << 10; - break; - default: - abort(); - break; - } - - if (cs->exception_index =3D=3D EXCP_MMU) { - cpu_abort(cs, "recursive faults\n"); - } - - /* TLB miss. */ - cs->exception_index =3D EXCP_MMU; - } - } else { + if (mmu_idx =3D=3D MMU_NOMMU_IDX) { /* MMU disabled or not available. */ address &=3D TARGET_PAGE_MASK; prot =3D PAGE_BITS; tlb_set_page(cs, address, address, prot, mmu_idx, TARGET_PAGE_SIZE= ); - r =3D 0; + return true; } - return r; + + hit =3D mmu_translate(&env->mmu, &lu, address, access_type, mmu_idx); + if (likely(hit)) { + uint32_t vaddr =3D address & TARGET_PAGE_MASK; + uint32_t paddr =3D lu.paddr + vaddr - lu.vaddr; + + qemu_log_mask(CPU_LOG_MMU, "MMU map mmu=3D%d v=3D%x p=3D%x prot=3D= %x\n", + mmu_idx, vaddr, paddr, lu.prot); + tlb_set_page(cs, vaddr, paddr, lu.prot, mmu_idx, TARGET_PAGE_SIZE); + return true; + } + + /* TLB miss. */ + if (probe) { + return false; + } + + qemu_log_mask(CPU_LOG_MMU, "mmu=3D%d miss v=3D%" VADDR_PRIx "\n", + mmu_idx, address); + + env->sregs[SR_EAR] =3D address; + switch (lu.err) { + case ERR_PROT: + env->sregs[SR_ESR] =3D access_type =3D=3D MMU_INST_FETCH ? 17 : 16; + env->sregs[SR_ESR] |=3D (access_type =3D=3D MMU_DATA_STORE) << 10; + break; + case ERR_MISS: + env->sregs[SR_ESR] =3D access_type =3D=3D MMU_INST_FETCH ? 19 : 18; + env->sregs[SR_ESR] |=3D (access_type =3D=3D MMU_DATA_STORE) << 10; + break; + default: + abort(); + } + + if (cs->exception_index =3D=3D EXCP_MMU) { + cpu_abort(cs, "recursive faults\n"); + } + + /* TLB miss. */ + cs->exception_index =3D EXCP_MMU; + cpu_loop_exit_restore(cs, retaddr); +} + +void tlb_fill(CPUState *cs, target_ulong addr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) +{ + mb_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); } =20 void mb_cpu_do_interrupt(CPUState *cs) diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index e23dcfdc20..b5dbb90d05 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -28,25 +28,6 @@ =20 #define D(x) =20 -#if !defined(CONFIG_USER_ONLY) - -/* Try to fill the TLB and return an exception if error. If retaddr is - * NULL, it means that the function was called in C code (i.e. not - * from generated code or from helper.c) - */ -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - int ret; - - ret =3D mb_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu_idx); - if (unlikely(ret)) { - /* now we have a real cpu fault */ - cpu_loop_exit_restore(cs, retaddr); - } -} -#endif - void helper_put(uint32_t id, uint32_t ctrl, uint32_t data) { int test =3D ctrl & STREAM_TEST; --=20 2.17.1 From nobody Tue Apr 30 04:47:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1557502056; cv=none; d=zoho.com; s=zohoarc; b=Ffk12rsxx9FqZ0tyDEGKGAKdRIbWtyFZL0HTJXjHXEbI6hZ4Q2wq4aqJufAryq+rIXRn+rbuBCYfFNsYzw4y7qiyD3LDtV6i4GZFkRQhQwaDquuJXz1e4nauWvZgHwDj/GSJEyC1Czzc38rp77XmO2OQrgvGDNFnhxkEg4yxvy8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1557502056; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=9CI4oI1nkvf0QxqoUGGat3a67tCPvWsOkb0Ljyg5Gsk=; b=UqVh7PMHnjS7wFYcdjuNEeCkCs/f7SZh92c0jy1lAVzxLCVk5afSsZ10htBQb8sBw+uieyYHCVllrDUTHSQJ9BBIwJIL/gJl1xZik6YpMdd1VAM414ga1QEgYKymP10CZjj304JIfAYfW6UXwi7gyeotNzfu/PtxZA3iC8cGob8= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1557502056146194.42691647228878; Fri, 10 May 2019 08:27:36 -0700 (PDT) Received: from localhost ([127.0.0.1]:45083 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hP7Qo-0005xl-0X for importer@patchew.org; Fri, 10 May 2019 11:27:30 -0400 Received: from eggs.gnu.org ([209.51.188.92]:56117) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hP7JZ-0007XE-K9 for qemu-devel@nongnu.org; Fri, 10 May 2019 11:20:02 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hP7JY-0008SO-P6 for qemu-devel@nongnu.org; Fri, 10 May 2019 11:20:01 -0400 Received: from mail-pl1-x643.google.com ([2607:f8b0:4864:20::643]:37514) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hP7JY-0008S4-JS for qemu-devel@nongnu.org; Fri, 10 May 2019 11:20:00 -0400 Received: by mail-pl1-x643.google.com with SMTP id p15so2989743pll.4 for ; Fri, 10 May 2019 08:20:00 -0700 (PDT) Received: from localhost.localdomain (97-113-13-231.tukw.qwest.net. [97.113.13.231]) by smtp.gmail.com with ESMTPSA id 19sm5920517pgz.24.2019.05.10.08.19.58 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 10 May 2019 08:19:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9CI4oI1nkvf0QxqoUGGat3a67tCPvWsOkb0Ljyg5Gsk=; b=VYt0RnZxKpvBAVDDq+CSEzv1d+0RsSm14ybtttKdZcKmfPqzLP9hTO8PkVhwRZfQH9 NPJOUOLrBnJMMTDgbiL554bpG3is/VcICqhg61Ht1xoO6UWB4DzdnZjF7eAQrU8syDBn 5XUJS1SH9igwOLgmeaneDwPsOYuAbpxtW19uOpoEwZTVvInlP3Y4ou0x2mJU6FQIWIN+ c3LWgUHqtgJ1NQc79QPfk7y4prtLBzBwWMXNpzaZhKTfEvNtBT/bhostrEpshrW/fsZH GSMzeafEXIAiH0TAB27iw+au7l5b0DNZJ7Q+z+Rpdk+MZr+Q5h122BVpiRxxjM5TQyEA u0pA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9CI4oI1nkvf0QxqoUGGat3a67tCPvWsOkb0Ljyg5Gsk=; b=uoIbIqrnuQRoXL5F0xFTkN2GP7gXxErJz3GPu1GWI8gL6CeprK6K/fyD/SSOneHqDP ZTpn6uO3CiXK6rn8F7klWSmOXwIvoOjxGauiPIB9TDX89HroTQVBcdmidbiZgPCH6W6k SWPoklfQYJSAFsdwYd3yLYvA1q3gwEgw41SSJcoDL+JCOI84usYyBc9xXF+pBktUEsup /DL4DMaPFscDvSUaZjsqG1G78zvaHsMBKefkIfkTuwC7r6OnKoeAfGFpHhZxRPStEfo+ +uOEqyQNH3zYlDBVw71EH+HgN5VOgs3zb1kOp0PdCJ527zLJ3JYG15ZGrVm9nu1X1fcP z80Q== X-Gm-Message-State: APjAAAV+p7oQy0YTBjg/pvVESrZ3PreW3fcfx95HnbbcqGJ2qinUGX+J RfyuY2jPhfUeoljrzQrBhSAaywjos2E= X-Google-Smtp-Source: APXvYqwMikYWQRQnVt46USr7TusNbzq874CTk8I3vZQ2+X4xwVVDMmeEwT5DEDuuuOW8qx13ajaToA== X-Received: by 2002:a17:902:b606:: with SMTP id b6mr14084714pls.100.1557501599442; Fri, 10 May 2019 08:19:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 10 May 2019 08:19:27 -0700 Message-Id: <20190510151944.22981-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190510151944.22981-1-richard.henderson@linaro.org> References: <20190510151944.22981-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 Subject: [Qemu-devel] [PULL 10/27] target/mips: Pass a valid error to raise_mmu_exception for user-only X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) At present we give ret =3D 0, or TLBRET_MATCH. This gets matched by the default case, which falls through to TLBRET_BADADDR. However, it makes more sense to use a proper value. All of the tlb-related exceptions are handled identically in cpu_loop.c, so TLBRET_BADADDR is as good as any other. Retain it. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/mips/helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/mips/helper.c b/target/mips/helper.c index c44cdca3b5..cc7be7703a 100644 --- a/target/mips/helper.c +++ b/target/mips/helper.c @@ -884,7 +884,7 @@ int mips_cpu_handle_mmu_fault(CPUState *cs, vaddr addre= ss, int size, int rw, int prot; int access_type; #endif - int ret =3D 0; + int ret =3D TLBRET_BADADDR; =20 #if 0 log_cpu_state(cs, 0); --=20 2.17.1 From nobody Tue Apr 30 04:47:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1557502825; cv=none; d=zoho.com; s=zohoarc; b=W418untcek8iupHbGMeWGkk5MXKEfP3PIXRLR2lQznjF7b0Av/NzxGRhQZn/rhVvfHTCfUQLQTrnkYkZU1PKB9JBBv8LbQtTEo45VkmkbHO1wRoCAN5ySU2Ar8diU6Bk3Uk6AdbPIIiahQQyVnjJcc/oeepM9LfwGYUM10XzIDE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1557502825; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=ZTH91pjxahUuQtOu1GsBhTY4d5CvJ+Jx8ktGJV35Xwc=; b=Wm1qTlHfOe0yJUwJbzLsKmKGsLYlZHHsu48M1PbPOJSP/h2QnDajz6PH5FCLxgMIK0gsI9lk9nosOhRQjKQnNgDCnjv1IukpZzx6JpikRDtjfC8GTSloUqMksl4+trAU3A4NrUrjo2pYFmUXVw94xDiTadp+gZCnSRBXk2FEwlA= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1557502825653431.0215862528411; Fri, 10 May 2019 08:40:25 -0700 (PDT) Received: from localhost ([127.0.0.1]:45252 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hP7dF-0001TN-L4 for importer@patchew.org; Fri, 10 May 2019 11:40:21 -0400 Received: from eggs.gnu.org ([209.51.188.92]:56141) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hP7Ja-0007ZR-UZ for qemu-devel@nongnu.org; Fri, 10 May 2019 11:20:07 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hP7JZ-0008TR-UA for qemu-devel@nongnu.org; Fri, 10 May 2019 11:20:02 -0400 Received: from mail-pl1-x642.google.com ([2607:f8b0:4864:20::642]:33570) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hP7JZ-0008T0-OK for qemu-devel@nongnu.org; Fri, 10 May 2019 11:20:01 -0400 Received: by mail-pl1-x642.google.com with SMTP id y3so2996738plp.0 for ; Fri, 10 May 2019 08:20:01 -0700 (PDT) Received: from localhost.localdomain (97-113-13-231.tukw.qwest.net. [97.113.13.231]) by smtp.gmail.com with ESMTPSA id 19sm5920517pgz.24.2019.05.10.08.19.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 10 May 2019 08:19:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ZTH91pjxahUuQtOu1GsBhTY4d5CvJ+Jx8ktGJV35Xwc=; b=joA0AKXMyY3BQHcLx+GIcFgwz5GAZXfeA6hScCTEGYm+l8g/J3oJ/9zSx4nkGZhpNP VMwK5+W80PXW/S5ibRy8IsqlAhRkXqiIJpdg62esSFrhEh4A2i3WnT8dmSg7XXxd1+bD RzRYknUv8/4TW/bJ0Mc84KniF17SsHKY0BuE0OI54cEkYrrMQo7bRrAOtG8xbv6kEzjW VrLTDb9VS2l17s3Gm+P35XC6xLzDAswPgLTxkEat1EgWdltbEHr2RVAUehQKHjkPUq61 gng319gUdWUGrPkGtLaMN0a/Oef/AxSGXZ3cx/KrUPNssnnCkS5dnmITL77q18WiNH3P HXAQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZTH91pjxahUuQtOu1GsBhTY4d5CvJ+Jx8ktGJV35Xwc=; b=Zp9D8pGgkoXZJaRp/y7lixzK58AT8C5j8/uiCo6PaZ4Po7qu02XIJD1K6vPO+zPPe6 wHFDTv3svmuexvvpyiGbMqlDLlMXUnaAkYPrxzHF38oYmQ6Z9gXQoUJfDnDACReoJJR8 Ox5uIo0iKA4rp9Q1FPA2haraCjV5ApJ3grzRvlH6s0KMJB+/Y5r2AjXqxA4u1C+7ViIb 759MT0THBLYtINmrYOTXLXhtwcGxsz34Tc3dPrphSvPnvLEDhLKIOvUlyyMlCumi2p2N 8uMhi7EXop8qC5AcUdQeorjEEjaw3ECBwv04PhROFDTybpmO8JFVNy7RV75A1n6RGp0W 7E5A== X-Gm-Message-State: APjAAAVzjGNUTYs4zETs19e0BvWvo4R7QBj8k1qFe3+bd09MAaPM2N0a lnTNftYVyS1Pm+0L4cbYHhgZ+6SikZU= X-Google-Smtp-Source: APXvYqxcmPKsQZu2RE9oM1IBIoXwq7JfTPjP+7/Bcbro2GhiTPUQ2IkF8fohSU5y/kf8uGNLFaADfw== X-Received: by 2002:a17:902:7883:: with SMTP id q3mr13718857pll.60.1557501600552; Fri, 10 May 2019 08:20:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 10 May 2019 08:19:28 -0700 Message-Id: <20190510151944.22981-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190510151944.22981-1-richard.henderson@linaro.org> References: <20190510151944.22981-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::642 Subject: [Qemu-devel] [PULL 11/27] target/mips: Tidy control flow in mips_cpu_handle_mmu_fault X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Since the only non-negative TLBRET_* value is TLBRET_MATCH, the subsequent test for ret < 0 is useless. Use early return to allow subsequent blocks to be unindented. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/mips/helper.c | 54 ++++++++++++++++++++------------------------ 1 file changed, 24 insertions(+), 30 deletions(-) diff --git a/target/mips/helper.c b/target/mips/helper.c index cc7be7703a..86e622efb8 100644 --- a/target/mips/helper.c +++ b/target/mips/helper.c @@ -915,41 +915,35 @@ int mips_cpu_handle_mmu_fault(CPUState *cs, vaddr add= ress, int size, int rw, tlb_set_page(cs, address & TARGET_PAGE_MASK, physical & TARGET_PAGE_MASK, prot | PAGE_EXEC, mmu_idx, TARGET_PAGE_SIZE); - ret =3D 0; - } else if (ret < 0) -#endif - { -#if !defined(CONFIG_USER_ONLY) + return 0; + } #if !defined(TARGET_MIPS64) - if ((ret =3D=3D TLBRET_NOMATCH) && (env->tlb->nb_tlb > 1)) { - /* - * Memory reads during hardware page table walking are perform= ed - * as if they were kernel-mode load instructions. - */ - int mode =3D (env->hflags & MIPS_HFLAG_KSU); - bool ret_walker; - env->hflags &=3D ~MIPS_HFLAG_KSU; - ret_walker =3D page_table_walk_refill(env, address, rw, mmu_id= x); - env->hflags |=3D mode; - if (ret_walker) { - ret =3D get_physical_address(env, &physical, &prot, - address, rw, access_type, mmu_i= dx); - if (ret =3D=3D TLBRET_MATCH) { - tlb_set_page(cs, address & TARGET_PAGE_MASK, - physical & TARGET_PAGE_MASK, prot | PAGE_EXEC, - mmu_idx, TARGET_PAGE_SIZE); - ret =3D 0; - return ret; - } + if ((ret =3D=3D TLBRET_NOMATCH) && (env->tlb->nb_tlb > 1)) { + /* + * Memory reads during hardware page table walking are performed + * as if they were kernel-mode load instructions. + */ + int mode =3D (env->hflags & MIPS_HFLAG_KSU); + bool ret_walker; + env->hflags &=3D ~MIPS_HFLAG_KSU; + ret_walker =3D page_table_walk_refill(env, address, rw, mmu_idx); + env->hflags |=3D mode; + if (ret_walker) { + ret =3D get_physical_address(env, &physical, &prot, + address, rw, access_type, mmu_idx); + if (ret =3D=3D TLBRET_MATCH) { + tlb_set_page(cs, address & TARGET_PAGE_MASK, + physical & TARGET_PAGE_MASK, prot | PAGE_EXEC, + mmu_idx, TARGET_PAGE_SIZE); + return 0; } } -#endif -#endif - raise_mmu_exception(env, address, rw, ret); - ret =3D 1; } +#endif +#endif =20 - return ret; + raise_mmu_exception(env, address, rw, ret); + return 1; } =20 #if !defined(CONFIG_USER_ONLY) --=20 2.17.1 From nobody Tue Apr 30 04:47:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1557501962; cv=none; d=zoho.com; s=zohoarc; b=BFBWQoMhY2j+5BsX0cq3/InTiz1kwEJhbxWz4KZDgB572Lth5aout5x9393xflsnPA7Hn4JP6f5kI4UZ4nhadLSqOohzTTVL16QpxnZPXBsHcBeoFN2ElBgvTyu0khacVP92IVzLHbsOIVgPgIHXmvET/vnhJSMjYon/m+3JZLA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; 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[97.113.13.231]) by smtp.gmail.com with ESMTPSA id 19sm5920517pgz.24.2019.05.10.08.20.00 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 10 May 2019 08:20:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8AceDIzAKZ/IbsaMhEPVD0M5uShF47/3BlNlJvJR/2s=; b=hGjmaRZJ6SsroPsebkbxKe+CgoX8Ue3qK9qGRzCpeZx5LwtcCQjsp0Cevvq87jIwyM gdkFEP/UmiQ53GERO+lHAylJwhcMJqar83e2DCcXs3A0S3lF/4/i4XhuhTIAbJUTI5B5 WaCHyfDBEBp9aWX5dW+ZWsNlXV6Ok+cw5P7RI2IFa8Ggq6IhHFB77gCTSjkVEb+SqIps nlPzWjMQeNmsOhJbNniXC8rxy7O65GbAAnZT4l2OZFullsBn8IJjiokkpiCIA64vzTvl RKlkOM7NM4XOE7DVwjuLIqzZluK993mAX+jgKueRj3JO/IewQDVo1MsxWKSrZlrnq82J NuMg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8AceDIzAKZ/IbsaMhEPVD0M5uShF47/3BlNlJvJR/2s=; b=A6R8mfD82G/GlINyL41MDV0YF3UBzjffQ/iny8+xX7G2Sb12gURJoaGttk9Tznjhfr ADA/zew0fmAKykzYAjISvRZEvYtnT1hZFdfCU68g+NKueDXQsOs5C+zWQL9/im6+rGLF 8YE1GjlzivDjZcvulweZwf6r6IqrKQOxrXt8BMgViKYkJgHA5/oYCW0MJntIGm0zAhQ5 tFOjmQPx9hW7UGvCLge58F2hoXburRrV4k5ELG7OFv1tKIegP8cmNmtiJyfKE75iEY34 a0W6MYuQqlCOieOxstgPADJ0+wki085jHKbxgBFiyPGShk4OGtNSf4ILEQOQf99Qq7uD oa7A== X-Gm-Message-State: APjAAAU9S1FP8v+XWgzaWsNo277iGRIKewO3SkQ65iwsFzElw9IwWTsG iBHB1t3KwrxT6MWLVfBn0kZ9VFBRWsw= X-Google-Smtp-Source: APXvYqziFxkG1iSiHSx2GDCr/LoIWeQCbM1Ti5+JfAMgELPakf9l+1/TPX1ybX5D0+K/iwLiyJPyuA== X-Received: by 2002:a17:902:7c93:: with SMTP id y19mr13688072pll.55.1557501601785; Fri, 10 May 2019 08:20:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 10 May 2019 08:19:29 -0700 Message-Id: <20190510151944.22981-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190510151944.22981-1-richard.henderson@linaro.org> References: <20190510151944.22981-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 Subject: [Qemu-devel] [PULL 12/27] target/mips: Convert to CPUClass::tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Rikalo , peter.maydell@linaro.org, Aleksandar Markovic Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Note that env->active_tc.PC is removed from the qemu_log as that value is garbage. The PC isn't recovered until cpu_restore_state, called from cpu_loop_exit_restore, called from do_raise_exception_err. Cc: Aleksandar Markovic Cc: Aleksandar Rikalo Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/mips/internal.h | 5 +++-- target/mips/cpu.c | 5 ++--- target/mips/helper.c | 45 ++++++++++++++++++++++------------------- target/mips/op_helper.c | 15 -------------- 4 files changed, 29 insertions(+), 41 deletions(-) diff --git a/target/mips/internal.h b/target/mips/internal.h index 286e3888ab..b2b41a51ab 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -202,8 +202,9 @@ void cpu_mips_start_count(CPUMIPSState *env); void cpu_mips_stop_count(CPUMIPSState *env); =20 /* helper.c */ -int mips_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int = rw, - int mmu_idx); +bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); =20 /* op_helper.c */ uint32_t float_class_s(uint32_t arg, float_status *fst); diff --git a/target/mips/cpu.c b/target/mips/cpu.c index e217fb3e36..ebdb834b97 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -197,9 +197,8 @@ static void mips_cpu_class_init(ObjectClass *c, void *d= ata) cc->synchronize_from_tb =3D mips_cpu_synchronize_from_tb; cc->gdb_read_register =3D mips_cpu_gdb_read_register; cc->gdb_write_register =3D mips_cpu_gdb_write_register; -#ifdef CONFIG_USER_ONLY - cc->handle_mmu_fault =3D mips_cpu_handle_mmu_fault; -#else + cc->tlb_fill =3D mips_cpu_tlb_fill; +#ifndef CONFIG_USER_ONLY cc->do_unassigned_access =3D mips_cpu_unassigned_access; cc->do_unaligned_access =3D mips_cpu_do_unaligned_access; cc->get_phys_page_debug =3D mips_cpu_get_phys_page_debug; diff --git a/target/mips/helper.c b/target/mips/helper.c index 86e622efb8..3a4917ce7b 100644 --- a/target/mips/helper.c +++ b/target/mips/helper.c @@ -874,31 +874,25 @@ refill: #endif #endif =20 -int mips_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int r= w, - int mmu_idx) +bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) { MIPSCPU *cpu =3D MIPS_CPU(cs); CPUMIPSState *env =3D &cpu->env; #if !defined(CONFIG_USER_ONLY) hwaddr physical; int prot; - int access_type; + int mips_access_type; #endif int ret =3D TLBRET_BADADDR; =20 -#if 0 - log_cpu_state(cs, 0); -#endif - qemu_log_mask(CPU_LOG_MMU, - "%s pc " TARGET_FMT_lx " ad %" VADDR_PRIx " rw %d mmu_idx %d= \n", - __func__, env->active_tc.PC, address, rw, mmu_idx); - /* data access */ #if !defined(CONFIG_USER_ONLY) /* XXX: put correct access by using cpu_restore_state() correctly */ - access_type =3D ACCESS_INT; - ret =3D get_physical_address(env, &physical, &prot, - address, rw, access_type, mmu_idx); + mips_access_type =3D ACCESS_INT; + ret =3D get_physical_address(env, &physical, &prot, address, + access_type, mips_access_type, mmu_idx); switch (ret) { case TLBRET_MATCH: qemu_log_mask(CPU_LOG_MMU, @@ -915,7 +909,7 @@ int mips_cpu_handle_mmu_fault(CPUState *cs, vaddr addre= ss, int size, int rw, tlb_set_page(cs, address & TARGET_PAGE_MASK, physical & TARGET_PAGE_MASK, prot | PAGE_EXEC, mmu_idx, TARGET_PAGE_SIZE); - return 0; + return true; } #if !defined(TARGET_MIPS64) if ((ret =3D=3D TLBRET_NOMATCH) && (env->tlb->nb_tlb > 1)) { @@ -926,27 +920,36 @@ int mips_cpu_handle_mmu_fault(CPUState *cs, vaddr add= ress, int size, int rw, int mode =3D (env->hflags & MIPS_HFLAG_KSU); bool ret_walker; env->hflags &=3D ~MIPS_HFLAG_KSU; - ret_walker =3D page_table_walk_refill(env, address, rw, mmu_idx); + ret_walker =3D page_table_walk_refill(env, address, access_type, m= mu_idx); env->hflags |=3D mode; if (ret_walker) { - ret =3D get_physical_address(env, &physical, &prot, - address, rw, access_type, mmu_idx); + ret =3D get_physical_address(env, &physical, &prot, address, + access_type, mips_access_type, mmu_= idx); if (ret =3D=3D TLBRET_MATCH) { tlb_set_page(cs, address & TARGET_PAGE_MASK, physical & TARGET_PAGE_MASK, prot | PAGE_EXEC, mmu_idx, TARGET_PAGE_SIZE); - return 0; + return true; } } } #endif + if (probe) { + return false; + } #endif =20 - raise_mmu_exception(env, address, rw, ret); - return 1; + raise_mmu_exception(env, address, access_type, ret); + do_raise_exception_err(env, cs->exception_index, env->error_code, reta= ddr); +} + +#ifndef CONFIG_USER_ONLY +void tlb_fill(CPUState *cs, target_ulong addr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) +{ + mips_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr= ); } =20 -#if !defined(CONFIG_USER_ONLY) hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address,= int rw) { hwaddr physical; diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index 0f272a5b93..6d86912958 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -2669,21 +2669,6 @@ void mips_cpu_do_unaligned_access(CPUState *cs, vadd= r addr, do_raise_exception_err(env, excp, error_code, retaddr); } =20 -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - int ret; - - ret =3D mips_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu_idx= ); - if (ret) { - MIPSCPU *cpu =3D MIPS_CPU(cs); - CPUMIPSState *env =3D &cpu->env; - - do_raise_exception_err(env, cs->exception_index, - env->error_code, retaddr); - } -} - void mips_cpu_unassigned_access(CPUState *cs, hwaddr addr, bool is_write, bool is_exec, int unused, unsigned size) --=20 2.17.1 From nobody Tue Apr 30 04:47:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[97.113.13.231]) by smtp.gmail.com with ESMTPSA id 19sm5920517pgz.24.2019.05.10.08.20.01 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 10 May 2019 08:20:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=SbdgfaYjW8ILfhiu0/mJqWKm/tBVnd5f44zvoNG8J24=; b=y6l5WHcHxqFLU9fWsT7tDzRc9SXW6pDNL6PQ8C9TsYLdi44PWcsYQm2e6IS/6Dq+jQ 1BZBcyL1FWghSJkzRBXbh+OEIro96F/sUu6Lq8HFuWUchlIR+hXZugk6TDRtN4oTLB6G +Nwht7yr6g/JnuSbPaK0ZNUbhQFyN2j1QcQ4E67dsadZ3tRnQd5Uh20hqSKR2YJH6pzQ muf1g2VplOlVhXmnFdJ3o1MU5f6H3LbaLkqFX9RjcncKFR7ceHKZqkP4sdd50Fz89IFG ysnesyb4oAj8pDOAEIqCoHScdXpFNl9nSsjRO4RxYWWJLB5lLgu90pJLdY6D/Ms/TxIH G9nQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=SbdgfaYjW8ILfhiu0/mJqWKm/tBVnd5f44zvoNG8J24=; b=CEzE7/qHaA3kZYtrUTm9Gxa1GtE9KxhQgU5tmUs07Hb3KwCK2c8O6jUf5xh3g9qSe9 5rgoa6aRHyXVt8QskM//Ap0PqfepMau7/otZkle8XZiXPMf3Ur+bzCEYsPR9QPfP83H7 zgFWkipqSCzq0xoRdwRIdILqe+WjzR0PIXbh13S5Nso+vP8CcHlAvHVUvP0LkgXwTVcW mmrDQrHIBbBjC2rzOoC20hbKPUH8EQb+VQJoPDK+GJ9B/Wzt7vCNJ/5a9evXk6iV9oF1 WbNPnbczG/YS7Psg5+Fg2QFqQNJN7mevcR4B8QNVtOevV3cpWZC7fjW2SY+WGh4clcF6 tH1g== X-Gm-Message-State: APjAAAW8En4rmEWcvIB2vDBVRRQmVHCKHiBPypFEFJjfrP4JwYJkVn+6 jJ9TbgeKEc2vVYhItS/+8QIPOV/oOxE= X-Google-Smtp-Source: APXvYqxPf8oyXDmi4u4MU/TQdiqNLqejVEXE0mmrquGfxCoTP+EizyTuMBWd8bRQqBws21sjRwm0/w== X-Received: by 2002:a17:902:59db:: with SMTP id d27mr14068990plj.332.1557501603260; Fri, 10 May 2019 08:20:03 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 10 May 2019 08:19:30 -0700 Message-Id: <20190510151944.22981-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190510151944.22981-1-richard.henderson@linaro.org> References: <20190510151944.22981-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::644 Subject: [Qemu-devel] [PULL 13/27] target/moxie: Convert to CPUClass::tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Anthony Green Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Remove the user-only functions, as we don't have a user-only config. Fix the unconditional call to tlb_set_page, even if the translation failed. Cc: Anthony Green Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/moxie/cpu.h | 5 ++-- target/moxie/cpu.c | 5 ++-- target/moxie/helper.c | 61 ++++++++++--------------------------------- 3 files changed, 19 insertions(+), 52 deletions(-) diff --git a/target/moxie/cpu.h b/target/moxie/cpu.h index f3b6d83ae7..a63a96bc05 100644 --- a/target/moxie/cpu.h +++ b/target/moxie/cpu.h @@ -139,7 +139,8 @@ static inline void cpu_get_tb_cpu_state(CPUMoxieState *= env, target_ulong *pc, *flags =3D 0; } =20 -int moxie_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, - int rw, int mmu_idx); +bool moxie_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); =20 #endif /* MOXIE_CPU_H */ diff --git a/target/moxie/cpu.c b/target/moxie/cpu.c index 46434e65ba..02b2b47574 100644 --- a/target/moxie/cpu.c +++ b/target/moxie/cpu.c @@ -112,9 +112,8 @@ static void moxie_cpu_class_init(ObjectClass *oc, void = *data) cc->do_interrupt =3D moxie_cpu_do_interrupt; cc->dump_state =3D moxie_cpu_dump_state; cc->set_pc =3D moxie_cpu_set_pc; -#ifdef CONFIG_USER_ONLY - cc->handle_mmu_fault =3D moxie_cpu_handle_mmu_fault; -#else + cc->tlb_fill =3D moxie_cpu_tlb_fill; +#ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D moxie_cpu_get_phys_page_debug; cc->vmsd =3D &vmstate_moxie_cpu; #endif diff --git a/target/moxie/helper.c b/target/moxie/helper.c index 287a45232c..216cef057e 100644 --- a/target/moxie/helper.c +++ b/target/moxie/helper.c @@ -26,18 +26,10 @@ #include "qemu/host-utils.h" #include "exec/helper-proto.h" =20 -/* Try to fill the TLB and return an exception if error. If retaddr is - NULL, it means that the function was called in C code (i.e. not - from generated code or from helper.c) */ void tlb_fill(CPUState *cs, target_ulong addr, int size, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) { - int ret; - - ret =3D moxie_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu_id= x); - if (unlikely(ret)) { - cpu_loop_exit_restore(cs, retaddr); - } + moxie_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retadd= r); } =20 void helper_raise_exception(CPUMoxieState *env, int ex) @@ -85,53 +77,29 @@ void helper_debug(CPUMoxieState *env) cpu_loop_exit(cs); } =20 -#if defined(CONFIG_USER_ONLY) - -void moxie_cpu_do_interrupt(CPUState *cs) -{ - CPUState *cs =3D CPU(moxie_env_get_cpu(env)); - - cs->exception_index =3D -1; -} - -int moxie_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, - int rw, int mmu_idx) -{ - MoxieCPU *cpu =3D MOXIE_CPU(cs); - - cs->exception_index =3D 0xaa; - cpu->env.debug1 =3D address; - cpu_dump_state(cs, stderr, 0); - return 1; -} - -#else /* !CONFIG_USER_ONLY */ - -int moxie_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, - int rw, int mmu_idx) +bool moxie_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) { MoxieCPU *cpu =3D MOXIE_CPU(cs); CPUMoxieState *env =3D &cpu->env; MoxieMMUResult res; int prot, miss; - target_ulong phy; - int r =3D 1; =20 address &=3D TARGET_PAGE_MASK; prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; - miss =3D moxie_mmu_translate(&res, env, address, rw, mmu_idx); - if (miss) { - /* handle the miss. */ - phy =3D 0; - cs->exception_index =3D MOXIE_EX_MMU_MISS; - } else { - phy =3D res.phy; - r =3D 0; + miss =3D moxie_mmu_translate(&res, env, address, access_type, mmu_idx); + if (likely(!miss)) { + tlb_set_page(cs, address, res.phy, prot, mmu_idx, TARGET_PAGE_SIZE= ); + return true; + } + if (probe) { + return false; } - tlb_set_page(cs, address, phy, prot, mmu_idx, TARGET_PAGE_SIZE); - return r; -} =20 + cs->exception_index =3D MOXIE_EX_MMU_MISS; + cpu_loop_exit_restore(cs, retaddr); +} =20 void moxie_cpu_do_interrupt(CPUState *cs) { @@ -156,4 +124,3 @@ hwaddr moxie_cpu_get_phys_page_debug(CPUState *cs, vadd= r addr) } return phy; } -#endif --=20 2.17.1 From nobody Tue Apr 30 04:47:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1557502677; cv=none; d=zoho.com; s=zohoarc; b=mjlYT+2WoXmFtsuGp3hzSzyRAHzvLW8OSLbweyOdheIWTMm0dL7jCeCQc37Rx/9nrpnV20/Gf2CmwmnmiArwOkRerk1nuKYj5ySGEq/Gt/HARhpoo+X42mmpc9xUovMMCQbvy0186/E7vnW2W5S/Y50e4UfJc87cygqNSd95r/0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1557502677; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=HbqwBnUY1nf/U3hx51h7fAODfIBTrHkKQ8MmHxK9GaE=; b=eIXlqvTc3zMLZN1IIoy+GZS5QNXP8wuU2lvOrPXMFZ7NA56q6JlLCEnV6MrMGWpDE+yAzbTpOdIlnCQpA567LMJNjsrkHvBu8kmtoCmngixR1W+AA3kuteEVddFOMd5k3oFPGYs8QqF4JnaNI36IAxIMtokjOPFUWdIRICvoz3g= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1557502677381556.7738498175282; Fri, 10 May 2019 08:37:57 -0700 (PDT) Received: from localhost ([127.0.0.1]:45228 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hP7ar-0007x6-A5 for importer@patchew.org; Fri, 10 May 2019 11:37:53 -0400 Received: from eggs.gnu.org ([209.51.188.92]:56206) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hP7Jg-0007es-MO for qemu-devel@nongnu.org; Fri, 10 May 2019 11:20:12 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hP7Jd-0008W8-To for qemu-devel@nongnu.org; Fri, 10 May 2019 11:20:08 -0400 Received: from mail-pl1-x643.google.com ([2607:f8b0:4864:20::643]:47091) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hP7Jd-0008VR-Je for qemu-devel@nongnu.org; Fri, 10 May 2019 11:20:05 -0400 Received: by mail-pl1-x643.google.com with SMTP id bi2so2971334plb.13 for ; Fri, 10 May 2019 08:20:05 -0700 (PDT) Received: from localhost.localdomain (97-113-13-231.tukw.qwest.net. [97.113.13.231]) by smtp.gmail.com with ESMTPSA id 19sm5920517pgz.24.2019.05.10.08.20.03 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 10 May 2019 08:20:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=HbqwBnUY1nf/U3hx51h7fAODfIBTrHkKQ8MmHxK9GaE=; b=mWSNiyZ1b2LBHN+cszDGxMxoP/pGqYFdmgqWjJ3UqDkORQe6BA2Te4QOKBBtnRh4wC yaL7nXaswXhFn+GeNXVQEZaOpWFmTCLw7Zig1/D+lsKNt9nId7gO4kYX81jPyrfe04Mr FaqgiBq5Rsc8u5NnNpuIb5tjpOMDhHzNS7y2kZHkPvrpNNUpmRW2phkpgZAq50R9/Wj9 aYdPVyuT5/9uOE7QTMCJ9ToYj7sil1ifECEc6mSCv3sDA6eiY+NSuAVZNikME6OLdTOA qDPTRspxQr0XbYk+fGUHygTbvv9h/yNQyIpVYUmedI/P5yVufxDROyIST9rKecE09eOo oZqg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=HbqwBnUY1nf/U3hx51h7fAODfIBTrHkKQ8MmHxK9GaE=; b=gnTOL1XV506BGK6CXAdXcbSt948Vgqr+FDk+aVawU/5qw5ejV8A56+by3d0PI6flwx d0T2zxPdBlG+bCLKdZetQ/MpdIPiBMb9E9ZetB2PiV1abq4jBIG/NdoEk4g5YG3Vn6+V T9EgfctnM75cfSEFCOr5Q9Y4LnbMQ6Vyz5DQQ6cZUwukYnmnsmt75pHyOgeDcxAxURZe hux3kUKLAK2iAqEI6RHirD/S0vk+zZ9XVN9/gN1r8EoHSeRgOKYpD3pacK089y2dW5by AspwMoqLPtt8/HYwUOCH+73kLG5Yt06pH9ysmaQoa2JBrtv7PVzyWABc1oaVi9hIzGHa N+LA== X-Gm-Message-State: APjAAAWagOebXRWQYSH5tHlBn1F/Ij5r3ziiEtQ1xSWfNQgeuVyfX2na ggkS7L4yPKyvnNChjRvbRh3HGC5IURw= X-Google-Smtp-Source: APXvYqz96ThR1F3IZlAJ7bHmh3i4GLz6TvJZBrlk/BArNloM+f7y5s8AnXSRjSAkvkGtwoMQ9KTp6A== X-Received: by 2002:a17:902:7892:: with SMTP id q18mr13779407pll.163.1557501604387; Fri, 10 May 2019 08:20:04 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 10 May 2019 08:19:31 -0700 Message-Id: <20190510151944.22981-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190510151944.22981-1-richard.henderson@linaro.org> References: <20190510151944.22981-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 Subject: [Qemu-devel] [PULL 14/27] target/nios2: Convert to CPUClass::tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marek Vasut , peter.maydell@linaro.org, Chris Wulff Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Remove the leftover debugging cpu_dump_state. Cc: Chris Wulff Cc: Marek Vasut Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/nios2/cpu.h | 5 +- target/nios2/cpu.c | 5 +- target/nios2/helper.c | 176 +++++++++++++++++++++--------------------- target/nios2/mmu.c | 12 --- 4 files changed, 91 insertions(+), 107 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 881e7d58c9..60a916b2e5 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -252,8 +252,9 @@ static inline int cpu_mmu_index(CPUNios2State *env, boo= l ifetch) MMU_SUPERVISOR_IDX; } =20 -int nios2_cpu_handle_mmu_fault(CPUState *env, vaddr address, int size, - int rw, int mmu_idx); +bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); =20 static inline int cpu_interrupts_enabled(CPUNios2State *env) { diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index fbfaa2ce26..186af4913d 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -200,9 +200,8 @@ static void nios2_cpu_class_init(ObjectClass *oc, void = *data) cc->dump_state =3D nios2_cpu_dump_state; cc->set_pc =3D nios2_cpu_set_pc; cc->disas_set_info =3D nios2_cpu_disas_set_info; -#ifdef CONFIG_USER_ONLY - cc->handle_mmu_fault =3D nios2_cpu_handle_mmu_fault; -#else + cc->tlb_fill =3D nios2_cpu_tlb_fill; +#ifndef CONFIG_USER_ONLY cc->do_unaligned_access =3D nios2_cpu_do_unaligned_access; cc->get_phys_page_debug =3D nios2_cpu_get_phys_page_debug; #endif diff --git a/target/nios2/helper.c b/target/nios2/helper.c index e01fc1ff3e..eb2eed7ad3 100644 --- a/target/nios2/helper.c +++ b/target/nios2/helper.c @@ -38,15 +38,12 @@ void nios2_cpu_do_interrupt(CPUState *cs) env->regs[R_EA] =3D env->regs[R_PC] + 4; } =20 -int nios2_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, - int rw, int mmu_idx) +bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) { cs->exception_index =3D 0xaa; - /* Page 0x1000 is kuser helper */ - if (address < 0x1000 || address >=3D 0x2000) { - cpu_dump_state(cs, stderr, 0); - } - return 1; + cpu_loop_exit_restore(cs, retaddr); } =20 #else /* !CONFIG_USER_ONLY */ @@ -203,89 +200,6 @@ void nios2_cpu_do_interrupt(CPUState *cs) } } =20 -static int cpu_nios2_handle_virtual_page( - CPUState *cs, target_ulong address, int rw, int mmu_idx) -{ - Nios2CPU *cpu =3D NIOS2_CPU(cs); - CPUNios2State *env =3D &cpu->env; - target_ulong vaddr, paddr; - Nios2MMULookup lu; - unsigned int hit; - hit =3D mmu_translate(env, &lu, address, rw, mmu_idx); - if (hit) { - vaddr =3D address & TARGET_PAGE_MASK; - paddr =3D lu.paddr + vaddr - lu.vaddr; - - if (((rw =3D=3D 0) && (lu.prot & PAGE_READ)) || - ((rw =3D=3D 1) && (lu.prot & PAGE_WRITE)) || - ((rw =3D=3D 2) && (lu.prot & PAGE_EXEC))) { - - tlb_set_page(cs, vaddr, paddr, lu.prot, - mmu_idx, TARGET_PAGE_SIZE); - return 0; - } else { - /* Permission violation */ - cs->exception_index =3D (rw =3D=3D 0) ? EXCP_TLBR : - ((rw =3D=3D 1) ? EXCP_TLBW : - EXCP_TLBX); - } - } else { - cs->exception_index =3D EXCP_TLBD; - } - - if (rw =3D=3D 2) { - env->regs[CR_TLBMISC] &=3D ~CR_TLBMISC_D; - } else { - env->regs[CR_TLBMISC] |=3D CR_TLBMISC_D; - } - env->regs[CR_PTEADDR] &=3D CR_PTEADDR_PTBASE_MASK; - env->regs[CR_PTEADDR] |=3D (address >> 10) & CR_PTEADDR_VPN_MASK; - env->mmu.pteaddr_wr =3D env->regs[CR_PTEADDR]; - env->regs[CR_BADADDR] =3D address; - return 1; -} - -int nios2_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, - int rw, int mmu_idx) -{ - Nios2CPU *cpu =3D NIOS2_CPU(cs); - CPUNios2State *env =3D &cpu->env; - - if (cpu->mmu_present) { - if (MMU_SUPERVISOR_IDX =3D=3D mmu_idx) { - if (address >=3D 0xC0000000) { - /* Kernel physical page - TLB bypassed */ - address &=3D TARGET_PAGE_MASK; - tlb_set_page(cs, address, address, PAGE_BITS, - mmu_idx, TARGET_PAGE_SIZE); - } else if (address >=3D 0x80000000) { - /* Kernel virtual page */ - return cpu_nios2_handle_virtual_page(cs, address, rw, mmu_= idx); - } else { - /* User virtual page */ - return cpu_nios2_handle_virtual_page(cs, address, rw, mmu_= idx); - } - } else { - if (address >=3D 0x80000000) { - /* Illegal access from user mode */ - cs->exception_index =3D EXCP_SUPERA; - env->regs[CR_BADADDR] =3D address; - return 1; - } else { - /* User virtual page */ - return cpu_nios2_handle_virtual_page(cs, address, rw, mmu_= idx); - } - } - } else { - /* No MMU */ - address &=3D TARGET_PAGE_MASK; - tlb_set_page(cs, address, address, PAGE_BITS, - mmu_idx, TARGET_PAGE_SIZE); - } - - return 0; -} - hwaddr nios2_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) { Nios2CPU *cpu =3D NIOS2_CPU(cs); @@ -321,4 +235,86 @@ void nios2_cpu_do_unaligned_access(CPUState *cs, vaddr= addr, env->regs[CR_EXCEPTION] =3D EXCP_UNALIGN << 2; helper_raise_exception(env, EXCP_UNALIGN); } + +bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) +{ + Nios2CPU *cpu =3D NIOS2_CPU(cs); + CPUNios2State *env =3D &cpu->env; + unsigned int excp =3D EXCP_TLBD; + target_ulong vaddr, paddr; + Nios2MMULookup lu; + unsigned int hit; + + if (!cpu->mmu_present) { + /* No MMU */ + address &=3D TARGET_PAGE_MASK; + tlb_set_page(cs, address, address, PAGE_BITS, + mmu_idx, TARGET_PAGE_SIZE); + return true; + } + + if (MMU_SUPERVISOR_IDX =3D=3D mmu_idx) { + if (address >=3D 0xC0000000) { + /* Kernel physical page - TLB bypassed */ + address &=3D TARGET_PAGE_MASK; + tlb_set_page(cs, address, address, PAGE_BITS, + mmu_idx, TARGET_PAGE_SIZE); + return true; + } + } else { + if (address >=3D 0x80000000) { + /* Illegal access from user mode */ + if (probe) { + return false; + } + cs->exception_index =3D EXCP_SUPERA; + env->regs[CR_BADADDR] =3D address; + cpu_loop_exit_restore(cs, retaddr); + } + } + + /* Virtual page. */ + hit =3D mmu_translate(env, &lu, address, access_type, mmu_idx); + if (hit) { + vaddr =3D address & TARGET_PAGE_MASK; + paddr =3D lu.paddr + vaddr - lu.vaddr; + + if (((access_type =3D=3D MMU_DATA_LOAD) && (lu.prot & PAGE_READ)) = || + ((access_type =3D=3D MMU_DATA_STORE) && (lu.prot & PAGE_WRITE)= ) || + ((access_type =3D=3D MMU_INST_FETCH) && (lu.prot & PAGE_EXEC))= ) { + tlb_set_page(cs, vaddr, paddr, lu.prot, + mmu_idx, TARGET_PAGE_SIZE); + return true; + } + + /* Permission violation */ + excp =3D (access_type =3D=3D MMU_DATA_LOAD ? EXCP_TLBR : + access_type =3D=3D MMU_DATA_STORE ? EXCP_TLBW : EXCP_TLBX); + } + + if (probe) { + return false; + } + + if (access_type =3D=3D MMU_INST_FETCH) { + env->regs[CR_TLBMISC] &=3D ~CR_TLBMISC_D; + } else { + env->regs[CR_TLBMISC] |=3D CR_TLBMISC_D; + } + env->regs[CR_PTEADDR] &=3D CR_PTEADDR_PTBASE_MASK; + env->regs[CR_PTEADDR] |=3D (address >> 10) & CR_PTEADDR_VPN_MASK; + env->mmu.pteaddr_wr =3D env->regs[CR_PTEADDR]; + + cs->exception_index =3D excp; + env->regs[CR_BADADDR] =3D address; + cpu_loop_exit_restore(cs, retaddr); +} + +void tlb_fill(CPUState *cs, target_ulong addr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) +{ + nios2_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retadd= r); +} #endif /* !CONFIG_USER_ONLY */ diff --git a/target/nios2/mmu.c b/target/nios2/mmu.c index 5acf442d8b..47fa474efb 100644 --- a/target/nios2/mmu.c +++ b/target/nios2/mmu.c @@ -36,18 +36,6 @@ #define MMU_LOG(x) #endif =20 -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - int ret; - - ret =3D nios2_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu_id= x); - if (unlikely(ret)) { - /* now we have a real cpu fault */ - cpu_loop_exit_restore(cs, retaddr); - } -} - void mmu_read_debug(CPUNios2State *env, uint32_t rn) { switch (rn) { --=20 2.17.1 From nobody Tue Apr 30 04:47:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1557503083; cv=none; d=zoho.com; s=zohoarc; b=Hm8nA9i7h830Lgav5WIhkhiLfb6JaRM2wd2e5KRRKJsaqkN3V1JuYgnd1q7qRR0tZQY/JQ43iEODIdh6RUgYb7+Fwqd+EgMCZ3D0GBH+gcxNxrdoPz/nLNNZmKkpWsLEe7o3uzoqN8366CzHrjkQPQuVnhEHsAhVZb+GqDZDq7M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1557503083; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=pyOmNQehrxQ+vJN1rBIdXnxr1kqTHPzFsWgERMP7ALs=; b=COdOdhd7cjYyeJ/luBYF6TSdU/cV3UaYfzN+SjCYfWs3Hr4IHgLzYg6IaKgirmygvtpjOPwSDuafhAWGUNfYrCcsVLM9Dtf3jSKoldN0AS9dEsEEZG2xoUnzeLSzFcNTp8KZc4ujgDnOJ7slomOD80682J7QIZN4W+DY9G2bf6o= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1557503083058237.85582881335813; Fri, 10 May 2019 08:44:43 -0700 (PDT) Received: from localhost ([127.0.0.1]:45329 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hP7hM-0005dL-WD for importer@patchew.org; Fri, 10 May 2019 11:44:37 -0400 Received: from eggs.gnu.org ([209.51.188.92]:56202) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hP7Jg-0007ea-Be for qemu-devel@nongnu.org; Fri, 10 May 2019 11:20:12 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hP7Jf-00005B-57 for qemu-devel@nongnu.org; Fri, 10 May 2019 11:20:08 -0400 Received: from mail-pg1-x52f.google.com ([2607:f8b0:4864:20::52f]:42390) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hP7Je-0008WP-VF for qemu-devel@nongnu.org; Fri, 10 May 2019 11:20:07 -0400 Received: by mail-pg1-x52f.google.com with SMTP id 145so3174133pgg.9 for ; Fri, 10 May 2019 08:20:06 -0700 (PDT) Received: from localhost.localdomain (97-113-13-231.tukw.qwest.net. [97.113.13.231]) by smtp.gmail.com with ESMTPSA id 19sm5920517pgz.24.2019.05.10.08.20.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 10 May 2019 08:20:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=pyOmNQehrxQ+vJN1rBIdXnxr1kqTHPzFsWgERMP7ALs=; b=ofUkvA8DKRJRBhSyTfuTP4CJrRpdtlPCRQ9u7qkB5GMg7qmgw5oSq3PloxFex8kwbZ kMDWQIjHFpstu6XI/zrz+mBSvb2DGowu4QXP4kbz9pFoqM/4xFTZ7JYnVadKJ6TkGxXP tL86OhSpxXTBYben9oI7QllprBrC9kEOBm/861TKqNbT+knqXCmWr5uaBZEyEof/mYI1 WD5KZyrg7NzCaZ+13njqy4mNnTOaSoPZlvBQlp9OWd93nHx+ru1+eBd9TZOZf95SknAb ZKGwjaVh/0oMavUez1jmQicq7xBvhJ78aGA2Rxn4hsss9Jtzm140IS4c+Mty7pupyfOY Ek5g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=pyOmNQehrxQ+vJN1rBIdXnxr1kqTHPzFsWgERMP7ALs=; b=kqBg2nSytpgFV9k0J+HtpqygaKVzWFXJOtfAFkVgoLNPgCK3N4ed0pBtF+TLCsnyZB qlPa5eosyzbKfC7B/3LnV8YAzjrfWXlyLUeS9N9f0/uobDQR8HhS904fJUkl+8y//wCc 9MRcH6IIEOv0Tx4kw8t0qv4LBM/sFC0Hg6fi/eEjW+4Q9XHG7dNWeGlsbXMKtZa0FMbW wisuBApvBsDe3TdS99azvIPnDKiHjMzHuMJpuks31xg9+4C/93wJ+/pMWryeoPjxLpHg uTOcjbyZFTaIbDsbbNWYvc1HPdV+9uRVEFVYWc3XPGXvssPMXxC4kdOXe1X1vSe9aPQL +Png== X-Gm-Message-State: APjAAAU8dOMG1cOTVThTinjBs4F1tj9Q4gterLwVjXNz6RYpX0S85AYO w70IRACCuFRTLss1WfywR0fxanJrcjY= X-Google-Smtp-Source: APXvYqxXpRbJyiovJlkp9WTm0Q+nxSPFLo2ost9doVl6R2NVxRkDCJ9N7u+NhgbnYkvqbtan4A0F5Q== X-Received: by 2002:aa7:8554:: with SMTP id y20mr14945470pfn.258.1557501605638; Fri, 10 May 2019 08:20:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 10 May 2019 08:19:32 -0700 Message-Id: <20190510151944.22981-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190510151944.22981-1-richard.henderson@linaro.org> References: <20190510151944.22981-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::52f Subject: [Qemu-devel] [PULL 15/27] target/openrisc: Convert to CPUClass::tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Stafford Horne Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Cc: Stafford Horne Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/openrisc/cpu.h | 5 ++-- target/openrisc/cpu.c | 5 ++-- target/openrisc/mmu.c | 65 ++++++++++++++++++++++--------------------- 3 files changed, 39 insertions(+), 36 deletions(-) diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 88a8c70092..9473d94d0c 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -344,8 +344,9 @@ hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cpu, = vaddr addr); int openrisc_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); int openrisc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void openrisc_translate_init(void); -int openrisc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, - int rw, int mmu_idx); +bool openrisc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); int cpu_openrisc_signal_handler(int host_signum, void *pinfo, void *puc); int print_insn_or1k(bfd_vma addr, disassemble_info *info); =20 diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index d125236977..3816baee70 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -149,9 +149,8 @@ static void openrisc_cpu_class_init(ObjectClass *oc, vo= id *data) cc->set_pc =3D openrisc_cpu_set_pc; cc->gdb_read_register =3D openrisc_cpu_gdb_read_register; cc->gdb_write_register =3D openrisc_cpu_gdb_write_register; -#ifdef CONFIG_USER_ONLY - cc->handle_mmu_fault =3D openrisc_cpu_handle_mmu_fault; -#else + cc->tlb_fill =3D openrisc_cpu_tlb_fill; +#ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D openrisc_cpu_get_phys_page_debug; dc->vmsd =3D &vmstate_openrisc_cpu; #endif diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c index 5dec68dcff..94c65a25fa 100644 --- a/target/openrisc/mmu.c +++ b/target/openrisc/mmu.c @@ -107,16 +107,42 @@ static void raise_mmu_exception(OpenRISCCPU *cpu, tar= get_ulong address, cpu->env.lock_addr =3D -1; } =20 -int openrisc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, - int rw, int mmu_idx) +bool openrisc_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) { -#ifdef CONFIG_USER_ONLY OpenRISCCPU *cpu =3D OPENRISC_CPU(cs); - raise_mmu_exception(cpu, address, EXCP_DPF); - return 1; -#else - g_assert_not_reached(); + int excp =3D EXCP_DPF; + +#ifndef CONFIG_USER_ONLY + int prot; + hwaddr phys_addr; + + if (mmu_idx =3D=3D MMU_NOMMU_IDX) { + /* The mmu is disabled; lookups never fail. */ + get_phys_nommu(&phys_addr, &prot, addr); + excp =3D 0; + } else { + bool super =3D mmu_idx =3D=3D MMU_SUPERVISOR_IDX; + int need =3D (access_type =3D=3D MMU_INST_FETCH ? PAGE_EXEC + : access_type =3D=3D MMU_DATA_STORE ? PAGE_WRITE + : PAGE_READ); + excp =3D get_phys_mmu(cpu, &phys_addr, &prot, addr, need, super); + } + + if (likely(excp =3D=3D 0)) { + tlb_set_page(cs, addr & TARGET_PAGE_MASK, + phys_addr & TARGET_PAGE_MASK, prot, + mmu_idx, TARGET_PAGE_SIZE); + return true; + } + if (probe) { + return false; + } #endif + + raise_mmu_exception(cpu, addr, excp); + cpu_loop_exit_restore(cs, retaddr); } =20 #ifndef CONFIG_USER_ONLY @@ -156,29 +182,6 @@ hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cs, = vaddr addr) void tlb_fill(CPUState *cs, target_ulong addr, int size, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) { - OpenRISCCPU *cpu =3D OPENRISC_CPU(cs); - int prot, excp; - hwaddr phys_addr; - - if (mmu_idx =3D=3D MMU_NOMMU_IDX) { - /* The mmu is disabled; lookups never fail. */ - get_phys_nommu(&phys_addr, &prot, addr); - excp =3D 0; - } else { - bool super =3D mmu_idx =3D=3D MMU_SUPERVISOR_IDX; - int need =3D (access_type =3D=3D MMU_INST_FETCH ? PAGE_EXEC - : access_type =3D=3D MMU_DATA_STORE ? PAGE_WRITE - : PAGE_READ); - excp =3D get_phys_mmu(cpu, &phys_addr, &prot, addr, need, super); - } - - if (unlikely(excp)) { - raise_mmu_exception(cpu, addr, excp); - cpu_loop_exit_restore(cs, retaddr); - } - - tlb_set_page(cs, addr & TARGET_PAGE_MASK, - phys_addr & TARGET_PAGE_MASK, prot, - mmu_idx, TARGET_PAGE_SIZE); + openrisc_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, 0, retaddr= ); } #endif --=20 2.17.1 From nobody Tue Apr 30 04:47:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1557502219; cv=none; d=zoho.com; s=zohoarc; b=CNInuehafy4nu0JeehHh5UOvTR9qsrvCBanUXCoQcutS5HojyhgulLXwm7m9XsOiPf1Xutuz8j6rlGgoaRGMQaC8jLPRrFoXTSrd152RXoYbP127YxK10mHhelKs+ZaluBsatHVynSwgDvVzEEnmJYMpBiFFaK/TZL/mt9ffsIY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1557502219; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=ERTfGga5mStSjhtEmfd35eidZa/k5s6k3BsixP9VyyI=; b=AQA9P1vUo8447QX/+IuHpzf1xBpAN7Vg++0itQEPhlwNK2sT1Q51l+wAwjgrGceagbW4xrhMA56GtHJK9egB7gTazHpQkIBQlV4oQtUqQoj3nMsx/vRo9iBk8+iW0XVhKaNtx+0dF44V8dC6PQ28uWRGvqWjEmxojh/XUSTjGRQ= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1557502219002726.1880814276725; Fri, 10 May 2019 08:30:19 -0700 (PDT) Received: from localhost ([127.0.0.1]:45111 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hP7TO-000067-UW for importer@patchew.org; Fri, 10 May 2019 11:30:10 -0400 Received: from eggs.gnu.org ([209.51.188.92]:56230) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hP7Jh-0007fV-FJ for qemu-devel@nongnu.org; Fri, 10 May 2019 11:20:12 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hP7Jg-00005x-6P for qemu-devel@nongnu.org; Fri, 10 May 2019 11:20:09 -0400 Received: from mail-pl1-x641.google.com ([2607:f8b0:4864:20::641]:37934) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hP7Jg-00005J-0y for qemu-devel@nongnu.org; Fri, 10 May 2019 11:20:08 -0400 Received: by mail-pl1-x641.google.com with SMTP id a59so2995912pla.5 for ; Fri, 10 May 2019 08:20:07 -0700 (PDT) Received: from localhost.localdomain (97-113-13-231.tukw.qwest.net. [97.113.13.231]) by smtp.gmail.com with ESMTPSA id 19sm5920517pgz.24.2019.05.10.08.20.05 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 10 May 2019 08:20:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ERTfGga5mStSjhtEmfd35eidZa/k5s6k3BsixP9VyyI=; b=TFUFnw6HA8dXeMZZN6tkZPD/k5JYIs2K/wQ5rMZhUbayZKyxF8+5x/ag4qhFBNWou2 VbKLZvDKTTEw/DHL0kWj1G4+WaH5FBEwSwHiNeZHu0dME2cGSPA73+jBv60gh9HCs/XE lKc1tygl/bHWS/GcCZdCcyduSV6PwV82GUmMtrUiQN86/vSnxl9EIJBO7KLFFezU4FWj 8jF0JhLzUPIngMRJRibwCDker8j1Mwj7xCWSiYOo44bUIZhhzcqalp0bhPUHpkoU8UVj A+eKXo9GHtkGctvbGLMGFcwpMKOV0EwVKoQydtFoi/l8Pp0fO1Wt5KyEv51qcvv1LOzg HtCw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ERTfGga5mStSjhtEmfd35eidZa/k5s6k3BsixP9VyyI=; b=rUZJ1jGjpTGf727ccV18egZwyMjfk72VX+un9R6EfpiyVy6E8dRQoZbrS4gNs7ZKtN S5VcPt5lnevYq3XbR4cbHVglg+e4+RrlY0funiOyB0oHuDkog1dDFSNHF11KmPUfVcR6 wwpO5Q3HjbrzGRlTSB739eXchHtbf+pkpGr+wvuXJ6kcd+G8d7cl/CErf3EKhLRAbQVx b+kG44mXlXmWs/8kj/Nb5mql/BuZWO3rXZtMFqzybe/LtcyuqxZa80pQ/pmg1JagZrMj ckuTUPcN3NOZmL9c/EuL5PXMGRCNn+Crln9pTX0oS1bznrxRLLm/aYd2Ty/FJevAFL1f QOwQ== X-Gm-Message-State: APjAAAWh6NCQ1wXggYtNmV/SoqVclwaPoi1UKUR//LQh8zqJPEUhym2d 6Y9AasPDamARGfdg8Pqvc9gB7aYNdtA= X-Google-Smtp-Source: APXvYqwKT35FukBqkKqiW0Qn9NLHJBRWqgiMsXtmsnKCxjQNVKEsVSg3OLp7G+flRZ/AqVTZHNK2Cw== X-Received: by 2002:a17:902:4281:: with SMTP id h1mr2833560pld.288.1557501606712; Fri, 10 May 2019 08:20:06 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 10 May 2019 08:19:33 -0700 Message-Id: <20190510151944.22981-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190510151944.22981-1-richard.henderson@linaro.org> References: <20190510151944.22981-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::641 Subject: [Qemu-devel] [PULL 16/27] target/ppc: Convert to CPUClass::tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-ppc@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Cc: qemu-ppc@nongnu.org Acked-by: David Gibson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/ppc/cpu.h | 7 +++---- target/ppc/mmu_helper.c | 22 +++++++++++++--------- target/ppc/translate_init.inc.c | 5 ++--- target/ppc/user_only_helper.c | 14 ++++++++------ 4 files changed, 26 insertions(+), 22 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 5e7cf54b2f..d7f23ad5e0 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1311,10 +1311,9 @@ void ppc_translate_init(void); * is returned if the signal was handled by the virtual CPU. */ int cpu_ppc_signal_handler(int host_signum, void *pinfo, void *puc); -#if defined(CONFIG_USER_ONLY) -int ppc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int r= w, - int mmu_idx); -#endif +bool ppc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); =20 #if !defined(CONFIG_USER_ONLY) void ppc_store_sdr1(CPUPPCState *env, target_ulong value); diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c index 1dbc9acb75..afcca50530 100644 --- a/target/ppc/mmu_helper.c +++ b/target/ppc/mmu_helper.c @@ -3057,15 +3057,9 @@ void helper_check_tlb_flush_global(CPUPPCState *env) =20 /*************************************************************************= ****/ =20 -/* - * try to fill the TLB and return an exception if error. If retaddr is - * NULL, it means that the function was called in C code (i.e. not - * from generated code or from helper.c) - * - * XXX: fix it to restore all registers - */ -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) +bool ppc_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) { PowerPCCPU *cpu =3D POWERPC_CPU(cs); PowerPCCPUClass *pcc =3D POWERPC_CPU_GET_CLASS(cs); @@ -3078,7 +3072,17 @@ void tlb_fill(CPUState *cs, target_ulong addr, int s= ize, ret =3D cpu_ppc_handle_mmu_fault(env, addr, access_type, mmu_idx); } if (unlikely(ret !=3D 0)) { + if (probe) { + return false; + } raise_exception_err_ra(env, cs->exception_index, env->error_code, retaddr); } + return true; +} + +void tlb_fill(CPUState *cs, target_ulong addr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) +{ + ppc_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); } diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.in= c.c index 0394a9ddad..3f847de36c 100644 --- a/target/ppc/translate_init.inc.c +++ b/target/ppc/translate_init.inc.c @@ -10592,9 +10592,8 @@ static void ppc_cpu_class_init(ObjectClass *oc, voi= d *data) cc->gdb_read_register =3D ppc_cpu_gdb_read_register; cc->gdb_write_register =3D ppc_cpu_gdb_write_register; cc->do_unaligned_access =3D ppc_cpu_do_unaligned_access; -#ifdef CONFIG_USER_ONLY - cc->handle_mmu_fault =3D ppc_cpu_handle_mmu_fault; -#else + cc->tlb_fill =3D ppc_cpu_tlb_fill; +#ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D ppc_cpu_get_phys_page_debug; cc->vmsd =3D &vmstate_ppc_cpu; #endif diff --git a/target/ppc/user_only_helper.c b/target/ppc/user_only_helper.c index 2f1477f102..683c03390d 100644 --- a/target/ppc/user_only_helper.c +++ b/target/ppc/user_only_helper.c @@ -20,21 +20,24 @@ =20 #include "qemu/osdep.h" #include "cpu.h" +#include "exec/exec-all.h" =20 -int ppc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw, - int mmu_idx) + +bool ppc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) { PowerPCCPU *cpu =3D POWERPC_CPU(cs); CPUPPCState *env =3D &cpu->env; int exception, error_code; =20 - if (rw =3D=3D 2) { + if (access_type =3D=3D MMU_INST_FETCH) { exception =3D POWERPC_EXCP_ISI; error_code =3D 0x40000000; } else { exception =3D POWERPC_EXCP_DSI; error_code =3D 0x40000000; - if (rw) { + if (access_type =3D=3D MMU_DATA_STORE) { error_code |=3D 0x02000000; } env->spr[SPR_DAR] =3D address; @@ -42,6 +45,5 @@ int ppc_cpu_handle_mmu_fault(CPUState *cs, vaddr address,= int size, int rw, } cs->exception_index =3D exception; env->error_code =3D error_code; - - return 1; + cpu_loop_exit_restore(cs, retaddr); } --=20 2.17.1 From nobody Tue Apr 30 04:47:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[97.113.13.231]) by smtp.gmail.com with ESMTPSA id 19sm5920517pgz.24.2019.05.10.08.20.06 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 10 May 2019 08:20:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=jFiOLbzDz1sji7rdhiIl1UIG07vaIVhoy6dgsMAsHtw=; b=xQ8t++6s8P84yjah1oodF4aP0tHt5TjP7r8j93p4dJPG7lprWwoEYapKJl0F3qFqpP 3QzK6CgZuYbhlNVv5SBTc1t6YJPbLHi+U3vniKmvLnIpeAZDwO18DqZI/vNW2ctlqfPs tbIqHtj9MUSkfK2KcnVGajsMx/SNhEl3QtL0lAfzOJiTV6pY+Jx944Flm82eSWQy1inO Z6MeKesS5KC1sr0+tIk6VX/V7f/JGTK2QFBuonjkpl5iD0SA37iqqahMSYTnATCVNdul 63OBQAaiQ5kYsGJdacgG/xKIy6wmbk5QZoeTt4FFNU5+CTY/Dyj84AjIys3D1fWqD74+ V1kg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=jFiOLbzDz1sji7rdhiIl1UIG07vaIVhoy6dgsMAsHtw=; b=AbIEv5jcYLGHZFVy5sY41erk7gAek+ozQF5u+fgMtO6oxxGD8zNJEbFa8+Dyz6ihJS AYveXIOSCK0V4eALGeteOWKwCMQAqVxYqxDkHARzRa2Jn26QnOPLPjZrpTioPpbPV7L7 TUvAal9mEwAeTA81L26adrOA5kRHQKGed62IMdKxXuWI/FQ5OBu5wtqsYl4Y1GHRqnWx 45hv2LZM3ZKch1aXHYlqiAuOp2/YPUKSwzHwJr6Z7v6yKEonRe/iO8XeWwz0C+d8TcTd WyrPtXDE/7qQg57SA6tqNeQQVhhkzLWntxdcauleg+9tPrgNLqcNJIm0BOySsk8qLef5 FrNA== X-Gm-Message-State: APjAAAWaURzhFCezA787dZ4apUoC4RWn1frqw8j5YTdhH5Kv37RLX99g lx0b+imlz4hNQkH3OAXqQB1zJk3eEFQ= X-Google-Smtp-Source: APXvYqwNtMn1Y1OzJ2nJNw4MNC2dIGvmgQNrZ7eHKVtuIfhczJaJG5t3ide5XsIiLAnCj/uPaUNkrQ== X-Received: by 2002:a62:570a:: with SMTP id l10mr14798979pfb.151.1557501607961; Fri, 10 May 2019 08:20:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 10 May 2019 08:19:34 -0700 Message-Id: <20190510151944.22981-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190510151944.22981-1-richard.henderson@linaro.org> References: <20190510151944.22981-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::441 Subject: [Qemu-devel] [PULL 17/27] target/riscv: Convert to CPUClass::tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Palmer Dabbelt , qemu-riscv@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Note that env->pc is removed from the qemu_log as that value is garbage. The PC isn't recovered until cpu_restore_state, called from cpu_loop_exit_restore, called from riscv_raise_exception. Cc: qemu-riscv@nongnu.org Cc: Palmer Dabbelt Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- target/riscv/cpu.h | 5 +++-- target/riscv/cpu.c | 5 ++--- target/riscv/cpu_helper.c | 46 ++++++++++++++++++--------------------- 3 files changed, 26 insertions(+), 30 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 7d9f48973f..c17184f4e4 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -261,8 +261,9 @@ hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vad= dr addr); void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr); -int riscv_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, - int rw, int mmu_idx); +bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); char *riscv_isa_string(RISCVCPU *cpu); void riscv_cpu_list(void); =20 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1bcf4eaeb8..34a54ef2ed 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -355,9 +355,8 @@ static void riscv_cpu_class_init(ObjectClass *c, void *= data) #endif cc->gdb_stop_before_watchpoint =3D true; cc->disas_set_info =3D riscv_cpu_disas_set_info; -#ifdef CONFIG_USER_ONLY - cc->handle_mmu_fault =3D riscv_cpu_handle_mmu_fault; -#else + cc->tlb_fill =3D riscv_cpu_tlb_fill; +#ifndef CONFIG_USER_ONLY cc->do_unaligned_access =3D riscv_cpu_do_unaligned_access; cc->get_phys_page_debug =3D riscv_cpu_get_phys_page_debug; #endif diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index b17f169681..2535435260 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -379,53 +379,49 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vadd= r addr, riscv_raise_exception(env, cs->exception_index, retaddr); } =20 -/* called by qemu's softmmu to fill the qemu tlb */ void tlb_fill(CPUState *cs, target_ulong addr, int size, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) { - int ret; - ret =3D riscv_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu_id= x); - if (ret =3D=3D TRANSLATE_FAIL) { - RISCVCPU *cpu =3D RISCV_CPU(cs); - CPURISCVState *env =3D &cpu->env; - riscv_raise_exception(env, cs->exception_index, retaddr); - } + riscv_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retadd= r); } - #endif =20 -int riscv_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, - int rw, int mmu_idx) +bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) { +#ifndef CONFIG_USER_ONLY RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; -#if !defined(CONFIG_USER_ONLY) hwaddr pa =3D 0; int prot; -#endif int ret =3D TRANSLATE_FAIL; =20 - qemu_log_mask(CPU_LOG_MMU, - "%s pc " TARGET_FMT_lx " ad %" VADDR_PRIx " rw %d mmu_idx \ - %d\n", __func__, env->pc, address, rw, mmu_idx); + qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n", + __func__, address, access_type, mmu_idx); + + ret =3D get_physical_address(env, &pa, &prot, address, access_type, mm= u_idx); =20 -#if !defined(CONFIG_USER_ONLY) - ret =3D get_physical_address(env, &pa, &prot, address, rw, mmu_idx); qemu_log_mask(CPU_LOG_MMU, - "%s address=3D%" VADDR_PRIx " ret %d physical " TARGET_FMT_plx - " prot %d\n", __func__, address, ret, pa, prot); + "%s address=3D%" VADDR_PRIx " ret %d physical " TARGET_F= MT_plx + " prot %d\n", __func__, address, ret, pa, prot); + if (riscv_feature(env, RISCV_FEATURE_PMP) && - !pmp_hart_has_privs(env, pa, TARGET_PAGE_SIZE, 1 << rw)) { + !pmp_hart_has_privs(env, pa, TARGET_PAGE_SIZE, 1 << access_type)) { ret =3D TRANSLATE_FAIL; } if (ret =3D=3D TRANSLATE_SUCCESS) { tlb_set_page(cs, address & TARGET_PAGE_MASK, pa & TARGET_PAGE_MASK, prot, mmu_idx, TARGET_PAGE_SIZE); - } else if (ret =3D=3D TRANSLATE_FAIL) { - raise_mmu_exception(env, address, rw); + return true; + } else if (probe) { + return false; + } else { + raise_mmu_exception(env, address, access_type); + riscv_raise_exception(env, cs->exception_index, retaddr); } #else - switch (rw) { + switch (access_type) { case MMU_INST_FETCH: cs->exception_index =3D RISCV_EXCP_INST_PAGE_FAULT; break; @@ -436,8 +432,8 @@ int riscv_cpu_handle_mmu_fault(CPUState *cs, vaddr addr= ess, int size, cs->exception_index =3D RISCV_EXCP_STORE_PAGE_FAULT; break; } + cpu_loop_exit_restore(cs, retaddr); #endif - return ret; } =20 /* --=20 2.17.1 From nobody Tue Apr 30 04:47:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1557502126; cv=none; d=zoho.com; s=zohoarc; b=hVpIBIrqF/TgS6NixaWufcOOpIL7/sCP+9z79wNXUllhmQk+QB6Zzh596l3aFftiOavCGIOL0I/DlW8SqZyAGoosovblOe0axX9m3fCRLNaneblnA8yAjDvMtZivexsZtxN+MSVqV/lANtCqdtdEsTeL6nyZXDVtItbI/WUcC24= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1557502126; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; 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X-Received-From: 2607:f8b0:4864:20::642 Subject: [Qemu-devel] [PULL 18/27] target/s390x: Convert to CPUClass::tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-s390x@nongnu.org, Cornelia Huck Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Cc: qemu-s390x@nongnu.org Cc: Cornelia Huck Reviewed-by: David Hildenbrand Signed-off-by: Richard Henderson --- target/s390x/internal.h | 5 +-- target/s390x/cpu.c | 5 ++- target/s390x/excp_helper.c | 73 ++++++++++++++++++++++++++------------ target/s390x/mem_helper.c | 16 --------- 4 files changed, 55 insertions(+), 44 deletions(-) diff --git a/target/s390x/internal.h b/target/s390x/internal.h index 26575f2130..56534b38e0 100644 --- a/target/s390x/internal.h +++ b/target/s390x/internal.h @@ -263,8 +263,9 @@ ObjectClass *s390_cpu_class_by_name(const char *name); void s390x_cpu_debug_excp_handler(CPUState *cs); void s390_cpu_do_interrupt(CPUState *cpu); bool s390_cpu_exec_interrupt(CPUState *cpu, int int_req); -int s390_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int = rw, - int mmu_idx); +bool s390_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); void s390x_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr); diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index b58ef0a8ef..e28939032b 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -478,9 +478,8 @@ static void s390_cpu_class_init(ObjectClass *oc, void *= data) cc->set_pc =3D s390_cpu_set_pc; cc->gdb_read_register =3D s390_cpu_gdb_read_register; cc->gdb_write_register =3D s390_cpu_gdb_write_register; -#ifdef CONFIG_USER_ONLY - cc->handle_mmu_fault =3D s390_cpu_handle_mmu_fault; -#else + cc->tlb_fill =3D s390_cpu_tlb_fill; +#ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D s390_cpu_get_phys_page_debug; cc->vmsd =3D &vmstate_s390_cpu; cc->write_elf64_note =3D s390_cpu_write_elf64_note; diff --git a/target/s390x/excp_helper.c b/target/s390x/excp_helper.c index f84bfb1284..a4e134bcab 100644 --- a/target/s390x/excp_helper.c +++ b/target/s390x/excp_helper.c @@ -74,8 +74,9 @@ void s390_cpu_do_interrupt(CPUState *cs) cs->exception_index =3D -1; } =20 -int s390_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, - int rw, int mmu_idx) +bool s390_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) { S390CPU *cpu =3D S390_CPU(cs); =20 @@ -83,7 +84,7 @@ int s390_cpu_handle_mmu_fault(CPUState *cs, vaddr address= , int size, /* On real machines this value is dropped into LowMem. Since this is userland, simply put this someplace that cpu_loop can find it. = */ cpu->env.__excp_addr =3D address; - return 1; + cpu_loop_exit_restore(cs, retaddr); } =20 #else /* !CONFIG_USER_ONLY */ @@ -102,19 +103,20 @@ static inline uint64_t cpu_mmu_idx_to_asc(int mmu_idx) } } =20 -int s390_cpu_handle_mmu_fault(CPUState *cs, vaddr orig_vaddr, int size, - int rw, int mmu_idx) +bool s390_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) { S390CPU *cpu =3D S390_CPU(cs); CPUS390XState *env =3D &cpu->env; target_ulong vaddr, raddr; uint64_t asc; - int prot; + int prot, fail; =20 qemu_log_mask(CPU_LOG_MMU, "%s: addr 0x%" VADDR_PRIx " rw %d mmu_idx %= d\n", - __func__, orig_vaddr, rw, mmu_idx); + __func__, address, access_type, mmu_idx); =20 - vaddr =3D orig_vaddr; + vaddr =3D address; =20 if (mmu_idx < MMU_REAL_IDX) { asc =3D cpu_mmu_idx_to_asc(mmu_idx); @@ -122,39 +124,64 @@ int s390_cpu_handle_mmu_fault(CPUState *cs, vaddr ori= g_vaddr, int size, if (!(env->psw.mask & PSW_MASK_64)) { vaddr &=3D 0x7fffffff; } - if (mmu_translate(env, vaddr, rw, asc, &raddr, &prot, true)) { - return 1; - } + fail =3D mmu_translate(env, vaddr, access_type, asc, &raddr, &prot= , true); } else if (mmu_idx =3D=3D MMU_REAL_IDX) { /* 31-Bit mode */ if (!(env->psw.mask & PSW_MASK_64)) { vaddr &=3D 0x7fffffff; } - if (mmu_translate_real(env, vaddr, rw, &raddr, &prot)) { - return 1; - } + fail =3D mmu_translate_real(env, vaddr, access_type, &raddr, &prot= ); } else { - abort(); + g_assert_not_reached(); } =20 /* check out of RAM access */ - if (!address_space_access_valid(&address_space_memory, raddr, - TARGET_PAGE_SIZE, rw, + if (!fail && + !address_space_access_valid(&address_space_memory, raddr, + TARGET_PAGE_SIZE, access_type, MEMTXATTRS_UNSPECIFIED)) { qemu_log_mask(CPU_LOG_MMU, "%s: raddr %" PRIx64 " > ram_size %" PRIx64 "\n", __func__, (uint64_t)raddr, (uint64_t)ram_size); trigger_pgm_exception(env, PGM_ADDRESSING, ILEN_AUTO); - return 1; + fail =3D 1; } =20 - qemu_log_mask(CPU_LOG_MMU, "%s: set tlb %" PRIx64 " -> %" PRIx64 " (%x= )\n", - __func__, (uint64_t)vaddr, (uint64_t)raddr, prot); + if (!fail) { + qemu_log_mask(CPU_LOG_MMU, + "%s: set tlb %" PRIx64 " -> %" PRIx64 " (%x)\n", + __func__, (uint64_t)vaddr, (uint64_t)raddr, prot); + tlb_set_page(cs, address & TARGET_PAGE_MASK, raddr, prot, + mmu_idx, TARGET_PAGE_SIZE); + return true; + } + if (probe) { + return false; + } =20 - tlb_set_page(cs, orig_vaddr & TARGET_PAGE_MASK, raddr, prot, - mmu_idx, TARGET_PAGE_SIZE); + cpu_restore_state(cs, retaddr, true); =20 - return 0; + /* + * The ILC value for code accesses is undefined. The important + * thing here is to *not* leave env->int_pgm_ilen set to ILEN_AUTO, + * which would cause do_program_interrupt to attempt to read from + * env->psw.addr again. C.f. the condition in trigger_page_fault, + * but is not universally applied. + * + * ??? If we remove ILEN_AUTO, by moving the computation of ILEN + * into cpu_restore_state, then we may remove this entirely. + */ + if (access_type =3D=3D MMU_INST_FETCH) { + env->int_pgm_ilen =3D 2; + } + + cpu_loop_exit(cs); +} + +void tlb_fill(CPUState *cs, target_ulong addr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) +{ + s390_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr= ); } =20 static void do_program_interrupt(CPUS390XState *env) diff --git a/target/s390x/mem_helper.c b/target/s390x/mem_helper.c index 3f76a8abfd..ffd5f02fbe 100644 --- a/target/s390x/mem_helper.c +++ b/target/s390x/mem_helper.c @@ -33,22 +33,6 @@ =20 /*************************************************************************= ****/ /* Softmmu support */ -#if !defined(CONFIG_USER_ONLY) - -/* try to fill the TLB and return an exception if error. If retaddr is - NULL, it means that the function was called in C code (i.e. not - from generated code or from helper.c) */ -/* XXX: fix it to restore all registers */ -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - int ret =3D s390_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu= _idx); - if (unlikely(ret !=3D 0)) { - cpu_loop_exit_restore(cs, retaddr); - } -} - -#endif =20 /* #define DEBUG_HELPER */ #ifdef DEBUG_HELPER --=20 2.17.1 From nobody Tue Apr 30 04:47:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1557502840; cv=none; d=zoho.com; s=zohoarc; b=RRc9icuENHivKogHTji8omCRy/5baxEG/aGLZR5EnPhXseUvLi+paDswgVhMqxaGJVJWXvtXTOf8qbMvGYLP0ewEbmzO/wVlpEMlEqkXqQmuZMhYYCPXihLG4q7BfVBuxCG6PObZCbe7X48TY1k5P5boJWa1oetaTfQOvf648l4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1557502840; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=13zPpr8eu2CJQOgqlDgYW1euE5CjP18/vmWEohkbXwc=; b=kLccd2ApozDu/TYyJFSh3nebN2cr3akE9JDha/uPIPUk0MJ48g/MxCcdqZQXEPF9pCmsIp4FlMLbzMVAYdk+LUaz07e0UWzsdvd3iI5E+cPF/XJrPyPMZkRDoPnLc4qEms33KBqN2ogHgsxNLUpjsyP8Oz7PCF1MdDS3/WE0HiQ= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1557502840537349.0264247868721; Fri, 10 May 2019 08:40:40 -0700 (PDT) Received: from localhost ([127.0.0.1]:45274 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hP7dU-0001cN-HX for importer@patchew.org; Fri, 10 May 2019 11:40:36 -0400 Received: from eggs.gnu.org ([209.51.188.92]:56318) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hP7Jl-0007jb-CA for qemu-devel@nongnu.org; Fri, 10 May 2019 11:20:14 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hP7Jj-0000Cb-PW for qemu-devel@nongnu.org; Fri, 10 May 2019 11:20:13 -0400 Received: from mail-pg1-x542.google.com ([2607:f8b0:4864:20::542]:41798) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hP7Jj-0000BS-Hi for qemu-devel@nongnu.org; Fri, 10 May 2019 11:20:11 -0400 Received: by mail-pg1-x542.google.com with SMTP id z3so3175178pgp.8 for ; Fri, 10 May 2019 08:20:11 -0700 (PDT) Received: from localhost.localdomain (97-113-13-231.tukw.qwest.net. [97.113.13.231]) by smtp.gmail.com with ESMTPSA id 19sm5920517pgz.24.2019.05.10.08.20.09 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 10 May 2019 08:20:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=13zPpr8eu2CJQOgqlDgYW1euE5CjP18/vmWEohkbXwc=; b=fDlCn18UKtMmkf3KNXSl+izmHVQq2M7sw8GZb2r0jiE7FmEtsBiaux2VJwK5Jp0DmG X44fWbN9wsCB8FDuy8SJ/FEg9HqC4lg0MmJW+4IFdlAObXxeyOmUVGIAhp2rrw2TwF/O AW65UgC9mrxzHDmEuft9ZwAlbYekzgf8lULqU/ME6akEmFRXQg0vQaH267mrF+En3HQW ZqsoLA7hqn8cKp+y/8ZvTlHIj/OpNj6cYBzKqUvnrK8GxwSFDCwOm4HFpsCXHr/6DMiO SucxGXRUIor/yx5HUUVlbnbE1lH8uXPvLSpzP2n2eso5NaQHmXYWJRBYwyvG93icM65h 67Tg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=13zPpr8eu2CJQOgqlDgYW1euE5CjP18/vmWEohkbXwc=; b=Ud4SFlQkVlKmw/AL7gWqXfoIJQXuObkpk7SJYZfv13YN4s7ZCLZhW0duZkJj+aGfCD u5skRbbLDFbAYEQwdG9B6F1qskiCbnSOkUXzkckTAZ9kWucjanZQlEidFVJ9jxHe+ULi IkJ9ukiPueAO76L1/r21qFH6Kj9rkq4f4lgxwPao8xJre+YWVp3A3O5HV9N3hoV2xId0 jnsLaW3pM18MLX+I+N978QpxHGcyvncxykso2LwrSjVpChxbwyiAgx6nGy/ZGUKQ/Kq6 5aLzn73lH9cOB+aqOtSCnm2FhVXEz2ixfZM9jAMT3ifLLuJVqAX1aGY8yf2RqSiztOs4 td7g== X-Gm-Message-State: APjAAAUDG+d6ka9JFRZBzkkShJ6P+Vs3p8XdUzilHCIwZFysKHT31jDN llPS4qjs8NKsTRZWdCphvOLAdH1L+bM= X-Google-Smtp-Source: APXvYqz9sL8LvWfwGcYDfsAxRh4rCJ+jocwQjWNoJYqTkwHvlLmUUlQM9kQwY7xLDK44v2BXf1johw== X-Received: by 2002:a62:ee05:: with SMTP id e5mr13260336pfi.117.1557501610322; Fri, 10 May 2019 08:20:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 10 May 2019 08:19:36 -0700 Message-Id: <20190510151944.22981-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190510151944.22981-1-richard.henderson@linaro.org> References: <20190510151944.22981-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::542 Subject: [Qemu-devel] [PULL 19/27] target/sh4: Convert to CPUClass::tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Aurelien Jarno Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Cc: Aurelien Jarno Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/sh4/cpu.h | 5 +- target/sh4/cpu.c | 5 +- target/sh4/helper.c | 197 ++++++++++++++++++++--------------------- target/sh4/op_helper.c | 12 --- 4 files changed, 101 insertions(+), 118 deletions(-) diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index 1be36fe875..547194aac7 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -243,8 +243,9 @@ void superh_cpu_do_unaligned_access(CPUState *cpu, vadd= r addr, void sh4_translate_init(void); int cpu_sh4_signal_handler(int host_signum, void *pinfo, void *puc); -int superh_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, in= t rw, - int mmu_idx); +bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); =20 void sh4_cpu_list(void); #if !defined(CONFIG_USER_ONLY) diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index da2799082e..c4736a0a73 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -229,9 +229,8 @@ static void superh_cpu_class_init(ObjectClass *oc, void= *data) cc->synchronize_from_tb =3D superh_cpu_synchronize_from_tb; cc->gdb_read_register =3D superh_cpu_gdb_read_register; cc->gdb_write_register =3D superh_cpu_gdb_write_register; -#ifdef CONFIG_USER_ONLY - cc->handle_mmu_fault =3D superh_cpu_handle_mmu_fault; -#else + cc->tlb_fill =3D superh_cpu_tlb_fill; +#ifndef CONFIG_USER_ONLY cc->do_unaligned_access =3D superh_cpu_do_unaligned_access; cc->get_phys_page_debug =3D superh_cpu_get_phys_page_debug; #endif diff --git a/target/sh4/helper.c b/target/sh4/helper.c index fa51269fb1..1517a6152f 100644 --- a/target/sh4/helper.c +++ b/target/sh4/helper.c @@ -27,43 +27,6 @@ #include "hw/sh4/sh_intc.h" #endif =20 -#if defined(CONFIG_USER_ONLY) - -void superh_cpu_do_interrupt(CPUState *cs) -{ - cs->exception_index =3D -1; -} - -int superh_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int= rw, - int mmu_idx) -{ - SuperHCPU *cpu =3D SUPERH_CPU(cs); - CPUSH4State *env =3D &cpu->env; - - env->tea =3D address; - cs->exception_index =3D -1; - switch (rw) { - case 0: - cs->exception_index =3D 0x0a0; - break; - case 1: - cs->exception_index =3D 0x0c0; - break; - case 2: - cs->exception_index =3D 0x0a0; - break; - } - return 1; -} - -int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr) -{ - /* For user mode, only U0 area is cacheable. */ - return !(addr & 0x80000000); -} - -#else /* !CONFIG_USER_ONLY */ - #define MMU_OK 0 #define MMU_ITLB_MISS (-1) #define MMU_ITLB_MULTIPLE (-2) @@ -79,6 +42,21 @@ int cpu_sh4_is_cached(CPUSH4State * env, target_ulong ad= dr) #define MMU_DADDR_ERROR_READ (-12) #define MMU_DADDR_ERROR_WRITE (-13) =20 +#if defined(CONFIG_USER_ONLY) + +void superh_cpu_do_interrupt(CPUState *cs) +{ + cs->exception_index =3D -1; +} + +int cpu_sh4_is_cached(CPUSH4State *env, target_ulong addr) +{ + /* For user mode, only U0 area is cacheable. */ + return !(addr & 0x80000000); +} + +#else /* !CONFIG_USER_ONLY */ + void superh_cpu_do_interrupt(CPUState *cs) { SuperHCPU *cpu =3D SUPERH_CPU(cs); @@ -458,69 +436,6 @@ static int get_physical_address(CPUSH4State * env, tar= get_ulong * physical, return get_mmu_address(env, physical, prot, address, rw, access_type); } =20 -int superh_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int= rw, - int mmu_idx) -{ - SuperHCPU *cpu =3D SUPERH_CPU(cs); - CPUSH4State *env =3D &cpu->env; - target_ulong physical; - int prot, ret, access_type; - - access_type =3D ACCESS_INT; - ret =3D - get_physical_address(env, &physical, &prot, address, rw, - access_type); - - if (ret !=3D MMU_OK) { - env->tea =3D address; - if (ret !=3D MMU_DTLB_MULTIPLE && ret !=3D MMU_ITLB_MULTIPLE) { - env->pteh =3D (env->pteh & PTEH_ASID_MASK) | - (address & PTEH_VPN_MASK); - } - switch (ret) { - case MMU_ITLB_MISS: - case MMU_DTLB_MISS_READ: - cs->exception_index =3D 0x040; - break; - case MMU_DTLB_MULTIPLE: - case MMU_ITLB_MULTIPLE: - cs->exception_index =3D 0x140; - break; - case MMU_ITLB_VIOLATION: - cs->exception_index =3D 0x0a0; - break; - case MMU_DTLB_MISS_WRITE: - cs->exception_index =3D 0x060; - break; - case MMU_DTLB_INITIAL_WRITE: - cs->exception_index =3D 0x080; - break; - case MMU_DTLB_VIOLATION_READ: - cs->exception_index =3D 0x0a0; - break; - case MMU_DTLB_VIOLATION_WRITE: - cs->exception_index =3D 0x0c0; - break; - case MMU_IADDR_ERROR: - case MMU_DADDR_ERROR_READ: - cs->exception_index =3D 0x0e0; - break; - case MMU_DADDR_ERROR_WRITE: - cs->exception_index =3D 0x100; - break; - default: - cpu_abort(cs, "Unhandled MMU fault"); - } - return 1; - } - - address &=3D TARGET_PAGE_MASK; - physical &=3D TARGET_PAGE_MASK; - - tlb_set_page(cs, address, physical, prot, mmu_idx, TARGET_PAGE_SIZE); - return 0; -} - hwaddr superh_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) { SuperHCPU *cpu =3D SUPERH_CPU(cs); @@ -745,7 +660,6 @@ void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, hwa= ddr addr, if (needs_tlb_flush) { tlb_flush_page(CPU(sh_env_get_cpu(s)), vpn << 10); } - =20 } else { int index =3D (addr & 0x00003f00) >> 8; tlb_t * entry =3D &s->utlb[index]; @@ -885,3 +799,84 @@ bool superh_cpu_exec_interrupt(CPUState *cs, int inter= rupt_request) } return false; } + +bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) +{ + SuperHCPU *cpu =3D SUPERH_CPU(cs); + CPUSH4State *env =3D &cpu->env; + int ret; + +#ifdef CONFIG_USER_ONLY + ret =3D (access_type =3D=3D MMU_DATA_STORE ? MMU_DTLB_VIOLATION_WRITE : + access_type =3D=3D MMU_INST_FETCH ? MMU_ITLB_VIOLATION : + MMU_DTLB_VIOLATION_READ); +#else + target_ulong physical; + int prot, sh_access_type; + + sh_access_type =3D ACCESS_INT; + ret =3D get_physical_address(env, &physical, &prot, address, + access_type, sh_access_type); + + if (ret =3D=3D MMU_OK) { + address &=3D TARGET_PAGE_MASK; + physical &=3D TARGET_PAGE_MASK; + tlb_set_page(cs, address, physical, prot, mmu_idx, TARGET_PAGE_SIZ= E); + return true; + } + if (probe) { + return false; + } + + if (ret !=3D MMU_DTLB_MULTIPLE && ret !=3D MMU_ITLB_MULTIPLE) { + env->pteh =3D (env->pteh & PTEH_ASID_MASK) | (address & PTEH_VPN_M= ASK); + } +#endif + + env->tea =3D address; + switch (ret) { + case MMU_ITLB_MISS: + case MMU_DTLB_MISS_READ: + cs->exception_index =3D 0x040; + break; + case MMU_DTLB_MULTIPLE: + case MMU_ITLB_MULTIPLE: + cs->exception_index =3D 0x140; + break; + case MMU_ITLB_VIOLATION: + cs->exception_index =3D 0x0a0; + break; + case MMU_DTLB_MISS_WRITE: + cs->exception_index =3D 0x060; + break; + case MMU_DTLB_INITIAL_WRITE: + cs->exception_index =3D 0x080; + break; + case MMU_DTLB_VIOLATION_READ: + cs->exception_index =3D 0x0a0; + break; + case MMU_DTLB_VIOLATION_WRITE: + cs->exception_index =3D 0x0c0; + break; + case MMU_IADDR_ERROR: + case MMU_DADDR_ERROR_READ: + cs->exception_index =3D 0x0e0; + break; + case MMU_DADDR_ERROR_WRITE: + cs->exception_index =3D 0x100; + break; + default: + cpu_abort(cs, "Unhandled MMU fault"); + } + cpu_loop_exit_restore(cs, retaddr); +} + +#ifndef CONFIG_USER_ONLY +void tlb_fill(CPUState *cs, target_ulong addr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) +{ + superh_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retad= dr); +} +#endif diff --git a/target/sh4/op_helper.c b/target/sh4/op_helper.c index 28027f9e0b..bd5d782b50 100644 --- a/target/sh4/op_helper.c +++ b/target/sh4/op_helper.c @@ -41,18 +41,6 @@ void superh_cpu_do_unaligned_access(CPUState *cs, vaddr = addr, cpu_loop_exit_restore(cs, retaddr); } =20 -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - int ret; - - ret =3D superh_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu_i= dx); - if (ret) { - /* now we have a real cpu fault */ - cpu_loop_exit_restore(cs, retaddr); - } -} - #endif =20 void helper_ldtlb(CPUSH4State *env) --=20 2.17.1 From nobody Tue Apr 30 04:47:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1557502406; cv=none; d=zoho.com; s=zohoarc; b=Tbde/DJe/0DGRRFmcxXEJ++qlD7mxsju8kVsuDRJzR6bQWcIXkMBFXsjbxMcQps90wfz8dxiVvDEQ6t42UqLMpwWIVnj5O0kQgho6joHQKTJsokMooS+qV41DJzbdSNXWbz2bQswRTh2FOWPhfTndjc8RauXfUpnj9k8WhAJ8OE= ARC-Message-Signature: i=1; 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[97.113.13.231]) by smtp.gmail.com with ESMTPSA id 19sm5920517pgz.24.2019.05.10.08.20.10 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 10 May 2019 08:20:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=31uk4YjQMNkXp7x9DtppMMcO/OZFqofAl5izW1hAuMk=; b=g1nhb+LXT/rD9mXKm+Qn3BTNHG4VcTPDGKD4xfSatkGioggBzYi4HpKyn/ZObWpHXn oW7rVsOaYuDU4YJAR2pohuNrHzImhf6hdAbM/LMAUhvXEUgFRT3A+PC7Z4P/27GOyTtp 4HLlIMP2Vu77GTMQX9Sph3IMlnNL9gr+AacDW4DaK4cwGyW++BiWTAaIjaoYQJyzRpbg wcepPhRt+eOKIWG1zUO+S1WG7aylHTB2M/14BD8H2Z9+eLrSI2TuHwG+lgU1xHo986dG ItdaCoUVl1ZxDAgLMzV4+C4SL2j+Zuqw+GroPFB0Ap6+Bmtu1szEj4+Aa8sPjkv5wEqe /hyQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=31uk4YjQMNkXp7x9DtppMMcO/OZFqofAl5izW1hAuMk=; b=IuAocMJ0VD+lA+Pkd0yCXDFSSdnv0UVLcS8e6RIvFkN+NQrnuS70+zulTYoPT9K1lV uanQprXf3gPTmzOu4cn5WX4RjWpVyCaYFo9XyBOAO8ULcGPkq2HLVZXmjb1bFykpAJF/ FFI00vvsy7RztP09YIHOdz5dal0NOXSZEA+SvgPKFhXUoJtmGWA4dtrLCy/dszoSGhSQ lBVMcw7RikHyWZ3yze5smu2lz3N9vg2I1vWgdVi7TnvA+axkhnETbNhbBFA6znzd5y0S cFJn6gD3Fi7qqjMPGOvLOKydqnrJSvEBmNuRv8LsdhVfSRLCcdG3bc+fzh0G+s4bDnU/ 8WdQ== X-Gm-Message-State: APjAAAVu5DlemfePax05HslbRb/+xHrYJL9SQfCyhAMmZ5fA66R4oms7 WwPpnFvXY0X2Ef7kMOO5mO2YThwCNhQ= X-Google-Smtp-Source: APXvYqx/B/89IM9k0UhcjQqvlrCAzJy+dEu0vS6rs6WztCtsqNzLJh7OkTPjNGdv32UW5lzpA1zpwQ== X-Received: by 2002:aa7:95bb:: with SMTP id a27mr3076563pfk.30.1557501611584; Fri, 10 May 2019 08:20:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 10 May 2019 08:19:37 -0700 Message-Id: <20190510151944.22981-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190510151944.22981-1-richard.henderson@linaro.org> References: <20190510151944.22981-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PULL 20/27] target/sparc: Convert to CPUClass::tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Mark Cave-Ayland , Artyom Tarasenko Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Cc: Artyom Tarasenko Cc: Mark Cave-Ayland Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/sparc/cpu.h | 5 ++-- target/sparc/cpu.c | 5 ++-- target/sparc/ldst_helper.c | 11 +------- target/sparc/mmu_helper.c | 58 ++++++++++++++++++++++++-------------- 4 files changed, 43 insertions(+), 36 deletions(-) diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 85b9665ccc..f31e8535df 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -579,8 +579,9 @@ void cpu_raise_exception_ra(CPUSPARCState *, int, uintp= tr_t) QEMU_NORETURN; void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu); void sparc_cpu_list(void); /* mmu_helper.c */ -int sparc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int= rw, - int mmu_idx); +bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmule= v); void dump_mmu(CPUSPARCState *env); =20 diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 4654c2a6a0..f93ce72eb9 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -875,9 +875,8 @@ static void sparc_cpu_class_init(ObjectClass *oc, void = *data) cc->synchronize_from_tb =3D sparc_cpu_synchronize_from_tb; cc->gdb_read_register =3D sparc_cpu_gdb_read_register; cc->gdb_write_register =3D sparc_cpu_gdb_write_register; -#ifdef CONFIG_USER_ONLY - cc->handle_mmu_fault =3D sparc_cpu_handle_mmu_fault; -#else + cc->tlb_fill =3D sparc_cpu_tlb_fill; +#ifndef CONFIG_USER_ONLY cc->do_unassigned_access =3D sparc_cpu_unassigned_access; cc->do_unaligned_access =3D sparc_cpu_do_unaligned_access; cc->get_phys_page_debug =3D sparc_cpu_get_phys_page_debug; diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c index a7fcb84ac0..2558c08a64 100644 --- a/target/sparc/ldst_helper.c +++ b/target/sparc/ldst_helper.c @@ -1925,18 +1925,9 @@ void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPU= State *cs, vaddr addr, cpu_raise_exception_ra(env, TT_UNALIGNED, retaddr); } =20 -/* try to fill the TLB and return an exception if error. If retaddr is - NULL, it means that the function was called in C code (i.e. not - from generated code or from helper.c) */ -/* XXX: fix it to restore all registers */ void tlb_fill(CPUState *cs, target_ulong addr, int size, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) { - int ret; - - ret =3D sparc_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu_id= x); - if (ret) { - cpu_loop_exit_restore(cs, retaddr); - } + sparc_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retadd= r); } #endif diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index afcc5b617d..facc0c60e9 100644 --- a/target/sparc/mmu_helper.c +++ b/target/sparc/mmu_helper.c @@ -27,13 +27,14 @@ =20 #if defined(CONFIG_USER_ONLY) =20 -int sparc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int = rw, - int mmu_idx) +bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) { SPARCCPU *cpu =3D SPARC_CPU(cs); CPUSPARCState *env =3D &cpu->env; =20 - if (rw & 2) { + if (access_type =3D=3D MMU_INST_FETCH) { cs->exception_index =3D TT_TFAULT; } else { cs->exception_index =3D TT_DFAULT; @@ -43,7 +44,7 @@ int sparc_cpu_handle_mmu_fault(CPUState *cs, vaddr addres= s, int size, int rw, env->mmuregs[4] =3D address; #endif } - return 1; + cpu_loop_exit_restore(cs, retaddr); } =20 #else @@ -208,8 +209,9 @@ static int get_physical_address(CPUSPARCState *env, hwa= ddr *physical, } =20 /* Perform address translation */ -int sparc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int = rw, - int mmu_idx) +bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) { SPARCCPU *cpu =3D SPARC_CPU(cs); CPUSPARCState *env =3D &cpu->env; @@ -218,16 +220,26 @@ int sparc_cpu_handle_mmu_fault(CPUState *cs, vaddr ad= dress, int size, int rw, target_ulong page_size; int error_code =3D 0, prot, access_index; =20 + /* + * TODO: If we ever need tlb_vaddr_to_host for this target, + * then we must figure out how to manipulate FSR and FAR + * when both MMU_NF and probe are set. In the meantime, + * do not support this use case. + */ + assert(!probe); + address &=3D TARGET_PAGE_MASK; error_code =3D get_physical_address(env, &paddr, &prot, &access_index, - address, rw, mmu_idx, &page_size); + address, access_type, + mmu_idx, &page_size); vaddr =3D address; - if (error_code =3D=3D 0) { + if (likely(error_code =3D=3D 0)) { qemu_log_mask(CPU_LOG_MMU, - "Translate at %" VADDR_PRIx " -> " TARGET_FMT_plx ", vaddr= " - TARGET_FMT_lx "\n", address, paddr, vaddr); + "Translate at %" VADDR_PRIx " -> " + TARGET_FMT_plx ", vaddr " TARGET_FMT_lx "\n", + address, paddr, vaddr); tlb_set_page(cs, vaddr, paddr, prot, mmu_idx, page_size); - return 0; + return true; } =20 if (env->mmuregs[3]) { /* Fault status register */ @@ -243,14 +255,14 @@ int sparc_cpu_handle_mmu_fault(CPUState *cs, vaddr ad= dress, int size, int rw, switching to normal mode. */ prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; tlb_set_page(cs, vaddr, paddr, prot, mmu_idx, TARGET_PAGE_SIZE); - return 0; + return true; } else { - if (rw & 2) { + if (access_type =3D=3D MMU_INST_FETCH) { cs->exception_index =3D TT_TFAULT; } else { cs->exception_index =3D TT_DFAULT; } - return 1; + cpu_loop_exit_restore(cs, retaddr); } } =20 @@ -713,8 +725,9 @@ static int get_physical_address(CPUSPARCState *env, hwa= ddr *physical, } =20 /* Perform address translation */ -int sparc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int = rw, - int mmu_idx) +bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) { SPARCCPU *cpu =3D SPARC_CPU(cs); CPUSPARCState *env =3D &cpu->env; @@ -725,8 +738,9 @@ int sparc_cpu_handle_mmu_fault(CPUState *cs, vaddr addr= ess, int size, int rw, =20 address &=3D TARGET_PAGE_MASK; error_code =3D get_physical_address(env, &paddr, &prot, &access_index, - address, rw, mmu_idx, &page_size); - if (error_code =3D=3D 0) { + address, access_type, + mmu_idx, &page_size); + if (likely(error_code =3D=3D 0)) { vaddr =3D address; =20 trace_mmu_helper_mmu_fault(address, paddr, mmu_idx, env->tl, @@ -734,10 +748,12 @@ int sparc_cpu_handle_mmu_fault(CPUState *cs, vaddr ad= dress, int size, int rw, env->dmmu.mmu_secondary_context); =20 tlb_set_page(cs, vaddr, paddr, prot, mmu_idx, page_size); - return 0; + return true; } - /* XXX */ - return 1; + if (probe) { + return false; + } + cpu_loop_exit_restore(cs, retaddr); } =20 void dump_mmu(CPUSPARCState *env) --=20 2.17.1 From nobody Tue Apr 30 04:47:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; 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[97.113.13.231]) by smtp.gmail.com with ESMTPSA id 19sm5920517pgz.24.2019.05.10.08.20.11 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 10 May 2019 08:20:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=s4MN+agLoZqxLhzSptzqanZ4wwu5I/aQQC+BedaVD0U=; b=zgg8PjH4YnENq5WLwCWpzZ+Nr3n7SoYjq2Tf9O+KHz4AQpUpOW4bykeeVfmHJEpYHb LLOLoUNZCJVdbVJ5JC9DJy6PQ1OQRe1DFhX3HMxM2tAIQ0PQNReB7c6wpni4wZFITqym kCmtC5qnsHa41DftzqZl0JABtEO20wxr/BeLLLCuQUtDIVPwIXLEAcpo3y03Ldu6wtdW uIia4tTkmrTI7OeKtauk+Man9Zo18O7m4m6S1eYmr8rYnCBkBdobx1wGwqtohI5AX71t KOEkZzpXR5GFcJoXdAuIXTTl28JGlDEsrUTIk29+m1yYlcITUJfwUnPrXdpRbmHSdmvx bFnw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=s4MN+agLoZqxLhzSptzqanZ4wwu5I/aQQC+BedaVD0U=; b=uoMpDwuW8t1rc99MkLxne4WH/YxOrKSmHJPR7c3O90HjsDNmqp4oAV1dn/vzOxvQl4 jeRLgWcSvrmc+YE7ajEQ4dxzV573q8FVFUBMCc0xaVfAOq46b+s6/VL5gUK103+inNfk HY4kJ2+FqVMZTKU1BFXqPLoiO1NtcYY6VwbjS/3bW6+PohRhzDU+DXg3J2cJrnn70QPn WUCkVX3VTHWPF6w03DPnrW15lO8QXsQEzgmadYkkFR+Z85paIkRgvPhEfXgoladdhSrv qbVYZTg8sZKLGb/XU+D8oWQGvpar+McWHwd6OGCq9cGF5JTJk532D8qsBrYIM8PIbXo3 Q/Pg== X-Gm-Message-State: APjAAAWVV09ZylIW1u575SchUmY9iGMv+ahgWx2ocjGE//uf4lUdlqAB c4YoZp+fPD4i9vh31BHHotAF8JWyDMg= X-Google-Smtp-Source: APXvYqxYZtoiEwGRG66TePA+BlifD40hFFUvFgRCy1S1LWAF96I4YMTek2DRwbyggXSwO5tSucJ9YA== X-Received: by 2002:aa7:8453:: with SMTP id r19mr15042988pfn.44.1557501612868; Fri, 10 May 2019 08:20:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 10 May 2019 08:19:38 -0700 Message-Id: <20190510151944.22981-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190510151944.22981-1-richard.henderson@linaro.org> References: <20190510151944.22981-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::534 Subject: [Qemu-devel] [PULL 21/27] target/tilegx: Convert to CPUClass::tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/tilegx/cpu.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/target/tilegx/cpu.c b/target/tilegx/cpu.c index b9d37105fa..b209c55387 100644 --- a/target/tilegx/cpu.c +++ b/target/tilegx/cpu.c @@ -25,6 +25,7 @@ #include "hw/qdev-properties.h" #include "linux-user/syscall_defs.h" #include "qemu/qemu-print.h" +#include "exec/exec-all.h" =20 static void tilegx_cpu_dump_state(CPUState *cs, FILE *f, int flags) { @@ -111,8 +112,9 @@ static void tilegx_cpu_do_interrupt(CPUState *cs) cs->exception_index =3D -1; } =20 -static int tilegx_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int si= ze, - int rw, int mmu_idx) +static bool tilegx_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) { TileGXCPU *cpu =3D TILEGX_CPU(cs); =20 @@ -122,7 +124,7 @@ static int tilegx_cpu_handle_mmu_fault(CPUState *cs, va= ddr address, int size, cpu->env.signo =3D TARGET_SIGSEGV; cpu->env.sigcode =3D 0; =20 - return 1; + cpu_loop_exit_restore(cs, retaddr); } =20 static bool tilegx_cpu_exec_interrupt(CPUState *cs, int interrupt_request) @@ -152,7 +154,7 @@ static void tilegx_cpu_class_init(ObjectClass *oc, void= *data) cc->cpu_exec_interrupt =3D tilegx_cpu_exec_interrupt; cc->dump_state =3D tilegx_cpu_dump_state; cc->set_pc =3D tilegx_cpu_set_pc; - cc->handle_mmu_fault =3D tilegx_cpu_handle_mmu_fault; + cc->tlb_fill =3D tilegx_cpu_tlb_fill; cc->gdb_num_core_regs =3D 0; cc->tcg_initialize =3D tilegx_tcg_init; } --=20 2.17.1 From nobody Tue Apr 30 04:47:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1557503089; cv=none; d=zoho.com; s=zohoarc; b=SDm1am/GtaeNE1zpf56mujOpcRhAoCBndJcDOYXTbJX66JRSvR6s+S4gW2ECYnJvv4qv+NgxiyF4xKUHNF7Gx1rzRshgSisyBOxYdJQeCriEEUh7Mhv5BFvJc2jtsnw4cEe175PIbnUTHpM/sMRjvvFXF6kSNUUxBJO2CwenBRQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1557503089; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=m8b1TfwrtSp/bIRpBWvKs+DLGDtPKUANT8NhwLlWDyg=; b=k9anfQ/CpEWEti/ZaYjt8E25M8WK5Ufce0vn9GRWVICmsIg+308+lJNAVyWACP2i5p0Wzv6v7aw+x87ZeYlvOLAypC0z2JOI+eO55Dt6Li9zDnY5vpwyNJfu2Smo820eKaj8+v23rGr8KFr9trc8ZJTzl+tQyNMBRcOjwjs4dG4= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1557503089818152.39605362908253; Fri, 10 May 2019 08:44:49 -0700 (PDT) Received: from localhost ([127.0.0.1]:45332 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hP7hV-0005jb-QB for importer@patchew.org; Fri, 10 May 2019 11:44:45 -0400 Received: from eggs.gnu.org ([209.51.188.92]:56367) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hP7Jo-0007pq-SG for qemu-devel@nongnu.org; Fri, 10 May 2019 11:20:18 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hP7Jn-0000GT-LK for qemu-devel@nongnu.org; Fri, 10 May 2019 11:20:16 -0400 Received: from mail-pg1-x535.google.com ([2607:f8b0:4864:20::535]:33187) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hP7Jn-0000Fq-F3 for qemu-devel@nongnu.org; Fri, 10 May 2019 11:20:15 -0400 Received: by mail-pg1-x535.google.com with SMTP id h17so3194448pgv.0 for ; Fri, 10 May 2019 08:20:15 -0700 (PDT) Received: from localhost.localdomain (97-113-13-231.tukw.qwest.net. [97.113.13.231]) by smtp.gmail.com with ESMTPSA id 19sm5920517pgz.24.2019.05.10.08.20.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 10 May 2019 08:20:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=m8b1TfwrtSp/bIRpBWvKs+DLGDtPKUANT8NhwLlWDyg=; b=gF0ARZK4cj+gkEGp7aUCbIQDNiAp18oKWD7gfsU78opsuT47nUJZtOmJYr7nPxfJX9 Ul0yMY5hebWanfg0/i0OF0L6vgDPi9ZnqHyH8NfovNd7SWUOVRt8tDxGTiQIi5EvCKKR K+ZFJOf9idlQlpApCVHa8HjlWXUtqsiLH9Xc7e88JLUSeSrbDT+4TamjhbUrTHsxqxSm 2lNvLl2+ePXsSfwYUfIzR0XSva94DsBhKTt/MP8jf+Z1uQBB98T4bD1xsp9m/iuU6Cq0 p1jNz44mcNCZqV6Ug12oVVaPKtj2zH+t25LQRGwsEqksyajqb4115OLHH66HiGT/hMAg Q4cg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=m8b1TfwrtSp/bIRpBWvKs+DLGDtPKUANT8NhwLlWDyg=; b=JLZOsbikiDdk0w/ZLgo+wGH6Qoy1H8x9bo0wqOVkvv+ygUHzZDd5c+zi+ydWwy45WQ OuMYKkx0Hv7l1ZSJUqcfgCMJ8y4BeQqd8sOHjyHdVOARIxftm/oHXQnQ1q4Xo/kCvZkQ RgKzSSRn7njouscLt0mw0S9x+pSKX4kyRxf4u5XzcTo1LKlQPrAb8Gc9+bRFoUnAprjR sN7YoFWbxcQI4Lf1nOpVj/faTKcNaCgeZcaM+jC3oEfp/C5d66NEhYlljocttROB5lNb 9I4pBFjDpUyYAStovSmkHBjshP7vKe5BON1m4Saq7C4PREXl0C0+FL4bcHR++svLQnm/ oL3g== X-Gm-Message-State: APjAAAWB6Mthdq5G5JUuGYv5BmAv0HM3ki+ruJC1JSC1e3OcKNhtynBH x0UlHp2rqNwBEijhqmpE9n7W8WIFAfY= X-Google-Smtp-Source: APXvYqzE1nlFj+QtNdjseMRqawBjCtuv0vRBXn+jh3p4vcqIGOB8FQu5z1k4cc9lcLyW+bAgebl+Sg== X-Received: by 2002:aa7:9116:: with SMTP id 22mr14842707pfh.165.1557501614042; Fri, 10 May 2019 08:20:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 10 May 2019 08:19:39 -0700 Message-Id: <20190510151944.22981-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190510151944.22981-1-richard.henderson@linaro.org> References: <20190510151944.22981-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::535 Subject: [Qemu-devel] [PULL 22/27] target/tricore: Convert to CPUClass::tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Acked-by: Bastian Koppelmann Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/tricore/cpu.h | 6 +++--- target/tricore/cpu.c | 1 + target/tricore/helper.c | 27 +++++++++++++++++++-------- target/tricore/op_helper.c | 26 -------------------------- 4 files changed, 23 insertions(+), 37 deletions(-) diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h index 64d1a9c75e..287f4328a3 100644 --- a/target/tricore/cpu.h +++ b/target/tricore/cpu.h @@ -417,8 +417,8 @@ static inline void cpu_get_tb_cpu_state(CPUTriCoreState= *env, target_ulong *pc, #define CPU_RESOLVING_TYPE TYPE_TRICORE_CPU =20 /* helpers.c */ -int cpu_tricore_handle_mmu_fault(CPUState *cpu, target_ulong address, - int rw, int mmu_idx); -#define cpu_handle_mmu_fault cpu_tricore_handle_mmu_fault +bool tricore_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); =20 #endif /* TRICORE_CPU_H */ diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index e8d37e4040..ea1199d27e 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -166,6 +166,7 @@ static void tricore_cpu_class_init(ObjectClass *c, void= *data) cc->synchronize_from_tb =3D tricore_cpu_synchronize_from_tb; cc->get_phys_page_attrs_debug =3D tricore_cpu_get_phys_page_attrs_debu= g; cc->tcg_initialize =3D tricore_tcg_init; + cc->tlb_fill =3D tricore_cpu_tlb_fill; } =20 #define DEFINE_TRICORE_CPU_TYPE(cpu_model, initfn) \ diff --git a/target/tricore/helper.c b/target/tricore/helper.c index 78ee87c9ea..ed184fee3a 100644 --- a/target/tricore/helper.c +++ b/target/tricore/helper.c @@ -50,8 +50,9 @@ static void raise_mmu_exception(CPUTriCoreState *env, tar= get_ulong address, { } =20 -int cpu_tricore_handle_mmu_fault(CPUState *cs, target_ulong address, - int rw, int mmu_idx) +bool tricore_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType rw, int mmu_idx, + bool probe, uintptr_t retaddr) { TriCoreCPU *cpu =3D TRICORE_CPU(cs); CPUTriCoreState *env =3D &cpu->env; @@ -64,20 +65,30 @@ int cpu_tricore_handle_mmu_fault(CPUState *cs, target_u= long address, access_type =3D ACCESS_INT; ret =3D get_physical_address(env, &physical, &prot, address, rw, access_type); - qemu_log_mask(CPU_LOG_MMU, "%s address=3D" TARGET_FMT_lx " ret %d phys= ical " TARGET_FMT_plx - " prot %d\n", __func__, address, ret, physical, prot); + + qemu_log_mask(CPU_LOG_MMU, "%s address=3D" TARGET_FMT_lx " ret %d phys= ical " + TARGET_FMT_plx " prot %d\n", + __func__, (target_ulong)address, ret, physical, prot); =20 if (ret =3D=3D TLBRET_MATCH) { tlb_set_page(cs, address & TARGET_PAGE_MASK, physical & TARGET_PAGE_MASK, prot | PAGE_EXEC, mmu_idx, TARGET_PAGE_SIZE); - ret =3D 0; - } else if (ret < 0) { + return true; + } else { + assert(ret < 0); + if (probe) { + return false; + } raise_mmu_exception(env, address, rw, ret); - ret =3D 1; + cpu_loop_exit_restore(cs, retaddr); } +} =20 - return ret; +void tlb_fill(CPUState *cs, target_ulong addr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) +{ + tricore_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, reta= ddr); } =20 static void tricore_cpu_list_entry(gpointer data, gpointer user_data) diff --git a/target/tricore/op_helper.c b/target/tricore/op_helper.c index ed9dc0c83e..601e92f92a 100644 --- a/target/tricore/op_helper.c +++ b/target/tricore/op_helper.c @@ -2793,29 +2793,3 @@ uint32_t helper_psw_read(CPUTriCoreState *env) { return psw_read(env); } - - -static inline void QEMU_NORETURN do_raise_exception_err(CPUTriCoreState *e= nv, - uint32_t exception, - int error_code, - uintptr_t pc) -{ - CPUState *cs =3D CPU(tricore_env_get_cpu(env)); - cs->exception_index =3D exception; - env->error_code =3D error_code; - /* now we have a real cpu fault */ - cpu_loop_exit_restore(cs, pc); -} - -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - int ret; - ret =3D cpu_tricore_handle_mmu_fault(cs, addr, access_type, mmu_idx); - if (ret) { - TriCoreCPU *cpu =3D TRICORE_CPU(cs); - CPUTriCoreState *env =3D &cpu->env; - do_raise_exception_err(env, cs->exception_index, - env->error_code, retaddr); - } -} --=20 2.17.1 From nobody Tue Apr 30 04:47:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1557502595; cv=none; d=zoho.com; s=zohoarc; b=f+8wTuAHv65VSwgDwl7lp6J2hWnWrGnrUXMUAK0wE9vxvLzKdbBeig9UvtyN5fPBkL1+lnPhPbQYo/JeDArF+KrWseUWX8NU9Jw4WCz+j8FCtlqRHSLKXMsuFKMpwxPKJt6w6njX3pbyXZkGOowJS0+g+koTek9F1Ng0PvpTO/U= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1557502595; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; 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[97.113.13.231]) by smtp.gmail.com with ESMTPSA id 19sm5920517pgz.24.2019.05.10.08.20.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 10 May 2019 08:20:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=LTrRBAzo3ZXhs7/OIQshe/0vUKzYgpD3ylIgF8SzGa8=; b=HvtWRwwVB1w9aF10ma3266UkhJwugJ2Xe237/AcUu98AJ0mWShJrnsyeNI9Lc/r5UO GVNbtYnI8EWn/nGjON+9NWJI6CXQSLNpAU6ne+9LYILoXin9r7d5eVSN6efyl8xN2ybU 8Ca09Y6WpgB0ALaztAQ8dt2X2OQH2oywhjmAUHFh2VLzTd6c+Xzx/GZwL7oZ3C8Fk3d3 jKF5UKibHLqKbs8L3NK8BijGdCsU39ZGH5e60WZ5bKWLZD1wvPADmiCwxe+ZNsIQXDMx 71EyIl1BJj9dkDjk6BJCLtlOdanGzRxAb2GpEMycn86abCne7kQUerf9KxVQlDUSBXBI K21g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=LTrRBAzo3ZXhs7/OIQshe/0vUKzYgpD3ylIgF8SzGa8=; b=P2TWrznBmPY89/XJny//j0AInD7KKTygESgbyZcjwKdnFFkUMidxw9iRaD6Zrqnv0C VVxKm2/cU7anmTr0pT4NnOkOGOVqBblKABnWGpZ0plDg9rOe92v7HRRwmpjjnLBEKZeT JN8IdTocQOxdbtKBOAxwdYm1BSDTUPc0L5J87BssS3sAwjEcEjjzIK2ihBUbIiuyQFq9 tK/aKzJYZ8uCuEL8sjffQXs9Fv9gMZ1frsJ0wo2AGMCe9+AdpeeiAvyyNjhsS15/1UTi H02dS1VjoHgBwLL+x1zNPNaEcHrirgXBs9/9deqzCUog6PRbSUv8wfA9C6mzZYVRRz1R j2vQ== X-Gm-Message-State: APjAAAVDN4r8GeNQqKpczgchaHAv/y0OAz2NqUKz0lupkbNlujGtMhHG uPMaomuEEmNKOwKIYN5CBtRdSfT0vl0= X-Google-Smtp-Source: APXvYqxy6tX9Mi6oLp0cu6mQnMLweSIFsnt80yXlbL/MnQ/JTRS8u16EaIBK4o1v7Jr+4NMSCS0Dgg== X-Received: by 2002:a17:902:9a08:: with SMTP id v8mr13552234plp.105.1557501615201; Fri, 10 May 2019 08:20:15 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 10 May 2019 08:19:40 -0700 Message-Id: <20190510151944.22981-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190510151944.22981-1-richard.henderson@linaro.org> References: <20190510151944.22981-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::642 Subject: [Qemu-devel] [PULL 23/27] target/unicore32: Convert to CPUClass::tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Guan Xuetao Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Remove the user-only functions, as we no longer have a user-only config. Cc: Guan Xuetao Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/unicore32/cpu.h | 5 +++-- target/unicore32/cpu.c | 5 +---- target/unicore32/helper.c | 23 ----------------------- target/unicore32/op_helper.c | 14 -------------- target/unicore32/softmmu.c | 19 +++++++++++++++---- 5 files changed, 19 insertions(+), 47 deletions(-) diff --git a/target/unicore32/cpu.h b/target/unicore32/cpu.h index 24abe5e5c0..f052ee08bf 100644 --- a/target/unicore32/cpu.h +++ b/target/unicore32/cpu.h @@ -178,8 +178,9 @@ static inline void cpu_get_tb_cpu_state(CPUUniCore32Sta= te *env, target_ulong *pc } } =20 -int uc32_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int = rw, - int mmu_idx); +bool uc32_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); void uc32_translate_init(void); void switch_mode(CPUUniCore32State *, int); =20 diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c index 2b49d1ca40..3f57c508a0 100644 --- a/target/unicore32/cpu.c +++ b/target/unicore32/cpu.c @@ -138,11 +138,8 @@ static void uc32_cpu_class_init(ObjectClass *oc, void = *data) cc->cpu_exec_interrupt =3D uc32_cpu_exec_interrupt; cc->dump_state =3D uc32_cpu_dump_state; cc->set_pc =3D uc32_cpu_set_pc; -#ifdef CONFIG_USER_ONLY - cc->handle_mmu_fault =3D uc32_cpu_handle_mmu_fault; -#else + cc->tlb_fill =3D uc32_cpu_tlb_fill; cc->get_phys_page_debug =3D uc32_cpu_get_phys_page_debug; -#endif cc->tcg_initialize =3D uc32_translate_init; dc->vmsd =3D &vmstate_uc32_cpu; } diff --git a/target/unicore32/helper.c b/target/unicore32/helper.c index a5ff2ddb74..0d4914b48d 100644 --- a/target/unicore32/helper.c +++ b/target/unicore32/helper.c @@ -215,29 +215,6 @@ void helper_cp1_putc(target_ulong x) } #endif =20 -#ifdef CONFIG_USER_ONLY -void switch_mode(CPUUniCore32State *env, int mode) -{ - UniCore32CPU *cpu =3D uc32_env_get_cpu(env); - - if (mode !=3D ASR_MODE_USER) { - cpu_abort(CPU(cpu), "Tried to switch out of user mode\n"); - } -} - -void uc32_cpu_do_interrupt(CPUState *cs) -{ - cpu_abort(cs, "NO interrupt in user mode\n"); -} - -int uc32_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, - int access_type, int mmu_idx) -{ - cpu_abort(cs, "NO mmu fault in user mode\n"); - return 1; -} -#endif - bool uc32_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { if (interrupt_request & CPU_INTERRUPT_HARD) { diff --git a/target/unicore32/op_helper.c b/target/unicore32/op_helper.c index e0a15882d3..797ba60dc9 100644 --- a/target/unicore32/op_helper.c +++ b/target/unicore32/op_helper.c @@ -242,17 +242,3 @@ uint32_t HELPER(ror_cc)(CPUUniCore32State *env, uint32= _t x, uint32_t i) return ((uint32_t)x >> shift) | (x << (32 - shift)); } } - -#ifndef CONFIG_USER_ONLY -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - int ret; - - ret =3D uc32_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu_idx= ); - if (unlikely(ret)) { - /* now we have a real cpu fault */ - cpu_loop_exit_restore(cs, retaddr); - } -} -#endif diff --git a/target/unicore32/softmmu.c b/target/unicore32/softmmu.c index 00c7e0d028..13678df4d7 100644 --- a/target/unicore32/softmmu.c +++ b/target/unicore32/softmmu.c @@ -215,8 +215,9 @@ do_fault: return code; } =20 -int uc32_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, - int access_type, int mmu_idx) +bool uc32_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) { UniCore32CPU *cpu =3D UNICORE32_CPU(cs); CPUUniCore32State *env =3D &cpu->env; @@ -257,7 +258,11 @@ int uc32_cpu_handle_mmu_fault(CPUState *cs, vaddr addr= ess, int size, phys_addr &=3D TARGET_PAGE_MASK; address &=3D TARGET_PAGE_MASK; tlb_set_page(cs, address, phys_addr, prot, mmu_idx, page_size); - return 0; + return true; + } + + if (probe) { + return false; } =20 env->cp0.c3_faultstatus =3D ret; @@ -267,7 +272,13 @@ int uc32_cpu_handle_mmu_fault(CPUState *cs, vaddr addr= ess, int size, } else { cs->exception_index =3D UC32_EXCP_DTRAP; } - return ret; + cpu_loop_exit_restore(cs, retaddr); +} + +void tlb_fill(CPUState *cs, target_ulong addr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) +{ + uc32_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr= ); 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[97.113.13.231]) by smtp.gmail.com with ESMTPSA id 19sm5920517pgz.24.2019.05.10.08.20.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 10 May 2019 08:20:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=bWfPEK+qkU+H+gRl4yZYfGof/Snf7uW20Ba+qkEL858=; b=UoWgTuLQZR1/s5vdZUOVe5/548PhR4bjgDwviQ5/ypWDXRVGNHotq52am3pdItJ7/V krQ2CZyHn6DsbECkPiFiJpq9EbKKi3ZCQBQCqSpTXOGJ/jnA3+vtgUty0V+6b9pCOQID ZpfS5PHY92BR018U3FcQEUHulqSjdIEspu5krE+E4jSep3RYh44SsdSfOvTXdknHVdjN RSahWcHRAqPGbcQ0gU8y66f8FPDHnZpy7Q4nSv89pvM4FHUw5ByV+HQmurc5uHF+BxZ5 FGAitO8SxCArx9N1OPby0+r9UumgEa6+QCyvzj4kvf4Va2dx2wdZF7W1Orb0InOT9jFQ pivQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=bWfPEK+qkU+H+gRl4yZYfGof/Snf7uW20Ba+qkEL858=; b=cTQyXY9Hrpqv7OFdPsg0MX5l8DqEKG5EiXhZLTeNaABB58BQsoCBl2eM+6+xJ7TAsB OLUgI8Y+SdnCNlQ5KdnHTWyjZDoB4b60kQqTKb15xlv6OXl+hRl2S98JyrQmubnljgih yg/E22nblSiYcYXDzbxbxIvD8RPQNoz+IEwLto90RVjkI90nTSk5brAlylTNwqFqWNw7 RBnTDX9NSxn1msDpQ6fFyVG6MeEkxiwMoM+KHZgW8ZEl3VBrGXzmpCuqUi1HYxcLbyTg kO/liENz6ArwgbnSP4sP0YZsy28zg3wfzqT8jqMwU4ixDg60MnjI6zf0XsKv+Vyxg52k RxtA== X-Gm-Message-State: APjAAAW7JGr/cgRjNszq2K/KFY2uQN0OUGigP2YNOuQ2IKTls9ViEARt hYULQMsbxutRSZrW7p7is52EM7DkxYA= X-Google-Smtp-Source: APXvYqxRrSzUMLXBVDjIpDD2Ip9mllM2Ch1rQKEosvnfdvjB7NFQzCMD9n7enEly/G53rDL+3htUMA== X-Received: by 2002:a62:3381:: with SMTP id z123mr15461144pfz.42.1557501616646; Fri, 10 May 2019 08:20:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 10 May 2019 08:19:41 -0700 Message-Id: <20190510151944.22981-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190510151944.22981-1-richard.henderson@linaro.org> References: <20190510151944.22981-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::42c Subject: [Qemu-devel] [PULL 24/27] target/xtensa: Convert to CPUClass::tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Max Filippov Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Cc: Max Filippov Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/xtensa/cpu.h | 5 +++-- target/xtensa/cpu.c | 5 ++--- target/xtensa/helper.c | 39 ++++++++++++++++++++++++++------------- 3 files changed, 31 insertions(+), 18 deletions(-) diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 5d23e1345b..68d89f8faf 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -552,8 +552,9 @@ static inline XtensaCPU *xtensa_env_get_cpu(const CPUXt= ensaState *env) #define ENV_OFFSET offsetof(XtensaCPU, env) =20 =20 -int xtensa_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, int s= ize, - int mmu_idx); +bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); void xtensa_cpu_do_interrupt(CPUState *cpu); bool xtensa_cpu_exec_interrupt(CPUState *cpu, int interrupt_request); void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr= addr, diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index a54dbe4260..da1236377e 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -181,9 +181,8 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void= *data) cc->gdb_read_register =3D xtensa_cpu_gdb_read_register; cc->gdb_write_register =3D xtensa_cpu_gdb_write_register; cc->gdb_stop_before_watchpoint =3D true; -#ifdef CONFIG_USER_ONLY - cc->handle_mmu_fault =3D xtensa_cpu_handle_mmu_fault; -#else + cc->tlb_fill =3D xtensa_cpu_tlb_fill; +#ifndef CONFIG_USER_ONLY cc->do_unaligned_access =3D xtensa_cpu_do_unaligned_access; cc->get_phys_page_debug =3D xtensa_cpu_get_phys_page_debug; cc->do_transaction_failed =3D xtensa_cpu_do_transaction_failed; diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c index 5f37f378a3..5c94f934dd 100644 --- a/target/xtensa/helper.c +++ b/target/xtensa/helper.c @@ -240,19 +240,21 @@ void xtensa_cpu_list(void) =20 #ifdef CONFIG_USER_ONLY =20 -int xtensa_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int= rw, - int mmu_idx) +bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) { XtensaCPU *cpu =3D XTENSA_CPU(cs); CPUXtensaState *env =3D &cpu->env; =20 qemu_log_mask(CPU_LOG_INT, "%s: rw =3D %d, address =3D 0x%08" VADDR_PRIx ", size = =3D %d\n", - __func__, rw, address, size); + __func__, access_type, address, size); env->sregs[EXCVADDR] =3D address; - env->sregs[EXCCAUSE] =3D rw ? STORE_PROHIBITED_CAUSE : LOAD_PROHIBITED= _CAUSE; + env->sregs[EXCCAUSE] =3D (access_type =3D=3D MMU_DATA_STORE ? + STORE_PROHIBITED_CAUSE : LOAD_PROHIBITED_CAUSE= ); cs->exception_index =3D EXC_USER; - return 1; + cpu_loop_exit_restore(cs, retaddr); } =20 #else @@ -273,31 +275,42 @@ void xtensa_cpu_do_unaligned_access(CPUState *cs, } } =20 -void tlb_fill(CPUState *cs, target_ulong vaddr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) +bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) { XtensaCPU *cpu =3D XTENSA_CPU(cs); CPUXtensaState *env =3D &cpu->env; uint32_t paddr; uint32_t page_size; unsigned access; - int ret =3D xtensa_get_physical_addr(env, true, vaddr, access_type, mm= u_idx, - &paddr, &page_size, &access); + int ret =3D xtensa_get_physical_addr(env, true, address, access_type, + mmu_idx, &paddr, &page_size, &acces= s); =20 - qemu_log_mask(CPU_LOG_MMU, "%s(%08x, %d, %d) -> %08x, ret =3D %d\n", - __func__, vaddr, access_type, mmu_idx, paddr, ret); + qemu_log_mask(CPU_LOG_MMU, "%s(%08" VADDR_PRIx + ", %d, %d) -> %08x, ret =3D %d\n", + __func__, address, access_type, mmu_idx, paddr, ret); =20 if (ret =3D=3D 0) { tlb_set_page(cs, - vaddr & TARGET_PAGE_MASK, + address & TARGET_PAGE_MASK, paddr & TARGET_PAGE_MASK, access, mmu_idx, page_size); + return true; + } else if (probe) { + return false; } else { cpu_restore_state(cs, retaddr, true); - HELPER(exception_cause_vaddr)(env, env->pc, ret, vaddr); + HELPER(exception_cause_vaddr)(env, env->pc, ret, address); } } =20 +void tlb_fill(CPUState *cs, target_ulong vaddr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) +{ + xtensa_cpu_tlb_fill(cs, vaddr, size, access_type, mmu_idx, false, reta= ddr); +} + void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr= addr, unsigned size, MMUAccessType access_= type, int mmu_idx, MemTxAttrs attrs, --=20 2.17.1 From nobody Tue Apr 30 04:47:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1557503218; cv=none; d=zoho.com; s=zohoarc; b=F1UmvsWPYwGcgGCnRo3Z/HCwTSd7TruSqMCptJwCCFQPYv1yqmaluhIA4ar/cDn6zv6Rmcxy3vxnoiHXRmFaVLiBfpm7Hyv0ibAlRo3uXgXl/kHttTT3cexvLHvnfK24Rce6mqBVkSQtKskwjl1NtPMinL8fxFGpMLs2P4dNUsA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1557503218; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=bMzkXC60BcwoBHMpxgJsN6EUo1CWOtE3C+TOmL7271Q=; b=cGef+6x0X12isH1+bUkI78obqwLLdHGbDp9wO8ETWBSfLldUT7UnFi5fcKDs9D61I4KGRoMlo6bllk+qKzR4jfi8GeX9rDNwQsaSWDOsTnvn3IbCI6m0vCBGMLO6ERNx2bp7fDjizylikbuREpgS8fZYjhYnWUU7VQ2rMSBZeLc= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 15575032180576.373676024622; Fri, 10 May 2019 08:46:58 -0700 (PDT) Received: from localhost ([127.0.0.1]:45387 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hP7jT-00077Z-Vc for importer@patchew.org; Fri, 10 May 2019 11:46:48 -0400 Received: from eggs.gnu.org ([209.51.188.92]:56412) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hP7Ju-0007ve-3z for qemu-devel@nongnu.org; Fri, 10 May 2019 11:20:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hP7Jr-0000NG-Si for qemu-devel@nongnu.org; Fri, 10 May 2019 11:20:21 -0400 Received: from mail-pl1-x644.google.com ([2607:f8b0:4864:20::644]:37937) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hP7Jr-0000Kq-J1 for qemu-devel@nongnu.org; Fri, 10 May 2019 11:20:19 -0400 Received: by mail-pl1-x644.google.com with SMTP id a59so2996139pla.5 for ; Fri, 10 May 2019 08:20:19 -0700 (PDT) Received: from localhost.localdomain (97-113-13-231.tukw.qwest.net. [97.113.13.231]) by smtp.gmail.com with ESMTPSA id 19sm5920517pgz.24.2019.05.10.08.20.16 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 10 May 2019 08:20:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=bMzkXC60BcwoBHMpxgJsN6EUo1CWOtE3C+TOmL7271Q=; b=HZNlQkbVYea9qTNlUTg5RemoRh9y3SGop+7CL6zPU0ujCqh7kNASIbK/GQ74BO0gze hy/ImTbIJ6L7477Cg5BzoxQgg2RhoJn6FbThHoxqpO3srbcl6P5pxR3Z+mfwqd1+BHz0 imsIQgs35HdH01sqUaWghrT+XS8To5q+P22EQ+/BxV+N62hOAoamiEnIJCjWHFmimcme yFeFleSO6+q70ULlUuabjrTSox2+9/aZonvnAvCNlvhRJaA7DMS+4icRJYjWurYYmqai D7a9ExauXqsoreuKF1t6xHsDSTcXnz6Ht9DiGe8GAGEPsYYygbBWminwMFYDZbsgHZbC Yl0A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bMzkXC60BcwoBHMpxgJsN6EUo1CWOtE3C+TOmL7271Q=; b=tjmkdVyoJUanpIv4cNoX/Gm71WD43xAN8t9pkpqg0p193tMTqdNPJxSboKMStK4WY6 saCy/a2Q7wvjjrgkl6vfSj2q//LvLiJoTVUNCVH25oiZlNdwvnkTGTAm17S/iPzmOivA NcUNYShBqXDcApQ/Kx9LGyrMSqLnsIXk2EhhvA2M8u/gFZ7h2NF2LyTGNp2+TYLhVvXv S6OJ5eCWhaw5FByzyAx7uQVIAWGOJymuh8H7qHKMvnHoxqqxAQvcqHeUpTgH+elH7ffB 4xN5nPCxZOEBFcxma4O+PQPHW86Uur1K/BMpIjOuCZ1LAtuJX25g8rLhIXzTJiW4dvT9 K4VQ== X-Gm-Message-State: APjAAAWL091nN/Hyc5TWOyOlW1ZCX7aQdOLFb0JPhxdSkxZy4A2HzlC7 YYczHkjKCa4+NlBehx6ezzXapMzSiZY= X-Google-Smtp-Source: APXvYqzqITVaefDlur41eIsK2L4bEy4fyuxKo+P9A622yVkYd2sGtzd9u4rFjCI3sQCI/7YVZ9GT3w== X-Received: by 2002:a17:902:12d:: with SMTP id 42mr7426838plb.4.1557501618263; Fri, 10 May 2019 08:20:18 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 10 May 2019 08:19:42 -0700 Message-Id: <20190510151944.22981-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190510151944.22981-1-richard.henderson@linaro.org> References: <20190510151944.22981-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::644 Subject: [Qemu-devel] [PULL 25/27] tcg: Use CPUClass::tlb_fill in cputlb.c X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) We can now use the CPUClass hook instead of a named function. Create a static tlb_fill function to avoid other changes within cputlb.c. This also isolates the asserts within. Remove the named tlb_fill function from all of the targets. Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 9 --------- accel/tcg/cputlb.c | 19 +++++++++++++++++++ target/alpha/helper.c | 6 ------ target/arm/helper.c | 8 -------- target/cris/helper.c | 6 ------ target/hppa/mem_helper.c | 6 ------ target/i386/excp_helper.c | 8 -------- target/lm32/helper.c | 6 ------ target/m68k/helper.c | 8 -------- target/microblaze/helper.c | 6 ------ target/mips/helper.c | 6 ------ target/moxie/helper.c | 6 ------ target/nios2/helper.c | 6 ------ target/openrisc/mmu.c | 6 ------ target/ppc/mmu_helper.c | 6 ------ target/riscv/cpu_helper.c | 6 ------ target/s390x/excp_helper.c | 6 ------ target/sh4/helper.c | 8 -------- target/sparc/ldst_helper.c | 6 ------ target/tricore/helper.c | 6 ------ target/unicore32/softmmu.c | 6 ------ target/xtensa/helper.c | 6 ------ 22 files changed, 19 insertions(+), 137 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 58e988b3b1..31f0ecc461 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -474,15 +474,6 @@ static inline void assert_no_pages_locked(void) */ struct MemoryRegionSection *iotlb_to_section(CPUState *cpu, hwaddr index, MemTxAttrs attr= s); - -/* - * Note: tlb_fill() can trigger a resize of the TLB. This means that all o= f the - * caller's prior references to the TLB table (e.g. CPUTLBEntry pointers) = must - * be discarded and looked up again (e.g. via tlb_entry()). - */ -void tlb_fill(CPUState *cpu, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr); - #endif =20 #if defined(CONFIG_USER_ONLY) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index f2f618217d..dfcd9ae168 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -855,6 +855,25 @@ static inline ram_addr_t qemu_ram_addr_from_host_nofai= l(void *ptr) return ram_addr; } =20 +/* + * Note: tlb_fill() can trigger a resize of the TLB. This means that all o= f the + * caller's prior references to the TLB table (e.g. CPUTLBEntry pointers) = must + * be discarded and looked up again (e.g. via tlb_entry()). + */ +static void tlb_fill(CPUState *cpu, target_ulong addr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t ret= addr) +{ + CPUClass *cc =3D CPU_GET_CLASS(cpu); + bool ok; + + /* + * This is not a probe, so only valid return is success; failure + * should result in exception + longjmp to the cpu loop. + */ + ok =3D cc->tlb_fill(cpu, addr, size, access_type, mmu_idx, false, reta= ddr); + assert(ok); +} + static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry, int mmu_idx, target_ulong addr, uintptr_t retaddr, diff --git a/target/alpha/helper.c b/target/alpha/helper.c index 929a217455..5fe9c87912 100644 --- a/target/alpha/helper.c +++ b/target/alpha/helper.c @@ -275,12 +275,6 @@ bool alpha_cpu_tlb_fill(CPUState *cs, vaddr addr, int = size, prot, mmu_idx, TARGET_PAGE_SIZE); return true; } - -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - alpha_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retadd= r); -} #endif /* USER_ONLY */ =20 void alpha_cpu_do_interrupt(CPUState *cs) diff --git a/target/arm/helper.c b/target/arm/helper.c index f1a2b94ddb..e2d5c8e34f 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -13127,14 +13127,6 @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address,= int size, #endif } =20 -#ifndef CONFIG_USER_ONLY -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - arm_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); -} -#endif - void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in) { /* Implement DC ZVA, which zeroes a fixed-length block of memory. diff --git a/target/cris/helper.c b/target/cris/helper.c index 69464837c8..b5159b8357 100644 --- a/target/cris/helper.c +++ b/target/cris/helper.c @@ -123,12 +123,6 @@ bool cris_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, cpu_loop_exit(cs); } =20 -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - cris_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr= ); -} - void crisv10_cpu_do_interrupt(CPUState *cs) { CRISCPU *cpu =3D CRIS_CPU(cs); diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index 5cee0c19b1..0fd3ac6645 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -260,12 +260,6 @@ bool hppa_cpu_tlb_fill(CPUState *cs, vaddr addr, int s= ize, return true; } =20 -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType type, int mmu_idx, uintptr_t retaddr) -{ - hppa_cpu_tlb_fill(cs, addr, size, type, mmu_idx, false, retaddr); -} - /* Insert (Insn/Data) TLB Address. Note this is PA 1.1 only. */ void HELPER(itlba)(CPUHPPAState *env, target_ulong addr, target_ureg reg) { diff --git a/target/i386/excp_helper.c b/target/i386/excp_helper.c index 68bf8e3f7c..fa1ead6404 100644 --- a/target/i386/excp_helper.c +++ b/target/i386/excp_helper.c @@ -700,11 +700,3 @@ bool x86_cpu_tlb_fill(CPUState *cs, vaddr addr, int si= ze, return true; #endif } - -#if !defined(CONFIG_USER_ONLY) -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - x86_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); -} -#endif diff --git a/target/lm32/helper.c b/target/lm32/helper.c index 1db9a5562e..20ea17ba23 100644 --- a/target/lm32/helper.c +++ b/target/lm32/helper.c @@ -44,12 +44,6 @@ bool lm32_cpu_tlb_fill(CPUState *cs, vaddr address, int = size, return true; } =20 -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - lm32_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr= ); -} - hwaddr lm32_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) { LM32CPU *cpu =3D LM32_CPU(cs); diff --git a/target/m68k/helper.c b/target/m68k/helper.c index 862f955f7b..9fc9e646ff 100644 --- a/target/m68k/helper.c +++ b/target/m68k/helper.c @@ -884,14 +884,6 @@ bool m68k_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, cpu_loop_exit_restore(cs, retaddr); } =20 -#ifndef CONFIG_USER_ONLY -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - m68k_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr= ); -} -#endif - uint32_t HELPER(bitrev)(uint32_t x) { x =3D ((x >> 1) & 0x55555555u) | ((x << 1) & 0xaaaaaaaau); diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index a523c77959..ab2ceeb055 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -108,12 +108,6 @@ bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int = size, cpu_loop_exit_restore(cs, retaddr); } =20 -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - mb_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); -} - void mb_cpu_do_interrupt(CPUState *cs) { MicroBlazeCPU *cpu =3D MICROBLAZE_CPU(cs); diff --git a/target/mips/helper.c b/target/mips/helper.c index 3a4917ce7b..9799f2ede1 100644 --- a/target/mips/helper.c +++ b/target/mips/helper.c @@ -944,12 +944,6 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, } =20 #ifndef CONFIG_USER_ONLY -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - mips_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr= ); -} - hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address,= int rw) { hwaddr physical; diff --git a/target/moxie/helper.c b/target/moxie/helper.c index 216cef057e..f5c1d4181c 100644 --- a/target/moxie/helper.c +++ b/target/moxie/helper.c @@ -26,12 +26,6 @@ #include "qemu/host-utils.h" #include "exec/helper-proto.h" =20 -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - moxie_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retadd= r); -} - void helper_raise_exception(CPUMoxieState *env, int ex) { CPUState *cs =3D CPU(moxie_env_get_cpu(env)); diff --git a/target/nios2/helper.c b/target/nios2/helper.c index eb2eed7ad3..ffb83fc104 100644 --- a/target/nios2/helper.c +++ b/target/nios2/helper.c @@ -311,10 +311,4 @@ bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, i= nt size, env->regs[CR_BADADDR] =3D address; cpu_loop_exit_restore(cs, retaddr); } - -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - nios2_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retadd= r); -} #endif /* !CONFIG_USER_ONLY */ diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c index 94c65a25fa..a73b12af03 100644 --- a/target/openrisc/mmu.c +++ b/target/openrisc/mmu.c @@ -178,10 +178,4 @@ hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cs, = vaddr addr) return phys_addr; } } - -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - openrisc_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, 0, retaddr= ); -} #endif diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c index afcca50530..e605efa883 100644 --- a/target/ppc/mmu_helper.c +++ b/target/ppc/mmu_helper.c @@ -3080,9 +3080,3 @@ bool ppc_cpu_tlb_fill(CPUState *cs, vaddr addr, int s= ize, } return true; } - -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - ppc_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); -} diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 2535435260..41d6db41c3 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -378,12 +378,6 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr= addr, env->badaddr =3D addr; riscv_raise_exception(env, cs->exception_index, retaddr); } - -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - riscv_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retadd= r); -} #endif =20 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, diff --git a/target/s390x/excp_helper.c b/target/s390x/excp_helper.c index a4e134bcab..3a467b72c5 100644 --- a/target/s390x/excp_helper.c +++ b/target/s390x/excp_helper.c @@ -178,12 +178,6 @@ bool s390_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, cpu_loop_exit(cs); } =20 -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - s390_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr= ); -} - static void do_program_interrupt(CPUS390XState *env) { uint64_t mask, addr; diff --git a/target/sh4/helper.c b/target/sh4/helper.c index 1517a6152f..fda195e7cb 100644 --- a/target/sh4/helper.c +++ b/target/sh4/helper.c @@ -872,11 +872,3 @@ bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, = int size, } cpu_loop_exit_restore(cs, retaddr); } - -#ifndef CONFIG_USER_ONLY -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - superh_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retad= dr); -} -#endif diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c index 2558c08a64..b4bf6faf41 100644 --- a/target/sparc/ldst_helper.c +++ b/target/sparc/ldst_helper.c @@ -1924,10 +1924,4 @@ void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPU= State *cs, vaddr addr, #endif cpu_raise_exception_ra(env, TT_UNALIGNED, retaddr); } - -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - sparc_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retadd= r); -} #endif diff --git a/target/tricore/helper.c b/target/tricore/helper.c index ed184fee3a..a680336850 100644 --- a/target/tricore/helper.c +++ b/target/tricore/helper.c @@ -85,12 +85,6 @@ bool tricore_cpu_tlb_fill(CPUState *cs, vaddr address, i= nt size, } } =20 -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - tricore_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, reta= ddr); -} - static void tricore_cpu_list_entry(gpointer data, gpointer user_data) { ObjectClass *oc =3D data; diff --git a/target/unicore32/softmmu.c b/target/unicore32/softmmu.c index 13678df4d7..27f218abf0 100644 --- a/target/unicore32/softmmu.c +++ b/target/unicore32/softmmu.c @@ -275,12 +275,6 @@ bool uc32_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, cpu_loop_exit_restore(cs, retaddr); } =20 -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - uc32_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr= ); -} - hwaddr uc32_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) { error_report("function uc32_cpu_get_phys_page_debug not " diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c index 5c94f934dd..efb966b3bf 100644 --- a/target/xtensa/helper.c +++ b/target/xtensa/helper.c @@ -305,12 +305,6 @@ bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, = int size, } } =20 -void tlb_fill(CPUState *cs, target_ulong vaddr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - xtensa_cpu_tlb_fill(cs, vaddr, size, access_type, mmu_idx, false, reta= ddr); -} - void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr= addr, unsigned size, MMUAccessType access_= type, int mmu_idx, MemTxAttrs attrs, --=20 2.17.1 From nobody Tue Apr 30 04:47:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1557502369; cv=none; d=zoho.com; s=zohoarc; b=m8nwli+Q67dzP8D5YALzD37V/oKlD/zbgfh5czq5mf0WIWgyE4stC7Ssf2CvmIxJTf7mk1hj2lJLiGcJ1i8cpCMbIFLkMc6A7dt7DASv3dAQBdUfXs1kIcEtPotXs427pW4jSpz84OGARTuBkOWF6dlxDDb+C6GyCDdBxUT67xc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; 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X-Received-From: 2607:f8b0:4864:20::42f Subject: [Qemu-devel] [PULL 26/27] tcg: Remove CPUClass::handle_mmu_fault X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) This hook is now completely replaced by tlb_fill. Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- include/qom/cpu.h | 3 --- accel/tcg/user-exec.c | 13 +++---------- 2 files changed, 3 insertions(+), 13 deletions(-) diff --git a/include/qom/cpu.h b/include/qom/cpu.h index c1f267b4e0..32983f27c3 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -117,7 +117,6 @@ struct TranslationBlock; * This always includes at least the program counter; some targets * will need to do more. If this hook is not implemented then the * default is to call @set_pc(tb->pc). - * @handle_mmu_fault: Callback for handling an MMU fault. * @tlb_fill: Callback for handling a softmmu tlb miss or user-only * address fault. For system mode, if the access is valid, call * tlb_set_page and return true; if the access is invalid, and @@ -195,8 +194,6 @@ typedef struct CPUClass { Error **errp); void (*set_pc)(CPUState *cpu, vaddr value); void (*synchronize_from_tb)(CPUState *cpu, struct TranslationBlock *tb= ); - int (*handle_mmu_fault)(CPUState *cpu, vaddr address, int size, int rw, - int mmu_index); bool (*tlb_fill)(CPUState *cpu, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 199f88c826..8cfbeb1b56 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -63,7 +63,6 @@ static inline int handle_cpu_signal(uintptr_t pc, siginfo= _t *info, { CPUState *cpu =3D current_cpu; CPUClass *cc; - int ret; unsigned long address =3D (unsigned long)info->si_addr; MMUAccessType access_type; =20 @@ -156,15 +155,9 @@ static inline int handle_cpu_signal(uintptr_t pc, sigi= nfo_t *info, helper_retaddr =3D 0; =20 cc =3D CPU_GET_CLASS(cpu); - if (cc->tlb_fill) { - access_type =3D is_write ? MMU_DATA_STORE : MMU_DATA_LOAD; - cc->tlb_fill(cpu, address, 0, access_type, MMU_USER_IDX, false, pc= ); - g_assert_not_reached(); - } else { - ret =3D cc->handle_mmu_fault(cpu, address, 0, is_write, MMU_USER_I= DX); - g_assert(ret > 0); - cpu_loop_exit_restore(cpu, pc); - } + access_type =3D is_write ? MMU_DATA_STORE : MMU_DATA_LOAD; + cc->tlb_fill(cpu, address, 0, access_type, MMU_USER_IDX, false, pc); + g_assert_not_reached(); } =20 #if defined(__i386__) --=20 2.17.1 From nobody Tue Apr 30 04:47:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1557503320; cv=none; d=zoho.com; s=zohoarc; b=dxCNJHv6rnrQwh0PCtsVzD06TG2hG6n3PoZlFtDEyndKuiNyKTzdn6LUpHxDbGvsIUQTVNK/zGQIrdjTb7uRucJ7ON3SpjWhXbGPYaK6ype97XlPyb1Be2WC0IoIyZEP4f8qvwU35ES0Cd1yHUQ8n9pLakbP/SUEdufhkn6iDSI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1557503320; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=r0SecknPCOTFJNz8WLFcQ0P40WSPEdkeOXrJuI8JGJI=; b=LupvD2N51abBqV4jJ561DcTFNu++aWFWJWFD2L99qIGf38AbFXzQzmha8U8vSXceJYiSsUPW1ZX7buj+yg+7FgllOovfXa4iQO7yPAIKcgWbEcilhk+TMWfb8vlEKWGyaCeB3ZCaMxbHpnbtKiakwIY8DQa61mnKpMEzpvoqQJ0= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1557503320314111.19844569665963; Fri, 10 May 2019 08:48:40 -0700 (PDT) Received: from localhost ([127.0.0.1]:45401 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hP7lB-0000U1-Vm for importer@patchew.org; Fri, 10 May 2019 11:48:34 -0400 Received: from eggs.gnu.org ([209.51.188.92]:56435) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hP7Jx-0007yv-JY for qemu-devel@nongnu.org; Fri, 10 May 2019 11:20:26 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hP7Jv-0000RN-Kb for qemu-devel@nongnu.org; Fri, 10 May 2019 11:20:25 -0400 Received: from mail-pg1-x542.google.com ([2607:f8b0:4864:20::542]:37591) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hP7Jv-0000QR-5X for qemu-devel@nongnu.org; Fri, 10 May 2019 11:20:23 -0400 Received: by mail-pg1-x542.google.com with SMTP id e6so3181674pgc.4 for ; Fri, 10 May 2019 08:20:23 -0700 (PDT) Received: from localhost.localdomain (97-113-13-231.tukw.qwest.net. [97.113.13.231]) by smtp.gmail.com with ESMTPSA id 19sm5920517pgz.24.2019.05.10.08.20.19 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 10 May 2019 08:20:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=r0SecknPCOTFJNz8WLFcQ0P40WSPEdkeOXrJuI8JGJI=; b=zGljSz4bJljiC8FoZ9eUzfl5/oy4Wu44aO3MYyh8+Q9v2PKF+Ef6Bcl+KnP0Js/l/f yODquTmoi1EY0M05+Qg7kDhyYsjEdSJOFk9G5GYysQHgBR6DdvjQEEMqsIkCavtwBJuD yEgLY06f33NVCe/HLlcnDK7L3euu0DOq4UvktnwVoSloEQW4jQjVJqua18BdRcaA5AGm 7M7dA/tAHWa1HWQQ9ejYFC+mSgdar9QxgMCU/pbM9UlOI5IeUDCQPfiz0SbSgphGqLVE wTLTJDCq6uIJUPqva0n6Tp8VemzfI9qwj9/AQDp6oTjTst9Rqp0jkzJB793BEtL8RJ1J Ai8g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=r0SecknPCOTFJNz8WLFcQ0P40WSPEdkeOXrJuI8JGJI=; b=X1LqZCuVEuAuha+hdE0cnhjjjnTQav6nGPM9B8Ph+CsWA2b7jiD/z1OJsee0dD8Pu+ oYdwxUeM2oxJ1TwqJ+GqKLNthYtVkt8725Sg4h9LsGqXae2jftedOmDcIpIFclfMjanY I8h7IbDLiysRaXkOTpG5Sne5voIoL3mZi4Zg7TULKATiUO6LUVc7cp6RJihyvZnnEa09 dJrn1/5uF1dc742AJrXObgu/vNs1XbRW5bilBJmOqungoivu9iAPJht6YNa4fYLyenRq yZB3WsE+2v0vHVQk1kS6T7QbJTLDbIM/xEhJJ5jMjiaGW60mE+LmwgFAotB+crMojeif LqaA== X-Gm-Message-State: APjAAAU+kKicwBy1uEtzKk9ZeVu+PAN/C/cKDyZf+GEl5iaYJLd9Wi1K sTv6cHH5K8jgzpfAOyJCiU14aTZuAWQ= X-Google-Smtp-Source: APXvYqyF/mK0iKfAqT5tXSNVBy29c4hozGirtrUJT4LZTI2pT1/Oqa5eL3o4ZhtzSmoEAH1zN1q1Eg== X-Received: by 2002:a63:6e0b:: with SMTP id j11mr1552224pgc.291.1557501621145; Fri, 10 May 2019 08:20:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 10 May 2019 08:19:44 -0700 Message-Id: <20190510151944.22981-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190510151944.22981-1-richard.henderson@linaro.org> References: <20190510151944.22981-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::542 Subject: [Qemu-devel] [PULL 27/27] tcg: Use tlb_fill probe from tlb_vaddr_to_host X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Most of the existing users would continue around a loop which would fault the tlb entry in via a normal load/store. But for AArch64 SVE we have an existing emulation bug wherein we would mark the first element of a no-fault vector load as faulted (within the FFR, not via exception) just because we did not have its address in the TLB. Now we can properly only mark it as faulted if there really is no valid, readable translation, while still not raising an exception. (Note that beyond the first element of the vector, the hardware may report a fault for any reason whatsoever; with at least one element loaded, forward progress is guaranteed.) Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- include/exec/cpu_ldst.h | 50 ++++++----------------------- accel/tcg/cputlb.c | 69 ++++++++++++++++++++++++++++++++++++----- target/arm/sve_helper.c | 6 +--- 3 files changed, 72 insertions(+), 53 deletions(-) diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index d78041d7a0..7b28a839d2 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -433,50 +433,20 @@ static inline CPUTLBEntry *tlb_entry(CPUArchState *en= v, uintptr_t mmu_idx, * @mmu_idx: MMU index to use for lookup * * Look up the specified guest virtual index in the TCG softmmu TLB. - * If the TLB contains a host virtual address suitable for direct RAM - * access, then return it. Otherwise (TLB miss, TLB entry is for an - * I/O access, etc) return NULL. - * - * This is the equivalent of the initial fast-path code used by - * TCG backends for guest load and store accesses. + * If we can translate a host virtual address suitable for direct RAM + * access, without causing a guest exception, then return it. + * Otherwise (TLB entry is for an I/O access, guest software + * TLB fill required, etc) return NULL. */ +#ifdef CONFIG_USER_ONLY static inline void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr, - int access_type, int mmu_idx) + MMUAccessType access_type, int mmu_i= dx) { -#if defined(CONFIG_USER_ONLY) return g2h(addr); -#else - CPUTLBEntry *tlbentry =3D tlb_entry(env, mmu_idx, addr); - abi_ptr tlb_addr; - uintptr_t haddr; - - switch (access_type) { - case 0: - tlb_addr =3D tlbentry->addr_read; - break; - case 1: - tlb_addr =3D tlb_addr_write(tlbentry); - break; - case 2: - tlb_addr =3D tlbentry->addr_code; - break; - default: - g_assert_not_reached(); - } - - if (!tlb_hit(tlb_addr, addr)) { - /* TLB entry is for a different page */ - return NULL; - } - - if (tlb_addr & ~TARGET_PAGE_MASK) { - /* IO access */ - return NULL; - } - - haddr =3D addr + tlbentry->addend; - return (void *)haddr; -#endif /* defined(CONFIG_USER_ONLY) */ } +#else +void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr, + MMUAccessType access_type, int mmu_idx); +#endif =20 #endif /* CPU_LDST_H */ diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index dfcd9ae168..45a5c4e123 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1007,6 +1007,16 @@ static void io_writex(CPUArchState *env, CPUIOTLBEnt= ry *iotlbentry, } } =20 +static inline target_ulong tlb_read_ofs(CPUTLBEntry *entry, size_t ofs) +{ +#if TCG_OVERSIZED_GUEST + return *(target_ulong *)((uintptr_t)entry + ofs); +#else + /* ofs might correspond to .addr_write, so use atomic_read */ + return atomic_read((target_ulong *)((uintptr_t)entry + ofs)); +#endif +} + /* Return true if ADDR is present in the victim tlb, and has been copied back to the main tlb. */ static bool victim_tlb_hit(CPUArchState *env, size_t mmu_idx, size_t index, @@ -1017,14 +1027,7 @@ static bool victim_tlb_hit(CPUArchState *env, size_t= mmu_idx, size_t index, assert_cpu_is_self(ENV_GET_CPU(env)); for (vidx =3D 0; vidx < CPU_VTLB_SIZE; ++vidx) { CPUTLBEntry *vtlb =3D &env->tlb_v_table[mmu_idx][vidx]; - target_ulong cmp; - - /* elt_ofs might correspond to .addr_write, so use atomic_read */ -#if TCG_OVERSIZED_GUEST - cmp =3D *(target_ulong *)((uintptr_t)vtlb + elt_ofs); -#else - cmp =3D atomic_read((target_ulong *)((uintptr_t)vtlb + elt_ofs)); -#endif + target_ulong cmp =3D tlb_read_ofs(vtlb, elt_ofs); =20 if (cmp =3D=3D page) { /* Found entry in victim tlb, swap tlb and iotlb. */ @@ -1108,6 +1111,56 @@ void probe_write(CPUArchState *env, target_ulong add= r, int size, int mmu_idx, } } =20 +void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr, + MMUAccessType access_type, int mmu_idx) +{ + CPUTLBEntry *entry =3D tlb_entry(env, mmu_idx, addr); + uintptr_t tlb_addr, page; + size_t elt_ofs; + + switch (access_type) { + case MMU_DATA_LOAD: + elt_ofs =3D offsetof(CPUTLBEntry, addr_read); + break; + case MMU_DATA_STORE: + elt_ofs =3D offsetof(CPUTLBEntry, addr_write); + break; + case MMU_INST_FETCH: + elt_ofs =3D offsetof(CPUTLBEntry, addr_code); + break; + default: + g_assert_not_reached(); + } + + page =3D addr & TARGET_PAGE_MASK; + tlb_addr =3D tlb_read_ofs(entry, elt_ofs); + + if (!tlb_hit_page(tlb_addr, page)) { + uintptr_t index =3D tlb_index(env, mmu_idx, addr); + + if (!victim_tlb_hit(env, mmu_idx, index, elt_ofs, page)) { + CPUState *cs =3D ENV_GET_CPU(env); + CPUClass *cc =3D CPU_GET_CLASS(cs); + + if (!cc->tlb_fill(cs, addr, 0, access_type, mmu_idx, true, 0))= { + /* Non-faulting page table read failed. */ + return NULL; + } + + /* TLB resize via tlb_fill may have moved the entry. */ + entry =3D tlb_entry(env, mmu_idx, addr); + } + tlb_addr =3D tlb_read_ofs(entry, elt_ofs); + } + + if (tlb_addr & ~TARGET_PAGE_MASK) { + /* IO access */ + return NULL; + } + + return (void *)(addr + entry->addend); +} + /* Probe for a read-modify-write atomic operation. Do not allow unaligned * operations, or io operations to proceed. Return the host address. */ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr, diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index bc847250dd..fd434c66ea 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -4598,11 +4598,7 @@ static void sve_ldnf1_r(CPUARMState *env, void *vg, = const target_ulong addr, * in the real world, obviously.) * * Then there are the annoying special cases with watchpoints... - * - * TODO: Add a form of tlb_fill that does not raise an exception, - * with a form of tlb_vaddr_to_host and a set of loads to match. - * The non_fault_vaddr_to_host would handle everything, usually, - * and the loads would handle the iomem path for watchpoints. + * TODO: Add a form of non-faulting loads using cc->tlb_fill(probe=3Dt= rue). */ host =3D tlb_vaddr_to_host(env, addr + mem_off, MMU_DATA_LOAD, mmu_idx= ); split =3D max_for_page(addr, mem_off, mem_max); --=20 2.17.1