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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id o8sm9849074wra.4.2019.05.10.04.03.58 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 10 May 2019 04:03:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=UTmgSX3YsyDWEgPgMU0oX1llXMLo7/qNT1U4uupCMLM=; b=BhIOPxWkX9rNrRiwgC5jphJezvVFyZonp4r5Jh+gGXEFFpUCLzKUACOLZOgGMvaHWk dhGnrNctd/qvxnLl4ZoeEmy7dsK9hty/ecWc0ZyjkcBVxnWkKB+KxALHlRO7XuacxvaT cC+H7N79eq0+UlR98Cdpq1MpuZh6MJZxPkdk4orW5IKnopojBiwQCrUb3uYocx0tdH3p rt/Z/j4DFnuIATqXD8fnOLiZ9B9KsgCJ313lYpGFBUhDwx4t9LX6vluptPzcQTZ9rCe5 FKXLyMJLWF/o9yHNWtGYjA4eR84oSLZ1c/C2FcNmKmPx1qXxagdn+0UhynZMXMFwCjz4 baAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=UTmgSX3YsyDWEgPgMU0oX1llXMLo7/qNT1U4uupCMLM=; b=fMPa2zP0KRxvW1ZH7Om6lYzXT8VerSZdHxoTLZMiR0oVKB1SuTw8+QowNmmOQTcYIL 9lJCxHUSx/k+syjaf0RDchJonhuzuyYRjgBlsjegwoLflYh7DJ+2ParBuJm7O9ucKh6Z MJFbOYfJvMKUJkDvKFsGw2SpRCLlcfJ2J3QIRRps0u60KGOLFMCtozvmBgIhoeAMDn0g 7HGfPqW6NN2oxL4N9G0zOSGNEUftY0HXy+VYTHxJ0YkJAVNmOwpffdkLXD3XNjoJ5IvB n1i7D/Nny0fnplow1nQMPNwEsz5h7ic2pJtaiqmotGlo0bE84iMB6WEwOY1RO1NB2Sd3 jBLw== X-Gm-Message-State: APjAAAXz23OgJTlkt2V+jbzsePPxBtAsECX01x7xOf/AoEf+YI8+RS1O CEmWWC8OxKW6Qr5UEStYzP3USw== X-Google-Smtp-Source: APXvYqzEbu+zPuVXyTcO4L9G4MazQNVAjghqENvFyOklPqwNEeJO8pmLo4KRBj4D9ldmISMLKgelkA== X-Received: by 2002:a1c:7c18:: with SMTP id x24mr6653589wmc.15.1557486240207; Fri, 10 May 2019 04:04:00 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Fri, 10 May 2019 12:03:57 +0100 Message-Id: <20190510110357.18825-1-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::344 Subject: [Qemu-devel] [PATCH v2] target/arm: Implement NSACR gating of floating point X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The NSACR register allows secure code to configure the FPU to be inaccessible to non-secure code. If the NSACR.CP10 bit is set then: * NS accesses to the FPU trap as UNDEF (ie to NS EL1 or EL2) * CPACR.{CP10,CP11} behave as if RAZ/WI * HCPTR.{TCP11,TCP10} behave as if RAO/WI Note that we do not implement the NSACR.NSASEDIS bit which gates only access to Advanced SIMD, in the same way that we don't implement the equivalent CPACR.ASEDIS and HCPTR.TASE. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- Changes v1->v2: * fixed bug in cptr_el2_read() that meant we were forcing HCPTR.{TCP11,TCP10} to 0 when they should be 1 --- target/arm/helper.c | 75 +++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 73 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 1e6eb0d0f36..f1fcce0313b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -928,9 +928,36 @@ static void cpacr_write(CPUARMState *env, const ARMCPR= egInfo *ri, } value &=3D mask; } + + /* + * For A-profile AArch32 EL3 (but not M-profile secure mode), if NSACR= .CP10 + * is 0 then CPACR.{CP11,CP10} ignore writes and read as 0b00. + */ + if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && + !arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) { + value &=3D ~(0xf << 20); + value |=3D env->cp15.cpacr_el1 & (0xf << 20); + } + env->cp15.cpacr_el1 =3D value; } =20 +static uint64_t cpacr_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + /* + * For A-profile AArch32 EL3 (but not M-profile secure mode), if NSACR= .CP10 + * is 0 then CPACR.{CP11,CP10} ignore writes and read as 0b00. + */ + uint64_t value =3D env->cp15.cpacr_el1; + + if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && + !arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) { + value &=3D ~(0xf << 20); + } + return value; +} + + static void cpacr_reset(CPUARMState *env, const ARMCPRegInfo *ri) { /* Call cpacr_write() so that we reset with the correct RAO bits set @@ -996,7 +1023,7 @@ static const ARMCPRegInfo v6_cp_reginfo[] =3D { { .name =3D "CPACR", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .crn =3D 1, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 2, .accessfn =3D cpac= r_access, .access =3D PL1_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.cpac= r_el1), - .resetfn =3D cpacr_reset, .writefn =3D cpacr_write }, + .resetfn =3D cpacr_reset, .writefn =3D cpacr_write, .readfn =3D cpac= r_read }, REGINFO_SENTINEL }; =20 @@ -4681,6 +4708,36 @@ uint64_t arm_hcr_el2_eff(CPUARMState *env) return ret; } =20 +static void cptr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* + * For A-profile AArch32 EL3, if NSACR.CP10 + * is 0 then HCPTR.{TCP11,TCP10} ignore writes and read as 1. + */ + if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && + !arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) { + value &=3D ~(0x3 << 10); + value |=3D env->cp15.cptr_el[2] & (0x3 << 10); + } + env->cp15.cptr_el[2] =3D value; +} + +static uint64_t cptr_el2_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + /* + * For A-profile AArch32 EL3, if NSACR.CP10 + * is 0 then HCPTR.{TCP11,TCP10} ignore writes and read as 1. + */ + uint64_t value =3D env->cp15.cptr_el[2]; + + if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && + !arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) { + value |=3D 0x3 << 10; + } + return value; +} + static const ARMCPRegInfo el2_cp_reginfo[] =3D { { .name =3D "HCR_EL2", .state =3D ARM_CP_STATE_AA64, .type =3D ARM_CP_IO, @@ -4728,7 +4785,8 @@ static const ARMCPRegInfo el2_cp_reginfo[] =3D { { .name =3D "CPTR_EL2", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 2, .access =3D PL2_RW, .accessfn =3D cptr_access, .resetvalue =3D 0, - .fieldoffset =3D offsetof(CPUARMState, cp15.cptr_el[2]) }, + .fieldoffset =3D offsetof(CPUARMState, cp15.cptr_el[2]), + .readfn =3D cptr_el2_read, .writefn =3D cptr_el2_write }, { .name =3D "MAIR_EL2", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 10, .crm =3D 2, .opc2 =3D 0, .access =3D PL2_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.mair= _el[2]), @@ -13527,6 +13585,19 @@ int fp_exception_el(CPUARMState *env, int cur_el) break; } =20 + /* + * The NSACR allows A-profile AArch32 EL3 and M-profile secure mode + * to control non-secure access to the FPU. It doesn't have any + * effect if EL3 is AArch64 or if EL3 doesn't exist at all. + */ + if ((arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && + cur_el <=3D 2 && !arm_is_secure_below_el3(env))) { + if (!extract32(env->cp15.nsacr, 10, 1)) { + /* FP insns act as UNDEF */ + return cur_el =3D=3D 2 ? 2 : 1; + } + } + /* For the CPTR registers we don't need to guard with an ARM_FEATURE * check because zero bits in the registers mean "don't trap". */ --=20 2.20.1