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X-Received-From: 2607:f8b0:4864:20::642 Subject: [Qemu-devel] [PATCH v3 20/27] target/sparc: Convert to CPUClass::tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Cave-Ayland , Artyom Tarasenko Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Cc: Artyom Tarasenko Cc: Mark Cave-Ayland Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- v2: Keep user-only, sparc32, and sparc64 tlb_fill separate. v3: Assert !probe for sparc32. --- target/sparc/cpu.h | 5 ++-- target/sparc/cpu.c | 5 ++-- target/sparc/ldst_helper.c | 11 +------- target/sparc/mmu_helper.c | 58 ++++++++++++++++++++++++-------------- 4 files changed, 43 insertions(+), 36 deletions(-) diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 85b9665ccc..f31e8535df 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -579,8 +579,9 @@ void cpu_raise_exception_ra(CPUSPARCState *, int, uintp= tr_t) QEMU_NORETURN; void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu); void sparc_cpu_list(void); /* mmu_helper.c */ -int sparc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int= rw, - int mmu_idx); +bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmule= v); void dump_mmu(CPUSPARCState *env); =20 diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 4654c2a6a0..f93ce72eb9 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -875,9 +875,8 @@ static void sparc_cpu_class_init(ObjectClass *oc, void = *data) cc->synchronize_from_tb =3D sparc_cpu_synchronize_from_tb; cc->gdb_read_register =3D sparc_cpu_gdb_read_register; cc->gdb_write_register =3D sparc_cpu_gdb_write_register; -#ifdef CONFIG_USER_ONLY - cc->handle_mmu_fault =3D sparc_cpu_handle_mmu_fault; -#else + cc->tlb_fill =3D sparc_cpu_tlb_fill; +#ifndef CONFIG_USER_ONLY cc->do_unassigned_access =3D sparc_cpu_unassigned_access; cc->do_unaligned_access =3D sparc_cpu_do_unaligned_access; cc->get_phys_page_debug =3D sparc_cpu_get_phys_page_debug; diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c index a7fcb84ac0..2558c08a64 100644 --- a/target/sparc/ldst_helper.c +++ b/target/sparc/ldst_helper.c @@ -1925,18 +1925,9 @@ void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPU= State *cs, vaddr addr, cpu_raise_exception_ra(env, TT_UNALIGNED, retaddr); } =20 -/* try to fill the TLB and return an exception if error. If retaddr is - NULL, it means that the function was called in C code (i.e. not - from generated code or from helper.c) */ -/* XXX: fix it to restore all registers */ void tlb_fill(CPUState *cs, target_ulong addr, int size, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) { - int ret; - - ret =3D sparc_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu_id= x); - if (ret) { - cpu_loop_exit_restore(cs, retaddr); - } + sparc_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retadd= r); } #endif diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index afcc5b617d..facc0c60e9 100644 --- a/target/sparc/mmu_helper.c +++ b/target/sparc/mmu_helper.c @@ -27,13 +27,14 @@ =20 #if defined(CONFIG_USER_ONLY) =20 -int sparc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int = rw, - int mmu_idx) +bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) { SPARCCPU *cpu =3D SPARC_CPU(cs); CPUSPARCState *env =3D &cpu->env; =20 - if (rw & 2) { + if (access_type =3D=3D MMU_INST_FETCH) { cs->exception_index =3D TT_TFAULT; } else { cs->exception_index =3D TT_DFAULT; @@ -43,7 +44,7 @@ int sparc_cpu_handle_mmu_fault(CPUState *cs, vaddr addres= s, int size, int rw, env->mmuregs[4] =3D address; #endif } - return 1; + cpu_loop_exit_restore(cs, retaddr); } =20 #else @@ -208,8 +209,9 @@ static int get_physical_address(CPUSPARCState *env, hwa= ddr *physical, } =20 /* Perform address translation */ -int sparc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int = rw, - int mmu_idx) +bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) { SPARCCPU *cpu =3D SPARC_CPU(cs); CPUSPARCState *env =3D &cpu->env; @@ -218,16 +220,26 @@ int sparc_cpu_handle_mmu_fault(CPUState *cs, vaddr ad= dress, int size, int rw, target_ulong page_size; int error_code =3D 0, prot, access_index; =20 + /* + * TODO: If we ever need tlb_vaddr_to_host for this target, + * then we must figure out how to manipulate FSR and FAR + * when both MMU_NF and probe are set. In the meantime, + * do not support this use case. + */ + assert(!probe); + address &=3D TARGET_PAGE_MASK; error_code =3D get_physical_address(env, &paddr, &prot, &access_index, - address, rw, mmu_idx, &page_size); + address, access_type, + mmu_idx, &page_size); vaddr =3D address; - if (error_code =3D=3D 0) { + if (likely(error_code =3D=3D 0)) { qemu_log_mask(CPU_LOG_MMU, - "Translate at %" VADDR_PRIx " -> " TARGET_FMT_plx ", vaddr= " - TARGET_FMT_lx "\n", address, paddr, vaddr); + "Translate at %" VADDR_PRIx " -> " + TARGET_FMT_plx ", vaddr " TARGET_FMT_lx "\n", + address, paddr, vaddr); tlb_set_page(cs, vaddr, paddr, prot, mmu_idx, page_size); - return 0; + return true; } =20 if (env->mmuregs[3]) { /* Fault status register */ @@ -243,14 +255,14 @@ int sparc_cpu_handle_mmu_fault(CPUState *cs, vaddr ad= dress, int size, int rw, switching to normal mode. */ prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; tlb_set_page(cs, vaddr, paddr, prot, mmu_idx, TARGET_PAGE_SIZE); - return 0; + return true; } else { - if (rw & 2) { + if (access_type =3D=3D MMU_INST_FETCH) { cs->exception_index =3D TT_TFAULT; } else { cs->exception_index =3D TT_DFAULT; } - return 1; + cpu_loop_exit_restore(cs, retaddr); } } =20 @@ -713,8 +725,9 @@ static int get_physical_address(CPUSPARCState *env, hwa= ddr *physical, } =20 /* Perform address translation */ -int sparc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int = rw, - int mmu_idx) +bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) { SPARCCPU *cpu =3D SPARC_CPU(cs); CPUSPARCState *env =3D &cpu->env; @@ -725,8 +738,9 @@ int sparc_cpu_handle_mmu_fault(CPUState *cs, vaddr addr= ess, int size, int rw, =20 address &=3D TARGET_PAGE_MASK; error_code =3D get_physical_address(env, &paddr, &prot, &access_index, - address, rw, mmu_idx, &page_size); - if (error_code =3D=3D 0) { + address, access_type, + mmu_idx, &page_size); + if (likely(error_code =3D=3D 0)) { vaddr =3D address; =20 trace_mmu_helper_mmu_fault(address, paddr, mmu_idx, env->tl, @@ -734,10 +748,12 @@ int sparc_cpu_handle_mmu_fault(CPUState *cs, vaddr ad= dress, int size, int rw, env->dmmu.mmu_secondary_context); =20 tlb_set_page(cs, vaddr, paddr, prot, mmu_idx, page_size); - return 0; + return true; } - /* XXX */ - return 1; + if (probe) { + return false; + } + cpu_loop_exit_restore(cs, retaddr); } =20 void dump_mmu(CPUSPARCState *env) --=20 2.17.1