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[97.113.13.231]) by smtp.gmail.com with ESMTPSA id m2sm4490521pfi.24.2019.05.09.15.26.34 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 09 May 2019 15:26:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=7ZAIu4sKS6YB4WebUUhTxA56tE0hF5se6ULN034aZNQ=; b=x7C7VdUR/J75eALT7laVxfbag0DNejwYdKa1FQi1YfsU5rw7mEhcs/G2Tn52tQR0Jk 8wfpxpSfT1KfGA02VsKNsDh6sR2sgb8WpmqI3I++ZqKX6jACMmh6x38yuvn0E4qel5mO vtI7kZBBGmUTq7O32LKgnuwJQwVH1uROLPn+zIdBTIi3/qR/pxRerZXK4zmD6ZunYXwB 1dVQ4j46dwKAvMjRFY6G4QMngs+WkU7zMTx+K18Ba/AvctbusToTIur84dC3VISrnL43 bSqMddxCXyTwJGYbS17qbfRN2lyyZKp3XYyDV6T+qWL2Ow3rUS/r02Q3c8+2aR11WyDK ka3g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7ZAIu4sKS6YB4WebUUhTxA56tE0hF5se6ULN034aZNQ=; b=fAcBkdrTwW72Qs/D/xzsDNyVVXrG3gLY4v5BOh8s2U3flVakhSPJn3gnOQMb2kEAeY ae0ZOnKs17BmeJVBZCqce2RjmYtk7Uj2kmZ2hW0Wm7jHxPXRbcb5l3JfB5f6AiT2dM8d 8PwUbSQFSLkg0e3Hke8s3XdcvUuzRp+tAa/1e1Mi3Wwu+0Au/2a9SGezLM1mEgvgrIXS XNDtB0oiLhvTjWQvamoIWv10u4k7Pu0hZmnQpznXBf+Tm2cNruse3BKCify297LTWPwL Um4iM2uQx6mXyVstZDz7EmUVjMDqG8vrq3i2I3uMRxK/Oe/+2Z7ld1PkG1AigzacoReD xWXw== X-Gm-Message-State: APjAAAVlNfOczWncHBZ6hPxkjZZitICPq7tkbVLuBXoPc08QyXLdKyA4 xfhvCPbRHC+uUE+d2BkcaZcqL8InhuU= X-Google-Smtp-Source: APXvYqyyEjm37f/QnYr/uejeCMMjlx3vp1L3LnYaL+w+gWz/GJ1FVLYiSkMbYk8BUivF+AMimJXraA== X-Received: by 2002:a63:1d05:: with SMTP id d5mr8881169pgd.157.1557440795175; Thu, 09 May 2019 15:26:35 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 9 May 2019 15:26:05 -0700 Message-Id: <20190509222631.14271-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190509222631.14271-1-richard.henderson@linaro.org> References: <20190509222631.14271-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::542 Subject: [Qemu-devel] [PATCH v3 01/27] tcg: Add CPUClass::tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) This hook will replace the (user-only mode specific) handle_mmu_fault hook, and the (system mode specific) tlb_fill function. The handle_mmu_fault hook was written as if there was a valid way to recover from an mmu fault, and had 3 possible return states. In reality, the only valid action is to raise an exception, return to the main loop, and deliver the SIGSEGV to the guest. Note that all of the current implementations of handle_mmu_fault for guests which support linux-user do in fact only ever return 1, which is the signal to return to the main loop. Using the hook for system mode requires that all targets be converted, so for now the hook is (optionally) used only from user-only mode. Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- include/qom/cpu.h | 9 +++++++++ accel/tcg/user-exec.c | 39 ++++++++++++++------------------------- 2 files changed, 23 insertions(+), 25 deletions(-) diff --git a/include/qom/cpu.h b/include/qom/cpu.h index 08abcbd3fe..c1f267b4e0 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -118,6 +118,12 @@ struct TranslationBlock; * will need to do more. If this hook is not implemented then the * default is to call @set_pc(tb->pc). * @handle_mmu_fault: Callback for handling an MMU fault. + * @tlb_fill: Callback for handling a softmmu tlb miss or user-only + * address fault. For system mode, if the access is valid, call + * tlb_set_page and return true; if the access is invalid, and + * probe is true, return false; otherwise raise an exception and + * do not return. For user-only mode, always raise an exception + * and do not return. * @get_phys_page_debug: Callback for obtaining a physical address. * @get_phys_page_attrs_debug: Callback for obtaining a physical address a= nd the * associated memory transaction attributes to use for the access. @@ -191,6 +197,9 @@ typedef struct CPUClass { void (*synchronize_from_tb)(CPUState *cpu, struct TranslationBlock *tb= ); int (*handle_mmu_fault)(CPUState *cpu, vaddr address, int size, int rw, int mmu_index); + bool (*tlb_fill)(CPUState *cpu, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr); hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr, MemTxAttrs *attrs); diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 0789984fe6..199f88c826 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -65,6 +65,7 @@ static inline int handle_cpu_signal(uintptr_t pc, siginfo= _t *info, CPUClass *cc; int ret; unsigned long address =3D (unsigned long)info->si_addr; + MMUAccessType access_type; =20 /* We must handle PC addresses from two different sources: * a call return address and a signal frame address. @@ -147,35 +148,23 @@ static inline int handle_cpu_signal(uintptr_t pc, sig= info_t *info, are still valid segv ones */ address =3D h2g_nocheck(address); =20 - cc =3D CPU_GET_CLASS(cpu); - /* see if it is an MMU fault */ - g_assert(cc->handle_mmu_fault); - ret =3D cc->handle_mmu_fault(cpu, address, 0, is_write, MMU_USER_IDX); - - if (ret =3D=3D 0) { - /* The MMU fault was handled without causing real CPU fault. - * Retain helper_retaddr for a possible second fault. - */ - return 1; - } - - /* All other paths lead to cpu_exit; clear helper_retaddr - * for next execution. + /* + * There is no way the target can handle this other than raising + * an exception. Undo signal and retaddr state prior to longjmp. */ + sigprocmask(SIG_SETMASK, old_set, NULL); helper_retaddr =3D 0; =20 - if (ret < 0) { - return 0; /* not an MMU fault */ + cc =3D CPU_GET_CLASS(cpu); + if (cc->tlb_fill) { + access_type =3D is_write ? MMU_DATA_STORE : MMU_DATA_LOAD; + cc->tlb_fill(cpu, address, 0, access_type, MMU_USER_IDX, false, pc= ); + g_assert_not_reached(); + } else { + ret =3D cc->handle_mmu_fault(cpu, address, 0, is_write, MMU_USER_I= DX); + g_assert(ret > 0); + cpu_loop_exit_restore(cpu, pc); } - - /* Now we have a real cpu fault. */ - cpu_restore_state(cpu, pc, true); - - sigprocmask(SIG_SETMASK, old_set, NULL); - cpu_loop_exit(cpu); - - /* never comes here */ - return 1; } =20 #if defined(__i386__) --=20 2.17.1 From nobody Mon May 6 12:42:50 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1557441110; cv=none; d=zoho.com; s=zohoarc; b=kt04joBGk88DRsZn6vvBUqkcgQ7UnejNSYCVCnFC5Jteo16w0B+REVGH7Gr6Wyx/V5quIL+llWZhsAQrIZa+nzpEKxC8SBceZHAbsxbTqEieuNyBHfMj4zkttRQWEnVbnYAPttgYWUcozwamoCsPFoZfop/nRaf95OGTzqYY3Hg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1557441110; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=nXQKQmWv/YKHXQBl4iXWce1fvy4Q62aar83khsKjymg=; b=gGHDKhQr+KK7X2hvh7i/5T9SaZlTzvwXCsuHf/uSwBG1NYSGjG4jPrwin5ukb+/qgmq40rL2HyLvOsNOnv+HnPVfoFT70bKSNmfUdOeemZA4xSw3RNYkFI4b1S/VhO2I3GLeT4kWHIa+TD3I1owH3SuG2qzk5zMq06Y4P+Uakyg= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1557441110426726.7540292818742; Thu, 9 May 2019 15:31:50 -0700 (PDT) Received: from localhost ([127.0.0.1]:33500 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hOrZo-0002i5-5W for importer@patchew.org; Thu, 09 May 2019 18:31:44 -0400 Received: from eggs.gnu.org ([209.51.188.92]:32822) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hOrUt-0007Vl-Bq for qemu-devel@nongnu.org; Thu, 09 May 2019 18:26:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hOrUs-0005NK-7M for qemu-devel@nongnu.org; Thu, 09 May 2019 18:26:39 -0400 Received: from mail-pg1-x541.google.com ([2607:f8b0:4864:20::541]:41913) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hOrUs-0005N4-1M for qemu-devel@nongnu.org; Thu, 09 May 2019 18:26:38 -0400 Received: by mail-pg1-x541.google.com with SMTP id z3so1917845pgp.8 for ; Thu, 09 May 2019 15:26:37 -0700 (PDT) Received: from localhost.localdomain (97-113-13-231.tukw.qwest.net. [97.113.13.231]) by smtp.gmail.com with ESMTPSA id m2sm4490521pfi.24.2019.05.09.15.26.35 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 09 May 2019 15:26:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=nXQKQmWv/YKHXQBl4iXWce1fvy4Q62aar83khsKjymg=; b=QIufI29MTORtO+OHVlp9TjqlBuZZiKinoDQc/iLnX2ChP1xYp2lwQJPTOpI3N5NpGO tcqTBc7unyWtOiY5QNQ1469ryqPQzuNJ2Lw87pmw6NQYUFg2/j4w5TgVoSupJiCD1+cY 7lXb7EEP7SoqpNUTHEcsckqRqqiN/fLFxb4DepEK6d6EN436mx6qW58XZ00oanChQfqN kkDTPmDVZUtW/TCaMyspA8CwhB6K4YU5ycyvCVqlqFh1UyBOnO/S4SdRaHYjH9D4TcRG Qs+WN9bS7fgZEQwvS6RISQ8UX1SNO9fRCEocsE5gsxvCCgDZ82J1xQmvmUCcXRzjlT4s ZJBA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=nXQKQmWv/YKHXQBl4iXWce1fvy4Q62aar83khsKjymg=; b=C9SI0YnSj5BTZKe8qOL4lbESZ+DaDe5Q4UMR/PF+mhYCspeW3gV2Ktc16NUyIHNwq1 StkNKXrNCcIgoc0C8/Ss/p1TBnwj1UOFQcEBdQ7jgV0kcGufOrWHQ3nLg8OZS6l6Rn2N EKZPPDl/oxLh5Cg29H396Guh/xNtCeCv0QbHdMUVy/CKfAXTlE8zbOTr7cnC2haeD3fB TDHeTCwIwbpagAx/joJi5da0XwNjKoOvPopMj/dqcUilz6CS22OWUml3W7OiQgfsadm7 EK3Llk2uqfjxc+HZJwXXnGqMtmXlAU5qfgYHUxNpgz+5Ft+zh9KOXSu31jNnPMs2oN05 veUg== X-Gm-Message-State: APjAAAUokJ8+MXTcfFzxMRXlO+SbdM1NfPAYOtz7HROVPG2LX8vdOnDi P/vRV9KljqZOydTFh/fQpMEkWMzywuk= X-Google-Smtp-Source: APXvYqyFkXGjcEQT82nLW8p3wpqf4g628Ax9hrRvP5Vf0LRKkS354X0dyb2viULCYbBHtSFfMQW61w== X-Received: by 2002:a63:5742:: with SMTP id h2mr9017998pgm.194.1557440796601; Thu, 09 May 2019 15:26:36 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 9 May 2019 15:26:06 -0700 Message-Id: <20190509222631.14271-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190509222631.14271-1-richard.henderson@linaro.org> References: <20190509222631.14271-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH v3 02/27] target/alpha: Convert to CPUClass::tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v2: Keep user-only and system tlb_fill separate. --- target/alpha/cpu.h | 5 +++-- target/alpha/cpu.c | 5 ++--- target/alpha/helper.c | 30 +++++++++++++++++++++--------- target/alpha/mem_helper.c | 16 ---------------- 4 files changed, 26 insertions(+), 30 deletions(-) diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index 63bf3618ff..cf09112b6a 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -475,8 +475,9 @@ void alpha_cpu_list(void); is returned if the signal was handled by the virtual CPU. */ int cpu_alpha_signal_handler(int host_signum, void *pinfo, void *puc); -int alpha_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int= rw, - int mmu_idx); +bool alpha_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); void QEMU_NORETURN dynamic_excp(CPUAlphaState *, uintptr_t, int, int); void QEMU_NORETURN arith_excp(CPUAlphaState *, uintptr_t, int, uint64_t); =20 diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index ad3588a44a..7c81be4111 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -225,9 +225,8 @@ static void alpha_cpu_class_init(ObjectClass *oc, void = *data) cc->set_pc =3D alpha_cpu_set_pc; cc->gdb_read_register =3D alpha_cpu_gdb_read_register; cc->gdb_write_register =3D alpha_cpu_gdb_write_register; -#ifdef CONFIG_USER_ONLY - cc->handle_mmu_fault =3D alpha_cpu_handle_mmu_fault; -#else + cc->tlb_fill =3D alpha_cpu_tlb_fill; +#ifndef CONFIG_USER_ONLY cc->do_transaction_failed =3D alpha_cpu_do_transaction_failed; cc->do_unaligned_access =3D alpha_cpu_do_unaligned_access; cc->get_phys_page_debug =3D alpha_cpu_get_phys_page_debug; diff --git a/target/alpha/helper.c b/target/alpha/helper.c index 7201576aae..929a217455 100644 --- a/target/alpha/helper.c +++ b/target/alpha/helper.c @@ -104,14 +104,15 @@ void cpu_alpha_store_gr(CPUAlphaState *env, unsigned = reg, uint64_t val) } =20 #if defined(CONFIG_USER_ONLY) -int alpha_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, - int rw, int mmu_idx) +bool alpha_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) { AlphaCPU *cpu =3D ALPHA_CPU(cs); =20 cs->exception_index =3D EXCP_MMFAULT; cpu->env.trap_arg0 =3D address; - return 1; + cpu_loop_exit_restore(cs, retaddr); } #else /* Returns the OSF/1 entMM failure indication, or -1 on success. */ @@ -248,26 +249,37 @@ hwaddr alpha_cpu_get_phys_page_debug(CPUState *cs, va= ddr addr) return (fail >=3D 0 ? -1 : phys); } =20 -int alpha_cpu_handle_mmu_fault(CPUState *cs, vaddr addr, int size, int rw, - int mmu_idx) +bool alpha_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) { AlphaCPU *cpu =3D ALPHA_CPU(cs); CPUAlphaState *env =3D &cpu->env; target_ulong phys; int prot, fail; =20 - fail =3D get_physical_address(env, addr, 1 << rw, mmu_idx, &phys, &pro= t); + fail =3D get_physical_address(env, addr, 1 << access_type, + mmu_idx, &phys, &prot); if (unlikely(fail >=3D 0)) { + if (probe) { + return false; + } cs->exception_index =3D EXCP_MMFAULT; env->trap_arg0 =3D addr; env->trap_arg1 =3D fail; - env->trap_arg2 =3D (rw =3D=3D 2 ? -1 : rw); - return 1; + env->trap_arg2 =3D (access_type =3D=3D MMU_INST_FETCH ? -1 : acces= s_type); + cpu_loop_exit_restore(cs, retaddr); } =20 tlb_set_page(cs, addr & TARGET_PAGE_MASK, phys & TARGET_PAGE_MASK, prot, mmu_idx, TARGET_PAGE_SIZE); - return 0; + return true; +} + +void tlb_fill(CPUState *cs, target_ulong addr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) +{ + alpha_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retadd= r); } #endif /* USER_ONLY */ =20 diff --git a/target/alpha/mem_helper.c b/target/alpha/mem_helper.c index 011bc73dca..934faa1d6f 100644 --- a/target/alpha/mem_helper.c +++ b/target/alpha/mem_helper.c @@ -62,20 +62,4 @@ void alpha_cpu_do_transaction_failed(CPUState *cs, hwadd= r physaddr, env->error_code =3D 0; cpu_loop_exit_restore(cs, retaddr); } - -/* try to fill the TLB and return an exception if error. If retaddr is - NULL, it means that the function was called in C code (i.e. not - from generated code or from helper.c) */ -/* XXX: fix it to restore all registers */ -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - int ret; - - ret =3D alpha_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu_id= x); - if (unlikely(ret !=3D 0)) { - /* Exception index and error code are already set */ - cpu_loop_exit_restore(cs, retaddr); - } -} #endif /* CONFIG_USER_ONLY */ --=20 2.17.1 From nobody Mon May 6 12:42:50 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1557440942; cv=none; d=zoho.com; s=zohoarc; b=Js+n5ri/xqyUMog2RFqnADb3usbGWn2cvU/xfvLL+7xAlagMLsvrkFEb+yPGxQU0WtnZ2rSe5k6jhjC7kKFODOvwi4cpTrk4J+GhCscbZgDOmag/9ns2mEA/OnEozXP6QzUM3HWwSCTenbA1ZS7uHxIsIG0wrTAN5CN7+joA8TI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1557440942; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=HvxWFIl5ESd8k7Qsj0PgQnqNr4PAJyQFVyC1Otdr98A=; b=nrIGcQ53SbgUPKm/AQFTyp7Sqs8VKerjA0dA4i7ncuOSHnJ5JvSm7jBs+HJCPOXpw/qA+OHkfE/UCIXwdNf+18LVV/5wTur9bDL15Ja1TffNaiFwMTqcWOBtAiGwJqhdTXgVMnqPjhsm+fOf057fRc2P75P/3o6onnyiaWQf154= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1557440942916623.1931936978128; Thu, 9 May 2019 15:29:02 -0700 (PDT) Received: from localhost ([127.0.0.1]:33448 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hOrX8-0000b1-Oo for importer@patchew.org; Thu, 09 May 2019 18:28:58 -0400 Received: from eggs.gnu.org ([209.51.188.92]:32842) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hOrUv-0007W0-1w for qemu-devel@nongnu.org; Thu, 09 May 2019 18:26:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hOrUt-0005Nv-Hh for qemu-devel@nongnu.org; Thu, 09 May 2019 18:26:41 -0400 Received: from mail-pf1-x442.google.com ([2607:f8b0:4864:20::442]:36269) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hOrUt-0005NX-Af for qemu-devel@nongnu.org; Thu, 09 May 2019 18:26:39 -0400 Received: by mail-pf1-x442.google.com with SMTP id v80so2055058pfa.3 for ; Thu, 09 May 2019 15:26:39 -0700 (PDT) Received: from localhost.localdomain (97-113-13-231.tukw.qwest.net. [97.113.13.231]) by smtp.gmail.com with ESMTPSA id m2sm4490521pfi.24.2019.05.09.15.26.36 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 09 May 2019 15:26:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=HvxWFIl5ESd8k7Qsj0PgQnqNr4PAJyQFVyC1Otdr98A=; b=gUfTxFzhaXQuV8dwJ0wkQ0p2Qe6zBoOtZ2neNzDUcc9sBktcQ59QT7PqqRhe6YtaFI KyDUe9S23v4Fi3ZrbwEtPmmXCz9UmWF76QeiK9kTDSHMO7zgKKmBwIF1lBzWB/N2zkR7 bNHdjnyvL2r8JoWjNgvbxBhYw/6wU78u2ttwaWhFlmzAvpBO2YY26PNi3qRM3Tp2+C8z O4/f/X4FJ9A3yDLJ2r+u8y6uUet4dLI1Zw0WP8WdXG5O/aASkv4XN86J0ylm2DctXw7L NQBLihdIOxREE5wQohbOdWny+Vvsupbhbh7b00FrKcOdS629NWBq0325wfxDs6jXmf3y H9gA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=HvxWFIl5ESd8k7Qsj0PgQnqNr4PAJyQFVyC1Otdr98A=; b=hy8/MU5N7G5FPyKF65LMuPpVzmbXtqhA9y17mc/pZrnGxfqTzycBQKIToeuWhBeqBX 29ibKbw85RG7ecehw4mhH8vW+KutbjLoyznhElZPLsy2L8rWrDw67G7u4KojmD/niRK/ P+3ModNFErPQZhzW5zNGtQkzZGjPdxWynecj2NImdAdHgRTvECO8oX8L0HYnbEpKGuRF JtTeJ6OOafGiiuSJ3Lsplrik6hTQwakmvNMKAb/C3xJInwfs5zjMyjLXo+tWuvDzoORg DuAVi//1zUhbpayzBTjYhlDtapncC8TSZTx+cKSGzaKkLfWk96EbTpjPKcnO8ngHKek2 cn0A== X-Gm-Message-State: APjAAAWTW6fqBs/zF02qAw7+o+eThkzbdiRvypyacdk2YRJwNA9AYPym Z7iuG3Tc1oRjYI0A3HUP/fIboPkgW9s= X-Google-Smtp-Source: APXvYqyE67el0EEc1uXkk5KKzszJFys3MIZBTu0YJq5Hym8nsVRaeX1gswPrxDyJlJrlWCHoVRGS5Q== X-Received: by 2002:a63:445d:: with SMTP id t29mr8960638pgk.303.1557440798060; Thu, 09 May 2019 15:26:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 9 May 2019 15:26:07 -0700 Message-Id: <20190509222631.14271-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190509222631.14271-1-richard.henderson@linaro.org> References: <20190509222631.14271-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH v3 03/27] target/arm: Convert to CPUClass::tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Cc: qemu-arm@nongnu.org Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v2: Reword a comment to match the new interface. --- target/arm/internals.h | 10 +++-- target/arm/cpu.c | 22 +--------- target/arm/helper.c | 98 ++++++++++++++++++++++++++---------------- target/arm/op_helper.c | 29 ++----------- 4 files changed, 73 insertions(+), 86 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 587a1ddf58..5a02f458f3 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -761,10 +761,12 @@ static inline bool arm_extabort_type(MemTxResult resu= lt) return result !=3D MEMTX_DECODE_ERROR; } =20 -/* Do a page table walk and add page to TLB if possible */ -bool arm_tlb_fill(CPUState *cpu, vaddr address, - MMUAccessType access_type, int mmu_idx, - ARMMMUFaultInfo *fi); +bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); + +void arm_deliver_fault(ARMCPU *cpu, vaddr addr, MMUAccessType access_type, + int mmu_idx, ARMMMUFaultInfo *fi) QEMU_NORETURN; =20 /* Return true if the stage 1 translation regime is using LPAE format page * tables */ diff --git a/target/arm/cpu.c b/target/arm/cpu.c index a181fa8dc1..bb8e824c3e 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2133,23 +2133,6 @@ static Property arm_cpu_properties[] =3D { DEFINE_PROP_END_OF_LIST() }; =20 -#ifdef CONFIG_USER_ONLY -static int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, - int rw, int mmu_idx) -{ - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; - - env->exception.vaddress =3D address; - if (rw =3D=3D 2) { - cs->exception_index =3D EXCP_PREFETCH_ABORT; - } else { - cs->exception_index =3D EXCP_DATA_ABORT; - } - return 1; -} -#endif - static gchar *arm_gdb_arch_name(CPUState *cs) { ARMCPU *cpu =3D ARM_CPU(cs); @@ -2182,9 +2165,8 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) cc->synchronize_from_tb =3D arm_cpu_synchronize_from_tb; cc->gdb_read_register =3D arm_cpu_gdb_read_register; cc->gdb_write_register =3D arm_cpu_gdb_write_register; -#ifdef CONFIG_USER_ONLY - cc->handle_mmu_fault =3D arm_cpu_handle_mmu_fault; -#else + cc->tlb_fill =3D arm_cpu_tlb_fill; +#ifndef CONFIG_USER_ONLY cc->do_interrupt =3D arm_cpu_do_interrupt; cc->do_unaligned_access =3D arm_cpu_do_unaligned_access; cc->do_transaction_failed =3D arm_cpu_do_transaction_failed; diff --git a/target/arm/helper.c b/target/arm/helper.c index 1e6eb0d0f3..f1a2b94ddb 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -12596,43 +12596,6 @@ static bool get_phys_addr(CPUARMState *env, target= _ulong address, } } =20 -/* Walk the page table and (if the mapping exists) add the page - * to the TLB. Return false on success, or true on failure. Populate - * fsr with ARM DFSR/IFSR fault register format value on failure. - */ -bool arm_tlb_fill(CPUState *cs, vaddr address, - MMUAccessType access_type, int mmu_idx, - ARMMMUFaultInfo *fi) -{ - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; - hwaddr phys_addr; - target_ulong page_size; - int prot; - int ret; - MemTxAttrs attrs =3D {}; - - ret =3D get_phys_addr(env, address, access_type, - core_to_arm_mmu_idx(env, mmu_idx), &phys_addr, - &attrs, &prot, &page_size, fi, NULL); - if (!ret) { - /* - * Map a single [sub]page. Regions smaller than our declared - * target page size are handled specially, so for those we - * pass in the exact addresses. - */ - if (page_size >=3D TARGET_PAGE_SIZE) { - phys_addr &=3D TARGET_PAGE_MASK; - address &=3D TARGET_PAGE_MASK; - } - tlb_set_page_with_attrs(cs, address, phys_addr, attrs, - prot, mmu_idx, page_size); - return 0; - } - - return ret; -} - hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, MemTxAttrs *attrs) { @@ -13111,6 +13074,67 @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t= addr, uint32_t op) =20 #endif =20 +bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + +#ifdef CONFIG_USER_ONLY + cpu->env.exception.vaddress =3D address; + if (access_type =3D=3D MMU_INST_FETCH) { + cs->exception_index =3D EXCP_PREFETCH_ABORT; + } else { + cs->exception_index =3D EXCP_DATA_ABORT; + } + cpu_loop_exit_restore(cs, retaddr); +#else + hwaddr phys_addr; + target_ulong page_size; + int prot, ret; + MemTxAttrs attrs =3D {}; + ARMMMUFaultInfo fi =3D {}; + + /* + * Walk the page table and (if the mapping exists) add the page + * to the TLB. On success, return true. Otherwise, if probing, + * return false. Otherwise populate fsr with ARM DFSR/IFSR fault + * register format, and signal the fault. + */ + ret =3D get_phys_addr(&cpu->env, address, access_type, + core_to_arm_mmu_idx(&cpu->env, mmu_idx), + &phys_addr, &attrs, &prot, &page_size, &fi, NULL); + if (likely(!ret)) { + /* + * Map a single [sub]page. Regions smaller than our declared + * target page size are handled specially, so for those we + * pass in the exact addresses. + */ + if (page_size >=3D TARGET_PAGE_SIZE) { + phys_addr &=3D TARGET_PAGE_MASK; + address &=3D TARGET_PAGE_MASK; + } + tlb_set_page_with_attrs(cs, address, phys_addr, attrs, + prot, mmu_idx, page_size); + return true; + } else if (probe) { + return false; + } else { + /* now we have a real cpu fault */ + cpu_restore_state(cs, retaddr, true); + arm_deliver_fault(cpu, address, access_type, mmu_idx, &fi); + } +#endif +} + +#ifndef CONFIG_USER_ONLY +void tlb_fill(CPUState *cs, target_ulong addr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) +{ + arm_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); +} +#endif + void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in) { /* Implement DC ZVA, which zeroes a fixed-length block of memory. diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 8698b4dc83..8ee15a4bd4 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -126,8 +126,8 @@ static inline uint32_t merge_syn_data_abort(uint32_t te= mplate_syn, return syn; } =20 -static void deliver_fault(ARMCPU *cpu, vaddr addr, MMUAccessType access_ty= pe, - int mmu_idx, ARMMMUFaultInfo *fi) +void arm_deliver_fault(ARMCPU *cpu, vaddr addr, MMUAccessType access_type, + int mmu_idx, ARMMMUFaultInfo *fi) { CPUARMState *env =3D &cpu->env; int target_el; @@ -179,27 +179,6 @@ static void deliver_fault(ARMCPU *cpu, vaddr addr, MMU= AccessType access_type, raise_exception(env, exc, syn, target_el); } =20 -/* try to fill the TLB and return an exception if error. If retaddr is - * NULL, it means that the function was called in C code (i.e. not - * from generated code or from helper.c) - */ -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - bool ret; - ARMMMUFaultInfo fi =3D {}; - - ret =3D arm_tlb_fill(cs, addr, access_type, mmu_idx, &fi); - if (unlikely(ret)) { - ARMCPU *cpu =3D ARM_CPU(cs); - - /* now we have a real cpu fault */ - cpu_restore_state(cs, retaddr, true); - - deliver_fault(cpu, addr, access_type, mmu_idx, &fi); - } -} - /* Raise a data fault alignment exception for the specified virtual addres= s */ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, MMUAccessType access_type, @@ -212,7 +191,7 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr va= ddr, cpu_restore_state(cs, retaddr, true); =20 fi.type =3D ARMFault_Alignment; - deliver_fault(cpu, vaddr, access_type, mmu_idx, &fi); + arm_deliver_fault(cpu, vaddr, access_type, mmu_idx, &fi); } =20 /* arm_cpu_do_transaction_failed: handle a memory system error response @@ -233,7 +212,7 @@ void arm_cpu_do_transaction_failed(CPUState *cs, hwaddr= physaddr, =20 fi.ea =3D arm_extabort_type(response); fi.type =3D ARMFault_SyncExternal; - deliver_fault(cpu, addr, access_type, mmu_idx, &fi); + arm_deliver_fault(cpu, addr, access_type, mmu_idx, &fi); } =20 #endif /* !defined(CONFIG_USER_ONLY) */ --=20 2.17.1 From nobody Mon May 6 12:42:50 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1557441135; cv=none; d=zoho.com; s=zohoarc; b=F78ND9hZjeun6sn/2Rlp2h31UeVcD1lPJvVR0VOe+t/k+lqQKcZDMB7GFfnEfvmkbWpjcIxYmXq708ax/qqVL4UIB9pPqONAo7cEi/7wbN8aU7b2MT30R0A6JglZNWV57GAJM+MrcCfuDE0x7zrwZXkZonxivJx+GovX4EfVbO8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1557441135; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=PI6csDpWdG6t7BSfq5z2Q2G3DWQrj5ohp4MLYzjDA0s=; b=G6i7BtY6CNweDPjIOCjg1cydfuQqMobTVSIuGLIRP6vugKj+nBx+jEZBW8Sopqdjo84SnMoY/fwxzk/XrQ92cuxRzP3qgUB0yqJ9vj6jPdb4RV+AdQkjvxiiv5db6QhcmDJBBQ6UHt07JtgrK4APPY/OYrn3O4QWZbj6eGKtUwA= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1557441135369601.5282322993334; Thu, 9 May 2019 15:32:15 -0700 (PDT) Received: from localhost ([127.0.0.1]:33504 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hOraA-000318-3k for importer@patchew.org; Thu, 09 May 2019 18:32:06 -0400 Received: from eggs.gnu.org ([209.51.188.92]:32858) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hOrUv-0007Xj-Vj for qemu-devel@nongnu.org; Thu, 09 May 2019 18:26:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hOrUu-0005Og-JS for qemu-devel@nongnu.org; Thu, 09 May 2019 18:26:41 -0400 Received: from mail-pf1-x442.google.com ([2607:f8b0:4864:20::442]:43060) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hOrUu-0005OI-D1 for qemu-devel@nongnu.org; Thu, 09 May 2019 18:26:40 -0400 Received: by mail-pf1-x442.google.com with SMTP id c6so2034953pfa.10 for ; Thu, 09 May 2019 15:26:40 -0700 (PDT) Received: from localhost.localdomain (97-113-13-231.tukw.qwest.net. [97.113.13.231]) by smtp.gmail.com with ESMTPSA id m2sm4490521pfi.24.2019.05.09.15.26.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 09 May 2019 15:26:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=PI6csDpWdG6t7BSfq5z2Q2G3DWQrj5ohp4MLYzjDA0s=; b=QAtV+oiHuH571Lhxu80eQ4dRIKFTbHhoUfv7/ajK7NfDx24QyxTUbD2dyKAD9yogRm CM4ZRn7NKkbp7ekqG6Kifg5hmHg7F+M8BeHlrkzNuW8Nlt68ENyMN7UnlhK4Is1c478U x7lkHPEaHl71zSzyKnCqC79Tqsz2K2L4Aie3pykpQO8MyTLIta96P0+7GW42AztV/Cpw RNLPXzmWA68qphY7CBRdn7+MfZ9+8KuZXK3VRoKTDjhTbseiRvG/2ZPitCpVAq9OQKDV CcVTyNVtJ8sbGTJMTCQXurfcDGoxg8LNDIVrXfDYZDUR0fh6ME0gpodO5h+lZUnabdS3 tc7g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=PI6csDpWdG6t7BSfq5z2Q2G3DWQrj5ohp4MLYzjDA0s=; b=KbfuiMN6knhXxqIWh27+IufIRiKiCN66/nIt69zL0xisjlwZnBSoQ0J7C/fAdoKDJr ypYQKyCzHtWV5uyLyccEBYLtY6tpt3zCfe0BSPwR6F0BoxXwLxqtJQvghssNz85L/60U yeXwXWJh+AOjqKVxyJ3NhPaJ7zXV8vVWuuh2+15xPc7xc3oWE1Sa9r9A2V2iTQ7bVdy1 Q4fufKnpfR2FiTtGr0p6E84sWYeU4Z9i5FHREdqcPrTS5G3NIYEKhMflVwAqTCAetlNA QZuliAAsphYyGKAy8Afgqp06oeeZk7sOJdY1W/beOVZpVypR77jAFfdZB850a/XqIFB1 BGGg== X-Gm-Message-State: APjAAAUBlNhRbQ4aUOCaZPsEWAr5PFhp7SWPlniTrQmNLEGcYz+ntJ4/ bl0ysaKcAHelZuiyxfY30ys/cdMbGBY= X-Google-Smtp-Source: APXvYqxQNHo/Gp7cRZny7SUxjH5s0UPej4jL+ZxsBWf16kZjC33xd7JYdQ2kGb0E6ZUYX9gTp/tCSA== X-Received: by 2002:a63:f843:: with SMTP id v3mr8949371pgj.69.1557440799216; Thu, 09 May 2019 15:26:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 9 May 2019 15:26:08 -0700 Message-Id: <20190509222631.14271-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190509222631.14271-1-richard.henderson@linaro.org> References: <20190509222631.14271-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH v3 04/27] target/cris: Convert to CPUClass::tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Remove dumping of cpu state. Remove logging of PC, as that value is garbage until cpu_restore_state. Cc: Edgar E. Iglesias Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/cris/cpu.h | 5 +-- target/cris/cpu.c | 5 ++- target/cris/helper.c | 67 +++++++++++++++++++++++------------------ target/cris/op_helper.c | 28 ----------------- 4 files changed, 42 insertions(+), 63 deletions(-) diff --git a/target/cris/cpu.h b/target/cris/cpu.h index 0fbe771639..857de79e24 100644 --- a/target/cris/cpu.h +++ b/target/cris/cpu.h @@ -281,8 +281,9 @@ static inline int cpu_mmu_index (CPUCRISState *env, boo= l ifetch) return !!(env->pregs[PR_CCS] & U_FLAG); } =20 -int cris_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int = rw, - int mmu_idx); +bool cris_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); =20 /* Support function regs. */ #define SFR_RW_GC_CFG 0][0 diff --git a/target/cris/cpu.c b/target/cris/cpu.c index 75729bfdd5..4e5288ae80 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -269,9 +269,8 @@ static void cris_cpu_class_init(ObjectClass *oc, void *= data) cc->set_pc =3D cris_cpu_set_pc; cc->gdb_read_register =3D cris_cpu_gdb_read_register; cc->gdb_write_register =3D cris_cpu_gdb_write_register; -#ifdef CONFIG_USER_ONLY - cc->handle_mmu_fault =3D cris_cpu_handle_mmu_fault; -#else + cc->tlb_fill =3D cris_cpu_tlb_fill; +#ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D cris_cpu_get_phys_page_debug; dc->vmsd =3D &vmstate_cris_cpu; #endif diff --git a/target/cris/helper.c b/target/cris/helper.c index 3939603c73..69464837c8 100644 --- a/target/cris/helper.c +++ b/target/cris/helper.c @@ -24,6 +24,7 @@ #include "qemu/host-utils.h" #include "exec/exec-all.h" #include "exec/cpu_ldst.h" +#include "exec/helper-proto.h" =20 =20 //#define CRIS_HELPER_DEBUG @@ -53,15 +54,15 @@ void crisv10_cpu_do_interrupt(CPUState *cs) cris_cpu_do_interrupt(cs); } =20 -int cris_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int r= w, - int mmu_idx) +bool cris_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) { CRISCPU *cpu =3D CRIS_CPU(cs); =20 cs->exception_index =3D 0xaa; cpu->env.pregs[PR_EDA] =3D address; - cpu_dump_state(cs, stderr, 0); - return 1; + cpu_loop_exit_restore(cs, retaddr); } =20 #else /* !CONFIG_USER_ONLY */ @@ -76,33 +77,19 @@ static void cris_shift_ccs(CPUCRISState *env) env->pregs[PR_CCS] =3D ccs; } =20 -int cris_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int r= w, - int mmu_idx) +bool cris_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) { CRISCPU *cpu =3D CRIS_CPU(cs); CPUCRISState *env =3D &cpu->env; struct cris_mmu_result res; int prot, miss; - int r =3D -1; target_ulong phy; =20 - qemu_log_mask(CPU_LOG_MMU, "%s addr=3D%" VADDR_PRIx " pc=3D%x rw=3D%x\= n", - __func__, address, env->pc, rw); miss =3D cris_mmu_translate(&res, env, address & TARGET_PAGE_MASK, - rw, mmu_idx, 0); - if (miss) { - if (cs->exception_index =3D=3D EXCP_BUSFAULT) { - cpu_abort(cs, - "CRIS: Illegal recursive bus fault." - "addr=3D%" VADDR_PRIx " rw=3D%d\n", - address, rw); - } - - env->pregs[PR_EDA] =3D address; - cs->exception_index =3D EXCP_BUSFAULT; - env->fault_vector =3D res.bf_vec; - r =3D 1; - } else { + access_type, mmu_idx, 0); + if (likely(!miss)) { /* * Mask off the cache selection bit. The ETRAX busses do not * see the top bit. @@ -111,15 +98,35 @@ int cris_cpu_handle_mmu_fault(CPUState *cs, vaddr addr= ess, int size, int rw, prot =3D res.prot; tlb_set_page(cs, address & TARGET_PAGE_MASK, phy, prot, mmu_idx, TARGET_PAGE_SIZE); - r =3D 0; + return true; } - if (r > 0) { - qemu_log_mask(CPU_LOG_MMU, - "%s returns %d irqreq=3D%x addr=3D%" VADDR_PRIx " phy=3D%x= vec=3D%x" - " pc=3D%x\n", __func__, r, cs->interrupt_request, address, - res.phy, res.bf_vec, env->pc); + + if (probe) { + return false; } - return r; + + if (cs->exception_index =3D=3D EXCP_BUSFAULT) { + cpu_abort(cs, "CRIS: Illegal recursive bus fault." + "addr=3D%" VADDR_PRIx " access_type=3D%d\n", + address, access_type); + } + + env->pregs[PR_EDA] =3D address; + cs->exception_index =3D EXCP_BUSFAULT; + env->fault_vector =3D res.bf_vec; + if (retaddr) { + if (cpu_restore_state(cs, retaddr, true)) { + /* Evaluate flags after retranslation. */ + helper_top_evaluate_flags(env); + } + } + cpu_loop_exit(cs); +} + +void tlb_fill(CPUState *cs, target_ulong addr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) +{ + cris_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr= ); } =20 void crisv10_cpu_do_interrupt(CPUState *cs) diff --git a/target/cris/op_helper.c b/target/cris/op_helper.c index 0ee3a3117b..26a395b413 100644 --- a/target/cris/op_helper.c +++ b/target/cris/op_helper.c @@ -37,34 +37,6 @@ #define D_LOG(...) do { } while (0) #endif =20 -#if !defined(CONFIG_USER_ONLY) -/* Try to fill the TLB and return an exception if error. If retaddr is - NULL, it means that the function was called in C code (i.e. not - from generated code or from helper.c) */ -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - CRISCPU *cpu =3D CRIS_CPU(cs); - CPUCRISState *env =3D &cpu->env; - int ret; - - D_LOG("%s pc=3D%x tpc=3D%x ra=3D%p\n", __func__, - env->pc, env->pregs[PR_EDA], (void *)retaddr); - ret =3D cris_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu_idx= ); - if (unlikely(ret)) { - if (retaddr) { - /* now we have a real cpu fault */ - if (cpu_restore_state(cs, retaddr, true)) { - /* Evaluate flags after retranslation. */ - helper_top_evaluate_flags(env); - } - } - cpu_loop_exit(cs); - } -} - -#endif - void helper_raise_exception(CPUCRISState *env, uint32_t index) { CPUState *cs =3D CPU(cris_env_get_cpu(env)); --=20 2.17.1 From nobody Mon May 6 12:42:50 2024 Delivered-To: importer@patchew.org Received-SPF: temperror (zoho.com: Error in retrieving data from DNS) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1557441494; cv=none; d=zoho.com; s=zohoarc; b=oIT8kEbRCqjWM7s8vEb0pVnTIa2zHZveWVF5YaRnKHHHPkckX9r6lXD9BZicOrhm0wundoK4PK9FOLvKQfEYyNSlSXuBzU0dhRApnJhvfgedMuhVE2BWnm/w3LvtYvdnpT1NDMv/5SQZCRJfiYxoU5/pFB/tFOk3OstiMIKvWiw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1557441494; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=w7l/Pbs/dkuyE6y60mYyZzngNGSZYjs+O6jEPehbb2U=; b=B5ZxMAZNxlZiPtoVmndiJo97GjT3L/12FZKYNWyB4kJo4YZyrCTcB8LLLbQyYO1domdDV55WtOQWw2fuxBkdwUNL9aYKhoJu6yNbJ5rx4RDCZOHNQQl9kS5Q8J3l5a7vFwWEyO5PGELYkD8LNssPUyfNwSVWrCNlZ3WT/dsqrBc= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1557441494492443.87063332463015; Thu, 9 May 2019 15:38:14 -0700 (PDT) Received: from localhost ([127.0.0.1]:33587 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hOrfr-0000oO-8r for importer@patchew.org; Thu, 09 May 2019 18:37:59 -0400 Received: from eggs.gnu.org ([209.51.188.92]:32885) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hOrUx-0007aB-Bu for qemu-devel@nongnu.org; Thu, 09 May 2019 18:26:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hOrUw-0005Qr-1c for qemu-devel@nongnu.org; Thu, 09 May 2019 18:26:43 -0400 Received: from mail-pg1-x544.google.com ([2607:f8b0:4864:20::544]:39155) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hOrUv-0005P2-RY for qemu-devel@nongnu.org; Thu, 09 May 2019 18:26:41 -0400 Received: by mail-pg1-x544.google.com with SMTP id w22so1921338pgi.6 for ; Thu, 09 May 2019 15:26:41 -0700 (PDT) Received: from localhost.localdomain (97-113-13-231.tukw.qwest.net. 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X-Received-From: 2607:f8b0:4864:20::544 Subject: [Qemu-devel] [PATCH v3 05/27] target/hppa: Convert to CPUClass::tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 8 ++++---- target/hppa/cpu.c | 5 ++--- target/hppa/mem_helper.c | 22 +++++++++++++++++----- 3 files changed, 23 insertions(+), 12 deletions(-) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 923346adb6..c1e0215e66 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -360,10 +360,10 @@ int hppa_cpu_gdb_write_register(CPUState *cpu, uint8_= t *buf, int reg); void hppa_cpu_do_interrupt(CPUState *cpu); bool hppa_cpu_exec_interrupt(CPUState *cpu, int int_req); void hppa_cpu_dump_state(CPUState *cs, FILE *f, int); -#ifdef CONFIG_USER_ONLY -int hppa_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, - int rw, int midx); -#else +bool hppa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); +#ifndef CONFIG_USER_ONLY int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, int type, hwaddr *pphys, int *pprot); extern const MemoryRegionOps hppa_io_eir_ops; diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index e64f48581e..9717ea1798 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -163,9 +163,8 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *= data) cc->synchronize_from_tb =3D hppa_cpu_synchronize_from_tb; cc->gdb_read_register =3D hppa_cpu_gdb_read_register; cc->gdb_write_register =3D hppa_cpu_gdb_write_register; -#ifdef CONFIG_USER_ONLY - cc->handle_mmu_fault =3D hppa_cpu_handle_mmu_fault; -#else + cc->tlb_fill =3D hppa_cpu_tlb_fill; +#ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D hppa_cpu_get_phys_page_debug; dc->vmsd =3D &vmstate_hppa_cpu; #endif diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index 77fb544838..5cee0c19b1 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -25,8 +25,9 @@ #include "trace.h" =20 #ifdef CONFIG_USER_ONLY -int hppa_cpu_handle_mmu_fault(CPUState *cs, vaddr address, - int size, int rw, int mmu_idx) +bool hppa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) { HPPACPU *cpu =3D HPPA_CPU(cs); =20 @@ -34,7 +35,7 @@ int hppa_cpu_handle_mmu_fault(CPUState *cs, vaddr address, which would affect si_code. */ cs->exception_index =3D EXCP_DMP; cpu->env.cr[CR_IOR] =3D address; - return 1; + cpu_loop_exit_restore(cs, retaddr); } #else static hppa_tlb_entry *hppa_find_tlb(CPUHPPAState *env, vaddr addr) @@ -213,8 +214,9 @@ hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr= addr) return excp =3D=3D EXCP_DTLB_MISS ? -1 : phys; } =20 -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType type, int mmu_idx, uintptr_t retaddr) +bool hppa_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, + MMUAccessType type, int mmu_idx, + bool probe, uintptr_t retaddr) { HPPACPU *cpu =3D HPPA_CPU(cs); CPUHPPAState *env =3D &cpu->env; @@ -236,6 +238,9 @@ void tlb_fill(CPUState *cs, target_ulong addr, int size, excp =3D hppa_get_physical_address(env, addr, mmu_idx, a_prot, &phys, &prot); if (unlikely(excp >=3D 0)) { + if (probe) { + return false; + } trace_hppa_tlb_fill_excp(env, addr, size, type, mmu_idx); /* Failure. Raise the indicated exception. */ cs->exception_index =3D excp; @@ -252,6 +257,13 @@ void tlb_fill(CPUState *cs, target_ulong addr, int siz= e, /* Success! Store the translation into the QEMU TLB. */ tlb_set_page(cs, addr & TARGET_PAGE_MASK, phys & TARGET_PAGE_MASK, prot, mmu_idx, TARGET_PAGE_SIZE); + return true; +} + +void tlb_fill(CPUState *cs, target_ulong addr, int size, + MMUAccessType type, int mmu_idx, uintptr_t retaddr) +{ + hppa_cpu_tlb_fill(cs, addr, size, type, mmu_idx, false, retaddr); } =20 /* Insert (Insn/Data) TLB Address. Note this is PA 1.1 only. */ --=20 2.17.1 From nobody Mon May 6 12:42:50 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1557441315; cv=none; d=zoho.com; s=zohoarc; b=R7Ik2JpuKTrb7FPzj0rXR0PvzEx0W4Cw1yLyaDuKr8ahKVQb3aufYJeWFfBfk4WzfCz2EDSLCWXQgPX67xQUM8ZLaLM9xrdLEarHLE04VBOTiSGSw0GteB12Li79ypqI7MIJI8hCfolS4Rb1RXCr8gdk/ZFiiN/ZHLdKNXJFCTI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1557441315; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=s87CuOmfhyfGLXIPM91Iv48ElcI94bqoXpVc6e0DK1o=; b=h1lfXzyeYShS/j3+CrDO2Du5bfSKGlSAOMgjsLIdur2JJQPTi4hNbOAFiwIzJd/urtSMCEfHTKtjMSfOSKrt6sVUcdpND6NN9pvC5aXvfesN8s/RxTD36dJzyHper4WAuvMtIYhE+yaEVEuD4I3ZPjFjL0lJB+oRyyZqbAaNlt0= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1557441314985290.6578597661014; Thu, 9 May 2019 15:35:14 -0700 (PDT) Received: from localhost ([127.0.0.1]:33531 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hOrd9-0006Ry-U9 for importer@patchew.org; Thu, 09 May 2019 18:35:11 -0400 Received: from eggs.gnu.org ([209.51.188.92]:32897) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hOrUy-0007au-82 for qemu-devel@nongnu.org; Thu, 09 May 2019 18:26:45 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hOrUx-0005RV-23 for qemu-devel@nongnu.org; Thu, 09 May 2019 18:26:44 -0400 Received: from mail-pg1-x541.google.com ([2607:f8b0:4864:20::541]:35650) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hOrUw-0005RE-SO for qemu-devel@nongnu.org; Thu, 09 May 2019 18:26:43 -0400 Received: by mail-pg1-x541.google.com with SMTP id h1so1930148pgs.2 for ; Thu, 09 May 2019 15:26:42 -0700 (PDT) Received: from localhost.localdomain (97-113-13-231.tukw.qwest.net. [97.113.13.231]) by smtp.gmail.com with ESMTPSA id m2sm4490521pfi.24.2019.05.09.15.26.40 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 09 May 2019 15:26:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=s87CuOmfhyfGLXIPM91Iv48ElcI94bqoXpVc6e0DK1o=; b=x8hk+beMmINKTHxQ4tsNFIFj0lQ4X/EJFQqBKEmcCxzdW49rBv9MAIxkrrTs7q4mXB aURbhMbuu447VXWEZob1gdI2gjUAGpkqY3gRNrjjF7LoSEYQMYbDl+zyEeF9fgfg4dPe h60UnvNYYeNb1diwfd7hsGkDVBnZpSq1XrkhxHE2i/OVXiCgBuO22dLf2u+O2E/t0Tby F9JPiRfq6SNymTRsUXVSlFGrKZsO9W3obEAJUvQSrfMSBgF/2LZjIKeMUQkM/R7lNxdX Eld/ZfYUDb8gi96dZwY4TvJBq7a3TTeYa9BlnpJqMn6Jbl36FrptkXQlly0LGIEYkih2 lDPQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=s87CuOmfhyfGLXIPM91Iv48ElcI94bqoXpVc6e0DK1o=; b=M15alLF4UJWEkhoP0ZdWF3oAs8X0SExtA5aJb4GbHV5cBMbVqwlkXrBGljvQM9eoWp Xpy4d7tL+1d+vLJSDN6UDe59V9f19vaot18TJC+fT4cEO0TCphVvP7soi9bDXx2Z3kIT n4I6v/0nijX1Abxi3TlTpd73/junc0AZbYxuJQT7EOdwtjr8Br6/RG/UPZTHXgTxtQ3N EPOPF0hbjWh7ddJYy8+WtMPhzQ8uVRnByQOcDfs15kCcWcQnBi4MoBvhVTal57tFFrFQ zvqfrXyzuAOpT8ww71bTUblwCq9sog888ff3Jonl+l2bvdlfLfxIyojG2R1uJTz7HfqA KyiQ== X-Gm-Message-State: APjAAAV/hBIgwY9PrVe5YBpo1hdEE37oY/Ifbc7bWzSfrzQ4fhJhNaNj wNuEfrPWsOIQ4zLp1Rj+1h4Edyi6eQs= X-Google-Smtp-Source: APXvYqx3RfPTTnHIUGzRcxrRgeRtXtBi6C3wv/wT/BSf9+hJ5BWRci/Bd0wGF1glpkfXMDk1GJoTbg== X-Received: by 2002:a62:d286:: with SMTP id c128mr9060320pfg.159.1557440801627; Thu, 09 May 2019 15:26:41 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 9 May 2019 15:26:10 -0700 Message-Id: <20190509222631.14271-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190509222631.14271-1-richard.henderson@linaro.org> References: <20190509222631.14271-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH v3 06/27] target/i386: Convert to CPUClass::tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Eduardo Habkost Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We do not support probing, but we do not need it yet either. Cc: Paolo Bonzini Cc: Eduardo Habkost Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/i386/cpu.h | 5 ++-- target/i386/cpu.c | 5 ++-- target/i386/excp_helper.c | 61 +++++++++++++++++++++++++-------------- target/i386/mem_helper.c | 21 -------------- 4 files changed, 44 insertions(+), 48 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 0128910661..fce6660bac 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1656,8 +1656,9 @@ void host_cpuid(uint32_t function, uint32_t count, void host_vendor_fms(char *vendor, int *family, int *model, int *stepping); =20 /* helper.c */ -int x86_cpu_handle_mmu_fault(CPUState *cpu, vaddr addr, int size, - int is_write, int mmu_idx); +bool x86_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); void x86_cpu_set_a20(X86CPU *cpu, int a20_state); =20 #ifndef CONFIG_USER_ONLY diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 722c5514d4..3c98869577 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -5915,9 +5915,8 @@ static void x86_cpu_common_class_init(ObjectClass *oc= , void *data) cc->gdb_write_register =3D x86_cpu_gdb_write_register; cc->get_arch_id =3D x86_cpu_get_arch_id; cc->get_paging_enabled =3D x86_cpu_get_paging_enabled; -#ifdef CONFIG_USER_ONLY - cc->handle_mmu_fault =3D x86_cpu_handle_mmu_fault; -#else + cc->tlb_fill =3D x86_cpu_tlb_fill; +#ifndef CONFIG_USER_ONLY cc->asidx_from_attrs =3D x86_asidx_from_attrs; cc->get_memory_mapping =3D x86_cpu_get_memory_mapping; cc->get_phys_page_debug =3D x86_cpu_get_phys_page_debug; diff --git a/target/i386/excp_helper.c b/target/i386/excp_helper.c index 49231f6b69..68bf8e3f7c 100644 --- a/target/i386/excp_helper.c +++ b/target/i386/excp_helper.c @@ -137,26 +137,7 @@ void raise_exception_ra(CPUX86State *env, int exceptio= n_index, uintptr_t retaddr raise_interrupt2(env, exception_index, 0, 0, 0, retaddr); } =20 -#if defined(CONFIG_USER_ONLY) -int x86_cpu_handle_mmu_fault(CPUState *cs, vaddr addr, int size, - int is_write, int mmu_idx) -{ - X86CPU *cpu =3D X86_CPU(cs); - CPUX86State *env =3D &cpu->env; - - /* user mode only emulation */ - is_write &=3D 1; - env->cr[2] =3D addr; - env->error_code =3D (is_write << PG_ERROR_W_BIT); - env->error_code |=3D PG_ERROR_U_MASK; - cs->exception_index =3D EXCP0E_PAGE; - env->exception_is_int =3D 0; - env->exception_next_eip =3D -1; - return 1; -} - -#else - +#if !defined(CONFIG_USER_ONLY) static hwaddr get_hphys(CPUState *cs, hwaddr gphys, MMUAccessType access_t= ype, int *prot) { @@ -365,8 +346,8 @@ static hwaddr get_hphys(CPUState *cs, hwaddr gphys, MMU= AccessType access_type, * 0 =3D nothing more to do * 1 =3D generate PF fault */ -int x86_cpu_handle_mmu_fault(CPUState *cs, vaddr addr, int size, - int is_write1, int mmu_idx) +static int handle_mmu_fault(CPUState *cs, vaddr addr, int size, + int is_write1, int mmu_idx) { X86CPU *cpu =3D X86_CPU(cs); CPUX86State *env =3D &cpu->env; @@ -691,3 +672,39 @@ do_check_protect_pse36: return 1; } #endif + +bool x86_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) +{ + X86CPU *cpu =3D X86_CPU(cs); + CPUX86State *env =3D &cpu->env; + +#ifdef CONFIG_USER_ONLY + /* user mode only emulation */ + env->cr[2] =3D addr; + env->error_code =3D (access_type =3D=3D MMU_DATA_STORE) << PG_ERROR_W_= BIT; + env->error_code |=3D PG_ERROR_U_MASK; + cs->exception_index =3D EXCP0E_PAGE; + env->exception_is_int =3D 0; + env->exception_next_eip =3D -1; + cpu_loop_exit_restore(cs, retaddr); +#else + env->retaddr =3D retaddr; + if (handle_mmu_fault(cs, addr, size, access_type, mmu_idx)) { + /* FIXME: On error in get_hphys we have already jumped out. */ + g_assert(!probe); + raise_exception_err_ra(env, cs->exception_index, + env->error_code, retaddr); + } + return true; +#endif +} + +#if !defined(CONFIG_USER_ONLY) +void tlb_fill(CPUState *cs, target_ulong addr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) +{ + x86_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); +} +#endif diff --git a/target/i386/mem_helper.c b/target/i386/mem_helper.c index 6cc53bcb40..1885df29d2 100644 --- a/target/i386/mem_helper.c +++ b/target/i386/mem_helper.c @@ -191,24 +191,3 @@ void helper_boundl(CPUX86State *env, target_ulong a0, = int v) raise_exception_ra(env, EXCP05_BOUND, GETPC()); } } - -#if !defined(CONFIG_USER_ONLY) -/* try to fill the TLB and return an exception if error. If retaddr is - * NULL, it means that the function was called in C code (i.e. not - * from generated code or from helper.c) - */ -/* XXX: fix it to restore all registers */ -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - X86CPU *cpu =3D X86_CPU(cs); - CPUX86State *env =3D &cpu->env; - int ret; - - env->retaddr =3D retaddr; - ret =3D x86_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu_idx); - if (ret) { - raise_exception_err_ra(env, cs->exception_index, env->error_code, = retaddr); - } -} -#endif --=20 2.17.1 From nobody Mon May 6 12:42:50 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1557441664; cv=none; d=zoho.com; s=zohoarc; b=SUaNOLed8aDXnO3sqpNKFzm2DVAAR5W33JOLwa5iBW4kUNDzC99Da/loqz90jYTen5gBW2Y7dUW40/IutZUzYZDlV4lQV2iqWhV8r7rmt13sf31RJ+KEo5lB6BUbEZ4GW57RG2RxdqcBI65HCXXHdRAb/c0Lm407if2Ep38Pphg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1557441664; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=KDWMmeXDxeYaDrbtpgauY6pAF7pSEhxca7JLZhrlUgE=; b=Pu4YX2Mgw+jRzFlrN4u7hXgVn+tQLayilPhrvnWc7IzkZUk+vGZZqv/LEQsss/IYRfgpAVa2ZVcsOby2my3E+6MSg/9d/Z0y2ri6UcA6WWnubFHgidEflPo61pQCIGLjmv2u67ERnZaRVSIW6/0tlRga8z0NHO07XCuDRFND270= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1557441664581237.78429183067135; Thu, 9 May 2019 15:41:04 -0700 (PDT) Received: from localhost ([127.0.0.1]:33632 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hOrin-00038g-Jc for importer@patchew.org; Thu, 09 May 2019 18:41:01 -0400 Received: from eggs.gnu.org ([209.51.188.92]:32916) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hOrUz-0007cd-Vg for qemu-devel@nongnu.org; Thu, 09 May 2019 18:26:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hOrUy-0005SA-GK for qemu-devel@nongnu.org; Thu, 09 May 2019 18:26:45 -0400 Received: from mail-pf1-x444.google.com ([2607:f8b0:4864:20::444]:36271) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hOrUy-0005Ro-9n for qemu-devel@nongnu.org; Thu, 09 May 2019 18:26:44 -0400 Received: by mail-pf1-x444.google.com with SMTP id v80so2055163pfa.3 for ; Thu, 09 May 2019 15:26:44 -0700 (PDT) Received: from localhost.localdomain (97-113-13-231.tukw.qwest.net. [97.113.13.231]) by smtp.gmail.com with ESMTPSA id m2sm4490521pfi.24.2019.05.09.15.26.41 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 09 May 2019 15:26:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=KDWMmeXDxeYaDrbtpgauY6pAF7pSEhxca7JLZhrlUgE=; b=pVvhq8gtYlH2Wv/Df8oLL8kq7eodBSG86Aac7wLoyErexaTYcTyTLbYwZ/W7flcOqR eHxAdjAPekx0o6kQBBIC0+JcQEz8QSBbu3CXjROCgGb5Bz0uGMedRcjqjzNzegBiaIWq GmbmiK5FS8EqIL//FceR8NVD5QCEWKXRssxFZV944Dxf9P836J66tveeSCqV+RTiJAO9 w2qEqEohAhpTINe3+g/BpDCE1Z3p8rFFXaDfYMhLYJ7WaS5qvJDFzCaJSNZ8dH83mBRk vvpZKXeBqXdUatUkjwXLA4P/fOanzqXPh0YzJgwBrSx8xvK66R8CuenOIGokNFgJwIFq hA0Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=KDWMmeXDxeYaDrbtpgauY6pAF7pSEhxca7JLZhrlUgE=; b=SjtbUNiw3P6yykbYj3Z+4NV2KsyVjFynNa4rIMXdQIgZbY61h296gMUxoLC+FaV4t3 LunAKWP+9Nkv9TOTLN7ZgYAY5T7qUWE3oIX1R3TgdxV+AD5hNhdfbX/ied2uK1/3fllE 9p1ARbuf7pGrhIX+sIgtVms5BpjgOp2+uN5OmlBHZ5EwCjo3748IglbeKqSkLaqPNdUa 1JHIFUCEwE0HxsX1Sg63ffiE8JVHCRTS/ef6jbG9mQGCg8gztRbra2E/PDeqNNaTmj61 7eCQB+JjLu1WhtabHHRAaEX+SmjVmhYp1cCVdCvBZadlrqc+vU3tyHm0I62IOVtbrm+j mudw== X-Gm-Message-State: APjAAAXaZazZryWcDss6/vzAh80InOAz84yxFCO4n7RP//d4/Ky6gWHm WiuXLG3HujW9tD5hHbjco/MjKsnwwLY= X-Google-Smtp-Source: APXvYqxOvsJ5gQilxZbiRK/OZyQ6VuUTbB1yh+wpoie409yqq6QEm5AKMufbt+DlirUPAWGHirgwPQ== X-Received: by 2002:a62:570a:: with SMTP id l10mr8799792pfb.151.1557440802922; Thu, 09 May 2019 15:26:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 9 May 2019 15:26:11 -0700 Message-Id: <20190509222631.14271-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190509222631.14271-1-richard.henderson@linaro.org> References: <20190509222631.14271-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH v3 07/27] target/lm32: Convert to CPUClass::tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Walle Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Cc: Michael Walle Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/lm32/cpu.h | 5 +++-- target/lm32/cpu.c | 5 ++--- target/lm32/helper.c | 12 +++++++++--- target/lm32/op_helper.c | 16 ---------------- 4 files changed, 14 insertions(+), 24 deletions(-) diff --git a/target/lm32/cpu.h b/target/lm32/cpu.h index 9b1e6c2d58..d224d4426e 100644 --- a/target/lm32/cpu.h +++ b/target/lm32/cpu.h @@ -261,8 +261,9 @@ bool lm32_cpu_do_semihosting(CPUState *cs); #define cpu_list lm32_cpu_list #define cpu_signal_handler cpu_lm32_signal_handler =20 -int lm32_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int = rw, - int mmu_idx); +bool lm32_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); =20 #include "exec/cpu-all.h" =20 diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c index 282da19994..57c50c1578 100644 --- a/target/lm32/cpu.c +++ b/target/lm32/cpu.c @@ -231,9 +231,8 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *= data) cc->set_pc =3D lm32_cpu_set_pc; cc->gdb_read_register =3D lm32_cpu_gdb_read_register; cc->gdb_write_register =3D lm32_cpu_gdb_write_register; -#ifdef CONFIG_USER_ONLY - cc->handle_mmu_fault =3D lm32_cpu_handle_mmu_fault; -#else + cc->tlb_fill =3D lm32_cpu_tlb_fill; +#ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D lm32_cpu_get_phys_page_debug; cc->vmsd =3D &vmstate_lm32_cpu; #endif diff --git a/target/lm32/helper.c b/target/lm32/helper.c index a039a993ff..1db9a5562e 100644 --- a/target/lm32/helper.c +++ b/target/lm32/helper.c @@ -25,8 +25,9 @@ #include "exec/semihost.h" #include "exec/log.h" =20 -int lm32_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int r= w, - int mmu_idx) +bool lm32_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) { LM32CPU *cpu =3D LM32_CPU(cs); CPULM32State *env =3D &cpu->env; @@ -40,8 +41,13 @@ int lm32_cpu_handle_mmu_fault(CPUState *cs, vaddr addres= s, int size, int rw, } else { tlb_set_page(cs, address, address, prot, mmu_idx, TARGET_PAGE_SIZE= ); } + return true; +} =20 - return 0; +void tlb_fill(CPUState *cs, target_ulong addr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) +{ + lm32_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr= ); } =20 hwaddr lm32_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) diff --git a/target/lm32/op_helper.c b/target/lm32/op_helper.c index 234d55e056..be12b11b02 100644 --- a/target/lm32/op_helper.c +++ b/target/lm32/op_helper.c @@ -143,21 +143,5 @@ uint32_t HELPER(rcsr_jrx)(CPULM32State *env) { return lm32_juart_get_jrx(env->juart_state); } - -/* Try to fill the TLB and return an exception if error. If retaddr is - * NULL, it means that the function was called in C code (i.e. not - * from generated code or from helper.c) - */ -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - int ret; - - ret =3D lm32_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu_idx= ); - if (unlikely(ret)) { - /* now we have a real cpu fault */ - cpu_loop_exit_restore(cs, retaddr); - } -} #endif =20 --=20 2.17.1 From nobody Mon May 6 12:42:50 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1557441841; cv=none; d=zoho.com; s=zohoarc; b=agj4ThipAVRY3VLHn55DU+qhaGB4EWfocl6pwkpOv1ShWN311ICG4NZaHJ/mAWj6HJM6ec27zfS95eSK23tQqHYIysMiRnW2XdNy1JBvcRBR6GpRMvVoUXkSdncd+SQSLi5p89mjedbP+X9FxHPd5lei5jRByrwwxSzInCxlscs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1557441841; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=epdYlBTiLaV9VQx6jCDpGmNhfjLLlYzffabxUVX4RgQ=; b=QISdZ9tKtVuCsmX/cZFARxLJg2mcCpZhUj+pwpTYwvtvxiSowXplefg01zSA4uXJuk0Km8cnVXSALMnQ0Ac4PagllLdYZAuLy7aQqK3r+ch88herOcyP2pJ1BiAnYuXTFExrf4jDT+FIeBnXrtIMmCWSBtItUCNPlimTMqExpLU= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 155744184193992.3311427546854; Thu, 9 May 2019 15:44:01 -0700 (PDT) Received: from localhost ([127.0.0.1]:33684 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hOrlY-0005ZP-Rc for importer@patchew.org; Thu, 09 May 2019 18:43:52 -0400 Received: from eggs.gnu.org ([209.51.188.92]:32928) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hOrV0-0007di-RT for qemu-devel@nongnu.org; Thu, 09 May 2019 18:26:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hOrUz-0005SX-IY for qemu-devel@nongnu.org; Thu, 09 May 2019 18:26:46 -0400 Received: from mail-pf1-x442.google.com ([2607:f8b0:4864:20::442]:41937) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hOrUz-0005SJ-BJ for qemu-devel@nongnu.org; Thu, 09 May 2019 18:26:45 -0400 Received: by mail-pf1-x442.google.com with SMTP id l132so2041176pfc.8 for ; Thu, 09 May 2019 15:26:45 -0700 (PDT) Received: from localhost.localdomain (97-113-13-231.tukw.qwest.net. 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X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH v3 08/27] target/m68k: Convert to CPUClass::tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Cc: Laurent Vivier Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/m68k/cpu.h | 5 ++- target/m68k/cpu.c | 2 +- target/m68k/helper.c | 87 ++++++++++++++++++++++------------------- target/m68k/op_helper.c | 15 ------- 4 files changed, 50 insertions(+), 59 deletions(-) diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index ad41608341..683d3e2f79 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -542,8 +542,9 @@ static inline int cpu_mmu_index (CPUM68KState *env, boo= l ifetch) return (env->sr & SR_S) =3D=3D 0 ? 1 : 0; } =20 -int m68k_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int = rw, - int mmu_idx); +bool m68k_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); void m68k_cpu_unassigned_access(CPUState *cs, hwaddr addr, bool is_write, bool is_exec, int is_asi, unsigned size); diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 582e3a73b3..6f441bc973 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -269,7 +269,7 @@ static void m68k_cpu_class_init(ObjectClass *c, void *d= ata) cc->set_pc =3D m68k_cpu_set_pc; cc->gdb_read_register =3D m68k_cpu_gdb_read_register; cc->gdb_write_register =3D m68k_cpu_gdb_write_register; - cc->handle_mmu_fault =3D m68k_cpu_handle_mmu_fault; + cc->tlb_fill =3D m68k_cpu_tlb_fill; #if defined(CONFIG_SOFTMMU) cc->do_unassigned_access =3D m68k_cpu_unassigned_access; cc->get_phys_page_debug =3D m68k_cpu_get_phys_page_debug; diff --git a/target/m68k/helper.c b/target/m68k/helper.c index d958a34959..862f955f7b 100644 --- a/target/m68k/helper.c +++ b/target/m68k/helper.c @@ -353,20 +353,7 @@ void m68k_switch_sp(CPUM68KState *env) env->current_sp =3D new_sp; } =20 -#if defined(CONFIG_USER_ONLY) - -int m68k_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int r= w, - int mmu_idx) -{ - M68kCPU *cpu =3D M68K_CPU(cs); - - cs->exception_index =3D EXCP_ACCESS; - cpu->env.mmu.ar =3D address; - return 1; -} - -#else - +#if !defined(CONFIG_USER_ONLY) /* MMU: 68040 only */ =20 static void print_address_zone(uint32_t logical, uint32_t physical, @@ -795,11 +782,36 @@ hwaddr m68k_cpu_get_phys_page_debug(CPUState *cs, vad= dr addr) return phys_addr; } =20 -int m68k_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int r= w, - int mmu_idx) +/* + * Notify CPU of a pending interrupt. Prioritization and vectoring should + * be handled by the interrupt controller. Real hardware only requests + * the vector when the interrupt is acknowledged by the CPU. For + * simplicity we calculate it when the interrupt is signalled. + */ +void m68k_set_irq_level(M68kCPU *cpu, int level, uint8_t vector) +{ + CPUState *cs =3D CPU(cpu); + CPUM68KState *env =3D &cpu->env; + + env->pending_level =3D level; + env->pending_vector =3D vector; + if (level) { + cpu_interrupt(cs, CPU_INTERRUPT_HARD); + } else { + cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); + } +} + +#endif + +bool m68k_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType qemu_access_type, int mmu_idx, + bool probe, uintptr_t retaddr) { M68kCPU *cpu =3D M68K_CPU(cs); CPUM68KState *env =3D &cpu->env; + +#ifndef CONFIG_USER_ONLY hwaddr physical; int prot; int access_type; @@ -812,32 +824,35 @@ int m68k_cpu_handle_mmu_fault(CPUState *cs, vaddr add= ress, int size, int rw, address & TARGET_PAGE_MASK, PAGE_READ | PAGE_WRITE | PAGE_EXEC, mmu_idx, TARGET_PAGE_SIZE); - return 0; + return true; } =20 - if (rw =3D=3D 2) { + if (qemu_access_type =3D=3D MMU_INST_FETCH) { access_type =3D ACCESS_CODE; - rw =3D 0; } else { access_type =3D ACCESS_DATA; - if (rw) { + if (qemu_access_type =3D=3D MMU_DATA_STORE) { access_type |=3D ACCESS_STORE; } } - if (mmu_idx !=3D MMU_USER_IDX) { access_type |=3D ACCESS_SUPER; } =20 ret =3D get_physical_address(&cpu->env, &physical, &prot, address, access_type, &page_size); - if (ret =3D=3D 0) { + if (likely(ret =3D=3D 0)) { address &=3D TARGET_PAGE_MASK; physical +=3D address & (page_size - 1); tlb_set_page(cs, address, physical, prot, mmu_idx, TARGET_PAGE_SIZE); - return 0; + return true; } + + if (probe) { + return false; + } + /* page fault */ env->mmu.ssw =3D M68K_ATC_040; switch (size) { @@ -862,29 +877,19 @@ int m68k_cpu_handle_mmu_fault(CPUState *cs, vaddr add= ress, int size, int rw, if (!(access_type & ACCESS_STORE)) { env->mmu.ssw |=3D M68K_RW_040; } - env->mmu.ar =3D address; +#endif + cs->exception_index =3D EXCP_ACCESS; - return 1; + env->mmu.ar =3D address; + cpu_loop_exit_restore(cs, retaddr); } =20 -/* Notify CPU of a pending interrupt. Prioritization and vectoring should - be handled by the interrupt controller. Real hardware only requests - the vector when the interrupt is acknowledged by the CPU. For - simplicitly we calculate it when the interrupt is signalled. */ -void m68k_set_irq_level(M68kCPU *cpu, int level, uint8_t vector) +#ifndef CONFIG_USER_ONLY +void tlb_fill(CPUState *cs, target_ulong addr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) { - CPUState *cs =3D CPU(cpu); - CPUM68KState *env =3D &cpu->env; - - env->pending_level =3D level; - env->pending_vector =3D vector; - if (level) { - cpu_interrupt(cs, CPU_INTERRUPT_HARD); - } else { - cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); - } + m68k_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr= ); } - #endif =20 uint32_t HELPER(bitrev)(uint32_t x) diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c index 76f439985a..d421614727 100644 --- a/target/m68k/op_helper.c +++ b/target/m68k/op_helper.c @@ -36,21 +36,6 @@ static inline void do_interrupt_m68k_hardirq(CPUM68KStat= e *env) =20 #else =20 -/* Try to fill the TLB and return an exception if error. If retaddr is - NULL, it means that the function was called in C code (i.e. not - from generated code or from helper.c) */ -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - int ret; - - ret =3D m68k_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu_idx= ); - if (unlikely(ret)) { - /* now we have a real cpu fault */ - cpu_loop_exit_restore(cs, retaddr); - } -} - static void cf_rte(CPUM68KState *env) { uint32_t sp; --=20 2.17.1 From nobody Mon May 6 12:42:50 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1557441966; cv=none; d=zoho.com; s=zohoarc; b=oDZ+5/qugA8kxRhCvqSMY0vDaJt0YPrCQtieVZiYgRFGmH0JR55cXhmAJpSkjDZ2bqzKaUP9s9zbGSJroGpYR8XGGuj3VwOrpJTftuFbFg/MJlZTFeAPiDrQAA4D89shG6ukq3z1krh3XJhBfBqqDSEqvalKfAuBS2pg/WfnerY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1557441966; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=omewBU1W56CpN9jkgUsDwQLimncwo01SMHqSrNfd+ko=; b=DD3QKspQ0Pg5xt8L990MY2rbD1okt6hWgDi4yYdXPYsr747jA7MDxt9PRFsFgMjJCJ0GxrQFyQuXkzpMqs+lIgb4WPTyprD4m0qd9ZhG4oAdp20KWDUhIIvXNxhLeHIK7hJo/ZHGuQqCragXrazsMDdY9h/7m092+eQ4eJ8g6OY= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1557441966290248.54071338234007; Thu, 9 May 2019 15:46:06 -0700 (PDT) Received: from localhost ([127.0.0.1]:33743 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hOrnd-0007On-Ah for importer@patchew.org; Thu, 09 May 2019 18:46:01 -0400 Received: from eggs.gnu.org ([209.51.188.92]:32941) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hOrV2-0007ew-24 for qemu-devel@nongnu.org; Thu, 09 May 2019 18:26:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hOrV0-0005Sz-Ns for qemu-devel@nongnu.org; Thu, 09 May 2019 18:26:48 -0400 Received: from mail-pg1-x541.google.com ([2607:f8b0:4864:20::541]:40373) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hOrV0-0005Sm-Fv for qemu-devel@nongnu.org; Thu, 09 May 2019 18:26:46 -0400 Received: by mail-pg1-x541.google.com with SMTP id d31so1922864pgl.7 for ; Thu, 09 May 2019 15:26:46 -0700 (PDT) Received: from localhost.localdomain (97-113-13-231.tukw.qwest.net. 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X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH v3 09/27] target/microblaze: Convert to CPUClass::tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Cc: Edgar E. Iglesias Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v2: Keep user-only and system tlb_fill separate. --- target/microblaze/cpu.h | 5 +- target/microblaze/cpu.c | 5 +- target/microblaze/helper.c | 107 ++++++++++++++++++---------------- target/microblaze/op_helper.c | 19 ------ 4 files changed, 62 insertions(+), 74 deletions(-) diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index f20e796865..7a9fb8f4aa 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -374,8 +374,9 @@ static inline int cpu_mmu_index (CPUMBState *env, bool = ifetch) return MMU_KERNEL_IDX; } =20 -int mb_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int rw, - int mmu_idx); +bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); =20 #include "exec/cpu-all.h" =20 diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 5596cd5485..0ea549910b 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -304,9 +304,8 @@ static void mb_cpu_class_init(ObjectClass *oc, void *da= ta) cc->set_pc =3D mb_cpu_set_pc; cc->gdb_read_register =3D mb_cpu_gdb_read_register; cc->gdb_write_register =3D mb_cpu_gdb_write_register; -#ifdef CONFIG_USER_ONLY - cc->handle_mmu_fault =3D mb_cpu_handle_mmu_fault; -#else + cc->tlb_fill =3D mb_cpu_tlb_fill; +#ifndef CONFIG_USER_ONLY cc->do_transaction_failed =3D mb_cpu_transaction_failed; cc->get_phys_page_debug =3D mb_cpu_get_phys_page_debug; #endif diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index 9848e31d7f..a523c77959 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -38,73 +38,80 @@ void mb_cpu_do_interrupt(CPUState *cs) env->regs[14] =3D env->sregs[SR_PC]; } =20 -int mb_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw, - int mmu_idx) +bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) { cs->exception_index =3D 0xaa; - cpu_dump_state(cs, stderr, 0); - return 1; + cpu_loop_exit_restore(cs, retaddr); } =20 #else /* !CONFIG_USER_ONLY */ =20 -int mb_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw, - int mmu_idx) +bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) { MicroBlazeCPU *cpu =3D MICROBLAZE_CPU(cs); CPUMBState *env =3D &cpu->env; + struct microblaze_mmu_lookup lu; unsigned int hit; - int r =3D 1; int prot; =20 - /* Translate if the MMU is available and enabled. */ - if (mmu_idx !=3D MMU_NOMMU_IDX) { - uint32_t vaddr, paddr; - struct microblaze_mmu_lookup lu; - - hit =3D mmu_translate(&env->mmu, &lu, address, rw, mmu_idx); - if (hit) { - vaddr =3D address & TARGET_PAGE_MASK; - paddr =3D lu.paddr + vaddr - lu.vaddr; - - qemu_log_mask(CPU_LOG_MMU, "MMU map mmu=3D%d v=3D%x p=3D%x pro= t=3D%x\n", - mmu_idx, vaddr, paddr, lu.prot); - tlb_set_page(cs, vaddr, paddr, lu.prot, mmu_idx, TARGET_PAGE_S= IZE); - r =3D 0; - } else { - env->sregs[SR_EAR] =3D address; - qemu_log_mask(CPU_LOG_MMU, "mmu=3D%d miss v=3D%" VADDR_PRIx "\= n", - mmu_idx, address); - - switch (lu.err) { - case ERR_PROT: - env->sregs[SR_ESR] =3D rw =3D=3D 2 ? 17 : 16; - env->sregs[SR_ESR] |=3D (rw =3D=3D 1) << 10; - break; - case ERR_MISS: - env->sregs[SR_ESR] =3D rw =3D=3D 2 ? 19 : 18; - env->sregs[SR_ESR] |=3D (rw =3D=3D 1) << 10; - break; - default: - abort(); - break; - } - - if (cs->exception_index =3D=3D EXCP_MMU) { - cpu_abort(cs, "recursive faults\n"); - } - - /* TLB miss. */ - cs->exception_index =3D EXCP_MMU; - } - } else { + if (mmu_idx =3D=3D MMU_NOMMU_IDX) { /* MMU disabled or not available. */ address &=3D TARGET_PAGE_MASK; prot =3D PAGE_BITS; tlb_set_page(cs, address, address, prot, mmu_idx, TARGET_PAGE_SIZE= ); - r =3D 0; + return true; } - return r; + + hit =3D mmu_translate(&env->mmu, &lu, address, access_type, mmu_idx); + if (likely(hit)) { + uint32_t vaddr =3D address & TARGET_PAGE_MASK; + uint32_t paddr =3D lu.paddr + vaddr - lu.vaddr; + + qemu_log_mask(CPU_LOG_MMU, "MMU map mmu=3D%d v=3D%x p=3D%x prot=3D= %x\n", + mmu_idx, vaddr, paddr, lu.prot); + tlb_set_page(cs, vaddr, paddr, lu.prot, mmu_idx, TARGET_PAGE_SIZE); + return true; + } + + /* TLB miss. */ + if (probe) { + return false; + } + + qemu_log_mask(CPU_LOG_MMU, "mmu=3D%d miss v=3D%" VADDR_PRIx "\n", + mmu_idx, address); + + env->sregs[SR_EAR] =3D address; + switch (lu.err) { + case ERR_PROT: + env->sregs[SR_ESR] =3D access_type =3D=3D MMU_INST_FETCH ? 17 : 16; + env->sregs[SR_ESR] |=3D (access_type =3D=3D MMU_DATA_STORE) << 10; + break; + case ERR_MISS: + env->sregs[SR_ESR] =3D access_type =3D=3D MMU_INST_FETCH ? 19 : 18; + env->sregs[SR_ESR] |=3D (access_type =3D=3D MMU_DATA_STORE) << 10; + break; + default: + abort(); + } + + if (cs->exception_index =3D=3D EXCP_MMU) { + cpu_abort(cs, "recursive faults\n"); + } + + /* TLB miss. */ + cs->exception_index =3D EXCP_MMU; + cpu_loop_exit_restore(cs, retaddr); +} + +void tlb_fill(CPUState *cs, target_ulong addr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) +{ + mb_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); } =20 void mb_cpu_do_interrupt(CPUState *cs) diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index e23dcfdc20..b5dbb90d05 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -28,25 +28,6 @@ =20 #define D(x) =20 -#if !defined(CONFIG_USER_ONLY) - -/* Try to fill the TLB and return an exception if error. If retaddr is - * NULL, it means that the function was called in C code (i.e. not - * from generated code or from helper.c) - */ -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - int ret; - - ret =3D mb_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu_idx); - if (unlikely(ret)) { - /* now we have a real cpu fault */ - cpu_loop_exit_restore(cs, retaddr); - } -} -#endif - void helper_put(uint32_t id, uint32_t ctrl, uint32_t data) { int test =3D ctrl & STREAM_TEST; --=20 2.17.1 From nobody Mon May 6 12:42:50 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1557440985; cv=none; d=zoho.com; s=zohoarc; b=b5FblNUxRgpAeCW9VxmkARGbYQnqdQyaGasqV8xXCwC+e+WwSGGY9Tcr7eCYDnOtUZKLjDIuzCKO07bbUtA4W/rOvLjDZdLN3xi5VOLQaZs/S6OGEDhQY4PxiLgL1lU0mroO5xZcqkskLwkRKGo2+9146CqV79OJ2EG3ybWov54= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1557440985; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=9CI4oI1nkvf0QxqoUGGat3a67tCPvWsOkb0Ljyg5Gsk=; b=cX3HJp0IZD0ZZyMOuZbu2kqSXIe8SzRZao9EcgLb4u8x8nwcgYYu1Xj9B6BoWMXfmeN50yr91H7yNMy7tJQw/4X9LSOB/wefZ9npBqwD1f0l0wR/gaKEV3vJ5BRrARsEWVwWT2ga25pSYAv2ILMeSkySpwvBkV3WQi2PlApN4xY= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1557440985222845.1283065631155; Thu, 9 May 2019 15:29:45 -0700 (PDT) Received: from localhost ([127.0.0.1]:33450 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hOrXp-0001C4-5s for importer@patchew.org; Thu, 09 May 2019 18:29:41 -0400 Received: from eggs.gnu.org ([209.51.188.92]:32950) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hOrV2-0007fq-Ro for qemu-devel@nongnu.org; Thu, 09 May 2019 18:26:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hOrV1-0005TL-UT for qemu-devel@nongnu.org; Thu, 09 May 2019 18:26:48 -0400 Received: from mail-pf1-x442.google.com ([2607:f8b0:4864:20::442]:42807) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hOrV1-0005TE-Oz for qemu-devel@nongnu.org; Thu, 09 May 2019 18:26:47 -0400 Received: by mail-pf1-x442.google.com with SMTP id 13so2041243pfw.9 for ; Thu, 09 May 2019 15:26:47 -0700 (PDT) Received: from localhost.localdomain (97-113-13-231.tukw.qwest.net. [97.113.13.231]) by smtp.gmail.com with ESMTPSA id m2sm4490521pfi.24.2019.05.09.15.26.45 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 09 May 2019 15:26:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=9CI4oI1nkvf0QxqoUGGat3a67tCPvWsOkb0Ljyg5Gsk=; b=UQy5424kPPPWI4jgBR28IqDLu+Zq0U/tL5t6vQZK6SVOOhY3TM26QzfmXbx3dCQLFE rQAOcVZg7pUcT7Wpp/Kot1n9cgLRw8j7Ymo0RbrIckZLL0WrSVkEC4I/E7iN5WDwV7eN fKPW2PbBq9N4Nq1SqRRs5O/0uNvChUQvXnJqht7ZZpOH7QTpBtTLuWfMn1xFR8PEYDiH YM5aUfveJYPfD3oSphBAmm2bMjGNp+VMw8cYBJu1s98bQdiG/Ohub/dnwLAyn5ZQ+8mK tWoqVwzUN9STQTpJn3TWPnGt1ummSKaxQAe1Vm/QeQCntwxnnv8/vL6q6Xgm0VkpEjk+ 8Otg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9CI4oI1nkvf0QxqoUGGat3a67tCPvWsOkb0Ljyg5Gsk=; b=A3hG9D+S4U+mGj8+Vub00pAPaHKmhjtGqaaoBWwB9p1ucRQB4t/TJuqzut8Rm+VlyQ 6hUTLwTVu8Wb5yUBBbj1NAdJ1ryzMz33JY86FWgOWGpF/QCltpDipCtzPbZc5AjkmeF3 PPdukm1+acDdYXvQjEyjE0QkUQthODxtdu+JW3pMMLZiJskeP/MdvRndNQBtO+PcbZ8V GgRri7LDX6MhK7Dytdxoc1KA7QhFRZlxiIC/HCpyzHDBxxFq6wIcLrFKwL6xsHEWYDsy cFDfS+Wcd4mzHKmIqVNgqZRFzZ//ldkeaE63/mV+xzj51PY4X3svRFblprje0jfaUAPi +HCA== X-Gm-Message-State: APjAAAUDLuo4A3Cr2Fj4bEZSQVEuOAWVDd5aYkvw5uqZqBDG+xhC4NuE lHgOV8JFRuhVYcJ3rCzQnIShHnhZ7jQ= X-Google-Smtp-Source: APXvYqwuumf6KWL0RblLIbXnA1Rg/i/WyCl5tgH2BkaLiHjV10xagSCLEMaHDsD1UaslDG18hgmYGw== X-Received: by 2002:a62:4558:: with SMTP id s85mr9130985pfa.171.1557440806561; Thu, 09 May 2019 15:26:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 9 May 2019 15:26:14 -0700 Message-Id: <20190509222631.14271-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190509222631.14271-1-richard.henderson@linaro.org> References: <20190509222631.14271-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH v3 10/27] target/mips: Pass a valid error to raise_mmu_exception for user-only X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) At present we give ret =3D 0, or TLBRET_MATCH. This gets matched by the default case, which falls through to TLBRET_BADADDR. However, it makes more sense to use a proper value. All of the tlb-related exceptions are handled identically in cpu_loop.c, so TLBRET_BADADDR is as good as any other. Retain it. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/mips/helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/mips/helper.c b/target/mips/helper.c index c44cdca3b5..cc7be7703a 100644 --- a/target/mips/helper.c +++ b/target/mips/helper.c @@ -884,7 +884,7 @@ int mips_cpu_handle_mmu_fault(CPUState *cs, vaddr addre= ss, int size, int rw, int prot; int access_type; #endif - int ret =3D 0; + int ret =3D TLBRET_BADADDR; =20 #if 0 log_cpu_state(cs, 0); --=20 2.17.1 From nobody Mon May 6 12:42:50 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1557441510; cv=none; d=zoho.com; s=zohoarc; b=dnxd7ergM62VpItmH6U5PdLOy4u1Xt5CjChWDykrcQvtCJmmqdSGAD/Wx/6LHtvoU3O8gFML3B0OqIDq6ZgOXVEm1wtFnMhYa46SG8mmgAI/yvDu5iLQH7wzsZ43EADEoqFz7BmLn4W4Sg6w73DdqGUY3GWUeYh9IVdG2Cm+PtA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1557441510; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=ZTH91pjxahUuQtOu1GsBhTY4d5CvJ+Jx8ktGJV35Xwc=; b=iZOd8ea4jWAyQ8WxEgCYhivUtK3UG85LCrskgCF/8jTpzNzSq7lC+JOljbqFe4F53qPDBfuoT4/KGe+LNtK0YlyBqvEDexwWo6scyg+JRBGIuTY5hVTbc7AEyf2XIOrcU0Q7c3kGXro3p0i8MRZB1d12yc2QZrW/1Ylw5Xgvj0E= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1557441510022961.762449466274; Thu, 9 May 2019 15:38:30 -0700 (PDT) Received: from localhost ([127.0.0.1]:33589 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hOrgB-00012m-5B for importer@patchew.org; Thu, 09 May 2019 18:38:19 -0400 Received: from eggs.gnu.org ([209.51.188.92]:32967) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hOrV4-0007gz-12 for qemu-devel@nongnu.org; Thu, 09 May 2019 18:26:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hOrV3-0005Tn-1W for qemu-devel@nongnu.org; Thu, 09 May 2019 18:26:50 -0400 Received: from mail-pg1-x542.google.com ([2607:f8b0:4864:20::542]:44541) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hOrV2-0005Tc-SF for qemu-devel@nongnu.org; Thu, 09 May 2019 18:26:48 -0400 Received: by mail-pg1-x542.google.com with SMTP id z16so1911988pgv.11 for ; Thu, 09 May 2019 15:26:48 -0700 (PDT) Received: from localhost.localdomain (97-113-13-231.tukw.qwest.net. [97.113.13.231]) by smtp.gmail.com with ESMTPSA id m2sm4490521pfi.24.2019.05.09.15.26.46 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 09 May 2019 15:26:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=ZTH91pjxahUuQtOu1GsBhTY4d5CvJ+Jx8ktGJV35Xwc=; b=jly0vXlbBuquNpT6dXPh+FN3uq0/7K1FJmQH0+R8quBHx1OTzckS1blXc4YX/vcxPF fF0TUDOiBZcNFZaG6LMQVAVDghzFMnUSv9nsiGm0JdOGuNp2llFzl3WkhST2DgEoohaF s8umaHYI0UPob0NwUkyKe+CM0cOwKGg82UZ/AA8zkNr2oJ+lCd0CdhN9ObN8FopS0oR8 SmRAVh1uXHGWEPD2PAL7k1t5PSJXJbml/SZFvBAYYIjUcEHWtNj8P6c+dcwaHxdJqORD 5WZ/t8BtrggpdSO00JlAr9ZKOk7EN/SpwoaiYV7HzWHK5UwuUvDbbp8a7l4fxlZ+q3UJ OkEA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZTH91pjxahUuQtOu1GsBhTY4d5CvJ+Jx8ktGJV35Xwc=; b=WHBvc6odtoPlRAIwa5nNzrT4/XI7yvNgG24Ip4DaiF40bK9Ji9ut5DDnCMkV3fjP/Z uQDPimKlJiTO+Z+ZgCSRFBs+Eni662pIwQfk9F0on9VKPgSuy2bM7HvwdX3XsTFchyo8 nD/Qj/q8fBlReqjzle5otLe3FmcVRMpEDeg10mQYVWvQu4CslQmZBm5opMfbdxpS8oFJ 8X3gN8ZMQpG6OXpZctGjvLMVF0UbUOELXff1J2V9ftCCa00miq6EPQQx5a7X68rDrEfK tw/mtGCFbf+DtrUICOkrKb2xRM6PMmx+P9q3OrRV3bgYnQkO5jiCPB+jKJIMl2YJM8ls ZoGw== X-Gm-Message-State: APjAAAVB7y/ippPwaUpqiXq4TWgBCh9Db4002fou9XYGOHBWVL+SF8LB j4IPP76jrZrFCFSTL/0IOQmMpRprkMw= X-Google-Smtp-Source: APXvYqz8Ke3Ojh1/ycgD+ObrBfDug46QZes2y0yiknL7pPUlmP//ENsH+qZbusfJ7h1vtqQDcfwNTg== X-Received: by 2002:a62:3381:: with SMTP id z123mr9242587pfz.42.1557440807632; Thu, 09 May 2019 15:26:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 9 May 2019 15:26:15 -0700 Message-Id: <20190509222631.14271-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190509222631.14271-1-richard.henderson@linaro.org> References: <20190509222631.14271-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::542 Subject: [Qemu-devel] [PATCH v3 11/27] target/mips: Tidy control flow in mips_cpu_handle_mmu_fault X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Since the only non-negative TLBRET_* value is TLBRET_MATCH, the subsequent test for ret < 0 is useless. Use early return to allow subsequent blocks to be unindented. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/mips/helper.c | 54 ++++++++++++++++++++------------------------ 1 file changed, 24 insertions(+), 30 deletions(-) diff --git a/target/mips/helper.c b/target/mips/helper.c index cc7be7703a..86e622efb8 100644 --- a/target/mips/helper.c +++ b/target/mips/helper.c @@ -915,41 +915,35 @@ int mips_cpu_handle_mmu_fault(CPUState *cs, vaddr add= ress, int size, int rw, tlb_set_page(cs, address & TARGET_PAGE_MASK, physical & TARGET_PAGE_MASK, prot | PAGE_EXEC, mmu_idx, TARGET_PAGE_SIZE); - ret =3D 0; - } else if (ret < 0) -#endif - { -#if !defined(CONFIG_USER_ONLY) + return 0; + } #if !defined(TARGET_MIPS64) - if ((ret =3D=3D TLBRET_NOMATCH) && (env->tlb->nb_tlb > 1)) { - /* - * Memory reads during hardware page table walking are perform= ed - * as if they were kernel-mode load instructions. - */ - int mode =3D (env->hflags & MIPS_HFLAG_KSU); - bool ret_walker; - env->hflags &=3D ~MIPS_HFLAG_KSU; - ret_walker =3D page_table_walk_refill(env, address, rw, mmu_id= x); - env->hflags |=3D mode; - if (ret_walker) { - ret =3D get_physical_address(env, &physical, &prot, - address, rw, access_type, mmu_i= dx); - if (ret =3D=3D TLBRET_MATCH) { - tlb_set_page(cs, address & TARGET_PAGE_MASK, - physical & TARGET_PAGE_MASK, prot | PAGE_EXEC, - mmu_idx, TARGET_PAGE_SIZE); - ret =3D 0; - return ret; - } + if ((ret =3D=3D TLBRET_NOMATCH) && (env->tlb->nb_tlb > 1)) { + /* + * Memory reads during hardware page table walking are performed + * as if they were kernel-mode load instructions. + */ + int mode =3D (env->hflags & MIPS_HFLAG_KSU); + bool ret_walker; + env->hflags &=3D ~MIPS_HFLAG_KSU; + ret_walker =3D page_table_walk_refill(env, address, rw, mmu_idx); + env->hflags |=3D mode; + if (ret_walker) { + ret =3D get_physical_address(env, &physical, &prot, + address, rw, access_type, mmu_idx); + if (ret =3D=3D TLBRET_MATCH) { + tlb_set_page(cs, address & TARGET_PAGE_MASK, + physical & TARGET_PAGE_MASK, prot | PAGE_EXEC, + mmu_idx, TARGET_PAGE_SIZE); + return 0; } } -#endif -#endif - raise_mmu_exception(env, address, rw, ret); - ret =3D 1; } +#endif +#endif =20 - return ret; + raise_mmu_exception(env, address, rw, ret); + return 1; } =20 #if !defined(CONFIG_USER_ONLY) --=20 2.17.1 From nobody Mon May 6 12:42:50 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1557441177; cv=none; d=zoho.com; s=zohoarc; b=QfCvIU3SvH4iz8uaFl2FfCcZ01f9Ij76T7C1ejCC4VlGP9mK4qKRr5kGpz8iE0s3rJZqvs+AowwYQT7Qoozo022ZF4n7uo+0knsIFfePN/uw8bnLZLUgJXQgs5SaIOGShiLbdA8koG86Kjs02UEqtuEPwtWkQOySD/iveDmHuvU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; 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[97.113.13.231]) by smtp.gmail.com with ESMTPSA id m2sm4490521pfi.24.2019.05.09.15.26.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 09 May 2019 15:26:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=t5VoKM+l3Lq9jc+URQ3PZSk53GmjO2/IoQkt1bRH1n8=; b=bQ0N9wvliHWfwB6xiRY3293N8XBBGA1FEXdS7WZPjZm3S40hJBRwPQVNbAAmi9FsFT gezc5dhZ0gNxxmkTpCCH8rvp/cpl5xMhud5Ai1BbyFa+QsDeQyuN3Ml0YOecE7d3O0HC saqrymv7VOizP7UhZoeb0Mn97esNq/b3E7Yv6x9rDQ+SasbHkHIjc/5N+haCbXrA3wVx qmaiUrlTvA08Y3NtCde0svxHFsBD0dJfp/VEvjhhZyfLicVVhFdSGdgnV4NlPXC1IMTk dZ7eSX4ZsxuIgcjNYpFPCyQKMKOn35msD261O5p6uiOs15Oh10VK3j9OlsJpAQwISyXZ 7Gpg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=t5VoKM+l3Lq9jc+URQ3PZSk53GmjO2/IoQkt1bRH1n8=; b=MvDbHwombVSDdki/Jb+8PU2RzuhzbCozL7yDH7Nv/OiWc0x4Y9HOGiQSUQ8oxUR5UF LwgNFAf71fRpKXWv2kHJaISpIuqsWTYpfnsUsqER8Z7LTIe1waciaHhA1J7/iNCDcoRN FdrfY0oY4XNgHG+W4C6JCphy5xEU4SVDDxrnojfdZYwzUVOnj8GZuev33DZJiasuvBOl +pvgjs0cO3kbCxEVLCcBnOhGRsXTyZhWT0zq538OASFI5YBZ8tUdqh4SomSl9i0KgBld oO5un2pbz8M98LGkQBx/JxIkupOMyx/IHVqgv+Y5emFKaouikBcxZUBqnpu7eJXtl1fJ 87Eg== X-Gm-Message-State: APjAAAUp33KkcKfiGURuID62Ax/YT6zlorMMbyA4vP3qGE9c6ugH1xtd umg2yWGaNx6P6LupQaVHegHdsCuZnJA= X-Google-Smtp-Source: APXvYqyWDIV4Owc7UJN9M+nKlXe0O+KvIJqPlFl9/EKy0LPgE5JcWyP7u0lT7IxnogbhwEqZhm3ygQ== X-Received: by 2002:a63:7d03:: with SMTP id y3mr8736562pgc.8.1557440808714; Thu, 09 May 2019 15:26:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 9 May 2019 15:26:16 -0700 Message-Id: <20190509222631.14271-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190509222631.14271-1-richard.henderson@linaro.org> References: <20190509222631.14271-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH v3 12/27] target/mips: Convert to CPUClass::tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Rikalo , Aleksandar Markovic Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Note that env->active_tc.PC is removed from the qemu_log as that value is garbage. The PC isn't recovered until cpu_restore_state, called from cpu_loop_exit_restore, called from do_raise_exception_err. Cc: Aleksandar Markovic Cc: Aleksandar Rikalo Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- v2: Split out other mips cleanups to simplify the diff --- target/mips/internal.h | 5 +++-- target/mips/cpu.c | 5 ++--- target/mips/helper.c | 45 ++++++++++++++++++++++------------------- target/mips/op_helper.c | 15 -------------- 4 files changed, 29 insertions(+), 41 deletions(-) diff --git a/target/mips/internal.h b/target/mips/internal.h index 286e3888ab..b2b41a51ab 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -202,8 +202,9 @@ void cpu_mips_start_count(CPUMIPSState *env); void cpu_mips_stop_count(CPUMIPSState *env); =20 /* helper.c */ -int mips_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int = rw, - int mmu_idx); +bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); =20 /* op_helper.c */ uint32_t float_class_s(uint32_t arg, float_status *fst); diff --git a/target/mips/cpu.c b/target/mips/cpu.c index e217fb3e36..ebdb834b97 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -197,9 +197,8 @@ static void mips_cpu_class_init(ObjectClass *c, void *d= ata) cc->synchronize_from_tb =3D mips_cpu_synchronize_from_tb; cc->gdb_read_register =3D mips_cpu_gdb_read_register; cc->gdb_write_register =3D mips_cpu_gdb_write_register; -#ifdef CONFIG_USER_ONLY - cc->handle_mmu_fault =3D mips_cpu_handle_mmu_fault; -#else + cc->tlb_fill =3D mips_cpu_tlb_fill; +#ifndef CONFIG_USER_ONLY cc->do_unassigned_access =3D mips_cpu_unassigned_access; cc->do_unaligned_access =3D mips_cpu_do_unaligned_access; cc->get_phys_page_debug =3D mips_cpu_get_phys_page_debug; diff --git a/target/mips/helper.c b/target/mips/helper.c index 86e622efb8..3a4917ce7b 100644 --- a/target/mips/helper.c +++ b/target/mips/helper.c @@ -874,31 +874,25 @@ refill: #endif #endif =20 -int mips_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int r= w, - int mmu_idx) +bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) { MIPSCPU *cpu =3D MIPS_CPU(cs); CPUMIPSState *env =3D &cpu->env; #if !defined(CONFIG_USER_ONLY) hwaddr physical; int prot; - int access_type; + int mips_access_type; #endif int ret =3D TLBRET_BADADDR; =20 -#if 0 - log_cpu_state(cs, 0); -#endif - qemu_log_mask(CPU_LOG_MMU, - "%s pc " TARGET_FMT_lx " ad %" VADDR_PRIx " rw %d mmu_idx %d= \n", - __func__, env->active_tc.PC, address, rw, mmu_idx); - /* data access */ #if !defined(CONFIG_USER_ONLY) /* XXX: put correct access by using cpu_restore_state() correctly */ - access_type =3D ACCESS_INT; - ret =3D get_physical_address(env, &physical, &prot, - address, rw, access_type, mmu_idx); + mips_access_type =3D ACCESS_INT; + ret =3D get_physical_address(env, &physical, &prot, address, + access_type, mips_access_type, mmu_idx); switch (ret) { case TLBRET_MATCH: qemu_log_mask(CPU_LOG_MMU, @@ -915,7 +909,7 @@ int mips_cpu_handle_mmu_fault(CPUState *cs, vaddr addre= ss, int size, int rw, tlb_set_page(cs, address & TARGET_PAGE_MASK, physical & TARGET_PAGE_MASK, prot | PAGE_EXEC, mmu_idx, TARGET_PAGE_SIZE); - return 0; + return true; } #if !defined(TARGET_MIPS64) if ((ret =3D=3D TLBRET_NOMATCH) && (env->tlb->nb_tlb > 1)) { @@ -926,27 +920,36 @@ int mips_cpu_handle_mmu_fault(CPUState *cs, vaddr add= ress, int size, int rw, int mode =3D (env->hflags & MIPS_HFLAG_KSU); bool ret_walker; env->hflags &=3D ~MIPS_HFLAG_KSU; - ret_walker =3D page_table_walk_refill(env, address, rw, mmu_idx); + ret_walker =3D page_table_walk_refill(env, address, access_type, m= mu_idx); env->hflags |=3D mode; if (ret_walker) { - ret =3D get_physical_address(env, &physical, &prot, - address, rw, access_type, mmu_idx); + ret =3D get_physical_address(env, &physical, &prot, address, + access_type, mips_access_type, mmu_= idx); if (ret =3D=3D TLBRET_MATCH) { tlb_set_page(cs, address & TARGET_PAGE_MASK, physical & TARGET_PAGE_MASK, prot | PAGE_EXEC, mmu_idx, TARGET_PAGE_SIZE); - return 0; + return true; } } } #endif + if (probe) { + return false; + } #endif =20 - raise_mmu_exception(env, address, rw, ret); - return 1; + raise_mmu_exception(env, address, access_type, ret); + do_raise_exception_err(env, cs->exception_index, env->error_code, reta= ddr); +} + +#ifndef CONFIG_USER_ONLY +void tlb_fill(CPUState *cs, target_ulong addr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) +{ + mips_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr= ); } =20 -#if !defined(CONFIG_USER_ONLY) hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address,= int rw) { hwaddr physical; diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index 0f272a5b93..6d86912958 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -2669,21 +2669,6 @@ void mips_cpu_do_unaligned_access(CPUState *cs, vadd= r addr, do_raise_exception_err(env, excp, error_code, retaddr); } =20 -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - int ret; - - ret =3D mips_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu_idx= ); - if (ret) { - MIPSCPU *cpu =3D MIPS_CPU(cs); - CPUMIPSState *env =3D &cpu->env; - - do_raise_exception_err(env, cs->exception_index, - env->error_code, retaddr); - } -} - void mips_cpu_unassigned_access(CPUState *cs, hwaddr addr, bool is_write, bool is_exec, int unused, unsigned size) --=20 2.17.1 From nobody Mon May 6 12:42:50 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1557440943; cv=none; d=zoho.com; s=zohoarc; b=Q/Vo+AdJ7VRepa/Y2BAdtIDBY0AyjP8satlUL4cdcv0gTnsEiE+mczzA3rbma43TqcWIak/vzB7uHtnuFynSNgAX+hxgpl8+UTBDR4riFEwTDyCf/QbDZeLYuac0Ij0ZMudUseucli3KIdML65pcZhpPykp49na5KzvViX9u3JQ= ARC-Message-Signature: i=1; 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[97.113.13.231]) by smtp.gmail.com with ESMTPSA id m2sm4490521pfi.24.2019.05.09.15.26.48 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 09 May 2019 15:26:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=SbdgfaYjW8ILfhiu0/mJqWKm/tBVnd5f44zvoNG8J24=; b=yrmaTw1isYlaWL0h+7ulMQ5InyN7qPN1b6Vv8b3I86iMq+GoPcz0+KSzsakznlng0B JDD5fj8I4FK3bxucKKhEpvlWt+7wCYbD6jHWh6fI49PU8Sd9OKat5nuo2w3taJSvOkkI 8GNDqQjYUPDWUnOgHgwt/C2DzyeHctU07jK++Vdg6v9Gmr9bdcO445CPlddAN885sMqr WLW9oSlyEDJw8+FN9SQ2D8gRQw45siWMhhLMNF+TIp7PC9EaDWGTywBsRHOP4n5TiCxr OyVJkoB4mv7eodqTpo+N6/d7uMfpBWr+N+bx7ZGe7I7IFpjRvxKRFo+ZdUPwTHkHlryt /VrA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=SbdgfaYjW8ILfhiu0/mJqWKm/tBVnd5f44zvoNG8J24=; b=HucpIPX2+9GhkFk9PWJr1hW+BuSqN6lWnr2MOdGQx+KQ0fdIgjzEwpiypQGwyV/mbX l9QeccyquBIdkiaJd6tY5FE3Sk9RCsROkxb6DKEu4RttjLypXw4L98MfYjncSh80n05P NUlW3J8TfdH7x8UCALEnfDkexQEXpqWPmiWUHCnXPfirfdAYQOt7LrbQSKfdk8GN2uPj HA7ENbSDbGpRH/RbELY3jXp/IjWhvd0/C3ICQZ2YpBFdtsc000RzD965RfhZuBpvBHsx WPAcQYRBdA3idtWm9kUWx3cFLzkfZbMpc5Uro/HaXaSxIBCuypoEOwEUYs0uxLdXkuSo iv9g== X-Gm-Message-State: APjAAAVk/v6VrvXSFZ1Es5ZI/rnRQAXfaWsmmLZyatkHyeWNnwApib+I sGAkP8hcQd/wUH/5N1dCX3655bvr9do= X-Google-Smtp-Source: APXvYqwpxgHkkUFlnOasIkZ8iKDO2JPj61Cs4qqWju6M7Zvv4H4rixRKjU6369WnXE0MfMbzdUYWZg== X-Received: by 2002:aa7:8ec6:: with SMTP id b6mr8882550pfr.234.1557440809813; Thu, 09 May 2019 15:26:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 9 May 2019 15:26:17 -0700 Message-Id: <20190509222631.14271-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190509222631.14271-1-richard.henderson@linaro.org> References: <20190509222631.14271-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::443 Subject: [Qemu-devel] [PATCH v3 13/27] target/moxie: Convert to CPUClass::tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Anthony Green Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Remove the user-only functions, as we don't have a user-only config. Fix the unconditional call to tlb_set_page, even if the translation failed. Cc: Anthony Green Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/moxie/cpu.h | 5 ++-- target/moxie/cpu.c | 5 ++-- target/moxie/helper.c | 61 ++++++++++--------------------------------- 3 files changed, 19 insertions(+), 52 deletions(-) diff --git a/target/moxie/cpu.h b/target/moxie/cpu.h index f3b6d83ae7..a63a96bc05 100644 --- a/target/moxie/cpu.h +++ b/target/moxie/cpu.h @@ -139,7 +139,8 @@ static inline void cpu_get_tb_cpu_state(CPUMoxieState *= env, target_ulong *pc, *flags =3D 0; } =20 -int moxie_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, - int rw, int mmu_idx); +bool moxie_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); =20 #endif /* MOXIE_CPU_H */ diff --git a/target/moxie/cpu.c b/target/moxie/cpu.c index 46434e65ba..02b2b47574 100644 --- a/target/moxie/cpu.c +++ b/target/moxie/cpu.c @@ -112,9 +112,8 @@ static void moxie_cpu_class_init(ObjectClass *oc, void = *data) cc->do_interrupt =3D moxie_cpu_do_interrupt; cc->dump_state =3D moxie_cpu_dump_state; cc->set_pc =3D moxie_cpu_set_pc; -#ifdef CONFIG_USER_ONLY - cc->handle_mmu_fault =3D moxie_cpu_handle_mmu_fault; -#else + cc->tlb_fill =3D moxie_cpu_tlb_fill; +#ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D moxie_cpu_get_phys_page_debug; cc->vmsd =3D &vmstate_moxie_cpu; #endif diff --git a/target/moxie/helper.c b/target/moxie/helper.c index 287a45232c..216cef057e 100644 --- a/target/moxie/helper.c +++ b/target/moxie/helper.c @@ -26,18 +26,10 @@ #include "qemu/host-utils.h" #include "exec/helper-proto.h" =20 -/* Try to fill the TLB and return an exception if error. If retaddr is - NULL, it means that the function was called in C code (i.e. not - from generated code or from helper.c) */ void tlb_fill(CPUState *cs, target_ulong addr, int size, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) { - int ret; - - ret =3D moxie_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu_id= x); - if (unlikely(ret)) { - cpu_loop_exit_restore(cs, retaddr); - } + moxie_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retadd= r); } =20 void helper_raise_exception(CPUMoxieState *env, int ex) @@ -85,53 +77,29 @@ void helper_debug(CPUMoxieState *env) cpu_loop_exit(cs); } =20 -#if defined(CONFIG_USER_ONLY) - -void moxie_cpu_do_interrupt(CPUState *cs) -{ - CPUState *cs =3D CPU(moxie_env_get_cpu(env)); - - cs->exception_index =3D -1; -} - -int moxie_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, - int rw, int mmu_idx) -{ - MoxieCPU *cpu =3D MOXIE_CPU(cs); - - cs->exception_index =3D 0xaa; - cpu->env.debug1 =3D address; - cpu_dump_state(cs, stderr, 0); - return 1; -} - -#else /* !CONFIG_USER_ONLY */ - -int moxie_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, - int rw, int mmu_idx) +bool moxie_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) { MoxieCPU *cpu =3D MOXIE_CPU(cs); CPUMoxieState *env =3D &cpu->env; MoxieMMUResult res; int prot, miss; - target_ulong phy; - int r =3D 1; =20 address &=3D TARGET_PAGE_MASK; prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; - miss =3D moxie_mmu_translate(&res, env, address, rw, mmu_idx); - if (miss) { - /* handle the miss. */ - phy =3D 0; - cs->exception_index =3D MOXIE_EX_MMU_MISS; - } else { - phy =3D res.phy; - r =3D 0; + miss =3D moxie_mmu_translate(&res, env, address, access_type, mmu_idx); + if (likely(!miss)) { + tlb_set_page(cs, address, res.phy, prot, mmu_idx, TARGET_PAGE_SIZE= ); + return true; + } + if (probe) { + return false; } - tlb_set_page(cs, address, phy, prot, mmu_idx, TARGET_PAGE_SIZE); - return r; -} =20 + cs->exception_index =3D MOXIE_EX_MMU_MISS; + cpu_loop_exit_restore(cs, retaddr); +} =20 void moxie_cpu_do_interrupt(CPUState *cs) { @@ -156,4 +124,3 @@ hwaddr moxie_cpu_get_phys_page_debug(CPUState *cs, vadd= r addr) } return phy; } -#endif --=20 2.17.1 From nobody Mon May 6 12:42:50 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1557441364; cv=none; d=zoho.com; s=zohoarc; b=kGsnWp0/fyw6FrJzN+5J8OAsZUJuvFqQzeDH44wNaZRxg9w0oj4SJ/x2nDRJz6PprIPprjdTuO566iaLwKwLcMcryfzw8Kb+nj4VdyTSvm3bVD4QkV8izxxBkutGIPE1khz4oftl9ykbKC1gFmdE/XwzaRh+qQWw1gzl1v+13no= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1557441364; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=SpLH0uX/7VPwqZUU302UGF7XHUymHPBE4Y7Eq/kvJTk=; b=R8LHLZS0cl7t70oo8HKtDpMJdDb4EJAFcqpiI52UnKdOcwgUnOQyqziH73aT2kKxgQhQ+y5pAHfsrmmwhMOgPfI7ih+rcYam236OjEKLtMaDmBjE0qPx09fo0AJzD2sa/6fkVXRLsczXBJlusXQYsdsQLRrIAHaf1474vz4oeqA= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1557441364066179.24792165906217; Thu, 9 May 2019 15:36:04 -0700 (PDT) Received: from localhost ([127.0.0.1]:33565 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hOrdw-00074z-UQ for importer@patchew.org; Thu, 09 May 2019 18:36:01 -0400 Received: from eggs.gnu.org ([209.51.188.92]:33022) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hOrV9-0007mt-Lx for qemu-devel@nongnu.org; Thu, 09 May 2019 18:26:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hOrV6-0005WB-SL for qemu-devel@nongnu.org; Thu, 09 May 2019 18:26:55 -0400 Received: from mail-pl1-x641.google.com ([2607:f8b0:4864:20::641]:35132) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hOrV6-0005VN-Jw for qemu-devel@nongnu.org; Thu, 09 May 2019 18:26:52 -0400 Received: by mail-pl1-x641.google.com with SMTP id g5so1817391plt.2 for ; Thu, 09 May 2019 15:26:52 -0700 (PDT) Received: from localhost.localdomain (97-113-13-231.tukw.qwest.net. [97.113.13.231]) by smtp.gmail.com with ESMTPSA id m2sm4490521pfi.24.2019.05.09.15.26.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 09 May 2019 15:26:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=SpLH0uX/7VPwqZUU302UGF7XHUymHPBE4Y7Eq/kvJTk=; b=r/zWCjyBa6w3w3x1S/PuVzdlxrdCIhjd0JLLuUEIuVC5U+HSRHuLfBpV2s9tM6xmFw TrgARQAqHZWFSk1+rXyz57R7Vn1tuO5OYW9XMzAyRjc1mEvFDSKFhdszOk//MnXA/8Av 0ABgwdo7OSQ1b/YUAMoxL9nX40afaDpNcbtGFID/+lAIoac+axxEkKwThbXgQ4O0485+ lm7K5QFfTteyDpDlid9sz9wjPEzeyamvrCRho+vvJivhLiwgjlCIv6I4c7CSniNddBN1 HFItuQEi/pIdwga+L7O5kNn3Uc/Mvc0jRbbfzTHsZU6auDeDNDd4tMChOz88Dv0/onsG iELw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=SpLH0uX/7VPwqZUU302UGF7XHUymHPBE4Y7Eq/kvJTk=; b=cHbQE3I93iM3R5ob5AepCBOsI1+BokgrYecvUiZp3Husr78HCcMemuW81tpVOSMK17 p2LaGc62Xe+lZzUgHA93TUpYGd5AzpqUarejK3c//o8mW4KyRyAybvTIBX6ikrNsdQXf RBVlzFERjeIdPmgxub0NdRg0Sc2SGQHXJ75aXZMKPmJKzDmouoCos64VcbxZKwQn+Ez+ kDmIv6WmaP+prAh7XmOKQqJ61AuFcPsUI8FSKaciMiqyKpwtsHaG5su95BbOQLZ3sY3w jsDT8Yrc/utc2bFFwFsG3K7p/mxIBUyP4bEklA1U4hmhxtg43roS09TQ3ExPXf8pYhHq RNSQ== X-Gm-Message-State: APjAAAUQsKRS4hIPmWi8VpDiO8owCT9lZs4vkhOvhs9UfIcGm+PEYdHJ 0kFM6IaI/kH0H27N/vcfWDDERhx8CXU= X-Google-Smtp-Source: APXvYqy3FEyCPNlSmTNCD1QGifq+1Q6hxs237P1VbDUIm6NGFTIB9Cf4uVCMnOHtvvGC0iiJTGQSZQ== X-Received: by 2002:a17:902:28a9:: with SMTP id f38mr8343171plb.295.1557440811233; Thu, 09 May 2019 15:26:51 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 9 May 2019 15:26:18 -0700 Message-Id: <20190509222631.14271-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190509222631.14271-1-richard.henderson@linaro.org> References: <20190509222631.14271-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::641 Subject: [Qemu-devel] [PATCH v3 14/27] target/nios2: Convert to CPUClass::tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marek Vasut , Chris Wulff Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Remove the leftover debugging cpu_dump_state. Cc: Chris Wulff Cc: Marek Vasut Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- v2: Keep user-only and system tlb_fill separate. --- target/nios2/cpu.h | 5 +- target/nios2/cpu.c | 5 +- target/nios2/helper.c | 176 +++++++++++++++++++++--------------------- target/nios2/mmu.c | 12 --- 4 files changed, 91 insertions(+), 107 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 881e7d58c9..60a916b2e5 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -252,8 +252,9 @@ static inline int cpu_mmu_index(CPUNios2State *env, boo= l ifetch) MMU_SUPERVISOR_IDX; } =20 -int nios2_cpu_handle_mmu_fault(CPUState *env, vaddr address, int size, - int rw, int mmu_idx); +bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); =20 static inline int cpu_interrupts_enabled(CPUNios2State *env) { diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index fbfaa2ce26..186af4913d 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -200,9 +200,8 @@ static void nios2_cpu_class_init(ObjectClass *oc, void = *data) cc->dump_state =3D nios2_cpu_dump_state; cc->set_pc =3D nios2_cpu_set_pc; cc->disas_set_info =3D nios2_cpu_disas_set_info; -#ifdef CONFIG_USER_ONLY - cc->handle_mmu_fault =3D nios2_cpu_handle_mmu_fault; -#else + cc->tlb_fill =3D nios2_cpu_tlb_fill; +#ifndef CONFIG_USER_ONLY cc->do_unaligned_access =3D nios2_cpu_do_unaligned_access; cc->get_phys_page_debug =3D nios2_cpu_get_phys_page_debug; #endif diff --git a/target/nios2/helper.c b/target/nios2/helper.c index e01fc1ff3e..eb2eed7ad3 100644 --- a/target/nios2/helper.c +++ b/target/nios2/helper.c @@ -38,15 +38,12 @@ void nios2_cpu_do_interrupt(CPUState *cs) env->regs[R_EA] =3D env->regs[R_PC] + 4; } =20 -int nios2_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, - int rw, int mmu_idx) +bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) { cs->exception_index =3D 0xaa; - /* Page 0x1000 is kuser helper */ - if (address < 0x1000 || address >=3D 0x2000) { - cpu_dump_state(cs, stderr, 0); - } - return 1; + cpu_loop_exit_restore(cs, retaddr); } =20 #else /* !CONFIG_USER_ONLY */ @@ -203,89 +200,6 @@ void nios2_cpu_do_interrupt(CPUState *cs) } } =20 -static int cpu_nios2_handle_virtual_page( - CPUState *cs, target_ulong address, int rw, int mmu_idx) -{ - Nios2CPU *cpu =3D NIOS2_CPU(cs); - CPUNios2State *env =3D &cpu->env; - target_ulong vaddr, paddr; - Nios2MMULookup lu; - unsigned int hit; - hit =3D mmu_translate(env, &lu, address, rw, mmu_idx); - if (hit) { - vaddr =3D address & TARGET_PAGE_MASK; - paddr =3D lu.paddr + vaddr - lu.vaddr; - - if (((rw =3D=3D 0) && (lu.prot & PAGE_READ)) || - ((rw =3D=3D 1) && (lu.prot & PAGE_WRITE)) || - ((rw =3D=3D 2) && (lu.prot & PAGE_EXEC))) { - - tlb_set_page(cs, vaddr, paddr, lu.prot, - mmu_idx, TARGET_PAGE_SIZE); - return 0; - } else { - /* Permission violation */ - cs->exception_index =3D (rw =3D=3D 0) ? EXCP_TLBR : - ((rw =3D=3D 1) ? EXCP_TLBW : - EXCP_TLBX); - } - } else { - cs->exception_index =3D EXCP_TLBD; - } - - if (rw =3D=3D 2) { - env->regs[CR_TLBMISC] &=3D ~CR_TLBMISC_D; - } else { - env->regs[CR_TLBMISC] |=3D CR_TLBMISC_D; - } - env->regs[CR_PTEADDR] &=3D CR_PTEADDR_PTBASE_MASK; - env->regs[CR_PTEADDR] |=3D (address >> 10) & CR_PTEADDR_VPN_MASK; - env->mmu.pteaddr_wr =3D env->regs[CR_PTEADDR]; - env->regs[CR_BADADDR] =3D address; - return 1; -} - -int nios2_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, - int rw, int mmu_idx) -{ - Nios2CPU *cpu =3D NIOS2_CPU(cs); - CPUNios2State *env =3D &cpu->env; - - if (cpu->mmu_present) { - if (MMU_SUPERVISOR_IDX =3D=3D mmu_idx) { - if (address >=3D 0xC0000000) { - /* Kernel physical page - TLB bypassed */ - address &=3D TARGET_PAGE_MASK; - tlb_set_page(cs, address, address, PAGE_BITS, - mmu_idx, TARGET_PAGE_SIZE); - } else if (address >=3D 0x80000000) { - /* Kernel virtual page */ - return cpu_nios2_handle_virtual_page(cs, address, rw, mmu_= idx); - } else { - /* User virtual page */ - return cpu_nios2_handle_virtual_page(cs, address, rw, mmu_= idx); - } - } else { - if (address >=3D 0x80000000) { - /* Illegal access from user mode */ - cs->exception_index =3D EXCP_SUPERA; - env->regs[CR_BADADDR] =3D address; - return 1; - } else { - /* User virtual page */ - return cpu_nios2_handle_virtual_page(cs, address, rw, mmu_= idx); - } - } - } else { - /* No MMU */ - address &=3D TARGET_PAGE_MASK; - tlb_set_page(cs, address, address, PAGE_BITS, - mmu_idx, TARGET_PAGE_SIZE); - } - - return 0; -} - hwaddr nios2_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) { Nios2CPU *cpu =3D NIOS2_CPU(cs); @@ -321,4 +235,86 @@ void nios2_cpu_do_unaligned_access(CPUState *cs, vaddr= addr, env->regs[CR_EXCEPTION] =3D EXCP_UNALIGN << 2; helper_raise_exception(env, EXCP_UNALIGN); } + +bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) +{ + Nios2CPU *cpu =3D NIOS2_CPU(cs); + CPUNios2State *env =3D &cpu->env; + unsigned int excp =3D EXCP_TLBD; + target_ulong vaddr, paddr; + Nios2MMULookup lu; + unsigned int hit; + + if (!cpu->mmu_present) { + /* No MMU */ + address &=3D TARGET_PAGE_MASK; + tlb_set_page(cs, address, address, PAGE_BITS, + mmu_idx, TARGET_PAGE_SIZE); + return true; + } + + if (MMU_SUPERVISOR_IDX =3D=3D mmu_idx) { + if (address >=3D 0xC0000000) { + /* Kernel physical page - TLB bypassed */ + address &=3D TARGET_PAGE_MASK; + tlb_set_page(cs, address, address, PAGE_BITS, + mmu_idx, TARGET_PAGE_SIZE); + return true; + } + } else { + if (address >=3D 0x80000000) { + /* Illegal access from user mode */ + if (probe) { + return false; + } + cs->exception_index =3D EXCP_SUPERA; + env->regs[CR_BADADDR] =3D address; + cpu_loop_exit_restore(cs, retaddr); + } + } + + /* Virtual page. */ + hit =3D mmu_translate(env, &lu, address, access_type, mmu_idx); + if (hit) { + vaddr =3D address & TARGET_PAGE_MASK; + paddr =3D lu.paddr + vaddr - lu.vaddr; + + if (((access_type =3D=3D MMU_DATA_LOAD) && (lu.prot & PAGE_READ)) = || + ((access_type =3D=3D MMU_DATA_STORE) && (lu.prot & PAGE_WRITE)= ) || + ((access_type =3D=3D MMU_INST_FETCH) && (lu.prot & PAGE_EXEC))= ) { + tlb_set_page(cs, vaddr, paddr, lu.prot, + mmu_idx, TARGET_PAGE_SIZE); + return true; + } + + /* Permission violation */ + excp =3D (access_type =3D=3D MMU_DATA_LOAD ? EXCP_TLBR : + access_type =3D=3D MMU_DATA_STORE ? EXCP_TLBW : EXCP_TLBX); + } + + if (probe) { + return false; + } + + if (access_type =3D=3D MMU_INST_FETCH) { + env->regs[CR_TLBMISC] &=3D ~CR_TLBMISC_D; + } else { + env->regs[CR_TLBMISC] |=3D CR_TLBMISC_D; + } + env->regs[CR_PTEADDR] &=3D CR_PTEADDR_PTBASE_MASK; + env->regs[CR_PTEADDR] |=3D (address >> 10) & CR_PTEADDR_VPN_MASK; + env->mmu.pteaddr_wr =3D env->regs[CR_PTEADDR]; + + cs->exception_index =3D excp; + env->regs[CR_BADADDR] =3D address; + cpu_loop_exit_restore(cs, retaddr); +} + +void tlb_fill(CPUState *cs, target_ulong addr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) +{ + nios2_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retadd= r); +} #endif /* !CONFIG_USER_ONLY */ diff --git a/target/nios2/mmu.c b/target/nios2/mmu.c index 5acf442d8b..47fa474efb 100644 --- a/target/nios2/mmu.c +++ b/target/nios2/mmu.c @@ -36,18 +36,6 @@ #define MMU_LOG(x) #endif =20 -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - int ret; - - ret =3D nios2_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu_id= x); - if (unlikely(ret)) { - /* now we have a real cpu fault */ - cpu_loop_exit_restore(cs, retaddr); - } -} - void mmu_read_debug(CPUNios2State *env, uint32_t rn) { switch (rn) { --=20 2.17.1 From nobody Mon May 6 12:42:50 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1557441124; cv=none; d=zoho.com; s=zohoarc; b=aP1ESkLq/XJB2131WZpIygy8YUhNvvBf5CgP7dSl6spPVf5H+Gs+B7EBUTAuf2l2e9du6L13hG1QF14sAbNllFZIGB07gY6AOqohe/B5rCR2yUpnnhc2lOfoLhdV5b/EFnigjiA9cs4NSZwsi2R6e7Ny5B8yanQk7Wb0VRKMF2E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1557441124; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=pyOmNQehrxQ+vJN1rBIdXnxr1kqTHPzFsWgERMP7ALs=; b=KeFc3v/v3/b/7g81d9yyoeRjPsqgcoCFybxKAWLaGz5JhXfpzx3EbCRn6Xh4JzSISmbk+ALS3b8pQhFeeQQHlB1aY1RLZK1ZIApPAizX//hnSDyDrUt/Kj+0qMpbPa0Ecmjwx9pCWZ0TJpen2ab1B3Ia6YtLYXbCk1324KXoYFo= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1557441124053754.9606055883802; Thu, 9 May 2019 15:32:04 -0700 (PDT) Received: from localhost ([127.0.0.1]:33502 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hOra4-0002yF-01 for importer@patchew.org; Thu, 09 May 2019 18:32:00 -0400 Received: from eggs.gnu.org ([209.51.188.92]:33015) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hOrV9-0007mg-Fx for qemu-devel@nongnu.org; Thu, 09 May 2019 18:26:56 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hOrV8-0005WZ-CC for qemu-devel@nongnu.org; Thu, 09 May 2019 18:26:55 -0400 Received: from mail-pl1-x641.google.com ([2607:f8b0:4864:20::641]:41759) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hOrV8-0005WP-6G for qemu-devel@nongnu.org; Thu, 09 May 2019 18:26:54 -0400 Received: by mail-pl1-x641.google.com with SMTP id d9so1800873pls.8 for ; Thu, 09 May 2019 15:26:54 -0700 (PDT) Received: from localhost.localdomain (97-113-13-231.tukw.qwest.net. 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X-Received-From: 2607:f8b0:4864:20::641 Subject: [Qemu-devel] [PATCH v3 15/27] target/openrisc: Convert to CPUClass::tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stafford Horne Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Cc: Stafford Horne Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/openrisc/cpu.h | 5 ++-- target/openrisc/cpu.c | 5 ++-- target/openrisc/mmu.c | 65 ++++++++++++++++++++++--------------------- 3 files changed, 39 insertions(+), 36 deletions(-) diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 88a8c70092..9473d94d0c 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -344,8 +344,9 @@ hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cpu, = vaddr addr); int openrisc_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); int openrisc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void openrisc_translate_init(void); -int openrisc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, - int rw, int mmu_idx); +bool openrisc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); int cpu_openrisc_signal_handler(int host_signum, void *pinfo, void *puc); int print_insn_or1k(bfd_vma addr, disassemble_info *info); =20 diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index d125236977..3816baee70 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -149,9 +149,8 @@ static void openrisc_cpu_class_init(ObjectClass *oc, vo= id *data) cc->set_pc =3D openrisc_cpu_set_pc; cc->gdb_read_register =3D openrisc_cpu_gdb_read_register; cc->gdb_write_register =3D openrisc_cpu_gdb_write_register; -#ifdef CONFIG_USER_ONLY - cc->handle_mmu_fault =3D openrisc_cpu_handle_mmu_fault; -#else + cc->tlb_fill =3D openrisc_cpu_tlb_fill; +#ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D openrisc_cpu_get_phys_page_debug; dc->vmsd =3D &vmstate_openrisc_cpu; #endif diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c index 5dec68dcff..94c65a25fa 100644 --- a/target/openrisc/mmu.c +++ b/target/openrisc/mmu.c @@ -107,16 +107,42 @@ static void raise_mmu_exception(OpenRISCCPU *cpu, tar= get_ulong address, cpu->env.lock_addr =3D -1; } =20 -int openrisc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, - int rw, int mmu_idx) +bool openrisc_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) { -#ifdef CONFIG_USER_ONLY OpenRISCCPU *cpu =3D OPENRISC_CPU(cs); - raise_mmu_exception(cpu, address, EXCP_DPF); - return 1; -#else - g_assert_not_reached(); + int excp =3D EXCP_DPF; + +#ifndef CONFIG_USER_ONLY + int prot; + hwaddr phys_addr; + + if (mmu_idx =3D=3D MMU_NOMMU_IDX) { + /* The mmu is disabled; lookups never fail. */ + get_phys_nommu(&phys_addr, &prot, addr); + excp =3D 0; + } else { + bool super =3D mmu_idx =3D=3D MMU_SUPERVISOR_IDX; + int need =3D (access_type =3D=3D MMU_INST_FETCH ? PAGE_EXEC + : access_type =3D=3D MMU_DATA_STORE ? PAGE_WRITE + : PAGE_READ); + excp =3D get_phys_mmu(cpu, &phys_addr, &prot, addr, need, super); + } + + if (likely(excp =3D=3D 0)) { + tlb_set_page(cs, addr & TARGET_PAGE_MASK, + phys_addr & TARGET_PAGE_MASK, prot, + mmu_idx, TARGET_PAGE_SIZE); + return true; + } + if (probe) { + return false; + } #endif + + raise_mmu_exception(cpu, addr, excp); + cpu_loop_exit_restore(cs, retaddr); } =20 #ifndef CONFIG_USER_ONLY @@ -156,29 +182,6 @@ hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cs, = vaddr addr) void tlb_fill(CPUState *cs, target_ulong addr, int size, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) { - OpenRISCCPU *cpu =3D OPENRISC_CPU(cs); - int prot, excp; - hwaddr phys_addr; - - if (mmu_idx =3D=3D MMU_NOMMU_IDX) { - /* The mmu is disabled; lookups never fail. */ - get_phys_nommu(&phys_addr, &prot, addr); - excp =3D 0; - } else { - bool super =3D mmu_idx =3D=3D MMU_SUPERVISOR_IDX; - int need =3D (access_type =3D=3D MMU_INST_FETCH ? PAGE_EXEC - : access_type =3D=3D MMU_DATA_STORE ? PAGE_WRITE - : PAGE_READ); - excp =3D get_phys_mmu(cpu, &phys_addr, &prot, addr, need, super); - } - - if (unlikely(excp)) { - raise_mmu_exception(cpu, addr, excp); - cpu_loop_exit_restore(cs, retaddr); - } - - tlb_set_page(cs, addr & TARGET_PAGE_MASK, - phys_addr & TARGET_PAGE_MASK, prot, - mmu_idx, TARGET_PAGE_SIZE); + openrisc_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, 0, retaddr= ); } #endif --=20 2.17.1 From nobody Mon May 6 12:42:50 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1557442063; cv=none; d=zoho.com; s=zohoarc; b=fwYaIW/+zEGVIyMIpgGRqD5cyp+l/Wo5TGVa7Pmd82EEpkMRC0Zz/9Fw7sO3kNQgtxkDRV+tIkzBVpoSsf0yutjF/Zk+qiXfvEd8eHbsn43KObuVminj7rRylS5eR1gs+rzawoVFVjFJLEyrzPX0Zs6ReWxD5HfmCOEXJFy831E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1557442063; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=i61mEex2vpahjushkr4y22Y6q9/HL9JKMG8d2fXnTE0=; b=AlHzxIbbQEZHKXhJk/GzFpLVCFhPfayo2Md3FOhYTnnENpEfM88TyjBfcvcdm9Ok0dhHRweZrjgQuYr/GGkusr9nf5em0W3AxWYmsHSxeSEyoC5/leCO14fRe9FXIA1KYJlZfo1iMv+twjkfY/fPlYSBuabarM0WZmWk3EvVa8M= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1557442063310822.7272276086853; Thu, 9 May 2019 15:47:43 -0700 (PDT) Received: from localhost ([127.0.0.1]:33757 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hOrpE-0000VX-Ah for importer@patchew.org; Thu, 09 May 2019 18:47:40 -0400 Received: from eggs.gnu.org ([209.51.188.92]:33066) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hOrVB-0007oQ-6h for qemu-devel@nongnu.org; Thu, 09 May 2019 18:26:58 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hOrVA-0005Xn-0A for qemu-devel@nongnu.org; Thu, 09 May 2019 18:26:57 -0400 Received: from mail-pf1-x444.google.com ([2607:f8b0:4864:20::444]:41939) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hOrV9-0005XC-Qh for qemu-devel@nongnu.org; Thu, 09 May 2019 18:26:55 -0400 Received: by mail-pf1-x444.google.com with SMTP id l132so2041397pfc.8 for ; Thu, 09 May 2019 15:26:55 -0700 (PDT) Received: from localhost.localdomain (97-113-13-231.tukw.qwest.net. [97.113.13.231]) by smtp.gmail.com with ESMTPSA id m2sm4490521pfi.24.2019.05.09.15.26.53 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 09 May 2019 15:26:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=i61mEex2vpahjushkr4y22Y6q9/HL9JKMG8d2fXnTE0=; b=nm4DjUfSsSj9UfmRYqY4EAiqgB0VEcXrhjFYdPPYjrlMaGjIY1XNMkvzF0XI5vhSt5 73Eo8mjCsJ5zpnbjgik2+uolkQYlg/LsLuZ18vhkYvQ4ULJmKpdOgBskmVw4V4Tv0wrt DtEjWUOCoUaCnLYRq/Jq6C/cOEuTtsIehLsfAYjhJ3XoZYwmPaxVweYq1rrshrugGMx0 3IlUNEXxIXWOvJlZnc8EOMxKrJTtXsUMFurE8O8sFDAy/aLDO+k3QjkG4M5yuY94Sh8Z HgDq4lessUItxsgIpI5SRPYvXXde1BsymjjmxpzGtKOJV4sAkKv1V9FiGdSiJP8ac67n 4UpA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=i61mEex2vpahjushkr4y22Y6q9/HL9JKMG8d2fXnTE0=; b=laPQ7SKYRyYYXRsSfRLxXFvuUY8O9PNQC/VSLUksu4xBRiegeGcp97j0btmi4MpQuv OwLtHq/mwqN9L12SSYvsb1RVsyI4GXkTQNKhr9QI5yYYkh0fhopKpuDLNhbAQcvJcZKg oq/efFuh20W2eZnoH5JitlBKlJCCO0qin+lMdAzSVWy+O8txawECnaGbowQaiuiJTqlM RTrCSp5EVPKSIYv1Zb40UJcrf+93fcWdXr19oGEa8pVhbjXBHOdJ2bgpOqhR5/4ytvrM tRCUCsf1Vg195jhHZu1kHZoSFXzkCi2NUkC3na0UCawEiQ+B2I7jpsB7PyJ5ThQB6ggm GztQ== X-Gm-Message-State: APjAAAUFRILuRwQvaK8ekEDrl/+fWz1oQqsDdx+RXfI4JXp4LwMJT6vy S12pu4o+Z76k4FgFlcGoof1ZI87eLHw= X-Google-Smtp-Source: APXvYqy4cWjJwrgeqwh2DKvQHCMk9UnZg2GJa3y2dibrGD7+FYLV33CZrmbHZ47jtqY8Iw8o6CmVHA== X-Received: by 2002:a63:5c5b:: with SMTP id n27mr9165423pgm.52.1557440814573; Thu, 09 May 2019 15:26:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 9 May 2019 15:26:20 -0700 Message-Id: <20190509222631.14271-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190509222631.14271-1-richard.henderson@linaro.org> References: <20190509222631.14271-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH v3 16/27] target/ppc: Convert to CPUClass::tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Cc: qemu-ppc@nongnu.org Cc: David Gibson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Acked-by: David Gibson --- target/ppc/cpu.h | 7 +++---- target/ppc/mmu_helper.c | 22 +++++++++++++--------- target/ppc/translate_init.inc.c | 5 ++--- target/ppc/user_only_helper.c | 14 ++++++++------ 4 files changed, 26 insertions(+), 22 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 5e7cf54b2f..d7f23ad5e0 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1311,10 +1311,9 @@ void ppc_translate_init(void); * is returned if the signal was handled by the virtual CPU. */ int cpu_ppc_signal_handler(int host_signum, void *pinfo, void *puc); -#if defined(CONFIG_USER_ONLY) -int ppc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int r= w, - int mmu_idx); -#endif +bool ppc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); =20 #if !defined(CONFIG_USER_ONLY) void ppc_store_sdr1(CPUPPCState *env, target_ulong value); diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c index 1dbc9acb75..afcca50530 100644 --- a/target/ppc/mmu_helper.c +++ b/target/ppc/mmu_helper.c @@ -3057,15 +3057,9 @@ void helper_check_tlb_flush_global(CPUPPCState *env) =20 /*************************************************************************= ****/ =20 -/* - * try to fill the TLB and return an exception if error. If retaddr is - * NULL, it means that the function was called in C code (i.e. not - * from generated code or from helper.c) - * - * XXX: fix it to restore all registers - */ -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) +bool ppc_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) { PowerPCCPU *cpu =3D POWERPC_CPU(cs); PowerPCCPUClass *pcc =3D POWERPC_CPU_GET_CLASS(cs); @@ -3078,7 +3072,17 @@ void tlb_fill(CPUState *cs, target_ulong addr, int s= ize, ret =3D cpu_ppc_handle_mmu_fault(env, addr, access_type, mmu_idx); } if (unlikely(ret !=3D 0)) { + if (probe) { + return false; + } raise_exception_err_ra(env, cs->exception_index, env->error_code, retaddr); } + return true; +} + +void tlb_fill(CPUState *cs, target_ulong addr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) +{ + ppc_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); } diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.in= c.c index 0394a9ddad..3f847de36c 100644 --- a/target/ppc/translate_init.inc.c +++ b/target/ppc/translate_init.inc.c @@ -10592,9 +10592,8 @@ static void ppc_cpu_class_init(ObjectClass *oc, voi= d *data) cc->gdb_read_register =3D ppc_cpu_gdb_read_register; cc->gdb_write_register =3D ppc_cpu_gdb_write_register; cc->do_unaligned_access =3D ppc_cpu_do_unaligned_access; -#ifdef CONFIG_USER_ONLY - cc->handle_mmu_fault =3D ppc_cpu_handle_mmu_fault; -#else + cc->tlb_fill =3D ppc_cpu_tlb_fill; +#ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D ppc_cpu_get_phys_page_debug; cc->vmsd =3D &vmstate_ppc_cpu; #endif diff --git a/target/ppc/user_only_helper.c b/target/ppc/user_only_helper.c index 2f1477f102..683c03390d 100644 --- a/target/ppc/user_only_helper.c +++ b/target/ppc/user_only_helper.c @@ -20,21 +20,24 @@ =20 #include "qemu/osdep.h" #include "cpu.h" +#include "exec/exec-all.h" =20 -int ppc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw, - int mmu_idx) + +bool ppc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) { PowerPCCPU *cpu =3D POWERPC_CPU(cs); CPUPPCState *env =3D &cpu->env; int exception, error_code; =20 - if (rw =3D=3D 2) { + if (access_type =3D=3D MMU_INST_FETCH) { exception =3D POWERPC_EXCP_ISI; error_code =3D 0x40000000; } else { exception =3D POWERPC_EXCP_DSI; error_code =3D 0x40000000; - if (rw) { + if (access_type =3D=3D MMU_DATA_STORE) { error_code |=3D 0x02000000; } env->spr[SPR_DAR] =3D address; @@ -42,6 +45,5 @@ int ppc_cpu_handle_mmu_fault(CPUState *cs, vaddr address,= int size, int rw, } cs->exception_index =3D exception; env->error_code =3D error_code; - - return 1; + cpu_loop_exit_restore(cs, retaddr); } --=20 2.17.1 From nobody Mon May 6 12:42:50 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[97.113.13.231]) by smtp.gmail.com with ESMTPSA id m2sm4490521pfi.24.2019.05.09.15.26.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 09 May 2019 15:26:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=jFiOLbzDz1sji7rdhiIl1UIG07vaIVhoy6dgsMAsHtw=; b=aV3a8BO/vH4AIMaRdqrMLk1KK2MOingD2OeAuNiWNFHsiWnleab5viMP3EWhF39+hv FaPIkwdhPAcsdmAlDn32Fz/ZERWUx0YZdRRDHvipca806xlynz/qmF/5QqS+IXjJOe5m QjqcPZA2Fldc1cP7H5iMHG84RGZeMSKHTgIOQ6KXXCcVROdQllrKGQUm9ZoMp/YEaz5w Gb7F6G0OSp9KRTGXdLL5B0OE8UgJcU8GNvKi+L+FL/K4b1lvS8KicS6X17pyMaPHvZI9 VwL9j1/CKFi80H7p+41SwU1v08WRU81YqSFme27v+SCT/FtepvY+2tqK8rihQ0IdWXjE i7OQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=jFiOLbzDz1sji7rdhiIl1UIG07vaIVhoy6dgsMAsHtw=; b=jGSONJfg2l9ECsOk+XbKxwXawz5F5PbtPoRJv3hBqaKXSIQjcCaEbPAlb5JhRZBms3 tX6K+fLL0U4O6JOcSMnOHt3MgBa5GAgsTmxqEsxzWhEchhrJNsOQUF+ysQMSceL+b9BC HsBwZcD1086eOEftA1YM+FKp2LbgBe75xVs4O4+FVOFewqt9VahoBSWnZ6anHK4cpWvk 0CXA2zl1UMMXpVaBRD36JvSxZzmF8YDwF9m2dxNqQUSl+4RPkSFEEho+jgxc1m2Tnxs6 vSP6COBXNbkJEvOX2nRudnhCMU8cLdhxtURnJn2kBAUx0Zxi/09ZIAnKKpI5so+eZcFb 7GcA== X-Gm-Message-State: APjAAAXCwUGGjE9R+CwkfhdIjnVwBQFVXQLHjx3/DZBNpB6razZjfllA wvTJBL+IW2Hf+mRn0YjMVkcYxUvu8uQ= X-Google-Smtp-Source: APXvYqyRhxKS3HJLmHWZIlct/g7K5dInKnJQrqJUzKdzyP9V+/VeU4viCSiVVAdOjwoeW7uk+tYGDw== X-Received: by 2002:a17:902:f24:: with SMTP id 33mr8499442ply.33.1557440815722; Thu, 09 May 2019 15:26:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 9 May 2019 15:26:21 -0700 Message-Id: <20190509222631.14271-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190509222631.14271-1-richard.henderson@linaro.org> References: <20190509222631.14271-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 Subject: [Qemu-devel] [PATCH v3 17/27] target/riscv: Convert to CPUClass::tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Palmer Dabbelt , qemu-riscv@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Note that env->pc is removed from the qemu_log as that value is garbage. The PC isn't recovered until cpu_restore_state, called from cpu_loop_exit_restore, called from riscv_raise_exception. Cc: qemu-riscv@nongnu.org Cc: Palmer Dabbelt Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- target/riscv/cpu.h | 5 +++-- target/riscv/cpu.c | 5 ++--- target/riscv/cpu_helper.c | 46 ++++++++++++++++++--------------------- 3 files changed, 26 insertions(+), 30 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 7d9f48973f..c17184f4e4 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -261,8 +261,9 @@ hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vad= dr addr); void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr); -int riscv_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, - int rw, int mmu_idx); +bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); char *riscv_isa_string(RISCVCPU *cpu); void riscv_cpu_list(void); =20 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1bcf4eaeb8..34a54ef2ed 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -355,9 +355,8 @@ static void riscv_cpu_class_init(ObjectClass *c, void *= data) #endif cc->gdb_stop_before_watchpoint =3D true; cc->disas_set_info =3D riscv_cpu_disas_set_info; -#ifdef CONFIG_USER_ONLY - cc->handle_mmu_fault =3D riscv_cpu_handle_mmu_fault; -#else + cc->tlb_fill =3D riscv_cpu_tlb_fill; +#ifndef CONFIG_USER_ONLY cc->do_unaligned_access =3D riscv_cpu_do_unaligned_access; cc->get_phys_page_debug =3D riscv_cpu_get_phys_page_debug; #endif diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index b17f169681..2535435260 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -379,53 +379,49 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vadd= r addr, riscv_raise_exception(env, cs->exception_index, retaddr); } =20 -/* called by qemu's softmmu to fill the qemu tlb */ void tlb_fill(CPUState *cs, target_ulong addr, int size, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) { - int ret; - ret =3D riscv_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu_id= x); - if (ret =3D=3D TRANSLATE_FAIL) { - RISCVCPU *cpu =3D RISCV_CPU(cs); - CPURISCVState *env =3D &cpu->env; - riscv_raise_exception(env, cs->exception_index, retaddr); - } + riscv_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retadd= r); } - #endif =20 -int riscv_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, - int rw, int mmu_idx) +bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) { +#ifndef CONFIG_USER_ONLY RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; -#if !defined(CONFIG_USER_ONLY) hwaddr pa =3D 0; int prot; -#endif int ret =3D TRANSLATE_FAIL; =20 - qemu_log_mask(CPU_LOG_MMU, - "%s pc " TARGET_FMT_lx " ad %" VADDR_PRIx " rw %d mmu_idx \ - %d\n", __func__, env->pc, address, rw, mmu_idx); + qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n", + __func__, address, access_type, mmu_idx); + + ret =3D get_physical_address(env, &pa, &prot, address, access_type, mm= u_idx); =20 -#if !defined(CONFIG_USER_ONLY) - ret =3D get_physical_address(env, &pa, &prot, address, rw, mmu_idx); qemu_log_mask(CPU_LOG_MMU, - "%s address=3D%" VADDR_PRIx " ret %d physical " TARGET_FMT_plx - " prot %d\n", __func__, address, ret, pa, prot); + "%s address=3D%" VADDR_PRIx " ret %d physical " TARGET_F= MT_plx + " prot %d\n", __func__, address, ret, pa, prot); + if (riscv_feature(env, RISCV_FEATURE_PMP) && - !pmp_hart_has_privs(env, pa, TARGET_PAGE_SIZE, 1 << rw)) { + !pmp_hart_has_privs(env, pa, TARGET_PAGE_SIZE, 1 << access_type)) { ret =3D TRANSLATE_FAIL; } if (ret =3D=3D TRANSLATE_SUCCESS) { tlb_set_page(cs, address & TARGET_PAGE_MASK, pa & TARGET_PAGE_MASK, prot, mmu_idx, TARGET_PAGE_SIZE); - } else if (ret =3D=3D TRANSLATE_FAIL) { - raise_mmu_exception(env, address, rw); + return true; + } else if (probe) { + return false; + } else { + raise_mmu_exception(env, address, access_type); + riscv_raise_exception(env, cs->exception_index, retaddr); } #else - switch (rw) { + switch (access_type) { case MMU_INST_FETCH: cs->exception_index =3D RISCV_EXCP_INST_PAGE_FAULT; break; @@ -436,8 +432,8 @@ int riscv_cpu_handle_mmu_fault(CPUState *cs, vaddr addr= ess, int size, cs->exception_index =3D RISCV_EXCP_STORE_PAGE_FAULT; break; } + cpu_loop_exit_restore(cs, retaddr); #endif - return ret; } =20 /* --=20 2.17.1 From nobody Mon May 6 12:42:50 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1557442157; cv=none; d=zoho.com; s=zohoarc; b=oSBx5fngkdVdQyPSfa+iam7Z3mzSQ8KqkX4bjY5gHHcGJ4q3ECTcfn2IshXeNWY4+CW/b/KRbtvuMFWa3IEGzRoFJHdJzd12qMGvQ73GtzjQbmrNUdZLs1YvGPSdR3zAXgZA2rnGiLN7R3Wulcj5VSK8n5QF4cYJLvhvEBWTt7c= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1557442157; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; 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X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH v3 18/27] target/s390x: Convert to CPUClass::tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-s390x@nongnu.org, Cornelia Huck Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Cc: qemu-s390x@nongnu.org Cc: Cornelia Huck Reviewed-by: David Hildenbrand Signed-off-by: Richard Henderson --- v2: Keep user-only and system tlb_fill separate. --- target/s390x/internal.h | 5 +-- target/s390x/cpu.c | 5 ++- target/s390x/excp_helper.c | 73 ++++++++++++++++++++++++++------------ target/s390x/mem_helper.c | 16 --------- 4 files changed, 55 insertions(+), 44 deletions(-) diff --git a/target/s390x/internal.h b/target/s390x/internal.h index 26575f2130..56534b38e0 100644 --- a/target/s390x/internal.h +++ b/target/s390x/internal.h @@ -263,8 +263,9 @@ ObjectClass *s390_cpu_class_by_name(const char *name); void s390x_cpu_debug_excp_handler(CPUState *cs); void s390_cpu_do_interrupt(CPUState *cpu); bool s390_cpu_exec_interrupt(CPUState *cpu, int int_req); -int s390_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int = rw, - int mmu_idx); +bool s390_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); void s390x_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr); diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index b58ef0a8ef..e28939032b 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -478,9 +478,8 @@ static void s390_cpu_class_init(ObjectClass *oc, void *= data) cc->set_pc =3D s390_cpu_set_pc; cc->gdb_read_register =3D s390_cpu_gdb_read_register; cc->gdb_write_register =3D s390_cpu_gdb_write_register; -#ifdef CONFIG_USER_ONLY - cc->handle_mmu_fault =3D s390_cpu_handle_mmu_fault; -#else + cc->tlb_fill =3D s390_cpu_tlb_fill; +#ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D s390_cpu_get_phys_page_debug; cc->vmsd =3D &vmstate_s390_cpu; cc->write_elf64_note =3D s390_cpu_write_elf64_note; diff --git a/target/s390x/excp_helper.c b/target/s390x/excp_helper.c index f84bfb1284..a4e134bcab 100644 --- a/target/s390x/excp_helper.c +++ b/target/s390x/excp_helper.c @@ -74,8 +74,9 @@ void s390_cpu_do_interrupt(CPUState *cs) cs->exception_index =3D -1; } =20 -int s390_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, - int rw, int mmu_idx) +bool s390_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) { S390CPU *cpu =3D S390_CPU(cs); =20 @@ -83,7 +84,7 @@ int s390_cpu_handle_mmu_fault(CPUState *cs, vaddr address= , int size, /* On real machines this value is dropped into LowMem. Since this is userland, simply put this someplace that cpu_loop can find it. = */ cpu->env.__excp_addr =3D address; - return 1; + cpu_loop_exit_restore(cs, retaddr); } =20 #else /* !CONFIG_USER_ONLY */ @@ -102,19 +103,20 @@ static inline uint64_t cpu_mmu_idx_to_asc(int mmu_idx) } } =20 -int s390_cpu_handle_mmu_fault(CPUState *cs, vaddr orig_vaddr, int size, - int rw, int mmu_idx) +bool s390_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) { S390CPU *cpu =3D S390_CPU(cs); CPUS390XState *env =3D &cpu->env; target_ulong vaddr, raddr; uint64_t asc; - int prot; + int prot, fail; =20 qemu_log_mask(CPU_LOG_MMU, "%s: addr 0x%" VADDR_PRIx " rw %d mmu_idx %= d\n", - __func__, orig_vaddr, rw, mmu_idx); + __func__, address, access_type, mmu_idx); =20 - vaddr =3D orig_vaddr; + vaddr =3D address; =20 if (mmu_idx < MMU_REAL_IDX) { asc =3D cpu_mmu_idx_to_asc(mmu_idx); @@ -122,39 +124,64 @@ int s390_cpu_handle_mmu_fault(CPUState *cs, vaddr ori= g_vaddr, int size, if (!(env->psw.mask & PSW_MASK_64)) { vaddr &=3D 0x7fffffff; } - if (mmu_translate(env, vaddr, rw, asc, &raddr, &prot, true)) { - return 1; - } + fail =3D mmu_translate(env, vaddr, access_type, asc, &raddr, &prot= , true); } else if (mmu_idx =3D=3D MMU_REAL_IDX) { /* 31-Bit mode */ if (!(env->psw.mask & PSW_MASK_64)) { vaddr &=3D 0x7fffffff; } - if (mmu_translate_real(env, vaddr, rw, &raddr, &prot)) { - return 1; - } + fail =3D mmu_translate_real(env, vaddr, access_type, &raddr, &prot= ); } else { - abort(); + g_assert_not_reached(); } =20 /* check out of RAM access */ - if (!address_space_access_valid(&address_space_memory, raddr, - TARGET_PAGE_SIZE, rw, + if (!fail && + !address_space_access_valid(&address_space_memory, raddr, + TARGET_PAGE_SIZE, access_type, MEMTXATTRS_UNSPECIFIED)) { qemu_log_mask(CPU_LOG_MMU, "%s: raddr %" PRIx64 " > ram_size %" PRIx64 "\n", __func__, (uint64_t)raddr, (uint64_t)ram_size); trigger_pgm_exception(env, PGM_ADDRESSING, ILEN_AUTO); - return 1; + fail =3D 1; } =20 - qemu_log_mask(CPU_LOG_MMU, "%s: set tlb %" PRIx64 " -> %" PRIx64 " (%x= )\n", - __func__, (uint64_t)vaddr, (uint64_t)raddr, prot); + if (!fail) { + qemu_log_mask(CPU_LOG_MMU, + "%s: set tlb %" PRIx64 " -> %" PRIx64 " (%x)\n", + __func__, (uint64_t)vaddr, (uint64_t)raddr, prot); + tlb_set_page(cs, address & TARGET_PAGE_MASK, raddr, prot, + mmu_idx, TARGET_PAGE_SIZE); + return true; + } + if (probe) { + return false; + } =20 - tlb_set_page(cs, orig_vaddr & TARGET_PAGE_MASK, raddr, prot, - mmu_idx, TARGET_PAGE_SIZE); + cpu_restore_state(cs, retaddr, true); =20 - return 0; + /* + * The ILC value for code accesses is undefined. The important + * thing here is to *not* leave env->int_pgm_ilen set to ILEN_AUTO, + * which would cause do_program_interrupt to attempt to read from + * env->psw.addr again. C.f. the condition in trigger_page_fault, + * but is not universally applied. + * + * ??? If we remove ILEN_AUTO, by moving the computation of ILEN + * into cpu_restore_state, then we may remove this entirely. + */ + if (access_type =3D=3D MMU_INST_FETCH) { + env->int_pgm_ilen =3D 2; + } + + cpu_loop_exit(cs); +} + +void tlb_fill(CPUState *cs, target_ulong addr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) +{ + s390_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr= ); } =20 static void do_program_interrupt(CPUS390XState *env) diff --git a/target/s390x/mem_helper.c b/target/s390x/mem_helper.c index 3f76a8abfd..ffd5f02fbe 100644 --- a/target/s390x/mem_helper.c +++ b/target/s390x/mem_helper.c @@ -33,22 +33,6 @@ =20 /*************************************************************************= ****/ /* Softmmu support */ -#if !defined(CONFIG_USER_ONLY) - -/* try to fill the TLB and return an exception if error. If retaddr is - NULL, it means that the function was called in C code (i.e. not - from generated code or from helper.c) */ -/* XXX: fix it to restore all registers */ -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - int ret =3D s390_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu= _idx); - if (unlikely(ret !=3D 0)) { - cpu_loop_exit_restore(cs, retaddr); - } -} - -#endif =20 /* #define DEBUG_HELPER */ #ifdef DEBUG_HELPER --=20 2.17.1 From nobody Mon May 6 12:42:50 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1557441341; cv=none; d=zoho.com; s=zohoarc; b=YeDZ/YLDIZNMBooioGdlhuGJznd735fQHulZWZFIXuLcAKTfjB9FlUpASbuY61N4+FX4Azg41y+dornW9Kfl2jLVmoIyw2N4kYIed5ZMVXWk/6mRMuxr/h2HJBiuDs6N7sGFOdbuRjoSjtJQzqYA4pbJ6bLNcD5t/TDpa6D6or4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1557441341; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=13zPpr8eu2CJQOgqlDgYW1euE5CjP18/vmWEohkbXwc=; b=cgJsU+BNXgDCWpFU3Ho2yfH+S1Zx2SI2X87CibUFfkwWoVpEfGyHTExIp5jKZa9saSGRRuc4/T34ebsq7UjAI/2PnB01nceGV+2HOLmJ+g6x0LpZznx3FIKdc/753UG2w6kAg9b3fnUfFrJZPgxldP9UL3uHtY4osWyWLHwpRno= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1557441341951193.55440088117302; Thu, 9 May 2019 15:35:41 -0700 (PDT) Received: from localhost ([127.0.0.1]:33533 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hOrdW-0006hv-P1 for importer@patchew.org; Thu, 09 May 2019 18:35:34 -0400 Received: from eggs.gnu.org ([209.51.188.92]:33142) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hOrVJ-0007vf-AU for qemu-devel@nongnu.org; Thu, 09 May 2019 18:27:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hOrVG-0005ag-7L for qemu-devel@nongnu.org; Thu, 09 May 2019 18:27:05 -0400 Received: from mail-pl1-x641.google.com ([2607:f8b0:4864:20::641]:42882) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hOrVE-0005Zy-AS for qemu-devel@nongnu.org; Thu, 09 May 2019 18:27:02 -0400 Received: by mail-pl1-x641.google.com with SMTP id x15so1799287pln.9 for ; Thu, 09 May 2019 15:27:00 -0700 (PDT) Received: from localhost.localdomain (97-113-13-231.tukw.qwest.net. [97.113.13.231]) by smtp.gmail.com with ESMTPSA id m2sm4490521pfi.24.2019.05.09.15.26.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 09 May 2019 15:26:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=13zPpr8eu2CJQOgqlDgYW1euE5CjP18/vmWEohkbXwc=; b=dO1yfP9HxFuzKXeCT+GQcDf1ZjAVtRQSKIyV6vEoFBGhr/HhJRsLwD9YtGY9vT5m9c NLAWBMaz9RxtsSgFlzLeL7w5o72sBO2kJh8qAq8VsAH6H54GvprU8Qzch1Evx25MITes WPmxnV7yNoOP+TSHTBMmDbKAYyLFGzA690Q389UK/NQGDK5GVKi0rWTSyMeKwwRIXvMO RAg8bSsH0bQEyMwsbpNrxMHQ7XydpJkiDMxB3D2kQtHaz7L8QtRBC3osPl7mfmzbRVzm 22pPXMDgHK0gm22kKqWSu+hehfJMJ/TX14r92yds9b++kSMekkHZoeuoOtDOB//w8EMm 4MHQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=13zPpr8eu2CJQOgqlDgYW1euE5CjP18/vmWEohkbXwc=; b=JwvOuxEIFM5+ICi2wxNyakT6oE+V2gJTH0t0sNfTCcqP5iVoi8PcTkqRpb5Y8vL0q+ hLldRr1ffCoFirBwJQtxF/FnNmyPSZQlLjoojDEl0PrjAdfZloyrFl4p6LSVtJveVwcU adWUweWo9tydTK5UqvMSSZ1gV2p7Bbjxc96v+PBUXRBC65kxV1I7W0QPKrDA9JrMB2wN yBPUAZo0ZxyNKvXV6myZHlwDvr0jpABqApjkdV4EIxT2n89weWnwua2TpSCRM/c6ZhFo PmtXI0baajuzFeHcMk625QyTHip7RGm95g4geeynuSBF+QXzm6r7jq/MQ8lT5jvFnV1a 2JEA== X-Gm-Message-State: APjAAAWMBFCl7EnQAbWDmiL/XPxRIpzOaA4bM8mMg0un5PQdQxso/f3l KA4yI6sqXPM7MoHmtuQb5orxcIm7eh8= X-Google-Smtp-Source: APXvYqzYBbBsIATBIYYQQYe1Akw3VOYMorJJXtnQwyqC+wBQ84UUhrV+tZwblnsvqlWT7FEwB7qEzQ== X-Received: by 2002:a17:902:2c01:: with SMTP id m1mr3748693plb.108.1557440818972; Thu, 09 May 2019 15:26:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 9 May 2019 15:26:23 -0700 Message-Id: <20190509222631.14271-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190509222631.14271-1-richard.henderson@linaro.org> References: <20190509222631.14271-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::641 Subject: [Qemu-devel] [PATCH v3 19/27] target/sh4: Convert to CPUClass::tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aurelien Jarno Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Cc: Aurelien Jarno Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/sh4/cpu.h | 5 +- target/sh4/cpu.c | 5 +- target/sh4/helper.c | 197 ++++++++++++++++++++--------------------- target/sh4/op_helper.c | 12 --- 4 files changed, 101 insertions(+), 118 deletions(-) diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index 1be36fe875..547194aac7 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -243,8 +243,9 @@ void superh_cpu_do_unaligned_access(CPUState *cpu, vadd= r addr, void sh4_translate_init(void); int cpu_sh4_signal_handler(int host_signum, void *pinfo, void *puc); -int superh_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, in= t rw, - int mmu_idx); +bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); =20 void sh4_cpu_list(void); #if !defined(CONFIG_USER_ONLY) diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index da2799082e..c4736a0a73 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -229,9 +229,8 @@ static void superh_cpu_class_init(ObjectClass *oc, void= *data) cc->synchronize_from_tb =3D superh_cpu_synchronize_from_tb; cc->gdb_read_register =3D superh_cpu_gdb_read_register; cc->gdb_write_register =3D superh_cpu_gdb_write_register; -#ifdef CONFIG_USER_ONLY - cc->handle_mmu_fault =3D superh_cpu_handle_mmu_fault; -#else + cc->tlb_fill =3D superh_cpu_tlb_fill; +#ifndef CONFIG_USER_ONLY cc->do_unaligned_access =3D superh_cpu_do_unaligned_access; cc->get_phys_page_debug =3D superh_cpu_get_phys_page_debug; #endif diff --git a/target/sh4/helper.c b/target/sh4/helper.c index fa51269fb1..1517a6152f 100644 --- a/target/sh4/helper.c +++ b/target/sh4/helper.c @@ -27,43 +27,6 @@ #include "hw/sh4/sh_intc.h" #endif =20 -#if defined(CONFIG_USER_ONLY) - -void superh_cpu_do_interrupt(CPUState *cs) -{ - cs->exception_index =3D -1; -} - -int superh_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int= rw, - int mmu_idx) -{ - SuperHCPU *cpu =3D SUPERH_CPU(cs); - CPUSH4State *env =3D &cpu->env; - - env->tea =3D address; - cs->exception_index =3D -1; - switch (rw) { - case 0: - cs->exception_index =3D 0x0a0; - break; - case 1: - cs->exception_index =3D 0x0c0; - break; - case 2: - cs->exception_index =3D 0x0a0; - break; - } - return 1; -} - -int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr) -{ - /* For user mode, only U0 area is cacheable. */ - return !(addr & 0x80000000); -} - -#else /* !CONFIG_USER_ONLY */ - #define MMU_OK 0 #define MMU_ITLB_MISS (-1) #define MMU_ITLB_MULTIPLE (-2) @@ -79,6 +42,21 @@ int cpu_sh4_is_cached(CPUSH4State * env, target_ulong ad= dr) #define MMU_DADDR_ERROR_READ (-12) #define MMU_DADDR_ERROR_WRITE (-13) =20 +#if defined(CONFIG_USER_ONLY) + +void superh_cpu_do_interrupt(CPUState *cs) +{ + cs->exception_index =3D -1; +} + +int cpu_sh4_is_cached(CPUSH4State *env, target_ulong addr) +{ + /* For user mode, only U0 area is cacheable. */ + return !(addr & 0x80000000); +} + +#else /* !CONFIG_USER_ONLY */ + void superh_cpu_do_interrupt(CPUState *cs) { SuperHCPU *cpu =3D SUPERH_CPU(cs); @@ -458,69 +436,6 @@ static int get_physical_address(CPUSH4State * env, tar= get_ulong * physical, return get_mmu_address(env, physical, prot, address, rw, access_type); } =20 -int superh_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int= rw, - int mmu_idx) -{ - SuperHCPU *cpu =3D SUPERH_CPU(cs); - CPUSH4State *env =3D &cpu->env; - target_ulong physical; - int prot, ret, access_type; - - access_type =3D ACCESS_INT; - ret =3D - get_physical_address(env, &physical, &prot, address, rw, - access_type); - - if (ret !=3D MMU_OK) { - env->tea =3D address; - if (ret !=3D MMU_DTLB_MULTIPLE && ret !=3D MMU_ITLB_MULTIPLE) { - env->pteh =3D (env->pteh & PTEH_ASID_MASK) | - (address & PTEH_VPN_MASK); - } - switch (ret) { - case MMU_ITLB_MISS: - case MMU_DTLB_MISS_READ: - cs->exception_index =3D 0x040; - break; - case MMU_DTLB_MULTIPLE: - case MMU_ITLB_MULTIPLE: - cs->exception_index =3D 0x140; - break; - case MMU_ITLB_VIOLATION: - cs->exception_index =3D 0x0a0; - break; - case MMU_DTLB_MISS_WRITE: - cs->exception_index =3D 0x060; - break; - case MMU_DTLB_INITIAL_WRITE: - cs->exception_index =3D 0x080; - break; - case MMU_DTLB_VIOLATION_READ: - cs->exception_index =3D 0x0a0; - break; - case MMU_DTLB_VIOLATION_WRITE: - cs->exception_index =3D 0x0c0; - break; - case MMU_IADDR_ERROR: - case MMU_DADDR_ERROR_READ: - cs->exception_index =3D 0x0e0; - break; - case MMU_DADDR_ERROR_WRITE: - cs->exception_index =3D 0x100; - break; - default: - cpu_abort(cs, "Unhandled MMU fault"); - } - return 1; - } - - address &=3D TARGET_PAGE_MASK; - physical &=3D TARGET_PAGE_MASK; - - tlb_set_page(cs, address, physical, prot, mmu_idx, TARGET_PAGE_SIZE); - return 0; -} - hwaddr superh_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) { SuperHCPU *cpu =3D SUPERH_CPU(cs); @@ -745,7 +660,6 @@ void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, hwa= ddr addr, if (needs_tlb_flush) { tlb_flush_page(CPU(sh_env_get_cpu(s)), vpn << 10); } - =20 } else { int index =3D (addr & 0x00003f00) >> 8; tlb_t * entry =3D &s->utlb[index]; @@ -885,3 +799,84 @@ bool superh_cpu_exec_interrupt(CPUState *cs, int inter= rupt_request) } return false; } + +bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) +{ + SuperHCPU *cpu =3D SUPERH_CPU(cs); + CPUSH4State *env =3D &cpu->env; + int ret; + +#ifdef CONFIG_USER_ONLY + ret =3D (access_type =3D=3D MMU_DATA_STORE ? MMU_DTLB_VIOLATION_WRITE : + access_type =3D=3D MMU_INST_FETCH ? MMU_ITLB_VIOLATION : + MMU_DTLB_VIOLATION_READ); +#else + target_ulong physical; + int prot, sh_access_type; + + sh_access_type =3D ACCESS_INT; + ret =3D get_physical_address(env, &physical, &prot, address, + access_type, sh_access_type); + + if (ret =3D=3D MMU_OK) { + address &=3D TARGET_PAGE_MASK; + physical &=3D TARGET_PAGE_MASK; + tlb_set_page(cs, address, physical, prot, mmu_idx, TARGET_PAGE_SIZ= E); + return true; + } + if (probe) { + return false; + } + + if (ret !=3D MMU_DTLB_MULTIPLE && ret !=3D MMU_ITLB_MULTIPLE) { + env->pteh =3D (env->pteh & PTEH_ASID_MASK) | (address & PTEH_VPN_M= ASK); + } +#endif + + env->tea =3D address; + switch (ret) { + case MMU_ITLB_MISS: + case MMU_DTLB_MISS_READ: + cs->exception_index =3D 0x040; + break; + case MMU_DTLB_MULTIPLE: + case MMU_ITLB_MULTIPLE: + cs->exception_index =3D 0x140; + break; + case MMU_ITLB_VIOLATION: + cs->exception_index =3D 0x0a0; + break; + case MMU_DTLB_MISS_WRITE: + cs->exception_index =3D 0x060; + break; + case MMU_DTLB_INITIAL_WRITE: + cs->exception_index =3D 0x080; + break; + case MMU_DTLB_VIOLATION_READ: + cs->exception_index =3D 0x0a0; + break; + case MMU_DTLB_VIOLATION_WRITE: + cs->exception_index =3D 0x0c0; + break; + case MMU_IADDR_ERROR: + case MMU_DADDR_ERROR_READ: + cs->exception_index =3D 0x0e0; + break; + case MMU_DADDR_ERROR_WRITE: + cs->exception_index =3D 0x100; + break; + default: + cpu_abort(cs, "Unhandled MMU fault"); + } + cpu_loop_exit_restore(cs, retaddr); +} + +#ifndef CONFIG_USER_ONLY +void tlb_fill(CPUState *cs, target_ulong addr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) +{ + superh_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retad= dr); +} +#endif diff --git a/target/sh4/op_helper.c b/target/sh4/op_helper.c index 28027f9e0b..bd5d782b50 100644 --- a/target/sh4/op_helper.c +++ b/target/sh4/op_helper.c @@ -41,18 +41,6 @@ void superh_cpu_do_unaligned_access(CPUState *cs, vaddr = addr, cpu_loop_exit_restore(cs, retaddr); } =20 -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - int ret; - - ret =3D superh_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu_i= dx); - if (ret) { - /* now we have a real cpu fault */ - cpu_loop_exit_restore(cs, retaddr); - } -} - #endif =20 void helper_ldtlb(CPUSH4State *env) --=20 2.17.1 From nobody Mon May 6 12:42:50 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1557442359; cv=none; d=zoho.com; s=zohoarc; b=WnSPtoSI1DHwfqLjwuTizL5saxRTIeZzY3J++2vEygL7kfmy408g6Lpi1IjzKRkSlm7iupZoK/1V3uAgDef+zQCQFqeWrsWYB/4EMdzKPHzSPS28o1SmAsCcQ8gCVODPJar8D1guDG7mAj6d80ZIm4u6P3+qE4oqe6YQJVDTLWU= ARC-Message-Signature: i=1; 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[97.113.13.231]) by smtp.gmail.com with ESMTPSA id m2sm4490521pfi.24.2019.05.09.15.26.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 09 May 2019 15:26:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Pawv8gVKgvIshmjx0BG7faLy+gIe8qsSKFcm+yZ5sy0=; b=QYz7CEJOpCCzIzxIaLaOuDxGP0wFO+2/A3mDz2zV5UgfJ0a67XZMfp1/M29q0YGbqt bHY43tPVk7tVNK1WfGnpRoZNrtqm+vkr0uN+ALnefC9V7Sf2EQjLw24tPrlKFmA9fSZb S/eMwwzy00sfZYeZAkMROtJ5223Po5QtWuH+qbZzz2USuwl6D5dx2Oo0B9dUOIFOFnBE 89yX2ErWgwgAOpY53dwBYnXpgXF9ZPA3mnVRin95tWhfBbwYbX6UIDyg+zt/bUWi0AXk 502KgQK/JFAhEbfF6RM7HiITK0+7lFL/tL1GoDZmYAO30H7UubVGf8Oas2GzrB14CZqf GbeA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Pawv8gVKgvIshmjx0BG7faLy+gIe8qsSKFcm+yZ5sy0=; b=d/A7D+foJMDjgKgUzO49cPk1aixF9BHlSXykWO/i8ir7o9p8Kw/ko2KXS4IW7bZuzi knmEaRwfHRNrtovjdDF7SxvHA/xAhlsoeRQQMNSkJXvTQp1k7eLpiLVTEP3YadfzQleX 1HQnpz/ZoY0+orjAuk78b7j8cAwDLPadQ+6CaaYfCfMCu7fblV2bWPxu5wE4gzP9SriD 5pFbIGI9Mc/kTXioRRvB+47wrflcsNZzEmyMkg35Iisdg7dnwxJWpZCNayrtn69ozjiO xH9iroG4SPbAiduVZEs+6bNMmaVW3ToBFsXtom5kk5KV6SsM+j/FZPEc3Mu/kapWN6H/ RliQ== X-Gm-Message-State: APjAAAXcWzX2f3MEpQGgGjoqiDOWQP/+isDIxZKaf3tvmuPnxu4VyRtc iPvp/NrPcXGszqftLzdMTv2IaYlObzc= X-Google-Smtp-Source: APXvYqw0XRoKqmFVU30O/46yqdYrRZrBm870OoFkBy08/0ahJezEilHkBiVddyk+SlhEk8gtyKdbWA== X-Received: by 2002:a17:902:704c:: with SMTP id h12mr8532139plt.270.1557440820301; Thu, 09 May 2019 15:27:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 9 May 2019 15:26:24 -0700 Message-Id: <20190509222631.14271-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190509222631.14271-1-richard.henderson@linaro.org> References: <20190509222631.14271-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::642 Subject: [Qemu-devel] [PATCH v3 20/27] target/sparc: Convert to CPUClass::tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Cave-Ayland , Artyom Tarasenko Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Cc: Artyom Tarasenko Cc: Mark Cave-Ayland Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- v2: Keep user-only, sparc32, and sparc64 tlb_fill separate. v3: Assert !probe for sparc32. --- target/sparc/cpu.h | 5 ++-- target/sparc/cpu.c | 5 ++-- target/sparc/ldst_helper.c | 11 +------- target/sparc/mmu_helper.c | 58 ++++++++++++++++++++++++-------------- 4 files changed, 43 insertions(+), 36 deletions(-) diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 85b9665ccc..f31e8535df 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -579,8 +579,9 @@ void cpu_raise_exception_ra(CPUSPARCState *, int, uintp= tr_t) QEMU_NORETURN; void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu); void sparc_cpu_list(void); /* mmu_helper.c */ -int sparc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int= rw, - int mmu_idx); +bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmule= v); void dump_mmu(CPUSPARCState *env); =20 diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 4654c2a6a0..f93ce72eb9 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -875,9 +875,8 @@ static void sparc_cpu_class_init(ObjectClass *oc, void = *data) cc->synchronize_from_tb =3D sparc_cpu_synchronize_from_tb; cc->gdb_read_register =3D sparc_cpu_gdb_read_register; cc->gdb_write_register =3D sparc_cpu_gdb_write_register; -#ifdef CONFIG_USER_ONLY - cc->handle_mmu_fault =3D sparc_cpu_handle_mmu_fault; -#else + cc->tlb_fill =3D sparc_cpu_tlb_fill; +#ifndef CONFIG_USER_ONLY cc->do_unassigned_access =3D sparc_cpu_unassigned_access; cc->do_unaligned_access =3D sparc_cpu_do_unaligned_access; cc->get_phys_page_debug =3D sparc_cpu_get_phys_page_debug; diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c index a7fcb84ac0..2558c08a64 100644 --- a/target/sparc/ldst_helper.c +++ b/target/sparc/ldst_helper.c @@ -1925,18 +1925,9 @@ void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPU= State *cs, vaddr addr, cpu_raise_exception_ra(env, TT_UNALIGNED, retaddr); } =20 -/* try to fill the TLB and return an exception if error. If retaddr is - NULL, it means that the function was called in C code (i.e. not - from generated code or from helper.c) */ -/* XXX: fix it to restore all registers */ void tlb_fill(CPUState *cs, target_ulong addr, int size, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) { - int ret; - - ret =3D sparc_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu_id= x); - if (ret) { - cpu_loop_exit_restore(cs, retaddr); - } + sparc_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retadd= r); } #endif diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index afcc5b617d..facc0c60e9 100644 --- a/target/sparc/mmu_helper.c +++ b/target/sparc/mmu_helper.c @@ -27,13 +27,14 @@ =20 #if defined(CONFIG_USER_ONLY) =20 -int sparc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int = rw, - int mmu_idx) +bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) { SPARCCPU *cpu =3D SPARC_CPU(cs); CPUSPARCState *env =3D &cpu->env; =20 - if (rw & 2) { + if (access_type =3D=3D MMU_INST_FETCH) { cs->exception_index =3D TT_TFAULT; } else { cs->exception_index =3D TT_DFAULT; @@ -43,7 +44,7 @@ int sparc_cpu_handle_mmu_fault(CPUState *cs, vaddr addres= s, int size, int rw, env->mmuregs[4] =3D address; #endif } - return 1; + cpu_loop_exit_restore(cs, retaddr); } =20 #else @@ -208,8 +209,9 @@ static int get_physical_address(CPUSPARCState *env, hwa= ddr *physical, } =20 /* Perform address translation */ -int sparc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int = rw, - int mmu_idx) +bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) { SPARCCPU *cpu =3D SPARC_CPU(cs); CPUSPARCState *env =3D &cpu->env; @@ -218,16 +220,26 @@ int sparc_cpu_handle_mmu_fault(CPUState *cs, vaddr ad= dress, int size, int rw, target_ulong page_size; int error_code =3D 0, prot, access_index; =20 + /* + * TODO: If we ever need tlb_vaddr_to_host for this target, + * then we must figure out how to manipulate FSR and FAR + * when both MMU_NF and probe are set. In the meantime, + * do not support this use case. + */ + assert(!probe); + address &=3D TARGET_PAGE_MASK; error_code =3D get_physical_address(env, &paddr, &prot, &access_index, - address, rw, mmu_idx, &page_size); + address, access_type, + mmu_idx, &page_size); vaddr =3D address; - if (error_code =3D=3D 0) { + if (likely(error_code =3D=3D 0)) { qemu_log_mask(CPU_LOG_MMU, - "Translate at %" VADDR_PRIx " -> " TARGET_FMT_plx ", vaddr= " - TARGET_FMT_lx "\n", address, paddr, vaddr); + "Translate at %" VADDR_PRIx " -> " + TARGET_FMT_plx ", vaddr " TARGET_FMT_lx "\n", + address, paddr, vaddr); tlb_set_page(cs, vaddr, paddr, prot, mmu_idx, page_size); - return 0; + return true; } =20 if (env->mmuregs[3]) { /* Fault status register */ @@ -243,14 +255,14 @@ int sparc_cpu_handle_mmu_fault(CPUState *cs, vaddr ad= dress, int size, int rw, switching to normal mode. */ prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; tlb_set_page(cs, vaddr, paddr, prot, mmu_idx, TARGET_PAGE_SIZE); - return 0; + return true; } else { - if (rw & 2) { + if (access_type =3D=3D MMU_INST_FETCH) { cs->exception_index =3D TT_TFAULT; } else { cs->exception_index =3D TT_DFAULT; } - return 1; + cpu_loop_exit_restore(cs, retaddr); } } =20 @@ -713,8 +725,9 @@ static int get_physical_address(CPUSPARCState *env, hwa= ddr *physical, } =20 /* Perform address translation */ -int sparc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int = rw, - int mmu_idx) +bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) { SPARCCPU *cpu =3D SPARC_CPU(cs); CPUSPARCState *env =3D &cpu->env; @@ -725,8 +738,9 @@ int sparc_cpu_handle_mmu_fault(CPUState *cs, vaddr addr= ess, int size, int rw, =20 address &=3D TARGET_PAGE_MASK; error_code =3D get_physical_address(env, &paddr, &prot, &access_index, - address, rw, mmu_idx, &page_size); - if (error_code =3D=3D 0) { + address, access_type, + mmu_idx, &page_size); + if (likely(error_code =3D=3D 0)) { vaddr =3D address; =20 trace_mmu_helper_mmu_fault(address, paddr, mmu_idx, env->tl, @@ -734,10 +748,12 @@ int sparc_cpu_handle_mmu_fault(CPUState *cs, vaddr ad= dress, int size, int rw, env->dmmu.mmu_secondary_context); =20 tlb_set_page(cs, vaddr, paddr, prot, mmu_idx, page_size); - return 0; + return true; } - /* XXX */ - return 1; + if (probe) { + return false; + } + cpu_loop_exit_restore(cs, retaddr); } =20 void dump_mmu(CPUSPARCState *env) --=20 2.17.1 From nobody Mon May 6 12:42:50 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; 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X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH v3 21/27] target/tilegx: Convert to CPUClass::tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/tilegx/cpu.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/target/tilegx/cpu.c b/target/tilegx/cpu.c index b9d37105fa..b209c55387 100644 --- a/target/tilegx/cpu.c +++ b/target/tilegx/cpu.c @@ -25,6 +25,7 @@ #include "hw/qdev-properties.h" #include "linux-user/syscall_defs.h" #include "qemu/qemu-print.h" +#include "exec/exec-all.h" =20 static void tilegx_cpu_dump_state(CPUState *cs, FILE *f, int flags) { @@ -111,8 +112,9 @@ static void tilegx_cpu_do_interrupt(CPUState *cs) cs->exception_index =3D -1; } =20 -static int tilegx_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int si= ze, - int rw, int mmu_idx) +static bool tilegx_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) { TileGXCPU *cpu =3D TILEGX_CPU(cs); =20 @@ -122,7 +124,7 @@ static int tilegx_cpu_handle_mmu_fault(CPUState *cs, va= ddr address, int size, cpu->env.signo =3D TARGET_SIGSEGV; cpu->env.sigcode =3D 0; =20 - return 1; + cpu_loop_exit_restore(cs, retaddr); } =20 static bool tilegx_cpu_exec_interrupt(CPUState *cs, int interrupt_request) @@ -152,7 +154,7 @@ static void tilegx_cpu_class_init(ObjectClass *oc, void= *data) cc->cpu_exec_interrupt =3D tilegx_cpu_exec_interrupt; cc->dump_state =3D tilegx_cpu_dump_state; cc->set_pc =3D tilegx_cpu_set_pc; - cc->handle_mmu_fault =3D tilegx_cpu_handle_mmu_fault; + cc->tlb_fill =3D tilegx_cpu_tlb_fill; cc->gdb_num_core_regs =3D 0; cc->tcg_initialize =3D tilegx_tcg_init; } --=20 2.17.1 From nobody Mon May 6 12:42:50 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1557441521; cv=none; d=zoho.com; s=zohoarc; b=g4eDIVDiD/+x/NaKwURt9WfIZzCVAxibmf370ua34t1ujltCW3WKJ1RrKFJyVBxljJD2qpe3nuN+TfRzf+nD1S380R8P/7zrvC/km2tDWAxJId80KJk01+U2O2R5acGbR5JxBlLDCdHe14oCv6bLjcxCZ0uZiSvPTxvHWt0wjO8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1557441521; h=Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=m8b1TfwrtSp/bIRpBWvKs+DLGDtPKUANT8NhwLlWDyg=; b=T9BIAllduZgPIhnlnYpgXRbT76++VJoMnsam7NNqypR0oTNmQAm6q6H+iEJOMUQz9bOxQ/AwoUP7gCxvC9EgZIJcYnS8RFpG+VwcpFSGF9ND9QRyenuY4Y0mxBURfbOtS+4D9DesbgkFmJyogFjQyR1bvcCGf+zlZI6ROKsXrRM= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1557441521825428.7046065311363; Thu, 9 May 2019 15:38:41 -0700 (PDT) Received: from localhost ([127.0.0.1]:33591 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hOrgU-0001Jz-Mu for importer@patchew.org; Thu, 09 May 2019 18:38:38 -0400 Received: from eggs.gnu.org ([209.51.188.92]:33174) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hOrVK-0007w7-Iv for qemu-devel@nongnu.org; Thu, 09 May 2019 18:27:07 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hOrVJ-0005bs-C5 for qemu-devel@nongnu.org; Thu, 09 May 2019 18:27:06 -0400 Received: from mail-pf1-x443.google.com ([2607:f8b0:4864:20::443]:35319) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hOrVJ-0005az-53 for qemu-devel@nongnu.org; Thu, 09 May 2019 18:27:05 -0400 Received: by mail-pf1-x443.google.com with SMTP id t87so2057394pfa.2 for ; Thu, 09 May 2019 15:27:03 -0700 (PDT) Received: from localhost.localdomain (97-113-13-231.tukw.qwest.net. [97.113.13.231]) by smtp.gmail.com with ESMTPSA id m2sm4490521pfi.24.2019.05.09.15.27.01 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 09 May 2019 15:27:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=m8b1TfwrtSp/bIRpBWvKs+DLGDtPKUANT8NhwLlWDyg=; b=jWLDyA5jMLjv47uzbhTxFJ8YDNqF6mf9PAjZqLZtjOH3TiwiGTSXPFc1VjYICmakaE yk64kaPBMxJmjaVMCeL4Hkv4aUEk8bpCLBV8fNdVNoD5KsneOaapktLuyRhOLMdTVtym N/nIzo+6hWTRzWf1bQdfPyyDpDJVkk9DEjMMPYR7ctvVIpA7M6qGAemtJ8c3pHtF1zoq RmiHWym3PnR4PDv/kEgar/hgj715yFB+Yg0w1YtopBa4KJZdG56QoJ9qKDEKDymdzUap UiC9jLD89aF+I8KNfOtzKvsEtipmXAOus0TuTRcnS95LpJd/iEHdEyjO0vTaRG7yIu6L td1g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=m8b1TfwrtSp/bIRpBWvKs+DLGDtPKUANT8NhwLlWDyg=; b=qvMOylUFXDeCNDmRkACuSb6gZYNw9MKN/P5b2zdXTErojEGujQ5r+UJr+ow9KcmXgy j0ja7/4gR4Vatb7gJEdXRdYXrI9Wxy9wibgJG+OJpp14MpbYINZUWYMqlbdIZbATffCY m5fk019deSLHiwAGK/vqMJCKypxEi8e+QGmDQpJWly6cxcn3MJ+E5E8vIbxwyq5onbUC kIEmU2sLv5l3i8EiEMvdcju2HNDNKL/XY8CdJMFYOM9IGqBM+mC6Mzb5osYc9/5StR5e 4VJihL9Eab8j3z0XtC9r+ddTNag6ECaQQMoa1sDYDZ4/v+nOi327qQn8hPlwwbhNEG0j OKUw== X-Gm-Message-State: APjAAAWz3OojHEhxE4dMoe8sPBgWir6jT6po2YdIY+zp1TGeveV879GN AHl4bQtnagW0umXM6fAISGHC++7PUC4= X-Google-Smtp-Source: APXvYqx495eEHIy8Bo02eR0SuiFG1U/h8/JOgxaco6TNq2To0KHv7mNkKibqmAY67SXw+vR9X/Nq5Q== X-Received: by 2002:a65:5845:: with SMTP id s5mr8910438pgr.286.1557440822826; Thu, 09 May 2019 15:27:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 9 May 2019 15:26:26 -0700 Message-Id: <20190509222631.14271-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190509222631.14271-1-richard.henderson@linaro.org> References: <20190509222631.14271-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::443 Subject: [Qemu-devel] [PATCH v3 22/27] target/tricore: Convert to CPUClass::tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Acked-by: Bastian Koppelmann Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/tricore/cpu.h | 6 +++--- target/tricore/cpu.c | 1 + target/tricore/helper.c | 27 +++++++++++++++++++-------- target/tricore/op_helper.c | 26 -------------------------- 4 files changed, 23 insertions(+), 37 deletions(-) diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h index 64d1a9c75e..287f4328a3 100644 --- a/target/tricore/cpu.h +++ b/target/tricore/cpu.h @@ -417,8 +417,8 @@ static inline void cpu_get_tb_cpu_state(CPUTriCoreState= *env, target_ulong *pc, #define CPU_RESOLVING_TYPE TYPE_TRICORE_CPU =20 /* helpers.c */ -int cpu_tricore_handle_mmu_fault(CPUState *cpu, target_ulong address, - int rw, int mmu_idx); -#define cpu_handle_mmu_fault cpu_tricore_handle_mmu_fault +bool tricore_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); =20 #endif /* TRICORE_CPU_H */ diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index e8d37e4040..ea1199d27e 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -166,6 +166,7 @@ static void tricore_cpu_class_init(ObjectClass *c, void= *data) cc->synchronize_from_tb =3D tricore_cpu_synchronize_from_tb; cc->get_phys_page_attrs_debug =3D tricore_cpu_get_phys_page_attrs_debu= g; cc->tcg_initialize =3D tricore_tcg_init; + cc->tlb_fill =3D tricore_cpu_tlb_fill; } =20 #define DEFINE_TRICORE_CPU_TYPE(cpu_model, initfn) \ diff --git a/target/tricore/helper.c b/target/tricore/helper.c index 78ee87c9ea..ed184fee3a 100644 --- a/target/tricore/helper.c +++ b/target/tricore/helper.c @@ -50,8 +50,9 @@ static void raise_mmu_exception(CPUTriCoreState *env, tar= get_ulong address, { } =20 -int cpu_tricore_handle_mmu_fault(CPUState *cs, target_ulong address, - int rw, int mmu_idx) +bool tricore_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType rw, int mmu_idx, + bool probe, uintptr_t retaddr) { TriCoreCPU *cpu =3D TRICORE_CPU(cs); CPUTriCoreState *env =3D &cpu->env; @@ -64,20 +65,30 @@ int cpu_tricore_handle_mmu_fault(CPUState *cs, target_u= long address, access_type =3D ACCESS_INT; ret =3D get_physical_address(env, &physical, &prot, address, rw, access_type); - qemu_log_mask(CPU_LOG_MMU, "%s address=3D" TARGET_FMT_lx " ret %d phys= ical " TARGET_FMT_plx - " prot %d\n", __func__, address, ret, physical, prot); + + qemu_log_mask(CPU_LOG_MMU, "%s address=3D" TARGET_FMT_lx " ret %d phys= ical " + TARGET_FMT_plx " prot %d\n", + __func__, (target_ulong)address, ret, physical, prot); =20 if (ret =3D=3D TLBRET_MATCH) { tlb_set_page(cs, address & TARGET_PAGE_MASK, physical & TARGET_PAGE_MASK, prot | PAGE_EXEC, mmu_idx, TARGET_PAGE_SIZE); - ret =3D 0; - } else if (ret < 0) { + return true; + } else { + assert(ret < 0); + if (probe) { + return false; + } raise_mmu_exception(env, address, rw, ret); - ret =3D 1; + cpu_loop_exit_restore(cs, retaddr); } +} =20 - return ret; +void tlb_fill(CPUState *cs, target_ulong addr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) +{ + tricore_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, reta= ddr); } =20 static void tricore_cpu_list_entry(gpointer data, gpointer user_data) diff --git a/target/tricore/op_helper.c b/target/tricore/op_helper.c index ed9dc0c83e..601e92f92a 100644 --- a/target/tricore/op_helper.c +++ b/target/tricore/op_helper.c @@ -2793,29 +2793,3 @@ uint32_t helper_psw_read(CPUTriCoreState *env) { return psw_read(env); } - - -static inline void QEMU_NORETURN do_raise_exception_err(CPUTriCoreState *e= nv, - uint32_t exception, - int error_code, - uintptr_t pc) -{ - CPUState *cs =3D CPU(tricore_env_get_cpu(env)); - cs->exception_index =3D exception; - env->error_code =3D error_code; - /* now we have a real cpu fault */ - cpu_loop_exit_restore(cs, pc); -} - -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - int ret; - ret =3D cpu_tricore_handle_mmu_fault(cs, addr, access_type, mmu_idx); - if (ret) { - TriCoreCPU *cpu =3D TRICORE_CPU(cs); - CPUTriCoreState *env =3D &cpu->env; - do_raise_exception_err(env, cs->exception_index, - env->error_code, retaddr); - } -} --=20 2.17.1 From nobody Mon May 6 12:42:50 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1557441855; cv=none; d=zoho.com; s=zohoarc; b=H14Grcavr6v8jZrhAatwkFWV2j8jGX0faOQr9aAYP7UVkjZ7JDzCtF0o7S8RngBKBllUpVM8w5/oPtt4t9djZ2akupGAS6DN/srhxzDFXU/csiENGMF4Qm6k3R0OwQDHXS8oM+d17ld2aLEfIcw8jOq5mRHrJBfIr6jM1AVTovU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1557441855; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; 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[97.113.13.231]) by smtp.gmail.com with ESMTPSA id m2sm4490521pfi.24.2019.05.09.15.27.03 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 09 May 2019 15:27:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=LTrRBAzo3ZXhs7/OIQshe/0vUKzYgpD3ylIgF8SzGa8=; b=cF+grQo68Bk3UiRIPZiIGyy8MYaUpqaiNh9SDWNHZv6q/2IcdRSQLapaQl3GMeRPL+ 5oiL1cEsHlBSjudZVvZtG2Fu6utCOK2+Jl3dRx9DoXgHY35WT4Lb13JopQH4TYf1yep4 nmlypSkZ8Ga5hYM0yWxEWZcy7LaovC6X8Qe3lNy/HJwRIOaFfx/Z4f104otmVjH1RRgg Rzs3Iz4nStxa9Y/ifkA5wrn4bqYd4EY/0vdBl+e1lO5OQ5tjcvipi+WjdhJQL48TYwVR nKzxcqsTxKxzRORdlCqhFjmL+aXG5e3jRbrs0uR8Cb5RH3MoUVKyM9kgS/mRgBWulBPJ GaBQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=LTrRBAzo3ZXhs7/OIQshe/0vUKzYgpD3ylIgF8SzGa8=; b=H7EcC/NH64S/SWVjqnHiRxul8pWC/0++zjvy3ymliPNiVmfmiTJvECqftkaWXWg5Bx zzq5FIZLfEyx+Qv0WcFS23xVoBXZtx8jpRo3YzYKR152bIrxxgkDEj5LEAWJDrj9PVd9 a/df+r9chLCs7Ou2K9sgwppmtpsvrvLP6WYrP3GzQe4i9u0eRkVZzcQ0smE2w42xr5Wp 4Q+u/7NTszXJHZ2G19iu7hlbBCANy51V5Xba04Xd0M6lHYihpKhVs/fSCOgfF1EHTsme 1BhkIJx11cCZvOJ4FmYuYVfkmJIyI06IWKQBK8dUIDtUFrgrxGPj1yqef8vRcdyrnjb/ Yojw== X-Gm-Message-State: APjAAAXC1yf8mNxCAf6oD45TkLYfuNhyF5nb6PXvtfIS/FVASVcwh9Fe me8cKM71Rwtp62n+XtEW4ui2ZXgKCgU= X-Google-Smtp-Source: APXvYqwo0VvdNraOqqym9N01PNnXRNvhNTHXv1xikrQAS5SicN8mnlx4dxEiU6vuPRTspg/HGRmtHw== X-Received: by 2002:a65:48ca:: with SMTP id o10mr9091642pgs.136.1557440824221; Thu, 09 May 2019 15:27:04 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 9 May 2019 15:26:27 -0700 Message-Id: <20190509222631.14271-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190509222631.14271-1-richard.henderson@linaro.org> References: <20190509222631.14271-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::542 Subject: [Qemu-devel] [PATCH v3 23/27] target/unicore32: Convert to CPUClass::tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Guan Xuetao Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Remove the user-only functions, as we no longer have a user-only config. Cc: Guan Xuetao Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/unicore32/cpu.h | 5 +++-- target/unicore32/cpu.c | 5 +---- target/unicore32/helper.c | 23 ----------------------- target/unicore32/op_helper.c | 14 -------------- target/unicore32/softmmu.c | 19 +++++++++++++++---- 5 files changed, 19 insertions(+), 47 deletions(-) diff --git a/target/unicore32/cpu.h b/target/unicore32/cpu.h index 24abe5e5c0..f052ee08bf 100644 --- a/target/unicore32/cpu.h +++ b/target/unicore32/cpu.h @@ -178,8 +178,9 @@ static inline void cpu_get_tb_cpu_state(CPUUniCore32Sta= te *env, target_ulong *pc } } =20 -int uc32_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int = rw, - int mmu_idx); +bool uc32_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); void uc32_translate_init(void); void switch_mode(CPUUniCore32State *, int); =20 diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c index 2b49d1ca40..3f57c508a0 100644 --- a/target/unicore32/cpu.c +++ b/target/unicore32/cpu.c @@ -138,11 +138,8 @@ static void uc32_cpu_class_init(ObjectClass *oc, void = *data) cc->cpu_exec_interrupt =3D uc32_cpu_exec_interrupt; cc->dump_state =3D uc32_cpu_dump_state; cc->set_pc =3D uc32_cpu_set_pc; -#ifdef CONFIG_USER_ONLY - cc->handle_mmu_fault =3D uc32_cpu_handle_mmu_fault; -#else + cc->tlb_fill =3D uc32_cpu_tlb_fill; cc->get_phys_page_debug =3D uc32_cpu_get_phys_page_debug; -#endif cc->tcg_initialize =3D uc32_translate_init; dc->vmsd =3D &vmstate_uc32_cpu; } diff --git a/target/unicore32/helper.c b/target/unicore32/helper.c index a5ff2ddb74..0d4914b48d 100644 --- a/target/unicore32/helper.c +++ b/target/unicore32/helper.c @@ -215,29 +215,6 @@ void helper_cp1_putc(target_ulong x) } #endif =20 -#ifdef CONFIG_USER_ONLY -void switch_mode(CPUUniCore32State *env, int mode) -{ - UniCore32CPU *cpu =3D uc32_env_get_cpu(env); - - if (mode !=3D ASR_MODE_USER) { - cpu_abort(CPU(cpu), "Tried to switch out of user mode\n"); - } -} - -void uc32_cpu_do_interrupt(CPUState *cs) -{ - cpu_abort(cs, "NO interrupt in user mode\n"); -} - -int uc32_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, - int access_type, int mmu_idx) -{ - cpu_abort(cs, "NO mmu fault in user mode\n"); - return 1; -} -#endif - bool uc32_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { if (interrupt_request & CPU_INTERRUPT_HARD) { diff --git a/target/unicore32/op_helper.c b/target/unicore32/op_helper.c index e0a15882d3..797ba60dc9 100644 --- a/target/unicore32/op_helper.c +++ b/target/unicore32/op_helper.c @@ -242,17 +242,3 @@ uint32_t HELPER(ror_cc)(CPUUniCore32State *env, uint32= _t x, uint32_t i) return ((uint32_t)x >> shift) | (x << (32 - shift)); } } - -#ifndef CONFIG_USER_ONLY -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - int ret; - - ret =3D uc32_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu_idx= ); - if (unlikely(ret)) { - /* now we have a real cpu fault */ - cpu_loop_exit_restore(cs, retaddr); - } -} -#endif diff --git a/target/unicore32/softmmu.c b/target/unicore32/softmmu.c index 00c7e0d028..13678df4d7 100644 --- a/target/unicore32/softmmu.c +++ b/target/unicore32/softmmu.c @@ -215,8 +215,9 @@ do_fault: return code; } =20 -int uc32_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, - int access_type, int mmu_idx) +bool uc32_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) { UniCore32CPU *cpu =3D UNICORE32_CPU(cs); CPUUniCore32State *env =3D &cpu->env; @@ -257,7 +258,11 @@ int uc32_cpu_handle_mmu_fault(CPUState *cs, vaddr addr= ess, int size, phys_addr &=3D TARGET_PAGE_MASK; address &=3D TARGET_PAGE_MASK; tlb_set_page(cs, address, phys_addr, prot, mmu_idx, page_size); - return 0; + return true; + } + + if (probe) { + return false; } =20 env->cp0.c3_faultstatus =3D ret; @@ -267,7 +272,13 @@ int uc32_cpu_handle_mmu_fault(CPUState *cs, vaddr addr= ess, int size, } else { cs->exception_index =3D UC32_EXCP_DTRAP; } - return ret; + cpu_loop_exit_restore(cs, retaddr); +} + +void tlb_fill(CPUState *cs, target_ulong addr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) +{ + uc32_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr= ); 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X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH v3 24/27] target/xtensa: Convert to CPUClass::tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Max Filippov Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Cc: Max Filippov Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v2: Keep user-only and system tlb_fill separate. --- target/xtensa/cpu.h | 5 +++-- target/xtensa/cpu.c | 5 ++--- target/xtensa/helper.c | 39 ++++++++++++++++++++++++++------------- 3 files changed, 31 insertions(+), 18 deletions(-) diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 5d23e1345b..68d89f8faf 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -552,8 +552,9 @@ static inline XtensaCPU *xtensa_env_get_cpu(const CPUXt= ensaState *env) #define ENV_OFFSET offsetof(XtensaCPU, env) =20 =20 -int xtensa_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, int s= ize, - int mmu_idx); +bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); void xtensa_cpu_do_interrupt(CPUState *cpu); bool xtensa_cpu_exec_interrupt(CPUState *cpu, int interrupt_request); void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr= addr, diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index a54dbe4260..da1236377e 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -181,9 +181,8 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void= *data) cc->gdb_read_register =3D xtensa_cpu_gdb_read_register; cc->gdb_write_register =3D xtensa_cpu_gdb_write_register; cc->gdb_stop_before_watchpoint =3D true; -#ifdef CONFIG_USER_ONLY - cc->handle_mmu_fault =3D xtensa_cpu_handle_mmu_fault; -#else + cc->tlb_fill =3D xtensa_cpu_tlb_fill; +#ifndef CONFIG_USER_ONLY cc->do_unaligned_access =3D xtensa_cpu_do_unaligned_access; cc->get_phys_page_debug =3D xtensa_cpu_get_phys_page_debug; cc->do_transaction_failed =3D xtensa_cpu_do_transaction_failed; diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c index 5f37f378a3..5c94f934dd 100644 --- a/target/xtensa/helper.c +++ b/target/xtensa/helper.c @@ -240,19 +240,21 @@ void xtensa_cpu_list(void) =20 #ifdef CONFIG_USER_ONLY =20 -int xtensa_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int= rw, - int mmu_idx) +bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) { XtensaCPU *cpu =3D XTENSA_CPU(cs); CPUXtensaState *env =3D &cpu->env; =20 qemu_log_mask(CPU_LOG_INT, "%s: rw =3D %d, address =3D 0x%08" VADDR_PRIx ", size = =3D %d\n", - __func__, rw, address, size); + __func__, access_type, address, size); env->sregs[EXCVADDR] =3D address; - env->sregs[EXCCAUSE] =3D rw ? STORE_PROHIBITED_CAUSE : LOAD_PROHIBITED= _CAUSE; + env->sregs[EXCCAUSE] =3D (access_type =3D=3D MMU_DATA_STORE ? + STORE_PROHIBITED_CAUSE : LOAD_PROHIBITED_CAUSE= ); cs->exception_index =3D EXC_USER; - return 1; + cpu_loop_exit_restore(cs, retaddr); } =20 #else @@ -273,31 +275,42 @@ void xtensa_cpu_do_unaligned_access(CPUState *cs, } } =20 -void tlb_fill(CPUState *cs, target_ulong vaddr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) +bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) { XtensaCPU *cpu =3D XTENSA_CPU(cs); CPUXtensaState *env =3D &cpu->env; uint32_t paddr; uint32_t page_size; unsigned access; - int ret =3D xtensa_get_physical_addr(env, true, vaddr, access_type, mm= u_idx, - &paddr, &page_size, &access); + int ret =3D xtensa_get_physical_addr(env, true, address, access_type, + mmu_idx, &paddr, &page_size, &acces= s); =20 - qemu_log_mask(CPU_LOG_MMU, "%s(%08x, %d, %d) -> %08x, ret =3D %d\n", - __func__, vaddr, access_type, mmu_idx, paddr, ret); + qemu_log_mask(CPU_LOG_MMU, "%s(%08" VADDR_PRIx + ", %d, %d) -> %08x, ret =3D %d\n", + __func__, address, access_type, mmu_idx, paddr, ret); =20 if (ret =3D=3D 0) { tlb_set_page(cs, - vaddr & TARGET_PAGE_MASK, + address & TARGET_PAGE_MASK, paddr & TARGET_PAGE_MASK, access, mmu_idx, page_size); + return true; + } else if (probe) { + return false; } else { cpu_restore_state(cs, retaddr, true); - HELPER(exception_cause_vaddr)(env, env->pc, ret, vaddr); + HELPER(exception_cause_vaddr)(env, env->pc, ret, address); } } =20 +void tlb_fill(CPUState *cs, target_ulong vaddr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) +{ + xtensa_cpu_tlb_fill(cs, vaddr, size, access_type, mmu_idx, false, reta= ddr); +} + void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr= addr, unsigned size, MMUAccessType access_= type, int mmu_idx, MemTxAttrs attrs, --=20 2.17.1 From nobody Mon May 6 12:42:50 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1557441868; cv=none; d=zoho.com; s=zohoarc; b=hnZ0qYhbcWVJFh/+6e9+LFhm5Gg23pjNg1kJT8aQ+O//g9ivC7xnL2Qe45kAhgthT1TPphtIC0UR43rw5Hn11urInQjCA6imoCOB0zPyhsd8KtW6WWGlI4TKr/NiQCWyNI7yRDQLPRPbnBsnqbm9a23sxzbpKS7ueUVuGO6MRKk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1557441868; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=bMzkXC60BcwoBHMpxgJsN6EUo1CWOtE3C+TOmL7271Q=; b=GT/K7EDpUE15MFCzM8YqWerEZVpmlU+mqeiHQSNzaAEjTDR5Yivc0sn5p830BgFS1nsmrsMTlmkbAA6cllZiK7DG6DgDDXS0nv45DeRYYghvQvKMJJFFcVnvH1c+GnV7qcj1Ve6bdTKdnVncD6wb8UDFGWgK7bYS2JMnDJUac1g= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1557441868222382.6876509289659; Thu, 9 May 2019 15:44:28 -0700 (PDT) Received: from localhost ([127.0.0.1]:33690 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hOrm3-0005z9-3f for importer@patchew.org; Thu, 09 May 2019 18:44:23 -0400 Received: from eggs.gnu.org ([209.51.188.92]:33243) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hOrVP-00080H-NO for qemu-devel@nongnu.org; Thu, 09 May 2019 18:27:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hOrVN-0005dZ-Q7 for qemu-devel@nongnu.org; Thu, 09 May 2019 18:27:11 -0400 Received: from mail-pl1-x644.google.com ([2607:f8b0:4864:20::644]:33756) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hOrVM-0005cl-TB for qemu-devel@nongnu.org; Thu, 09 May 2019 18:27:09 -0400 Received: by mail-pl1-x644.google.com with SMTP id y3so1820011plp.0 for ; Thu, 09 May 2019 15:27:08 -0700 (PDT) Received: from localhost.localdomain (97-113-13-231.tukw.qwest.net. [97.113.13.231]) by smtp.gmail.com with ESMTPSA id m2sm4490521pfi.24.2019.05.09.15.27.05 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 09 May 2019 15:27:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=bMzkXC60BcwoBHMpxgJsN6EUo1CWOtE3C+TOmL7271Q=; b=ResWjWV5KJkQBdGlgZrPOyo6k2tBirWGsNl1YTsZdxFJjrMLe1e3tFP1xKu+sc9e2l /QnBIp546R9lLCmEuyMVYVHsvqOHpza6lAebZTyX9ErXqEL3UBZifsNXh/PtcnIfF8m5 FXgNiWlXUuKbu/q1aqsvYY5RWSCmMF5+lJ/0+dRLcnh5UNgBRvELkgfIOASJ+3zK3JU3 BlvkV2NzXv7RmK4weppm4/oGYDKNcS6aEM4alP8t+6RFHsbf5c0NjXSTiHUVuxWRH0hd /XOCexMqSn91tK9p0s4+5nFgjMkjxiO3iIFnQTVtwBnyzueWIcsJqmtY86D7OibQxjVz 5EeQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bMzkXC60BcwoBHMpxgJsN6EUo1CWOtE3C+TOmL7271Q=; b=RQRL+rl0wt5yOg70oJdy3rqqzAu9odetUmtAABphBAdHAScPrQXMboZU14VULuZgYl 8OAR6L/oHNZUgADgU2bW/mwXsB1yXlKATYtdFC2vMrbu/ax2ErPk2Oa5hCm55BHSG6mY /YjA9+Ze77LDEw0n2VKtjGhUU9RcHRRLXUqqQ8DwwhEbkLj4yd7w0CiC9VDlJHoOGKin 2PivVJMgMYkZCza89W2uwVuDEkedeXYaBhf3qYqcZXe7XEbxjo6NwTyu62r753KJ6Pfd /VY5r9lj15TC1JQXIPpJnMbOKOFXPn1gPPuS8DWARrBYMtGJecmMdjM5KpEdE7Mqpnsj vnUg== X-Gm-Message-State: APjAAAU99YE2pbXZUI1T77JCJMQ342E+y0Z/DBXnM6znCaxN3deAQ1dI 8qTYP0kw53i0uMo8ZBPP+oSjW01BNiE= X-Google-Smtp-Source: APXvYqwMmTrBOSO0MZpmV8loFJHFGT3XNryj7mTZE8GbeU0uRILun9MtHCm6M/Pw/35OO2px5kSsgg== X-Received: by 2002:a17:902:3281:: with SMTP id z1mr8445158plb.44.1557440826680; Thu, 09 May 2019 15:27:06 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 9 May 2019 15:26:29 -0700 Message-Id: <20190509222631.14271-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190509222631.14271-1-richard.henderson@linaro.org> References: <20190509222631.14271-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::644 Subject: [Qemu-devel] [PATCH v3 25/27] tcg: Use CPUClass::tlb_fill in cputlb.c X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) We can now use the CPUClass hook instead of a named function. Create a static tlb_fill function to avoid other changes within cputlb.c. This also isolates the asserts within. Remove the named tlb_fill function from all of the targets. Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 9 --------- accel/tcg/cputlb.c | 19 +++++++++++++++++++ target/alpha/helper.c | 6 ------ target/arm/helper.c | 8 -------- target/cris/helper.c | 6 ------ target/hppa/mem_helper.c | 6 ------ target/i386/excp_helper.c | 8 -------- target/lm32/helper.c | 6 ------ target/m68k/helper.c | 8 -------- target/microblaze/helper.c | 6 ------ target/mips/helper.c | 6 ------ target/moxie/helper.c | 6 ------ target/nios2/helper.c | 6 ------ target/openrisc/mmu.c | 6 ------ target/ppc/mmu_helper.c | 6 ------ target/riscv/cpu_helper.c | 6 ------ target/s390x/excp_helper.c | 6 ------ target/sh4/helper.c | 8 -------- target/sparc/ldst_helper.c | 6 ------ target/tricore/helper.c | 6 ------ target/unicore32/softmmu.c | 6 ------ target/xtensa/helper.c | 6 ------ 22 files changed, 19 insertions(+), 137 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 58e988b3b1..31f0ecc461 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -474,15 +474,6 @@ static inline void assert_no_pages_locked(void) */ struct MemoryRegionSection *iotlb_to_section(CPUState *cpu, hwaddr index, MemTxAttrs attr= s); - -/* - * Note: tlb_fill() can trigger a resize of the TLB. This means that all o= f the - * caller's prior references to the TLB table (e.g. CPUTLBEntry pointers) = must - * be discarded and looked up again (e.g. via tlb_entry()). - */ -void tlb_fill(CPUState *cpu, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr); - #endif =20 #if defined(CONFIG_USER_ONLY) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index f2f618217d..dfcd9ae168 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -855,6 +855,25 @@ static inline ram_addr_t qemu_ram_addr_from_host_nofai= l(void *ptr) return ram_addr; } =20 +/* + * Note: tlb_fill() can trigger a resize of the TLB. This means that all o= f the + * caller's prior references to the TLB table (e.g. CPUTLBEntry pointers) = must + * be discarded and looked up again (e.g. via tlb_entry()). + */ +static void tlb_fill(CPUState *cpu, target_ulong addr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t ret= addr) +{ + CPUClass *cc =3D CPU_GET_CLASS(cpu); + bool ok; + + /* + * This is not a probe, so only valid return is success; failure + * should result in exception + longjmp to the cpu loop. + */ + ok =3D cc->tlb_fill(cpu, addr, size, access_type, mmu_idx, false, reta= ddr); + assert(ok); +} + static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry, int mmu_idx, target_ulong addr, uintptr_t retaddr, diff --git a/target/alpha/helper.c b/target/alpha/helper.c index 929a217455..5fe9c87912 100644 --- a/target/alpha/helper.c +++ b/target/alpha/helper.c @@ -275,12 +275,6 @@ bool alpha_cpu_tlb_fill(CPUState *cs, vaddr addr, int = size, prot, mmu_idx, TARGET_PAGE_SIZE); return true; } - -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - alpha_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retadd= r); -} #endif /* USER_ONLY */ =20 void alpha_cpu_do_interrupt(CPUState *cs) diff --git a/target/arm/helper.c b/target/arm/helper.c index f1a2b94ddb..e2d5c8e34f 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -13127,14 +13127,6 @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address,= int size, #endif } =20 -#ifndef CONFIG_USER_ONLY -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - arm_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); -} -#endif - void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in) { /* Implement DC ZVA, which zeroes a fixed-length block of memory. diff --git a/target/cris/helper.c b/target/cris/helper.c index 69464837c8..b5159b8357 100644 --- a/target/cris/helper.c +++ b/target/cris/helper.c @@ -123,12 +123,6 @@ bool cris_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, cpu_loop_exit(cs); } =20 -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - cris_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr= ); -} - void crisv10_cpu_do_interrupt(CPUState *cs) { CRISCPU *cpu =3D CRIS_CPU(cs); diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index 5cee0c19b1..0fd3ac6645 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -260,12 +260,6 @@ bool hppa_cpu_tlb_fill(CPUState *cs, vaddr addr, int s= ize, return true; } =20 -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType type, int mmu_idx, uintptr_t retaddr) -{ - hppa_cpu_tlb_fill(cs, addr, size, type, mmu_idx, false, retaddr); -} - /* Insert (Insn/Data) TLB Address. Note this is PA 1.1 only. */ void HELPER(itlba)(CPUHPPAState *env, target_ulong addr, target_ureg reg) { diff --git a/target/i386/excp_helper.c b/target/i386/excp_helper.c index 68bf8e3f7c..fa1ead6404 100644 --- a/target/i386/excp_helper.c +++ b/target/i386/excp_helper.c @@ -700,11 +700,3 @@ bool x86_cpu_tlb_fill(CPUState *cs, vaddr addr, int si= ze, return true; #endif } - -#if !defined(CONFIG_USER_ONLY) -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - x86_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); -} -#endif diff --git a/target/lm32/helper.c b/target/lm32/helper.c index 1db9a5562e..20ea17ba23 100644 --- a/target/lm32/helper.c +++ b/target/lm32/helper.c @@ -44,12 +44,6 @@ bool lm32_cpu_tlb_fill(CPUState *cs, vaddr address, int = size, return true; } =20 -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - lm32_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr= ); -} - hwaddr lm32_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) { LM32CPU *cpu =3D LM32_CPU(cs); diff --git a/target/m68k/helper.c b/target/m68k/helper.c index 862f955f7b..9fc9e646ff 100644 --- a/target/m68k/helper.c +++ b/target/m68k/helper.c @@ -884,14 +884,6 @@ bool m68k_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, cpu_loop_exit_restore(cs, retaddr); } =20 -#ifndef CONFIG_USER_ONLY -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - m68k_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr= ); -} -#endif - uint32_t HELPER(bitrev)(uint32_t x) { x =3D ((x >> 1) & 0x55555555u) | ((x << 1) & 0xaaaaaaaau); diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index a523c77959..ab2ceeb055 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -108,12 +108,6 @@ bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int = size, cpu_loop_exit_restore(cs, retaddr); } =20 -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - mb_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); -} - void mb_cpu_do_interrupt(CPUState *cs) { MicroBlazeCPU *cpu =3D MICROBLAZE_CPU(cs); diff --git a/target/mips/helper.c b/target/mips/helper.c index 3a4917ce7b..9799f2ede1 100644 --- a/target/mips/helper.c +++ b/target/mips/helper.c @@ -944,12 +944,6 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, } =20 #ifndef CONFIG_USER_ONLY -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - mips_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr= ); -} - hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address,= int rw) { hwaddr physical; diff --git a/target/moxie/helper.c b/target/moxie/helper.c index 216cef057e..f5c1d4181c 100644 --- a/target/moxie/helper.c +++ b/target/moxie/helper.c @@ -26,12 +26,6 @@ #include "qemu/host-utils.h" #include "exec/helper-proto.h" =20 -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - moxie_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retadd= r); -} - void helper_raise_exception(CPUMoxieState *env, int ex) { CPUState *cs =3D CPU(moxie_env_get_cpu(env)); diff --git a/target/nios2/helper.c b/target/nios2/helper.c index eb2eed7ad3..ffb83fc104 100644 --- a/target/nios2/helper.c +++ b/target/nios2/helper.c @@ -311,10 +311,4 @@ bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, i= nt size, env->regs[CR_BADADDR] =3D address; cpu_loop_exit_restore(cs, retaddr); } - -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - nios2_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retadd= r); -} #endif /* !CONFIG_USER_ONLY */ diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c index 94c65a25fa..a73b12af03 100644 --- a/target/openrisc/mmu.c +++ b/target/openrisc/mmu.c @@ -178,10 +178,4 @@ hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cs, = vaddr addr) return phys_addr; } } - -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - openrisc_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, 0, retaddr= ); -} #endif diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c index afcca50530..e605efa883 100644 --- a/target/ppc/mmu_helper.c +++ b/target/ppc/mmu_helper.c @@ -3080,9 +3080,3 @@ bool ppc_cpu_tlb_fill(CPUState *cs, vaddr addr, int s= ize, } return true; } - -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - ppc_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); -} diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 2535435260..41d6db41c3 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -378,12 +378,6 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr= addr, env->badaddr =3D addr; riscv_raise_exception(env, cs->exception_index, retaddr); } - -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - riscv_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retadd= r); -} #endif =20 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, diff --git a/target/s390x/excp_helper.c b/target/s390x/excp_helper.c index a4e134bcab..3a467b72c5 100644 --- a/target/s390x/excp_helper.c +++ b/target/s390x/excp_helper.c @@ -178,12 +178,6 @@ bool s390_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, cpu_loop_exit(cs); } =20 -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - s390_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr= ); -} - static void do_program_interrupt(CPUS390XState *env) { uint64_t mask, addr; diff --git a/target/sh4/helper.c b/target/sh4/helper.c index 1517a6152f..fda195e7cb 100644 --- a/target/sh4/helper.c +++ b/target/sh4/helper.c @@ -872,11 +872,3 @@ bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, = int size, } cpu_loop_exit_restore(cs, retaddr); } - -#ifndef CONFIG_USER_ONLY -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - superh_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retad= dr); -} -#endif diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c index 2558c08a64..b4bf6faf41 100644 --- a/target/sparc/ldst_helper.c +++ b/target/sparc/ldst_helper.c @@ -1924,10 +1924,4 @@ void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPU= State *cs, vaddr addr, #endif cpu_raise_exception_ra(env, TT_UNALIGNED, retaddr); } - -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - sparc_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retadd= r); -} #endif diff --git a/target/tricore/helper.c b/target/tricore/helper.c index ed184fee3a..a680336850 100644 --- a/target/tricore/helper.c +++ b/target/tricore/helper.c @@ -85,12 +85,6 @@ bool tricore_cpu_tlb_fill(CPUState *cs, vaddr address, i= nt size, } } =20 -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - tricore_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, reta= ddr); -} - static void tricore_cpu_list_entry(gpointer data, gpointer user_data) { ObjectClass *oc =3D data; diff --git a/target/unicore32/softmmu.c b/target/unicore32/softmmu.c index 13678df4d7..27f218abf0 100644 --- a/target/unicore32/softmmu.c +++ b/target/unicore32/softmmu.c @@ -275,12 +275,6 @@ bool uc32_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, cpu_loop_exit_restore(cs, retaddr); } =20 -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - uc32_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr= ); -} - hwaddr uc32_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) { error_report("function uc32_cpu_get_phys_page_debug not " diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c index 5c94f934dd..efb966b3bf 100644 --- a/target/xtensa/helper.c +++ b/target/xtensa/helper.c @@ -305,12 +305,6 @@ bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, = int size, } } =20 -void tlb_fill(CPUState *cs, target_ulong vaddr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - xtensa_cpu_tlb_fill(cs, vaddr, size, access_type, mmu_idx, false, reta= ddr); -} - void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr= addr, unsigned size, MMUAccessType access_= type, int mmu_idx, MemTxAttrs attrs, --=20 2.17.1 From nobody Mon May 6 12:42:50 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1557441546; cv=none; d=zoho.com; s=zohoarc; b=InMcVDSxqlp4yHxbvjUARIK74E7f2mcw1ORJZ1DY2XGHZK/XWe0RtBmLTDdZVbV57txe6DOPCmGL75GdX98LPBqksxjp7+p7uHeHWEZJR0FnFkHVHNt9k2JDnAy9LvZ9M2kl7i/Hq5ER7eirty6XUUWIRb0opfWV1GoMYoadfVI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; 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X-Received-From: 2607:f8b0:4864:20::641 Subject: [Qemu-devel] [PATCH v3 26/27] tcg: Remove CPUClass::handle_mmu_fault X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) This hook is now completely replaced by tlb_fill. Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- include/qom/cpu.h | 3 --- accel/tcg/user-exec.c | 13 +++---------- 2 files changed, 3 insertions(+), 13 deletions(-) diff --git a/include/qom/cpu.h b/include/qom/cpu.h index c1f267b4e0..32983f27c3 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -117,7 +117,6 @@ struct TranslationBlock; * This always includes at least the program counter; some targets * will need to do more. If this hook is not implemented then the * default is to call @set_pc(tb->pc). - * @handle_mmu_fault: Callback for handling an MMU fault. * @tlb_fill: Callback for handling a softmmu tlb miss or user-only * address fault. For system mode, if the access is valid, call * tlb_set_page and return true; if the access is invalid, and @@ -195,8 +194,6 @@ typedef struct CPUClass { Error **errp); void (*set_pc)(CPUState *cpu, vaddr value); void (*synchronize_from_tb)(CPUState *cpu, struct TranslationBlock *tb= ); - int (*handle_mmu_fault)(CPUState *cpu, vaddr address, int size, int rw, - int mmu_index); bool (*tlb_fill)(CPUState *cpu, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 199f88c826..8cfbeb1b56 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -63,7 +63,6 @@ static inline int handle_cpu_signal(uintptr_t pc, siginfo= _t *info, { CPUState *cpu =3D current_cpu; CPUClass *cc; - int ret; unsigned long address =3D (unsigned long)info->si_addr; MMUAccessType access_type; =20 @@ -156,15 +155,9 @@ static inline int handle_cpu_signal(uintptr_t pc, sigi= nfo_t *info, helper_retaddr =3D 0; =20 cc =3D CPU_GET_CLASS(cpu); - if (cc->tlb_fill) { - access_type =3D is_write ? MMU_DATA_STORE : MMU_DATA_LOAD; - cc->tlb_fill(cpu, address, 0, access_type, MMU_USER_IDX, false, pc= ); - g_assert_not_reached(); - } else { - ret =3D cc->handle_mmu_fault(cpu, address, 0, is_write, MMU_USER_I= DX); - g_assert(ret > 0); - cpu_loop_exit_restore(cpu, pc); - } + access_type =3D is_write ? MMU_DATA_STORE : MMU_DATA_LOAD; + cc->tlb_fill(cpu, address, 0, access_type, MMU_USER_IDX, false, pc); + g_assert_not_reached(); } =20 #if defined(__i386__) --=20 2.17.1 From nobody Mon May 6 12:42:50 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1557441732; cv=none; d=zoho.com; s=zohoarc; b=HlaQ0ZHXbsTiT4V4sOZnCrxaXuZF3i3vXlFz3G0745PnQEmezoY9sk7RGPm3acKGxb14ZND8SoQIGEILKzWn7xKD44rx/1X2jS3BnvCamsfkZtZmdr8bYz0PNekkmHAiTVtOydIgqHwdjtberQ1t1T04CU48y9cXjsp5pn5VnGY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1557441732; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=g3xnMlX0kQIIsZFf0jn7V0Z3ghhMjOB9lPUnQDGY3Jc=; b=cnudmb9yW02rzaOGzs4ll7drv5bN5cwI5YrgyduQTTDmcBjroidNkxxlor9NS4pfxq0ivBLjuwvyRl/BkyB/fhsVvsbMxjwJ0XAW52YKwaAqx6tByHg1n4ZaVS0MqN5mkAzAz+nwB8mg4Jsk8wzLMIeOJUs1DUpC7wLRMtrMX5w= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 155744173212990.75255172315087; Thu, 9 May 2019 15:42:12 -0700 (PDT) Received: from localhost ([127.0.0.1]:33651 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hOrjs-00049I-RO for importer@patchew.org; Thu, 09 May 2019 18:42:08 -0400 Received: from eggs.gnu.org ([209.51.188.92]:33251) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hOrVR-00081V-0f for qemu-devel@nongnu.org; Thu, 09 May 2019 18:27:14 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hOrVP-0005eD-Iw for qemu-devel@nongnu.org; Thu, 09 May 2019 18:27:12 -0400 Received: from mail-pg1-x542.google.com ([2607:f8b0:4864:20::542]:36144) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hOrVP-0005dl-2E for qemu-devel@nongnu.org; Thu, 09 May 2019 18:27:11 -0400 Received: by mail-pg1-x542.google.com with SMTP id a3so1926741pgb.3 for ; Thu, 09 May 2019 15:27:10 -0700 (PDT) Received: from localhost.localdomain (97-113-13-231.tukw.qwest.net. [97.113.13.231]) by smtp.gmail.com with ESMTPSA id m2sm4490521pfi.24.2019.05.09.15.27.08 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 09 May 2019 15:27:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=g3xnMlX0kQIIsZFf0jn7V0Z3ghhMjOB9lPUnQDGY3Jc=; b=k4sHyyoIY8KL33M+u+uAPHFbeyMOYET+ZBPf8krxWJw3y3FfyOcJsO1Pw2aryidZP2 IF88MWUL32XgK6NEAUXBe/kiQZQ7W8s/rTL96l5bo9bg42hKSA2RFn5z76yEx5qPB5ao zt8os/f2HAd9vLlKUxa1JDNEBMoo9Mgl6psZyZI1iiXkS3qWeGFYbIUEVwc0IL1PY/2z 49O4ZmrVzXYeXD7Vrros5v+n8NV3LKy8NcfPnlI/ORGEwGSWjw1cggrJsOaDUxvhjubj D7PsQ4NqbZumsIrXiIJiAh9sCP9zv7JH9FPulcIXwI+rAROfEcPm3NTmKU0EtiXTwsIS awRw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=g3xnMlX0kQIIsZFf0jn7V0Z3ghhMjOB9lPUnQDGY3Jc=; b=Kr/i8A7mZY6w9UVi7uULn2zPtaYdkmEj7sBLXPna4qQ2n3pfbCLfQUR5anpooz6uH9 5ZdeftMdncbZto3mJeIk5JM2PHmR+dBbOehefAS2U+mGw2NNxpw9cVxywoem60ow0An/ tEFs6HmqIOO4cxI6JglI/oWcDXoIcUGgdmfGjkPaqFbCrQtuXT/9K8ZjK6w9/DuHBEe1 N+ZB1mfJtCtWRjdLtaGpuY+0byZt5XgxTodXj6EeF1UprwYt4uEPEPQLZglzbfur2OIt LgTV/ORCVCNNLTYa6Gnrd2zmTSaBdz5m+CRAKCkbUpXGrKH9vr5ynsyZk/otQUVfezcY 8EaQ== X-Gm-Message-State: APjAAAUIfyA/2FQbgfzxUOSzVTAy2sttU80lgOYB7ItbzZDIkfWu+U1F QhckQYoPvuy0EqMhowM/Bf9c9mwqcgs= X-Google-Smtp-Source: APXvYqz7TgSVUAlewtf5/Nc60IqQGia8I5OgHD1rKqgXKSlJxAAQ0A9mUQ6+Q5C9d+QmXM5BtLAmwg== X-Received: by 2002:a62:2703:: with SMTP id n3mr8887158pfn.199.1557440829250; Thu, 09 May 2019 15:27:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 9 May 2019 15:26:31 -0700 Message-Id: <20190509222631.14271-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190509222631.14271-1-richard.henderson@linaro.org> References: <20190509222631.14271-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::542 Subject: [Qemu-devel] [PATCH v3 27/27] tcg: Use tlb_fill probe from tlb_vaddr_to_host X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Most of the existing users would continue around a loop which would fault the tlb entry in via a normal load/store. But for AArch64 SVE we have an existing emulation bug wherein we would mark the first element of a no-fault vector load as faulted (within the FFR, not via exception) just because we did not have its address in the TLB. Now we can properly only mark it as faulted if there really is no valid, readable translation, while still not raising an exception. (Note that beyond the first element of the vector, the hardware may report a fault for any reason whatsoever; with at least one element loaded, forward progress is guaranteed.) Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v2: Update function docs comment. --- include/exec/cpu_ldst.h | 50 ++++++----------------------- accel/tcg/cputlb.c | 69 ++++++++++++++++++++++++++++++++++++----- target/arm/sve_helper.c | 6 +--- 3 files changed, 72 insertions(+), 53 deletions(-) diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index d78041d7a0..7b28a839d2 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -433,50 +433,20 @@ static inline CPUTLBEntry *tlb_entry(CPUArchState *en= v, uintptr_t mmu_idx, * @mmu_idx: MMU index to use for lookup * * Look up the specified guest virtual index in the TCG softmmu TLB. - * If the TLB contains a host virtual address suitable for direct RAM - * access, then return it. Otherwise (TLB miss, TLB entry is for an - * I/O access, etc) return NULL. - * - * This is the equivalent of the initial fast-path code used by - * TCG backends for guest load and store accesses. + * If we can translate a host virtual address suitable for direct RAM + * access, without causing a guest exception, then return it. + * Otherwise (TLB entry is for an I/O access, guest software + * TLB fill required, etc) return NULL. */ +#ifdef CONFIG_USER_ONLY static inline void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr, - int access_type, int mmu_idx) + MMUAccessType access_type, int mmu_i= dx) { -#if defined(CONFIG_USER_ONLY) return g2h(addr); -#else - CPUTLBEntry *tlbentry =3D tlb_entry(env, mmu_idx, addr); - abi_ptr tlb_addr; - uintptr_t haddr; - - switch (access_type) { - case 0: - tlb_addr =3D tlbentry->addr_read; - break; - case 1: - tlb_addr =3D tlb_addr_write(tlbentry); - break; - case 2: - tlb_addr =3D tlbentry->addr_code; - break; - default: - g_assert_not_reached(); - } - - if (!tlb_hit(tlb_addr, addr)) { - /* TLB entry is for a different page */ - return NULL; - } - - if (tlb_addr & ~TARGET_PAGE_MASK) { - /* IO access */ - return NULL; - } - - haddr =3D addr + tlbentry->addend; - return (void *)haddr; -#endif /* defined(CONFIG_USER_ONLY) */ } +#else +void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr, + MMUAccessType access_type, int mmu_idx); +#endif =20 #endif /* CPU_LDST_H */ diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index dfcd9ae168..45a5c4e123 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1007,6 +1007,16 @@ static void io_writex(CPUArchState *env, CPUIOTLBEnt= ry *iotlbentry, } } =20 +static inline target_ulong tlb_read_ofs(CPUTLBEntry *entry, size_t ofs) +{ +#if TCG_OVERSIZED_GUEST + return *(target_ulong *)((uintptr_t)entry + ofs); +#else + /* ofs might correspond to .addr_write, so use atomic_read */ + return atomic_read((target_ulong *)((uintptr_t)entry + ofs)); +#endif +} + /* Return true if ADDR is present in the victim tlb, and has been copied back to the main tlb. */ static bool victim_tlb_hit(CPUArchState *env, size_t mmu_idx, size_t index, @@ -1017,14 +1027,7 @@ static bool victim_tlb_hit(CPUArchState *env, size_t= mmu_idx, size_t index, assert_cpu_is_self(ENV_GET_CPU(env)); for (vidx =3D 0; vidx < CPU_VTLB_SIZE; ++vidx) { CPUTLBEntry *vtlb =3D &env->tlb_v_table[mmu_idx][vidx]; - target_ulong cmp; - - /* elt_ofs might correspond to .addr_write, so use atomic_read */ -#if TCG_OVERSIZED_GUEST - cmp =3D *(target_ulong *)((uintptr_t)vtlb + elt_ofs); -#else - cmp =3D atomic_read((target_ulong *)((uintptr_t)vtlb + elt_ofs)); -#endif + target_ulong cmp =3D tlb_read_ofs(vtlb, elt_ofs); =20 if (cmp =3D=3D page) { /* Found entry in victim tlb, swap tlb and iotlb. */ @@ -1108,6 +1111,56 @@ void probe_write(CPUArchState *env, target_ulong add= r, int size, int mmu_idx, } } =20 +void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr, + MMUAccessType access_type, int mmu_idx) +{ + CPUTLBEntry *entry =3D tlb_entry(env, mmu_idx, addr); + uintptr_t tlb_addr, page; + size_t elt_ofs; + + switch (access_type) { + case MMU_DATA_LOAD: + elt_ofs =3D offsetof(CPUTLBEntry, addr_read); + break; + case MMU_DATA_STORE: + elt_ofs =3D offsetof(CPUTLBEntry, addr_write); + break; + case MMU_INST_FETCH: + elt_ofs =3D offsetof(CPUTLBEntry, addr_code); + break; + default: + g_assert_not_reached(); + } + + page =3D addr & TARGET_PAGE_MASK; + tlb_addr =3D tlb_read_ofs(entry, elt_ofs); + + if (!tlb_hit_page(tlb_addr, page)) { + uintptr_t index =3D tlb_index(env, mmu_idx, addr); + + if (!victim_tlb_hit(env, mmu_idx, index, elt_ofs, page)) { + CPUState *cs =3D ENV_GET_CPU(env); + CPUClass *cc =3D CPU_GET_CLASS(cs); + + if (!cc->tlb_fill(cs, addr, 0, access_type, mmu_idx, true, 0))= { + /* Non-faulting page table read failed. */ + return NULL; + } + + /* TLB resize via tlb_fill may have moved the entry. */ + entry =3D tlb_entry(env, mmu_idx, addr); + } + tlb_addr =3D tlb_read_ofs(entry, elt_ofs); + } + + if (tlb_addr & ~TARGET_PAGE_MASK) { + /* IO access */ + return NULL; + } + + return (void *)(addr + entry->addend); +} + /* Probe for a read-modify-write atomic operation. Do not allow unaligned * operations, or io operations to proceed. Return the host address. */ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr, diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index bc847250dd..fd434c66ea 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -4598,11 +4598,7 @@ static void sve_ldnf1_r(CPUARMState *env, void *vg, = const target_ulong addr, * in the real world, obviously.) * * Then there are the annoying special cases with watchpoints... - * - * TODO: Add a form of tlb_fill that does not raise an exception, - * with a form of tlb_vaddr_to_host and a set of loads to match. - * The non_fault_vaddr_to_host would handle everything, usually, - * and the loads would handle the iomem path for watchpoints. + * TODO: Add a form of non-faulting loads using cc->tlb_fill(probe=3Dt= rue). */ host =3D tlb_vaddr_to_host(env, addr + mem_off, MMU_DATA_LOAD, mmu_idx= ); split =3D max_for_page(addr, mem_off, mem_max); --=20 2.17.1