From nobody Tue Feb 10 11:15:38 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1557274508; cv=none; d=zoho.com; s=zohoarc; b=aw5pl7emrOMDTdBoXIy2SZUg5Bup/iTi7r9E/T1J02wB0G5g6D4F12RmcPKGTaeR/c7SifT/eMh7UDkiDnproOqD+Jjn9E0AoxJR7bnvm4bXuunfAH2UFsaq/FSUVr2ULksA+bjIKTXLeuiUc2mPjONN2NlESuVj7HTtIANYLQg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1557274508; h=Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=I+zqVZlXdFBE8kSkU3W91aGwTmdsnt/2dGSYlzGlMbk=; b=lDPjU4wwEO3PmK8IL5n5Gud0mEHys4xIu8HvnhNPfP3PFDBq1fXkHA6fGiiMjE3Vi91YiwoBuH3OTn2gPAGrcqcnftb35glhK6mPvXLAjnxXhRr2u7bjbDutX95nOhXtkk4Qv3y34EEUJD3Ycmjzr2452Z9nzQHc6tBmuIvQpmE= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1557274508849208.30591091120903; Tue, 7 May 2019 17:15:08 -0700 (PDT) Received: from localhost ([127.0.0.1]:56476 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hOAEc-00051d-QR for importer@patchew.org; Tue, 07 May 2019 20:14:58 -0400 Received: from eggs.gnu.org ([209.51.188.92]:39362) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hOA6y-0007MO-2j for qemu-devel@nongnu.org; Tue, 07 May 2019 20:07:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hOA6u-0006P9-Q4 for qemu-devel@nongnu.org; Tue, 07 May 2019 20:07:04 -0400 Received: from mail-pl1-x643.google.com ([2607:f8b0:4864:20::643]:44545) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hOA6u-0006Fc-H0 for qemu-devel@nongnu.org; Tue, 07 May 2019 20:07:00 -0400 Received: by mail-pl1-x643.google.com with SMTP id d3so4946493plj.11 for ; Tue, 07 May 2019 17:06:58 -0700 (PDT) Received: from localhost.localdomain (97-113-189-189.tukw.qwest.net. [97.113.189.189]) by smtp.gmail.com with ESMTPSA id j1sm15793183pgp.91.2019.05.07.17.06.55 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 07 May 2019 17:06:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=I+zqVZlXdFBE8kSkU3W91aGwTmdsnt/2dGSYlzGlMbk=; b=DsCdUB20LeJHHVSBdFlseC4clPZTxplG9OVPgW0dVcHvVS02uwPkR1WClIJ9tmnEME apeFJEmAnra90lJdVtiHOxrzMqEvYEpHy1Ayyg7bgKw0u0P9SBLqqZzzwkpuJRL6n8Kh yiHnrM+7UboJFy4QacOgAF3EjRL7WJVXZd9yJXhhASZHybI3NluRfZt9bhupXlVi1RPs Rbvwq/zNr7fYs8U5OoBt9x+DHLJw1jW5UEKoCeiPIj7RV87ohBIzUYSZDmUtIUtX6F3C VAdHKkpj/c+QHIuVq0dgQ48SSkh3os1RYDwak5R3GlAZ8aHkB4BtbZRv2X9nmXthBasc dg7w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=I+zqVZlXdFBE8kSkU3W91aGwTmdsnt/2dGSYlzGlMbk=; b=XdoyXdVd1In4duhZYNy52Vg56W/UkKJkEdcjdTZCfX+7fdwFk7vxqpEy+/RDiIBfK4 fgZu4277/ECzldxWGiOUW+xgLGCmJIvyr7l+uHovEj/AFlynrSZIoJgsQzTNlT1zBLsn Ge9cawsnZ6dSp5mza5PAH/b/NYLpidOqDGATH4HFEk42rcbYVhJu2lh3oeXR13UuoB2G 8QPCSrlIhx8Wc4fC4MRxJi+ViAJNmzvAIMwCcxnqCWNOvwNkMT1gFVcAlHzK0SKaJANm 5AHE49NIuFRNBa/tqOE8W2Lwo1EesgYBOMHKc4nsZLBAvoHINwdgLPXTnV/tyhwVkIes Cq4A== X-Gm-Message-State: APjAAAVcNJprBri3cbdYXb5fEO2YucSOguh2uabbJQ1q2+fJhrIyrJ0y JV6uKxglHVc4YjkBgZT87jTq39sZ/HM= X-Google-Smtp-Source: APXvYqyZRvNur0QqmIM80ehJpJuCd1852PoSAIpSpW26ADU4cAOn3kIAhofPNnta/4jD7u8B5vm2qQ== X-Received: by 2002:a17:902:8698:: with SMTP id g24mr2006274plo.151.1557274016814; Tue, 07 May 2019 17:06:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 7 May 2019 17:06:12 -0700 Message-Id: <20190508000641.19090-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190508000641.19090-1-richard.henderson@linaro.org> References: <20190508000641.19090-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 Subject: [Qemu-devel] [PATCH v3 10/39] target/cris: Reindent mmu.c X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Fix all of the coding style errors in this file at once. Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/cris/mmu.c | 479 +++++++++++++++++++++++----------------------- 1 file changed, 237 insertions(+), 242 deletions(-) diff --git a/target/cris/mmu.c b/target/cris/mmu.c index b8db908823..9cb73bbfec 100644 --- a/target/cris/mmu.c +++ b/target/cris/mmu.c @@ -33,96 +33,99 @@ =20 void cris_mmu_init(CPUCRISState *env) { - env->mmu_rand_lfsr =3D 0xcccc; + env->mmu_rand_lfsr =3D 0xcccc; } =20 #define SR_POLYNOM 0x8805 static inline unsigned int compute_polynom(unsigned int sr) { - unsigned int i; - unsigned int f; + unsigned int i; + unsigned int f; =20 - f =3D 0; - for (i =3D 0; i < 16; i++) - f +=3D ((SR_POLYNOM >> i) & 1) & ((sr >> i) & 1); + f =3D 0; + for (i =3D 0; i < 16; i++) { + f +=3D ((SR_POLYNOM >> i) & 1) & ((sr >> i) & 1); + } =20 - return f; + return f; } =20 static void cris_mmu_update_rand_lfsr(CPUCRISState *env) { - unsigned int f; + unsigned int f; =20 - /* Update lfsr at every fault. */ - f =3D compute_polynom(env->mmu_rand_lfsr); - env->mmu_rand_lfsr >>=3D 1; - env->mmu_rand_lfsr |=3D (f << 15); - env->mmu_rand_lfsr &=3D 0xffff; + /* Update lfsr at every fault. */ + f =3D compute_polynom(env->mmu_rand_lfsr); + env->mmu_rand_lfsr >>=3D 1; + env->mmu_rand_lfsr |=3D (f << 15); + env->mmu_rand_lfsr &=3D 0xffff; } =20 static inline int cris_mmu_enabled(uint32_t rw_gc_cfg) { - return (rw_gc_cfg & 12) !=3D 0; + return (rw_gc_cfg & 12) !=3D 0; } =20 static inline int cris_mmu_segmented_addr(int seg, uint32_t rw_mm_cfg) { - return (1 << seg) & rw_mm_cfg; + return (1 << seg) & rw_mm_cfg; } =20 static uint32_t cris_mmu_translate_seg(CPUCRISState *env, int seg) { - uint32_t base; - int i; + uint32_t base; + int i; =20 - if (seg < 8) - base =3D env->sregs[SFR_RW_MM_KBASE_LO]; - else - base =3D env->sregs[SFR_RW_MM_KBASE_HI]; + if (seg < 8) { + base =3D env->sregs[SFR_RW_MM_KBASE_LO]; + } else { + base =3D env->sregs[SFR_RW_MM_KBASE_HI]; + } =20 - i =3D seg & 7; - base >>=3D i * 4; - base &=3D 15; + i =3D seg & 7; + base >>=3D i * 4; + base &=3D 15; =20 - base <<=3D 28; - return base; + base <<=3D 28; + return base; } -/* Used by the tlb decoder. */ -#define EXTRACT_FIELD(src, start, end) \ - (((src) >> start) & ((1 << (end - start + 1)) - 1)) =20 -static inline void set_field(uint32_t *dst, unsigned int val,=20 +/* Used by the tlb decoder. */ +#define EXTRACT_FIELD(src, start, end) \ + (((src) >> start) & ((1 << (end - start + 1)) - 1)) + +static inline void set_field(uint32_t *dst, unsigned int val, unsigned int offset, unsigned int width) { - uint32_t mask; + uint32_t mask; =20 - mask =3D (1 << width) - 1; - mask <<=3D offset; - val <<=3D offset; + mask =3D (1 << width) - 1; + mask <<=3D offset; + val <<=3D offset; =20 - val &=3D mask; - *dst &=3D ~(mask); - *dst |=3D val; + val &=3D mask; + *dst &=3D ~(mask); + *dst |=3D val; } =20 #ifdef DEBUG static void dump_tlb(CPUCRISState *env, int mmu) { - int set; - int idx; - uint32_t hi, lo, tlb_vpn, tlb_pfn; + int set; + int idx; + uint32_t hi, lo, tlb_vpn, tlb_pfn; =20 - for (set =3D 0; set < 4; set++) { - for (idx =3D 0; idx < 16; idx++) { - lo =3D env->tlbsets[mmu][set][idx].lo; - hi =3D env->tlbsets[mmu][set][idx].hi; - tlb_vpn =3D EXTRACT_FIELD(hi, 13, 31); - tlb_pfn =3D EXTRACT_FIELD(lo, 13, 31); + for (set =3D 0; set < 4; set++) { + for (idx =3D 0; idx < 16; idx++) { + lo =3D env->tlbsets[mmu][set][idx].lo; + hi =3D env->tlbsets[mmu][set][idx].hi; + tlb_vpn =3D EXTRACT_FIELD(hi, 13, 31); + tlb_pfn =3D EXTRACT_FIELD(lo, 13, 31); =20 - printf ("TLB: [%d][%d] hi=3D%x lo=3D%x v=3D%x p=3D%x\n",=20 - set, idx, hi, lo, tlb_vpn, tlb_pfn); - } - } + printf("TLB: [%d][%d] hi=3D%x lo=3D%x v=3D%x p=3D%x\n", + set, idx, hi, lo, tlb_vpn, tlb_pfn); + } + } } #endif =20 @@ -131,232 +134,224 @@ static int cris_mmu_translate_page(struct cris_mmu_= result *res, CPUCRISState *env, uint32_t vaddr, int rw, int usermode, int debug) { - unsigned int vpage; - unsigned int idx; - uint32_t pid, lo, hi; - uint32_t tlb_vpn, tlb_pfn =3D 0; - int tlb_pid, tlb_g, tlb_v, tlb_k, tlb_w, tlb_x; - int cfg_v, cfg_k, cfg_w, cfg_x;=09 - int set, match =3D 0; - uint32_t r_cause; - uint32_t r_cfg; - int rwcause; - int mmu =3D 1; /* Data mmu is default. */ - int vect_base; + unsigned int vpage; + unsigned int idx; + uint32_t pid, lo, hi; + uint32_t tlb_vpn, tlb_pfn =3D 0; + int tlb_pid, tlb_g, tlb_v, tlb_k, tlb_w, tlb_x; + int cfg_v, cfg_k, cfg_w, cfg_x; + int set, match =3D 0; + uint32_t r_cause; + uint32_t r_cfg; + int rwcause; + int mmu =3D 1; /* Data mmu is default. */ + int vect_base; =20 - r_cause =3D env->sregs[SFR_R_MM_CAUSE]; - r_cfg =3D env->sregs[SFR_RW_MM_CFG]; - pid =3D env->pregs[PR_PID] & 0xff; + r_cause =3D env->sregs[SFR_R_MM_CAUSE]; + r_cfg =3D env->sregs[SFR_RW_MM_CFG]; + pid =3D env->pregs[PR_PID] & 0xff; =20 - switch (rw) { - case 2: rwcause =3D CRIS_MMU_ERR_EXEC; mmu =3D 0; break; - case 1: rwcause =3D CRIS_MMU_ERR_WRITE; break; - default: - case 0: rwcause =3D CRIS_MMU_ERR_READ; break; - } + switch (rw) { + case 2: + rwcause =3D CRIS_MMU_ERR_EXEC; + mmu =3D 0; + break; + case 1: + rwcause =3D CRIS_MMU_ERR_WRITE; + break; + default: + case 0: + rwcause =3D CRIS_MMU_ERR_READ; + break; + } =20 - /* I exception vectors 4 - 7, D 8 - 11. */ - vect_base =3D (mmu + 1) * 4; + /* I exception vectors 4 - 7, D 8 - 11. */ + vect_base =3D (mmu + 1) * 4; =20 - vpage =3D vaddr >> 13; + vpage =3D vaddr >> 13; =20 - /* We know the index which to check on each set. - Scan both I and D. */ -#if 0 - for (set =3D 0; set < 4; set++) { - for (idx =3D 0; idx < 16; idx++) { - lo =3D env->tlbsets[mmu][set][idx].lo; - hi =3D env->tlbsets[mmu][set][idx].hi; - tlb_vpn =3D EXTRACT_FIELD(hi, 13, 31); - tlb_pfn =3D EXTRACT_FIELD(lo, 13, 31); + /* + * We know the index which to check on each set. + * Scan both I and D. + */ + idx =3D vpage & 15; + for (set =3D 0; set < 4; set++) { + lo =3D env->tlbsets[mmu][set][idx].lo; + hi =3D env->tlbsets[mmu][set][idx].hi; =20 - printf ("TLB: [%d][%d] hi=3D%x lo=3D%x v=3D%x p=3D%x\n",=20 - set, idx, hi, lo, tlb_vpn, tlb_pfn); - } - } -#endif + tlb_vpn =3D hi >> 13; + tlb_pid =3D EXTRACT_FIELD(hi, 0, 7); + tlb_g =3D EXTRACT_FIELD(lo, 4, 4); =20 - idx =3D vpage & 15; - for (set =3D 0; set < 4; set++) - { - lo =3D env->tlbsets[mmu][set][idx].lo; - hi =3D env->tlbsets[mmu][set][idx].hi; + D_LOG("TLB[%d][%d][%d] v=3D%x vpage=3D%x lo=3D%x hi=3D%x\n", + mmu, set, idx, tlb_vpn, vpage, lo, hi); + if ((tlb_g || (tlb_pid =3D=3D pid)) && tlb_vpn =3D=3D vpage) { + match =3D 1; + break; + } + } =20 - tlb_vpn =3D hi >> 13; - tlb_pid =3D EXTRACT_FIELD(hi, 0, 7); - tlb_g =3D EXTRACT_FIELD(lo, 4, 4); + res->bf_vec =3D vect_base; + if (match) { + cfg_w =3D EXTRACT_FIELD(r_cfg, 19, 19); + cfg_k =3D EXTRACT_FIELD(r_cfg, 18, 18); + cfg_x =3D EXTRACT_FIELD(r_cfg, 17, 17); + cfg_v =3D EXTRACT_FIELD(r_cfg, 16, 16); =20 - D_LOG("TLB[%d][%d][%d] v=3D%x vpage=3D%x lo=3D%x hi=3D%x\n",=20 - mmu, set, idx, tlb_vpn, vpage, lo, hi); - if ((tlb_g || (tlb_pid =3D=3D pid)) - && tlb_vpn =3D=3D vpage) { - match =3D 1; - break; - } - } + tlb_pfn =3D EXTRACT_FIELD(lo, 13, 31); + tlb_v =3D EXTRACT_FIELD(lo, 3, 3); + tlb_k =3D EXTRACT_FIELD(lo, 2, 2); + tlb_w =3D EXTRACT_FIELD(lo, 1, 1); + tlb_x =3D EXTRACT_FIELD(lo, 0, 0); =20 - res->bf_vec =3D vect_base; - if (match) { - cfg_w =3D EXTRACT_FIELD(r_cfg, 19, 19); - cfg_k =3D EXTRACT_FIELD(r_cfg, 18, 18); - cfg_x =3D EXTRACT_FIELD(r_cfg, 17, 17); - cfg_v =3D EXTRACT_FIELD(r_cfg, 16, 16); + /* + * set_exception_vector(0x04, i_mmu_refill); + * set_exception_vector(0x05, i_mmu_invalid); + * set_exception_vector(0x06, i_mmu_access); + * set_exception_vector(0x07, i_mmu_execute); + * set_exception_vector(0x08, d_mmu_refill); + * set_exception_vector(0x09, d_mmu_invalid); + * set_exception_vector(0x0a, d_mmu_access); + * set_exception_vector(0x0b, d_mmu_write); + */ + if (cfg_k && tlb_k && usermode) { + D(printf("tlb: kernel protected %x lo=3D%x pc=3D%x\n", + vaddr, lo, env->pc)); + match =3D 0; + res->bf_vec =3D vect_base + 2; + } else if (rw =3D=3D 1 && cfg_w && !tlb_w) { + D(printf("tlb: write protected %x lo=3D%x pc=3D%x\n", + vaddr, lo, env->pc)); + match =3D 0; + /* write accesses never go through the I mmu. */ + res->bf_vec =3D vect_base + 3; + } else if (rw =3D=3D 2 && cfg_x && !tlb_x) { + D(printf("tlb: exec protected %x lo=3D%x pc=3D%x\n", + vaddr, lo, env->pc)); + match =3D 0; + res->bf_vec =3D vect_base + 3; + } else if (cfg_v && !tlb_v) { + D(printf("tlb: invalid %x\n", vaddr)); + match =3D 0; + res->bf_vec =3D vect_base + 1; + } =20 - tlb_pfn =3D EXTRACT_FIELD(lo, 13, 31); - tlb_v =3D EXTRACT_FIELD(lo, 3, 3); - tlb_k =3D EXTRACT_FIELD(lo, 2, 2); - tlb_w =3D EXTRACT_FIELD(lo, 1, 1); - tlb_x =3D EXTRACT_FIELD(lo, 0, 0); + res->prot =3D 0; + if (match) { + res->prot |=3D PAGE_READ; + if (tlb_w) { + res->prot |=3D PAGE_WRITE; + } + if (mmu =3D=3D 0 && (cfg_x || tlb_x)) { + res->prot |=3D PAGE_EXEC; + } + } else { + D(dump_tlb(env, mmu)); + } + } else { + /* If refill, provide a randomized set. */ + set =3D env->mmu_rand_lfsr & 3; + } =20 - /* - set_exception_vector(0x04, i_mmu_refill); - set_exception_vector(0x05, i_mmu_invalid); - set_exception_vector(0x06, i_mmu_access); - set_exception_vector(0x07, i_mmu_execute); - set_exception_vector(0x08, d_mmu_refill); - set_exception_vector(0x09, d_mmu_invalid); - set_exception_vector(0x0a, d_mmu_access); - set_exception_vector(0x0b, d_mmu_write); - */ - if (cfg_k && tlb_k && usermode) { - D(printf ("tlb: kernel protected %x lo=3D%x pc=3D%x\n",=20 - vaddr, lo, env->pc)); - match =3D 0; - res->bf_vec =3D vect_base + 2; - } else if (rw =3D=3D 1 && cfg_w && !tlb_w) { - D(printf ("tlb: write protected %x lo=3D%x pc=3D%x\n",=20 - vaddr, lo, env->pc)); - match =3D 0; - /* write accesses never go through the I mmu. */ - res->bf_vec =3D vect_base + 3; - } else if (rw =3D=3D 2 && cfg_x && !tlb_x) { - D(printf ("tlb: exec protected %x lo=3D%x pc=3D%x\n",=20 - vaddr, lo, env->pc)); - match =3D 0; - res->bf_vec =3D vect_base + 3; - } else if (cfg_v && !tlb_v) { - D(printf ("tlb: invalid %x\n", vaddr)); - match =3D 0; - res->bf_vec =3D vect_base + 1; - } + if (!match && !debug) { + cris_mmu_update_rand_lfsr(env); =20 - res->prot =3D 0; - if (match) { - res->prot |=3D PAGE_READ; - if (tlb_w) - res->prot |=3D PAGE_WRITE; - if (mmu =3D=3D 0 && (cfg_x || tlb_x)) - res->prot |=3D PAGE_EXEC; - } - else - D(dump_tlb(env, mmu)); - } else { - /* If refill, provide a randomized set. */ - set =3D env->mmu_rand_lfsr & 3; - } + /* Compute index. */ + idx =3D vpage & 15; =20 - if (!match && !debug) { - cris_mmu_update_rand_lfsr(env); + /* Update RW_MM_TLB_SEL. */ + env->sregs[SFR_RW_MM_TLB_SEL] =3D 0; + set_field(&env->sregs[SFR_RW_MM_TLB_SEL], idx, 0, 4); + set_field(&env->sregs[SFR_RW_MM_TLB_SEL], set, 4, 2); =20 - /* Compute index. */ - idx =3D vpage & 15; + /* Update RW_MM_CAUSE. */ + set_field(&r_cause, rwcause, 8, 2); + set_field(&r_cause, vpage, 13, 19); + set_field(&r_cause, pid, 0, 8); + env->sregs[SFR_R_MM_CAUSE] =3D r_cause; + D(printf("refill vaddr=3D%x pc=3D%x\n", vaddr, env->pc)); + } =20 - /* Update RW_MM_TLB_SEL. */ - env->sregs[SFR_RW_MM_TLB_SEL] =3D 0; - set_field(&env->sregs[SFR_RW_MM_TLB_SEL], idx, 0, 4); - set_field(&env->sregs[SFR_RW_MM_TLB_SEL], set, 4, 2); + D(printf("%s rw=3D%d mtch=3D%d pc=3D%x va=3D%x vpn=3D%x tlbvpn=3D%x pf= n=3D%x pid=3D%x" + " %x cause=3D%x sel=3D%x sp=3D%x %x %x\n", + __func__, rw, match, env->pc, + vaddr, vpage, + tlb_vpn, tlb_pfn, tlb_pid, + pid, + r_cause, + env->sregs[SFR_RW_MM_TLB_SEL], + env->regs[R_SP], env->pregs[PR_USP], env->ksp)); =20 - /* Update RW_MM_CAUSE. */ - set_field(&r_cause, rwcause, 8, 2); - set_field(&r_cause, vpage, 13, 19); - set_field(&r_cause, pid, 0, 8); - env->sregs[SFR_R_MM_CAUSE] =3D r_cause; - D(printf("refill vaddr=3D%x pc=3D%x\n", vaddr, env->pc)); - } - - D(printf ("%s rw=3D%d mtch=3D%d pc=3D%x va=3D%x vpn=3D%x tlbvpn=3D%x pfn= =3D%x pid=3D%x" - " %x cause=3D%x sel=3D%x sp=3D%x %x %x\n", - __func__, rw, match, env->pc, - vaddr, vpage, - tlb_vpn, tlb_pfn, tlb_pid,=20 - pid, - r_cause, - env->sregs[SFR_RW_MM_TLB_SEL], - env->regs[R_SP], env->pregs[PR_USP], env->ksp)); - - res->phy =3D tlb_pfn << TARGET_PAGE_BITS; - return !match; + res->phy =3D tlb_pfn << TARGET_PAGE_BITS; + return !match; } =20 void cris_mmu_flush_pid(CPUCRISState *env, uint32_t pid) { CRISCPU *cpu =3D cris_env_get_cpu(env); - target_ulong vaddr; - unsigned int idx; - uint32_t lo, hi; - uint32_t tlb_vpn; - int tlb_pid, tlb_g, tlb_v; - unsigned int set; - unsigned int mmu; + target_ulong vaddr; + unsigned int idx; + uint32_t lo, hi; + uint32_t tlb_vpn; + int tlb_pid, tlb_g, tlb_v; + unsigned int set; + unsigned int mmu; =20 - pid &=3D 0xff; - for (mmu =3D 0; mmu < 2; mmu++) { - for (set =3D 0; set < 4; set++) - { - for (idx =3D 0; idx < 16; idx++) { - lo =3D env->tlbsets[mmu][set][idx].lo; - hi =3D env->tlbsets[mmu][set][idx].hi; - =09 - tlb_vpn =3D EXTRACT_FIELD(hi, 13, 31); - tlb_pid =3D EXTRACT_FIELD(hi, 0, 7); - tlb_g =3D EXTRACT_FIELD(lo, 4, 4); - tlb_v =3D EXTRACT_FIELD(lo, 3, 3); + pid &=3D 0xff; + for (mmu =3D 0; mmu < 2; mmu++) { + for (set =3D 0; set < 4; set++) { + for (idx =3D 0; idx < 16; idx++) { + lo =3D env->tlbsets[mmu][set][idx].lo; + hi =3D env->tlbsets[mmu][set][idx].hi; =20 - if (tlb_v && !tlb_g && (tlb_pid =3D=3D pid)) { - vaddr =3D tlb_vpn << TARGET_PAGE_BITS; - D_LOG("flush pid=3D%x vaddr=3D%x\n",=20 - pid, vaddr); + tlb_vpn =3D EXTRACT_FIELD(hi, 13, 31); + tlb_pid =3D EXTRACT_FIELD(hi, 0, 7); + tlb_g =3D EXTRACT_FIELD(lo, 4, 4); + tlb_v =3D EXTRACT_FIELD(lo, 3, 3); + + if (tlb_v && !tlb_g && (tlb_pid =3D=3D pid)) { + vaddr =3D tlb_vpn << TARGET_PAGE_BITS; + D_LOG("flush pid=3D%x vaddr=3D%x\n", pid, vaddr); tlb_flush_page(CPU(cpu), vaddr); - } - } - } - } + } + } + } + } } =20 int cris_mmu_translate(struct cris_mmu_result *res, CPUCRISState *env, uint32_t vaddr, int rw, int mmu_idx, int debug) { - int seg; - int miss =3D 0; - int is_user =3D mmu_idx =3D=3D MMU_USER_IDX; - uint32_t old_srs; + int seg; + int miss =3D 0; + int is_user =3D mmu_idx =3D=3D MMU_USER_IDX; + uint32_t old_srs; =20 - old_srs=3D env->pregs[PR_SRS]; + old_srs =3D env->pregs[PR_SRS]; =20 - /* rw =3D=3D 2 means exec, map the access to the insn mmu. */ - env->pregs[PR_SRS] =3D rw =3D=3D 2 ? 1 : 2; + /* rw =3D=3D 2 means exec, map the access to the insn mmu. */ + env->pregs[PR_SRS] =3D rw =3D=3D 2 ? 1 : 2; =20 - if (!cris_mmu_enabled(env->sregs[SFR_RW_GC_CFG])) { - res->phy =3D vaddr; - res->prot =3D PAGE_BITS; - goto done; - } + if (!cris_mmu_enabled(env->sregs[SFR_RW_GC_CFG])) { + res->phy =3D vaddr; + res->prot =3D PAGE_BITS; + goto done; + } =20 - seg =3D vaddr >> 28; - if (!is_user && cris_mmu_segmented_addr(seg, env->sregs[SFR_RW_MM_CFG])) - { - uint32_t base; + seg =3D vaddr >> 28; + if (!is_user && cris_mmu_segmented_addr(seg, env->sregs[SFR_RW_MM_CFG]= )) { + uint32_t base; =20 - miss =3D 0; - base =3D cris_mmu_translate_seg(env, seg); - res->phy =3D base | (0x0fffffff & vaddr); - res->prot =3D PAGE_BITS; - } else { - miss =3D cris_mmu_translate_page(res, env, vaddr, rw, - is_user, debug); - } - done: - env->pregs[PR_SRS] =3D old_srs; - return miss; + miss =3D 0; + base =3D cris_mmu_translate_seg(env, seg); + res->phy =3D base | (0x0fffffff & vaddr); + res->prot =3D PAGE_BITS; + } else { + miss =3D cris_mmu_translate_page(res, env, vaddr, rw, + is_user, debug); + } + done: + env->pregs[PR_SRS] =3D old_srs; + return miss; } --=20 2.17.1