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[97.113.189.189]) by smtp.gmail.com with ESMTPSA id j1sm15793183pgp.91.2019.05.07.17.06.54 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 07 May 2019 17:06:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=0WaSJU6hgAS7ikWQw9y/SEoow5igQ3I0D8DxUxjSTCA=; b=HY+pYQKIUl7Kg5TQPjkP7mS0OFR4+HPRNqwtod8qGpPayghGOI9pEBYusYlrbYECVz X71AcAcCHBaFmb+aJlkIvotAIcHWyxTxa1+kB5GnMkaO+Yj6GtVSVeU5QgU9jluu+8nt 36UJq73aBev6WZF+D8WYq0sOQrBxJOzH99DcF4FOY9Eh3bwA4ehIe1MTqXYuy/14plto IXMwMG3655U4zXKqWSIOeQ6HxHtT8JMMhb2n0NtaqBdy+kniciQjjm6VNX3Goy69UhWZ G4JwcMBZZOpzE+/xxP2qRM3uxTKEfkL+LpAz37zEwJTFLhfmCE7BjYpJTNCr53BPS1LL YkPg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=0WaSJU6hgAS7ikWQw9y/SEoow5igQ3I0D8DxUxjSTCA=; b=BVfcuvZ4jrR1H/axIkHuBhq/o/Be5/RyWkCDI43wTibzeXd4kSGMRByxHd6MPbF+A0 hJS7T8/a4mWY5/2cYLDixH/+EOWa+Z2YL2Ff+l/v0rh7ACNyX4Z43Xb9R/k6I+b6stOA wFVGaunMGsyq/HfHwUKCTq0R3hRBWTzKVSwDl46PKenmchVjaAtGtFSbq8Kl8F96tCcW 2i8MtWO7PqufDUF3rmsoyRLvP7WoJtNPqgn+c3ZOYx7I4GvjhsaGgFTYAUBR99puqLi9 WeeUhAMsKu7vsqgylSKGXNF6iuoRuXL6vJaAMiFNrLeug1ICnJLpKwjvkT0C2Wr2KQOt ovyQ== X-Gm-Message-State: APjAAAWjNVWxRQPaa31iOdEDov6PBoRYYQWSnBeF+WaMAukWITnu0+6N JAL+TS7yov/mE3RE7/TxemMDaCuA+14= X-Google-Smtp-Source: APXvYqw7okD2p2sc+j36M4Qm9T4GDwqzg3FVzComUmOzmvpylaxfM+b/z7ASA5TLCTWc6Ek0TxLbaA== X-Received: by 2002:a63:2943:: with SMTP id p64mr43564902pgp.151.1557274015292; Tue, 07 May 2019 17:06:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 7 May 2019 17:06:11 -0700 Message-Id: <20190508000641.19090-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190508000641.19090-1-richard.henderson@linaro.org> References: <20190508000641.19090-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::544 Subject: [Qemu-devel] [PATCH v3 09/39] target/arm: Use env_cpu, env_archcpu X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Combined uses of CPU(arm_env_get_cpu()) were failures to use the more proper, ENV_GET_CPU macro, now replaced by env_cpu. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis --- target/arm/cpu.h | 5 -- linux-user/aarch64/cpu_loop.c | 6 +- linux-user/aarch64/signal.c | 4 +- linux-user/arm/cpu_loop.c | 2 +- linux-user/syscall.c | 8 +-- target/arm/arm-semi.c | 4 +- target/arm/cpu64.c | 2 +- target/arm/helper-a64.c | 4 +- target/arm/helper.c | 120 +++++++++++++++++----------------- target/arm/op_helper.c | 21 +++--- target/arm/translate-a64.c | 2 +- target/arm/translate.c | 2 +- target/arm/vfp_helper.c | 2 +- 13 files changed, 88 insertions(+), 94 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index a633a233cc..c54c67fde4 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -911,11 +911,6 @@ struct ARMCPU { uint32_t sve_max_vq; }; =20 -static inline ARMCPU *arm_env_get_cpu(CPUARMState *env) -{ - return container_of(env, ARMCPU, env); -} - void arm_cpu_post_init(Object *obj); =20 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz); diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c index d75fd9d3e2..97f355ee23 100644 --- a/linux-user/aarch64/cpu_loop.c +++ b/linux-user/aarch64/cpu_loop.c @@ -72,7 +72,7 @@ /* AArch64 main loop */ void cpu_loop(CPUARMState *env) { - CPUState *cs =3D CPU(arm_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); int trapnr; abi_long ret; target_siginfo_t info; @@ -167,8 +167,8 @@ void arm_init_pauth_key(ARMPACKey *key) =20 void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) { - ARMCPU *cpu =3D arm_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); + ARMCPU *cpu =3D env_archcpu(env); + CPUState *cs =3D env_cpu(env); TaskState *ts =3D cs->opaque; struct image_info *info =3D ts->info; int i; diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c index f84a9cf28a..cd521ee42d 100644 --- a/linux-user/aarch64/signal.c +++ b/linux-user/aarch64/signal.c @@ -314,7 +314,7 @@ static int target_restore_sigframe(CPUARMState *env, break; =20 case TARGET_SVE_MAGIC: - if (cpu_isar_feature(aa64_sve, arm_env_get_cpu(env))) { + if (cpu_isar_feature(aa64_sve, env_archcpu(env))) { vq =3D (env->vfp.zcr_el[1] & 0xf) + 1; sve_size =3D QEMU_ALIGN_UP(TARGET_SVE_SIG_CONTEXT_SIZE(vq)= , 16); if (!sve && size =3D=3D sve_size) { @@ -433,7 +433,7 @@ static void target_setup_frame(int usig, struct target_= sigaction *ka, &layout); =20 /* SVE state needs saving only if it exists. */ - if (cpu_isar_feature(aa64_sve, arm_env_get_cpu(env))) { + if (cpu_isar_feature(aa64_sve, env_archcpu(env))) { vq =3D (env->vfp.zcr_el[1] & 0xf) + 1; sve_size =3D QEMU_ALIGN_UP(TARGET_SVE_SIG_CONTEXT_SIZE(vq), 16); sve_ofs =3D alloc_sigframe_space(sve_size, &layout); diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c index b7e7a6323c..ece4cf335e 100644 --- a/linux-user/arm/cpu_loop.c +++ b/linux-user/arm/cpu_loop.c @@ -206,7 +206,7 @@ do_kernel_trap(CPUARMState *env) =20 void cpu_loop(CPUARMState *env) { - CPUState *cs =3D CPU(arm_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); int trapnr; unsigned int n, insn; target_siginfo_t info; diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 9f110a7581..eb7fd9a1bf 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -9683,10 +9683,10 @@ static abi_long do_syscall1(void *cpu_env, int num,= abi_long arg1, * even though the current architectural maximum is VQ=3D16. */ ret =3D -TARGET_EINVAL; - if (cpu_isar_feature(aa64_sve, arm_env_get_cpu(cpu_env)) + if (cpu_isar_feature(aa64_sve, env_archcpu(cpu_env)) && arg2 >=3D 0 && arg2 <=3D 512 * 16 && !(arg2 & 15)) { CPUARMState *env =3D cpu_env; - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); uint32_t vq, old_vq; =20 old_vq =3D (env->vfp.zcr_el[1] & 0xf) + 1; @@ -9703,7 +9703,7 @@ static abi_long do_syscall1(void *cpu_env, int num, a= bi_long arg1, case TARGET_PR_SVE_GET_VL: ret =3D -TARGET_EINVAL; { - ARMCPU *cpu =3D arm_env_get_cpu(cpu_env); + ARMCPU *cpu =3D env_archcpu(cpu_env); if (cpu_isar_feature(aa64_sve, cpu)) { ret =3D ((cpu->env.vfp.zcr_el[1] & 0xf) + 1) * 16; } @@ -9712,7 +9712,7 @@ static abi_long do_syscall1(void *cpu_env, int num, a= bi_long arg1, case TARGET_PR_PAC_RESET_KEYS: { CPUARMState *env =3D cpu_env; - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); =20 if (arg3 || arg4 || arg5) { return -TARGET_EINVAL; diff --git a/target/arm/arm-semi.c b/target/arm/arm-semi.c index 8b5fd7bc6e..e998b014be 100644 --- a/target/arm/arm-semi.c +++ b/target/arm/arm-semi.c @@ -242,8 +242,8 @@ static target_ulong arm_gdb_syscall(ARMCPU *cpu, gdb_sy= scall_complete_cb cb, =20 target_ulong do_arm_semihosting(CPUARMState *env) { - ARMCPU *cpu =3D arm_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); + ARMCPU *cpu =3D env_archcpu(env); + CPUState *cs =3D env_cpu(env); target_ulong args; target_ulong arg0, arg1, arg2, arg3; char * s; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 228906f267..1150cec22d 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -44,7 +44,7 @@ static inline void unset_feature(CPUARMState *env, int fe= ature) #ifndef CONFIG_USER_ONLY static uint64_t a57_a53_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *= ri) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); =20 /* Number of cores is in [25:24]; otherwise we RAZ */ return (cpu->core_count - 1) << 24; diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 796ef34b55..44e45a8037 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -1005,7 +1005,7 @@ void HELPER(exception_return)(CPUARMState *env, uint6= 4_t new_pc) } =20 qemu_mutex_lock_iothread(); - arm_call_pre_el_change_hook(arm_env_get_cpu(env)); + arm_call_pre_el_change_hook(env_archcpu(env)); qemu_mutex_unlock_iothread(); =20 if (!return_to_aa64) { @@ -1047,7 +1047,7 @@ void HELPER(exception_return)(CPUARMState *env, uint6= 4_t new_pc) aarch64_sve_change_el(env, cur_el, new_el, return_to_aa64); =20 qemu_mutex_lock_iothread(); - arm_call_el_change_hook(arm_env_get_cpu(env)); + arm_call_el_change_hook(env_archcpu(env)); qemu_mutex_unlock_iothread(); =20 return; diff --git a/target/arm/helper.c b/target/arm/helper.c index 4c57c0ddd4..082ce89dcf 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -224,7 +224,7 @@ static void write_raw_cp_reg(CPUARMState *env, const AR= MCPRegInfo *ri, =20 static int arm_gdb_get_sysreg(CPUARMState *env, uint8_t *buf, int reg) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); const ARMCPRegInfo *ri; uint32_t key; =20 @@ -522,7 +522,7 @@ static CPAccessResult access_tpm(CPUARMState *env, cons= t ARMCPRegInfo *ri, =20 static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t = value) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); =20 raw_write(env, ri, value); tlb_flush(CPU(cpu)); /* Flush TLB as domain not tracked in TLB */ @@ -530,7 +530,7 @@ static void dacr_write(CPUARMState *env, const ARMCPReg= Info *ri, uint64_t value) =20 static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t = value) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); =20 if (raw_read(env, ri) !=3D value) { /* Unlike real hardware the qemu TLB uses virtual addresses, @@ -544,7 +544,7 @@ static void fcse_write(CPUARMState *env, const ARMCPReg= Info *ri, uint64_t value) static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); =20 if (raw_read(env, ri) !=3D value && !arm_feature(env, ARM_FEATURE_PMSA) && !extended_addresses_enabled(env)) { @@ -605,7 +605,7 @@ static void tlbiall_write(CPUARMState *env, const ARMCP= RegInfo *ri, uint64_t value) { /* Invalidate all (TLBIALL) */ - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); =20 if (tlb_force_broadcast(env)) { tlbiall_is_write(env, NULL, value); @@ -619,7 +619,7 @@ static void tlbimva_write(CPUARMState *env, const ARMCP= RegInfo *ri, uint64_t value) { /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */ - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); =20 if (tlb_force_broadcast(env)) { tlbimva_is_write(env, NULL, value); @@ -633,7 +633,7 @@ static void tlbiasid_write(CPUARMState *env, const ARMC= PRegInfo *ri, uint64_t value) { /* Invalidate by ASID (TLBIASID) */ - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); =20 if (tlb_force_broadcast(env)) { tlbiasid_is_write(env, NULL, value); @@ -647,7 +647,7 @@ static void tlbimvaa_write(CPUARMState *env, const ARMC= PRegInfo *ri, uint64_t value) { /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */ - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); =20 if (tlb_force_broadcast(env)) { tlbimvaa_is_write(env, NULL, value); @@ -1327,7 +1327,7 @@ static bool pmu_counter_enabled(CPUARMState *env, uin= t8_t counter) =20 static void pmu_update_irq(CPUARMState *env) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); qemu_set_irq(cpu->pmu_interrupt, (env->cp15.c9_pmcr & PMCRE) && (env->cp15.c9_pminten & env->cp15.c9_pmovsr)); } @@ -1382,7 +1382,7 @@ static void pmccntr_op_finish(CPUARMState *env) if (overflow_in > 0) { int64_t overflow_at =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + overflow_in; - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); timer_mod_anticipate_ns(cpu->pmu_timer, overflow_at); } #endif @@ -1431,7 +1431,7 @@ static void pmevcntr_op_finish(CPUARMState *env, uint= 8_t counter) if (overflow_in > 0) { int64_t overflow_at =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + overflow_in; - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); timer_mod_anticipate_ns(cpu->pmu_timer, overflow_at); } #endif @@ -1839,7 +1839,7 @@ static void scr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, uint64_t value) { /* Begin with base v8.0 state. */ uint32_t valid_mask =3D 0x3fff; - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); =20 if (arm_el_is_aa64(env, 3)) { value |=3D SCR_FW | SCR_AW; /* these two bits are RES1. */ @@ -1876,7 +1876,7 @@ static void scr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, uint64_t value) =20 static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); =20 /* Acquire the CSSELR index from the bank corresponding to the CCSIDR * bank @@ -2426,7 +2426,7 @@ static void gt_recalc_timer(ARMCPU *cpu, int timeridx) static void gt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri, int timeridx) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); =20 timer_del(cpu->gt_timer[timeridx]); } @@ -2447,7 +2447,7 @@ static void gt_cval_write(CPUARMState *env, const ARM= CPRegInfo *ri, { trace_arm_gt_cval_write(timeridx, value); env->cp15.c14_timer[timeridx].cval =3D value; - gt_recalc_timer(arm_env_get_cpu(env), timeridx); + gt_recalc_timer(env_archcpu(env), timeridx); } =20 static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri, @@ -2468,14 +2468,14 @@ static void gt_tval_write(CPUARMState *env, const A= RMCPRegInfo *ri, trace_arm_gt_tval_write(timeridx, value); env->cp15.c14_timer[timeridx].cval =3D gt_get_countervalue(env) - offs= et + sextract64(value, 0, 32); - gt_recalc_timer(arm_env_get_cpu(env), timeridx); + gt_recalc_timer(env_archcpu(env), timeridx); } =20 static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, int timeridx, uint64_t value) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); uint32_t oldval =3D env->cp15.c14_timer[timeridx].ctl; =20 trace_arm_gt_ctl_write(timeridx, value); @@ -2553,7 +2553,7 @@ static void gt_virt_ctl_write(CPUARMState *env, const= ARMCPRegInfo *ri, static void gt_cntvoff_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); =20 trace_arm_gt_cntvoff_write(value); raw_write(env, ri, value); @@ -3186,7 +3186,7 @@ static uint64_t pmsav7_read(CPUARMState *env, const A= RMCPRegInfo *ri) static void pmsav7_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); uint32_t *u32p =3D *(uint32_t **)raw_ptr(env, ri); =20 if (!u32p) { @@ -3201,7 +3201,7 @@ static void pmsav7_write(CPUARMState *env, const ARMC= PRegInfo *ri, static void pmsav7_rgnr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); uint32_t nrgs =3D cpu->pmsav7_dregion; =20 if (value >=3D nrgs) { @@ -3329,7 +3329,7 @@ static void vmsa_ttbcr_raw_write(CPUARMState *env, co= nst ARMCPRegInfo *ri, static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); TCR *tcr =3D raw_ptr(env, ri); =20 if (arm_feature(env, ARM_FEATURE_LPAE)) { @@ -3358,7 +3358,7 @@ static void vmsa_ttbcr_reset(CPUARMState *env, const = ARMCPRegInfo *ri) static void vmsa_tcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); TCR *tcr =3D raw_ptr(env, ri); =20 /* For AArch64 the A1 bit could result in a change of ASID, so TLB flu= sh. */ @@ -3372,7 +3372,7 @@ static void vmsa_ttbr_write(CPUARMState *env, const A= RMCPRegInfo *ri, /* If the ASID changes (with a 64-bit write), we must flush the TLB. = */ if (cpreg_field_is_64bit(ri) && extract64(raw_read(env, ri) ^ value, 48, 16) !=3D 0) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); tlb_flush(CPU(cpu)); } raw_write(env, ri, value); @@ -3381,7 +3381,7 @@ static void vmsa_ttbr_write(CPUARMState *env, const A= RMCPRegInfo *ri, static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); CPUState *cs =3D CPU(cpu); =20 /* Accesses to VTTBR may change the VMID so we must flush the TLB. */ @@ -3471,7 +3471,7 @@ static void omap_wfi_write(CPUARMState *env, const AR= MCPRegInfo *ri, uint64_t value) { /* Wait-for-interrupt (deprecated) */ - cpu_interrupt(CPU(arm_env_get_cpu(env)), CPU_INTERRUPT_HALT); + cpu_interrupt(env_cpu(env), CPU_INTERRUPT_HALT); } =20 static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -3624,7 +3624,7 @@ static const ARMCPRegInfo strongarm_cp_reginfo[] =3D { =20 static uint64_t midr_read(CPUARMState *env, const ARMCPRegInfo *ri) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); unsigned int cur_el =3D arm_current_el(env); bool secure =3D arm_is_secure(env); =20 @@ -3636,7 +3636,7 @@ static uint64_t midr_read(CPUARMState *env, const ARM= CPRegInfo *ri) =20 static uint64_t mpidr_read_val(CPUARMState *env) { - ARMCPU *cpu =3D ARM_CPU(arm_env_get_cpu(env)); + ARMCPU *cpu =3D env_archcpu(env); uint64_t mpidr =3D cpu->mp_affinity; =20 if (arm_feature(env, ARM_FEATURE_V7MP)) { @@ -3789,7 +3789,7 @@ static void tlbi_aa64_alle1_write(CPUARMState *env, c= onst ARMCPRegInfo *ri, * stage 2 translations, whereas most other scopes only invalidate * stage 1 translations. */ - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); CPUState *cs =3D CPU(cpu); =20 if (arm_is_secure_below_el3(env)) { @@ -3813,7 +3813,7 @@ static void tlbi_aa64_alle1_write(CPUARMState *env, c= onst ARMCPRegInfo *ri, static void tlbi_aa64_alle2_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); CPUState *cs =3D CPU(cpu); =20 tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_S1E2); @@ -3822,7 +3822,7 @@ static void tlbi_aa64_alle2_write(CPUARMState *env, c= onst ARMCPRegInfo *ri, static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); CPUState *cs =3D CPU(cpu); =20 tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_S1E3); @@ -3878,7 +3878,7 @@ static void tlbi_aa64_vae2_write(CPUARMState *env, co= nst ARMCPRegInfo *ri, * Currently handles both VAE2 and VALE2, since we don't support * flush-last-level-only. */ - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); CPUState *cs =3D CPU(cpu); uint64_t pageaddr =3D sextract64(value << 12, 0, 56); =20 @@ -3892,7 +3892,7 @@ static void tlbi_aa64_vae3_write(CPUARMState *env, co= nst ARMCPRegInfo *ri, * Currently handles both VAE3 and VALE3, since we don't support * flush-last-level-only. */ - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); CPUState *cs =3D CPU(cpu); uint64_t pageaddr =3D sextract64(value << 12, 0, 56); =20 @@ -3902,7 +3902,7 @@ static void tlbi_aa64_vae3_write(CPUARMState *env, co= nst ARMCPRegInfo *ri, static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *r= i, uint64_t value) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); CPUState *cs =3D CPU(cpu); bool sec =3D arm_is_secure_below_el3(env); uint64_t pageaddr =3D sextract64(value << 12, 0, 56); @@ -3926,7 +3926,7 @@ static void tlbi_aa64_vae1_write(CPUARMState *env, co= nst ARMCPRegInfo *ri, * since we don't support flush-for-specific-ASID-only or * flush-last-level-only. */ - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); CPUState *cs =3D CPU(cpu); uint64_t pageaddr =3D sextract64(value << 12, 0, 56); =20 @@ -3975,7 +3975,7 @@ static void tlbi_aa64_ipas2e1_write(CPUARMState *env,= const ARMCPRegInfo *ri, * translation information. * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero. */ - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); CPUState *cs =3D CPU(cpu); uint64_t pageaddr; =20 @@ -4018,7 +4018,7 @@ static CPAccessResult aa64_zva_access(CPUARMState *en= v, const ARMCPRegInfo *ri, =20 static uint64_t aa64_dczid_read(CPUARMState *env, const ARMCPRegInfo *ri) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); int dzp_bit =3D 1 << 4; =20 /* DZP indicates whether DC ZVA access is allowed */ @@ -4053,7 +4053,7 @@ static void spsel_write(CPUARMState *env, const ARMCP= RegInfo *ri, uint64_t val) static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); =20 if (raw_read(env, ri) =3D=3D value) { /* Skip the TLB flush if nothing actually changed; Linux likes @@ -4545,7 +4545,7 @@ static const ARMCPRegInfo el3_no_el2_v8_cp_reginfo[] = =3D { =20 static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t v= alue) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); uint64_t valid_mask =3D HCR_MASK; =20 if (arm_feature(env, ARM_FEATURE_EL3)) { @@ -5212,7 +5212,7 @@ int sve_exception_el(CPUARMState *env, int el) */ uint32_t sve_zcr_len_for_el(CPUARMState *env, int el) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); uint32_t zcr_len =3D cpu->sve_max_vq - 1; =20 if (el <=3D 1) { @@ -5380,7 +5380,7 @@ void hw_watchpoint_update_all(ARMCPU *cpu) static void dbgwvr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); int i =3D ri->crm; =20 /* Bits [63:49] are hardwired to the value of bit [48]; that is, the @@ -5396,7 +5396,7 @@ static void dbgwvr_write(CPUARMState *env, const ARMC= PRegInfo *ri, static void dbgwcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); int i =3D ri->crm; =20 raw_write(env, ri, value); @@ -5498,7 +5498,7 @@ void hw_breakpoint_update_all(ARMCPU *cpu) static void dbgbvr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); int i =3D ri->crm; =20 raw_write(env, ri, value); @@ -5508,7 +5508,7 @@ static void dbgbvr_write(CPUARMState *env, const ARMC= PRegInfo *ri, static void dbgbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); int i =3D ri->crm; =20 /* BAS[3] is a read-only copy of BAS[2], and BAS[1] a read-only @@ -5604,7 +5604,7 @@ static void define_debug_regs(ARMCPU *cpu) */ static uint64_t id_pfr1_read(CPUARMState *env, const ARMCPRegInfo *ri) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); uint64_t pfr1 =3D cpu->id_pfr1; =20 if (env->gicv3state) { @@ -5615,7 +5615,7 @@ static uint64_t id_pfr1_read(CPUARMState *env, const = ARMCPRegInfo *ri) =20 static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); uint64_t pfr0 =3D cpu->isar.id_aa64pfr0; =20 if (env->gicv3state) { @@ -7353,14 +7353,14 @@ uint32_t HELPER(rbit)(uint32_t x) /* These should probably raise undefined insn exceptions. */ void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); =20 cpu_abort(CPU(cpu), "v7m_msr %d\n", reg); } =20 uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); =20 cpu_abort(CPU(cpu), "v7m_mrs %d\n", reg); return 0; @@ -7420,7 +7420,7 @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t ad= dr, uint32_t op) =20 static void switch_mode(CPUARMState *env, int mode) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); =20 if (mode !=3D ARM_CPU_MODE_USR) { cpu_abort(CPU(cpu), "Tried to switch out of user mode\n"); @@ -7763,7 +7763,7 @@ void HELPER(v7m_preserve_fp_state)(CPUARMState *env) * PreserveFPState() pseudocode. * We may throw an exception if the stacking fails. */ - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); bool is_secure =3D env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_S_MASK; bool negpri =3D !(env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_HFRDY_MASK); bool is_priv =3D !(env->v7m.fpccr[is_secure] & R_V7M_FPCCR_USER_MASK); @@ -10865,7 +10865,7 @@ static bool get_phys_addr_v5(CPUARMState *env, uint= 32_t address, target_ulong *page_size, ARMMMUFaultInfo *fi) { - CPUState *cs =3D CPU(arm_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); int level =3D 1; uint32_t table; uint32_t desc; @@ -10986,7 +10986,7 @@ static bool get_phys_addr_v6(CPUARMState *env, uint= 32_t address, hwaddr *phys_ptr, MemTxAttrs *attrs, int *pro= t, target_ulong *page_size, ARMMMUFaultInfo *fi) { - CPUState *cs =3D CPU(arm_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); int level =3D 1; uint32_t table; uint32_t desc; @@ -11371,7 +11371,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, ta= rget_ulong address, target_ulong *page_size_ptr, ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheat= trs) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); CPUState *cs =3D CPU(cpu); /* Read an LPAE long-descriptor translation table. */ ARMFaultType fault_type =3D ARMFault_Translation; @@ -11729,7 +11729,7 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, = uint32_t address, target_ulong *page_size, ARMMMUFaultInfo *fi) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); int n; bool is_user =3D regime_is_user(env, mmu_idx); =20 @@ -11933,7 +11933,7 @@ static void v8m_security_lookup(CPUARMState *env, u= int32_t address, * pseudocode SecurityCheck() function. * We assume the caller has zero-initialized *sattrs. */ - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); int r; bool idau_exempt =3D false, idau_ns =3D true, idau_nsc =3D true; int idau_region =3D IREGION_NOTVALID; @@ -12046,7 +12046,7 @@ static bool pmsav8_mpu_lookup(CPUARMState *env, uin= t32_t address, * We set is_subpage to true if the region hit doesn't cover the * entire TARGET_PAGE the address is within. */ - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); bool is_user =3D regime_is_user(env, mmu_idx); uint32_t secure =3D regime_is_secure(env, mmu_idx); int n; @@ -12860,7 +12860,7 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t mas= kreg, uint32_t val) limit =3D is_psp ? env->v7m.psplim[false] : env->v7m.msplim[fa= lse]; =20 if (val < limit) { - CPUState *cs =3D CPU(arm_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 cpu_restore_state(cs, GETPC(), true); raise_exception(env, EXCP_STKOF, 0, 1); @@ -13088,7 +13088,7 @@ void HELPER(dc_zva)(CPUARMState *env, uint64_t vadd= r_in) * alignment faults or any memory attribute handling). */ =20 - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); uint64_t blocklen =3D 4 << cpu->dcz_blocksize; uint64_t vaddr =3D vaddr_in & ~(blocklen - 1); =20 @@ -13585,7 +13585,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_= ulong *pc, uint32_t flags =3D 0; =20 if (is_a64(env)) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); uint64_t sctlr; =20 *pc =3D env->pc; @@ -13758,7 +13758,7 @@ void aarch64_sve_narrow_vq(CPUARMState *env, unsign= ed vq) uint64_t pmask; =20 assert(vq >=3D 1 && vq <=3D ARM_MAX_VQ); - assert(vq <=3D arm_env_get_cpu(env)->sve_max_vq); + assert(vq <=3D env_archcpu(env)->sve_max_vq); =20 /* Zap the high bits of the zregs. */ for (i =3D 0; i < 32; i++) { @@ -13784,7 +13784,7 @@ void aarch64_sve_narrow_vq(CPUARMState *env, unsign= ed vq) void aarch64_sve_change_el(CPUARMState *env, int old_el, int new_el, bool el0_a64) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); int old_len, new_len; bool old_a64, new_a64; =20 diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 8698b4dc83..5af8a1f408 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -31,7 +31,7 @@ static CPUState *do_raise_exception(CPUARMState *env, uint32_t excp, uint32_t syndrome, uint32_t target_el) { - CPUState *cs =3D CPU(arm_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 if (target_el =3D=3D 1 && (arm_hcr_el2_eff(env) & HCR_TGE)) { /* @@ -245,7 +245,7 @@ void HELPER(v8m_stackcheck)(CPUARMState *env, uint32_t = newvalue) * raising an exception if the limit is breached. */ if (newvalue < v7m_sp_limit(env)) { - CPUState *cs =3D CPU(arm_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 /* * Stack limit exceptions are a rare case, so rather than syncing @@ -448,7 +448,7 @@ static inline int check_wfx_trap(CPUARMState *env, bool= is_wfe) =20 void HELPER(wfi)(CPUARMState *env, uint32_t insn_len) { - CPUState *cs =3D CPU(arm_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); int target_el =3D check_wfx_trap(env, false); =20 if (cpu_has_work(cs)) { @@ -483,8 +483,7 @@ void HELPER(wfe)(CPUARMState *env) =20 void HELPER(yield)(CPUARMState *env) { - ARMCPU *cpu =3D arm_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); + CPUState *cs =3D env_cpu(env); =20 /* This is a non-trappable hint instruction that generally indicates * that the guest is currently busy-looping. Yield control back to the @@ -502,7 +501,7 @@ void HELPER(yield)(CPUARMState *env) */ void HELPER(exception_internal)(CPUARMState *env, uint32_t excp) { - CPUState *cs =3D CPU(arm_env_get_cpu(env)); + CPUState *cs =3D env_cpu(env); =20 assert(excp_is_internal(excp)); cs->exception_index =3D excp; @@ -545,7 +544,7 @@ void HELPER(cpsr_write)(CPUARMState *env, uint32_t val,= uint32_t mask) void HELPER(cpsr_write_eret)(CPUARMState *env, uint32_t val) { qemu_mutex_lock_iothread(); - arm_call_pre_el_change_hook(arm_env_get_cpu(env)); + arm_call_pre_el_change_hook(env_archcpu(env)); qemu_mutex_unlock_iothread(); =20 cpsr_write(env, val, CPSR_ERET_MASK, CPSRWriteExceptionReturn); @@ -558,7 +557,7 @@ void HELPER(cpsr_write_eret)(CPUARMState *env, uint32_t= val) env->regs[15] &=3D (env->thumb ? ~1 : ~3); =20 qemu_mutex_lock_iothread(); - arm_call_el_change_hook(arm_env_get_cpu(env)); + arm_call_el_change_hook(env_archcpu(env)); qemu_mutex_unlock_iothread(); } =20 @@ -863,7 +862,7 @@ uint64_t HELPER(get_cp_reg64)(CPUARMState *env, void *r= ip) =20 void HELPER(pre_hvc)(CPUARMState *env) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); int cur_el =3D arm_current_el(env); /* FIXME: Use actual secure state. */ bool secure =3D false; @@ -903,7 +902,7 @@ void HELPER(pre_hvc)(CPUARMState *env) =20 void HELPER(pre_smc)(CPUARMState *env, uint32_t syndrome) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); int cur_el =3D arm_current_el(env); bool secure =3D arm_is_secure(env); bool smd_flag =3D env->cp15.scr_el3 & SCR_SMD; @@ -1177,7 +1176,7 @@ static bool check_breakpoints(ARMCPU *cpu) =20 void HELPER(check_breakpoints)(CPUARMState *env) { - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); =20 if (check_breakpoints(cpu)) { HELPER(exception_internal(env, EXCP_DEBUG)); diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index d0fefa798e..f998f1c629 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -14318,7 +14318,7 @@ static void aarch64_tr_init_disas_context(DisasCont= extBase *dcbase, { DisasContext *dc =3D container_of(dcbase, DisasContext, base); CPUARMState *env =3D cpu->env_ptr; - ARMCPU *arm_cpu =3D arm_env_get_cpu(env); + ARMCPU *arm_cpu =3D env_archcpu(env); uint32_t tb_flags =3D dc->base.tb->flags; int bound, core_mmu_idx; =20 diff --git a/target/arm/translate.c b/target/arm/translate.c index 10bc53f91c..2170f0f3cc 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -13380,7 +13380,7 @@ static void arm_tr_init_disas_context(DisasContextB= ase *dcbase, CPUState *cs) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); CPUARMState *env =3D cs->env_ptr; - ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); uint32_t tb_flags =3D dc->base.tb->flags; uint32_t condexec, core_mmu_idx; =20 diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c index 7a46d99148..d3e83b627b 100644 --- a/target/arm/vfp_helper.c +++ b/target/arm/vfp_helper.c @@ -101,7 +101,7 @@ void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t v= al) uint32_t changed =3D env->vfp.xregs[ARM_VFP_FPSCR]; =20 /* When ARMv8.2-FP16 is not supported, FZ16 is RES0. */ - if (!cpu_isar_feature(aa64_fp16, arm_env_get_cpu(env))) { + if (!cpu_isar_feature(aa64_fp16, env_archcpu(env))) { val &=3D ~FPCR_FZ16; } =20 --=20 2.17.1