From nobody Sun May 19 11:06:53 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1557233567; cv=none; d=zoho.com; s=zohoarc; b=EzfEmQashV+0S2K4XOYl89U4CI99fCj52r/jaUC/FCZ1zHFtH2ZZ22OSj9nPmFaLqxWj4fpkn271an3R5CQqVlsPdHuXBwZ2FJXsRQ5tBMugZsAvK3uMaEP+ntd16NWAIU/gzX4qNEig/Xy2OBjvGJE8BKVGwqARhjPVNHgmZfU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1557233567; h=Cc:Date:From:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:Sender:Subject:To:ARC-Authentication-Results; bh=nX1F78LeuexkNdhdiG4c4/bZts3oJzCHaG/Rv9lMmgQ=; b=Pz0xQ+usDUlBKuEZj8pu+4OeRsT2+4XvXV9/dnXjT4ADO5PptSwQbh6Ne1kZZyfjTPQYvi4Z+OHhn8C974kkUQB0v/3vd6WiLmIX/vo2fRFzffGkN+dULOIjhcSmk2NKEGZs2PlodL27FkQ+eW1xfEIJGsmrJ1Os+2R4/fCYDgg= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1557233567908324.53872650647895; Tue, 7 May 2019 05:52:47 -0700 (PDT) Received: from localhost ([127.0.0.1]:46413 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hNzaO-00021K-HB for importer@patchew.org; Tue, 07 May 2019 08:52:44 -0400 Received: from eggs.gnu.org ([209.51.188.92]:56342) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hNzZ9-0001Tp-Oo for qemu-devel@nongnu.org; Tue, 07 May 2019 08:51:28 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hNzZ8-0003Hh-IB for qemu-devel@nongnu.org; Tue, 07 May 2019 08:51:27 -0400 Received: from mga01.intel.com ([192.55.52.88]:34783) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hNzZ7-0003BO-WE for qemu-devel@nongnu.org; Tue, 07 May 2019 08:51:26 -0400 Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 07 May 2019 05:51:11 -0700 Received: from tao-optiplex-7060.sh.intel.com ([10.239.13.92]) by orsmga005.jf.intel.com with ESMTP; 07 May 2019 05:51:09 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 From: Tao Xu To: ehabkost@redhat.com, rth@twiddle.net, pbonzini@redhat.com Date: Tue, 7 May 2019 20:48:53 +0800 Message-Id: <20190507124853.9015-1-tao3.xu@intel.com> X-Mailer: git-send-email 2.17.1 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 192.55.52.88 Subject: [Qemu-devel] [PATCH v2] i386: Add some MSR based features on Cascadelake-Server CPU model X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: robert.hu@intel.com, tao3.xu@intel.com, xiaoyao.li@intel.com, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" As noted in http://lists.gnu.org/archive/html/qemu-devel/2018-09/msg02212.html Because MSR based feature has been supported by QEMU, we add CPUID_7_0_EDX_ARCH_CAPABILITIES on Cascadelake-Server CPU model, and add IA32_ARCH_CAPABILITIES MSR based features (RDCL_NO, IBRS_ALL and SKIP_L1DFL_VMENTRY). And "014018e19b i386: Make arch_capabilities migratable" has been in QEMU upstream, the CPUID_7_0_EDX_ARCH_CAPABILITIES can be safely added into CPU Model. Changes in v2: - rebased patch to latest qemu base Signed-off-by: Tao Xu --- hw/i386/pc.c | 7 ++++++- target/i386/cpu.c | 6 +++++- 2 files changed, 11 insertions(+), 2 deletions(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index d98b737b8f..27c3d25436 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -115,7 +115,12 @@ struct hpet_fw_config hpet_cfg =3D {.count =3D UINT8_M= AX}; /* Physical Address of PVH entry point read from kernel ELF NOTE */ static size_t pvh_start_addr; =20 -GlobalProperty pc_compat_4_0[] =3D {}; +GlobalProperty pc_compat_4_0[] =3D { + { "Cascadelake-Server" "-" TYPE_X86_CPU, "arch-capabilities", "off" }, + { "Cascadelake-Server" "-" TYPE_X86_CPU, "rdctl-no", "off" }, + { "Cascadelake-Server" "-" TYPE_X86_CPU, "ibrs-all", "off" }, + { "Cascadelake-Server" "-" TYPE_X86_CPU, "skip-l1dfl-vmentry", "off" }, +}; const size_t pc_compat_4_0_len =3D G_N_ELEMENTS(pc_compat_4_0); =20 GlobalProperty pc_compat_3_1[] =3D { diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 722c5514d4..2aa0a8f9ba 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -2536,7 +2536,8 @@ static X86CPUDefinition builtin_x86_defs[] =3D { CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_AVX512VNNI, .features[FEAT_7_0_EDX] =3D - CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD, + CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD | + CPUID_7_0_EDX_ARCH_CAPABILITIES, /* Missing: XSAVES (not supported by some Linux versions, * including v4.1 to v4.12). * KVM doesn't yet expose any XSAVES state save component, @@ -2548,6 +2549,9 @@ static X86CPUDefinition builtin_x86_defs[] =3D { CPUID_XSAVE_XGETBV1, .features[FEAT_6_EAX] =3D CPUID_6_EAX_ARAT, + .features[FEAT_ARCH_CAPABILITIES] =3D + MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | + MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY, .xlevel =3D 0x80000008, .model_id =3D "Intel Xeon Processor (Cascadelake)", }, --=20 2.17.1