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X-Received-From: 2607:f8b0:4864:20::433 Subject: [Qemu-devel] [PULL 3/3] decodetree: Add DisasContext argument to !function expanders X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This does require adjusting all existing users. Signed-off-by: Richard Henderson --- target/arm/translate-sve.c | 24 ++++++++++++------------ target/hppa/translate.c | 16 ++++++++-------- target/riscv/insn_trans/trans_rvc.inc.c | 10 +++++----- target/riscv/translate.c | 4 ++-- scripts/decodetree.py | 9 +++++---- 5 files changed, 32 insertions(+), 31 deletions(-) diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 245cd82621..80645db508 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -54,35 +54,35 @@ typedef void gen_helper_gvec_mem_scatter(TCGv_env, TCGv= _ptr, TCGv_ptr, /* See e.g. ASR (immediate, predicated). * Returns -1 for unallocated encoding; diagnose later. */ -static int tszimm_esz(int x) +static int tszimm_esz(DisasContext *s, int x) { x >>=3D 3; /* discard imm3 */ return 31 - clz32(x); } =20 -static int tszimm_shr(int x) +static int tszimm_shr(DisasContext *s, int x) { - return (16 << tszimm_esz(x)) - x; + return (16 << tszimm_esz(s, x)) - x; } =20 /* See e.g. LSL (immediate, predicated). */ -static int tszimm_shl(int x) +static int tszimm_shl(DisasContext *s, int x) { - return x - (8 << tszimm_esz(x)); + return x - (8 << tszimm_esz(s, x)); } =20 -static inline int plus1(int x) +static inline int plus1(DisasContext *s, int x) { return x + 1; } =20 /* The SH bit is in bit 8. Extract the low 8 and shift. */ -static inline int expand_imm_sh8s(int x) +static inline int expand_imm_sh8s(DisasContext *s, int x) { return (int8_t)x << (x & 0x100 ? 8 : 0); } =20 -static inline int expand_imm_sh8u(int x) +static inline int expand_imm_sh8u(DisasContext *s, int x) { return (uint8_t)x << (x & 0x100 ? 8 : 0); } @@ -90,7 +90,7 @@ static inline int expand_imm_sh8u(int x) /* Convert a 2-bit memory size (msz) to a 4-bit data type (dtype) * with unsigned data. C.f. SVE Memory Contiguous Load Group. */ -static inline int msz_dtype(int msz) +static inline int msz_dtype(DisasContext *s, int msz) { static const uint8_t dtype[4] =3D { 0, 5, 10, 15 }; return dtype[msz]; @@ -4834,7 +4834,7 @@ static void do_ldrq(DisasContext *s, int zt, int pg, = TCGv_i64 addr, int msz) int desc, poff; =20 /* Load the first quadword using the normal predicated load helpers. = */ - desc =3D sve_memopidx(s, msz_dtype(msz)); + desc =3D sve_memopidx(s, msz_dtype(s, msz)); desc |=3D zt << MEMOPIDX_SHIFT; desc =3D simd_desc(16, 16, desc); t_desc =3D tcg_const_i32(desc); @@ -5016,7 +5016,7 @@ static void do_st_zpa(DisasContext *s, int zt, int pg= , TCGv_i64 addr, fn =3D fn_multiple[be][nreg - 1][msz]; } assert(fn !=3D NULL); - do_mem_zpa(s, zt, pg, addr, msz_dtype(msz), fn); + do_mem_zpa(s, zt, pg, addr, msz_dtype(s, msz), fn); } =20 static bool trans_ST_zprr(DisasContext *s, arg_rprr_store *a) @@ -5065,7 +5065,7 @@ static void do_mem_zpz(DisasContext *s, int zt, int p= g, int zm, TCGv_i32 t_desc; int desc; =20 - desc =3D sve_memopidx(s, msz_dtype(msz)); + desc =3D sve_memopidx(s, msz_dtype(s, msz)); desc |=3D scale << MEMOPIDX_SHIFT; desc =3D simd_desc(vsz, vsz, desc); t_desc =3D tcg_const_i32(desc); diff --git a/target/hppa/translate.c b/target/hppa/translate.c index e1febdfea1..188fe688cb 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -279,7 +279,7 @@ typedef struct DisasContext { } DisasContext; =20 /* Note that ssm/rsm instructions number PSW_W and PSW_E differently. */ -static int expand_sm_imm(int val) +static int expand_sm_imm(DisasContext *ctx, int val) { if (val & PSW_SM_E) { val =3D (val & ~PSW_SM_E) | PSW_E; @@ -291,43 +291,43 @@ static int expand_sm_imm(int val) } =20 /* Inverted space register indicates 0 means sr0 not inferred from base. = */ -static int expand_sr3x(int val) +static int expand_sr3x(DisasContext *ctx, int val) { return ~val; } =20 /* Convert the M:A bits within a memory insn to the tri-state value we use for the final M. */ -static int ma_to_m(int val) +static int ma_to_m(DisasContext *ctx, int val) { return val & 2 ? (val & 1 ? -1 : 1) : 0; } =20 /* Convert the sign of the displacement to a pre or post-modify. */ -static int pos_to_m(int val) +static int pos_to_m(DisasContext *ctx, int val) { return val ? 1 : -1; } =20 -static int neg_to_m(int val) +static int neg_to_m(DisasContext *ctx, int val) { return val ? -1 : 1; } =20 /* Used for branch targets and fp memory ops. */ -static int expand_shl2(int val) +static int expand_shl2(DisasContext *ctx, int val) { return val << 2; } =20 /* Used for fp memory ops. */ -static int expand_shl3(int val) +static int expand_shl3(DisasContext *ctx, int val) { return val << 3; } =20 /* Used for assemble_21. */ -static int expand_shl11(int val) +static int expand_shl11(DisasContext *ctx, int val) { return val << 11; } diff --git a/target/riscv/insn_trans/trans_rvc.inc.c b/target/riscv/insn_tr= ans/trans_rvc.inc.c index ebcd977b2f..3e5d6fd5ea 100644 --- a/target/riscv/insn_trans/trans_rvc.inc.c +++ b/target/riscv/insn_trans/trans_rvc.inc.c @@ -48,13 +48,13 @@ static bool trans_c_flw_ld(DisasContext *ctx, arg_c_flw= _ld *a) REQUIRE_EXT(ctx, RVF); =20 arg_c_lw tmp; - decode_insn16_extract_cl_w(&tmp, ctx->opcode); + decode_insn16_extract_cl_w(ctx, &tmp, ctx->opcode); arg_flw arg =3D { .rd =3D tmp.rd, .rs1 =3D tmp.rs1, .imm =3D tmp.uimm = }; return trans_flw(ctx, &arg); #else /* C.LD ( RV64C/RV128C-only ) */ arg_c_fld tmp; - decode_insn16_extract_cl_d(&tmp, ctx->opcode); + decode_insn16_extract_cl_d(ctx, &tmp, ctx->opcode); arg_ld arg =3D { .rd =3D tmp.rd, .rs1 =3D tmp.rs1, .imm =3D tmp.uimm }; return trans_ld(ctx, &arg); #endif @@ -80,13 +80,13 @@ static bool trans_c_fsw_sd(DisasContext *ctx, arg_c_fsw= _sd *a) REQUIRE_EXT(ctx, RVF); =20 arg_c_sw tmp; - decode_insn16_extract_cs_w(&tmp, ctx->opcode); + decode_insn16_extract_cs_w(ctx, &tmp, ctx->opcode); arg_fsw arg =3D { .rs1 =3D tmp.rs1, .rs2 =3D tmp.rs2, .imm =3D tmp.uim= m }; return trans_fsw(ctx, &arg); #else /* C.SD ( RV64C/RV128C-only ) */ arg_c_fsd tmp; - decode_insn16_extract_cs_d(&tmp, ctx->opcode); + decode_insn16_extract_cs_d(ctx, &tmp, ctx->opcode); arg_sd arg =3D { .rs1 =3D tmp.rs1, .rs2 =3D tmp.rs2, .imm =3D tmp.uimm= }; return trans_sd(ctx, &arg); #endif @@ -107,7 +107,7 @@ static bool trans_c_jal_addiw(DisasContext *ctx, arg_c_= jal_addiw *a) #ifdef TARGET_RISCV32 /* C.JAL */ arg_c_j tmp; - decode_insn16_extract_cj(&tmp, ctx->opcode); + decode_insn16_extract_cj(ctx, &tmp, ctx->opcode); arg_jal arg =3D { .rd =3D 1, .imm =3D tmp.imm }; return trans_jal(ctx, &arg); #else diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 967eac7bc3..2ff6b49487 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -517,7 +517,7 @@ static void decode_RV32_64C(DisasContext *ctx) } =20 #define EX_SH(amount) \ - static int ex_shift_##amount(int imm) \ + static int ex_shift_##amount(DisasContext *ctx, int imm) \ { \ return imm << amount; \ } @@ -533,7 +533,7 @@ EX_SH(12) } \ } while (0) =20 -static int ex_rvc_register(int reg) +static int ex_rvc_register(DisasContext *ctx, int reg) { return 8 + reg; } diff --git a/scripts/decodetree.py b/scripts/decodetree.py index 4536e3a63d..81874e22cc 100755 --- a/scripts/decodetree.py +++ b/scripts/decodetree.py @@ -256,7 +256,7 @@ class FunctionField: return self.func + '(' + str(self.base) + ')' =20 def str_extract(self): - return self.func + '(' + self.base.str_extract() + ')' + return self.func + '(ctx, ' + self.base.str_extract() + ')' =20 def __eq__(self, other): return self.func =3D=3D other.func and self.base =3D=3D other.base @@ -318,7 +318,7 @@ class Format(General): return decode_function + '_extract_' + self.name =20 def output_extract(self): - output('static void ', self.extract_name(), '(', + output('static void ', self.extract_name(), '(DisasContext *ctx, ', self.base.struct_name(), ' *a, ', insntype, ' insn)\n{\n') for n, f in self.fields.items(): output(' a->', n, ' =3D ', f.str_extract(), ';\n') @@ -343,7 +343,8 @@ class Pattern(General): arg =3D self.base.base.name output(ind, '/* ', self.file, ':', str(self.lineno), ' */\n') if not extracted: - output(ind, self.base.extract_name(), '(&u.f_', arg, ', insn);= \n') + output(ind, self.base.extract_name(), + '(ctx, &u.f_', arg, ', insn);\n') for n, f in self.fields.items(): output(ind, 'u.f_', arg, '.', n, ' =3D ', f.str_extract(), ';\= n') output(ind, 'if (', translate_prefix, '_', self.name, @@ -894,7 +895,7 @@ class Tree: # extract the fields now. if not extracted and self.base: output(ind, self.base.extract_name(), - '(&u.f_', self.base.base.name, ', insn);\n') + '(ctx, &u.f_', self.base.base.name, ', insn);\n') extracted =3D True =20 # Attempt to aid the compiler in producing compact switch statemen= ts. --=20 2.17.1