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[97.113.189.189]) by smtp.gmail.com with ESMTPSA id 15sm6680423pfo.117.2019.05.03.22.53.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 03 May 2019 22:53:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=oB7VP5ATUZChOLMjOlpdWPN1IctJhwYBQQIlaCDVjkw=; b=ZN3z0+Wx4Ckd7Bz+92mm0xR6ZEmC12+z4/YNmrctazoL3a90rBrP0Cd+qNl3CRl0bA FAeg9xS0Atv0zhsd4R4Yd8gEhbZt6qykz5yObK6GlhzpbCtN5cxZ2OishmX5UDGlm2CP d/eYVi1rbbTfaZ0l750kF/okdLqJjZflNUaikeXv6pRHLmgO9/RKffgZOqi2SJoVGPi2 E5UDwmVhoLPthGkgAT0h+xy2ybEY17/pSqPa+ajSaoAQiZQHgd9k8RlhrnEKDU7tx+zU GFjxGxOLj0MWRcKZg0Jfamkr0ls8u8FfiFu5Ygc4DnmM6WyJ2myDULzsBNjIO86Tx0HV 951Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=oB7VP5ATUZChOLMjOlpdWPN1IctJhwYBQQIlaCDVjkw=; b=Nf8lQiL2umXwyDCgT+TRtEdV/qPGQxxMrR4AVHdFNhrTIsC38i2Y3unK66qtWUKH4S z6GKlqO6TuRrzOc04x5TELYldpCM8Mn6EVy6xBgNo3fXAooI1VSTvpF5ohUGVwXuyrkq fIOIyRRNcUkbEdnCZGA/t3hDK0RUgL0LUNo9SJKv9u/WZXwCqVsNgbjiioCPw1A1FIRz k9A1H4JVFSrrXEUI5vr8zirMr7Fuv/nCIodiQfS+k56lqKvwUz24sOyU+MYNadkFlPpp 4mw63OZI7+yYyY5TQZ87n9R64H04hZcPwAHhbXIYBxktw8GT9tAMeZKhoIXRKZhv7dM7 RZXg== X-Gm-Message-State: APjAAAXo9XSGbQKTNQpHamhcl7VNvfuM5YIcGF+nd20VErhEmFY9cfUE /5m/8r5k02F1M9iIDAX8yWta/QL3i7g= X-Google-Smtp-Source: APXvYqzWLetqo1I/alzsuBBa8zDNfOUEAf2LbjwEvVKFnP5kg/QG1eIFdcLIPfW/khiNpRq5D55GYQ== X-Received: by 2002:a63:d016:: with SMTP id z22mr16343866pgf.116.1556949205972; Fri, 03 May 2019 22:53:25 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 3 May 2019 22:52:49 -0700 Message-Id: <20190504055300.18426-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190504055300.18426-1-richard.henderson@linaro.org> References: <20190504055300.18426-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 Subject: [Qemu-devel] [PATCH v3 20/31] tcg: Add support for integer absolute value X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Remove a function of the same name from target/arm/. Use a branchless implementation of abs gleaned from gcc. Reviewed-by: Alex Benn=C3=A9e Reviewed-by: David Hildenbrand Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/tcg-op.h | 5 +++++ target/arm/translate.c | 10 ---------- tcg/tcg-op.c | 20 ++++++++++++++++++++ 3 files changed, 25 insertions(+), 10 deletions(-) diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h index 472b73cb38..660fe205d0 100644 --- a/tcg/tcg-op.h +++ b/tcg/tcg-op.h @@ -335,6 +335,7 @@ void tcg_gen_smin_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32= arg2); void tcg_gen_smax_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_umin_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_umax_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2); +void tcg_gen_abs_i32(TCGv_i32, TCGv_i32); =20 static inline void tcg_gen_discard_i32(TCGv_i32 arg) { @@ -534,6 +535,7 @@ void tcg_gen_smin_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64= arg2); void tcg_gen_smax_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_umin_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_umax_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2); +void tcg_gen_abs_i64(TCGv_i64, TCGv_i64); =20 #if TCG_TARGET_REG_BITS =3D=3D 64 static inline void tcg_gen_discard_i64(TCGv_i64 arg) @@ -973,6 +975,7 @@ void tcg_gen_nor_vec(unsigned vece, TCGv_vec r, TCGv_ve= c a, TCGv_vec b); void tcg_gen_eqv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); void tcg_gen_not_vec(unsigned vece, TCGv_vec r, TCGv_vec a); void tcg_gen_neg_vec(unsigned vece, TCGv_vec r, TCGv_vec a); +void tcg_gen_abs_vec(unsigned vece, TCGv_vec r, TCGv_vec a); void tcg_gen_ssadd_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); void tcg_gen_usadd_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); void tcg_gen_sssub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); @@ -1019,6 +1022,7 @@ void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr base, TCGAr= g offset, TCGType t); #define tcg_gen_addi_tl tcg_gen_addi_i64 #define tcg_gen_sub_tl tcg_gen_sub_i64 #define tcg_gen_neg_tl tcg_gen_neg_i64 +#define tcg_gen_abs_tl tcg_gen_abs_i64 #define tcg_gen_subfi_tl tcg_gen_subfi_i64 #define tcg_gen_subi_tl tcg_gen_subi_i64 #define tcg_gen_and_tl tcg_gen_and_i64 @@ -1131,6 +1135,7 @@ void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr base, TCGAr= g offset, TCGType t); #define tcg_gen_addi_tl tcg_gen_addi_i32 #define tcg_gen_sub_tl tcg_gen_sub_i32 #define tcg_gen_neg_tl tcg_gen_neg_i32 +#define tcg_gen_abs_tl tcg_gen_abs_i32 #define tcg_gen_subfi_tl tcg_gen_subfi_i32 #define tcg_gen_subi_tl tcg_gen_subi_i32 #define tcg_gen_and_tl tcg_gen_and_i32 diff --git a/target/arm/translate.c b/target/arm/translate.c index 35bd426a3d..b25781554f 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -604,16 +604,6 @@ static void gen_sar(TCGv_i32 dest, TCGv_i32 t0, TCGv_i= 32 t1) tcg_temp_free_i32(tmp1); } =20 -static void tcg_gen_abs_i32(TCGv_i32 dest, TCGv_i32 src) -{ - TCGv_i32 c0 =3D tcg_const_i32(0); - TCGv_i32 tmp =3D tcg_temp_new_i32(); - tcg_gen_neg_i32(tmp, src); - tcg_gen_movcond_i32(TCG_COND_GT, dest, src, c0, src, tmp); - tcg_temp_free_i32(c0); - tcg_temp_free_i32(tmp); -} - static void shifter_out_im(TCGv_i32 var, int shift) { if (shift =3D=3D 0) { diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index a00d1df37e..0ac291f1c4 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -1091,6 +1091,16 @@ void tcg_gen_umax_i32(TCGv_i32 ret, TCGv_i32 a, TCGv= _i32 b) tcg_gen_movcond_i32(TCG_COND_LTU, ret, a, b, b, a); } =20 +void tcg_gen_abs_i32(TCGv_i32 ret, TCGv_i32 a) +{ + TCGv_i32 t =3D tcg_temp_new_i32(); + + tcg_gen_sari_i32(t, a, 31); + tcg_gen_xor_i32(ret, a, t); + tcg_gen_sub_i32(ret, ret, t); + tcg_temp_free_i32(t); +} + /* 64-bit ops */ =20 #if TCG_TARGET_REG_BITS =3D=3D 32 @@ -2548,6 +2558,16 @@ void tcg_gen_umax_i64(TCGv_i64 ret, TCGv_i64 a, TCGv= _i64 b) tcg_gen_movcond_i64(TCG_COND_LTU, ret, a, b, b, a); } =20 +void tcg_gen_abs_i64(TCGv_i64 ret, TCGv_i64 a) +{ + TCGv_i64 t =3D tcg_temp_new_i64(); + + tcg_gen_sari_i64(t, a, 63); + tcg_gen_xor_i64(ret, a, t); + tcg_gen_sub_i64(ret, ret, t); + tcg_temp_free_i64(t); +} + /* Size changing operations. */ =20 void tcg_gen_extrl_i64_i32(TCGv_i32 ret, TCGv_i64 arg) --=20 2.17.1