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[97.113.189.189]) by smtp.gmail.com with ESMTPSA id 15sm6680423pfo.117.2019.05.03.22.53.02 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 03 May 2019 22:53:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Apjrpc9r2vVqQ7yc2aMigKmKRzCXYxZj/bYKRWwstvE=; b=MnlesDdDe+fUyrlYUPLMYWqZ+KfWEvrS4EP1LPPOgtfaPCvSVe7fQFeXeYw+d0cQ8T ADPTHU/w28wnzLiEYtihbN316BF9N/NZ5/RTLaV19AI5e1ndG11GxeVthETmFh9mjxbO szRoMLdsbkPpZ6TPaW4hx2aaW/vtERE5ASgY3od46QU3u1IxT2WO+91/P6VOw7rDh5FT fexLwJkXm+RBMlQsoOGVUm4MFVPugE2hbkBIsgbmIY2gtJxLSQNbgJ9eewtxsvYEna/F fQRxrlmvj4YdxiNy4hdV9Uj7+0BNkcqIgjBnF0nXgc981WdDKdcmm8clAq9kb61rYIMZ xVUw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Apjrpc9r2vVqQ7yc2aMigKmKRzCXYxZj/bYKRWwstvE=; b=ZBQcisbpciYv8FOGf9XyQhZjYf/O+5A+sJMGqmq9NagjtSXLB+cXw+7Ffcw2MgGgBe U+J1N7UopzXc1gOF+R04jo8abyrPoARm3lj9esjpAI7bJFJ1b8XPHax0kLZkPFE1ngr1 s7CJTrVXO963vttYRoiMN7f4TssyUhTvVT+1qJXq3ONMbmya+w/t95yEw8IxPxhsoIm3 dORdlGq6YDDu0LBel+pv9+FLVn1WiG49Q57p2RiJk/IO7T0eeVrvirqn9ONf2i61Sodn SqlCV7Wf5jVyYO76Hfx0CpSWRkN9uXxcdIcwlb0juFLPtGZ0ugezXijw3snhRdThP7JV DJlA== X-Gm-Message-State: APjAAAX6DNv3JikIUI6lnX4o8VRtLHsYR5Iqa9ca7CMjMch6Gsh0++cL yEIYB7keV5PVKvVsE/gWXM2DMP23wuc= X-Google-Smtp-Source: APXvYqxX0GruJe2xta6nAbBb7SDE36bA1Jbgo5MckDERP3DfPD6NCFaDFtn/oZ16GNqBOR/csbG1jQ== X-Received: by 2002:aa7:82cb:: with SMTP id f11mr17434903pfn.0.1556949183963; Fri, 03 May 2019 22:53:03 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 3 May 2019 22:52:30 -0700 Message-Id: <20190504055300.18426-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190504055300.18426-1-richard.henderson@linaro.org> References: <20190504055300.18426-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH v3 01/31] tcg: Implement tcg_gen_gvec_3i() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: David Hildenbrand Let's add tcg_gen_gvec_3i(), similar to tcg_gen_gvec_2i(), however without introducing "gen_helper_gvec_3i *fnoi", as it isn't needed for now. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: David Hildenbrand Message-Id: <20190416185301.25344-2-david@redhat.com> Signed-off-by: Richard Henderson --- tcg/tcg-op-gvec.h | 24 ++++++++ tcg/tcg-op-gvec.c | 139 ++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 163 insertions(+) diff --git a/tcg/tcg-op-gvec.h b/tcg/tcg-op-gvec.h index 850da32ded..c093243c4c 100644 --- a/tcg/tcg-op-gvec.h +++ b/tcg/tcg-op-gvec.h @@ -164,6 +164,27 @@ typedef struct { bool load_dest; } GVecGen3; =20 +typedef struct { + /* + * Expand inline as a 64-bit or 32-bit integer. Only one of these will= be + * non-NULL. + */ + void (*fni8)(TCGv_i64, TCGv_i64, TCGv_i64, int64_t); + void (*fni4)(TCGv_i32, TCGv_i32, TCGv_i32, int32_t); + /* Expand inline with a host vector type. */ + void (*fniv)(unsigned, TCGv_vec, TCGv_vec, TCGv_vec, int64_t); + /* Expand out-of-line helper w/descriptor, data in descriptor. */ + gen_helper_gvec_3 *fno; + /* The opcode, if any, to which this corresponds. */ + TCGOpcode opc; + /* The vector element size, if applicable. */ + uint8_t vece; + /* Prefer i64 to v64. */ + bool prefer_i64; + /* Load dest as a 3rd source operand. */ + bool load_dest; +} GVecGen3i; + typedef struct { /* Expand inline as a 64-bit or 32-bit integer. Only one of these will be non-NULL. */ @@ -193,6 +214,9 @@ void tcg_gen_gvec_2s(uint32_t dofs, uint32_t aofs, uint= 32_t oprsz, uint32_t maxsz, TCGv_i64 c, const GVecGen2s *); void tcg_gen_gvec_3(uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t oprsz, uint32_t maxsz, const GVecGen3 *); +void tcg_gen_gvec_3i(uint32_t dofs, uint32_t aofs, uint32_t bofs, + uint32_t oprsz, uint32_t maxsz, int64_t c, + const GVecGen3i *); void tcg_gen_gvec_4(uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t = cofs, uint32_t oprsz, uint32_t maxsz, const GVecGen4 *); =20 diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c index 0996ef0812..f831adb4e7 100644 --- a/tcg/tcg-op-gvec.c +++ b/tcg/tcg-op-gvec.c @@ -663,6 +663,29 @@ static void expand_3_i32(uint32_t dofs, uint32_t aofs, tcg_temp_free_i32(t0); } =20 +static void expand_3i_i32(uint32_t dofs, uint32_t aofs, uint32_t bofs, + uint32_t oprsz, int32_t c, bool load_dest, + void (*fni)(TCGv_i32, TCGv_i32, TCGv_i32, int32_= t)) +{ + TCGv_i32 t0 =3D tcg_temp_new_i32(); + TCGv_i32 t1 =3D tcg_temp_new_i32(); + TCGv_i32 t2 =3D tcg_temp_new_i32(); + uint32_t i; + + for (i =3D 0; i < oprsz; i +=3D 4) { + tcg_gen_ld_i32(t0, cpu_env, aofs + i); + tcg_gen_ld_i32(t1, cpu_env, bofs + i); + if (load_dest) { + tcg_gen_ld_i32(t2, cpu_env, dofs + i); + } + fni(t2, t0, t1, c); + tcg_gen_st_i32(t2, cpu_env, dofs + i); + } + tcg_temp_free_i32(t0); + tcg_temp_free_i32(t1); + tcg_temp_free_i32(t2); +} + /* Expand OPSZ bytes worth of three-operand operations using i32 elements.= */ static void expand_4_i32(uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t cofs, uint32_t oprsz, bool write_aofs, @@ -770,6 +793,29 @@ static void expand_3_i64(uint32_t dofs, uint32_t aofs, tcg_temp_free_i64(t0); } =20 +static void expand_3i_i64(uint32_t dofs, uint32_t aofs, uint32_t bofs, + uint32_t oprsz, int64_t c, bool load_dest, + void (*fni)(TCGv_i64, TCGv_i64, TCGv_i64, int64_= t)) +{ + TCGv_i64 t0 =3D tcg_temp_new_i64(); + TCGv_i64 t1 =3D tcg_temp_new_i64(); + TCGv_i64 t2 =3D tcg_temp_new_i64(); + uint32_t i; + + for (i =3D 0; i < oprsz; i +=3D 8) { + tcg_gen_ld_i64(t0, cpu_env, aofs + i); + tcg_gen_ld_i64(t1, cpu_env, bofs + i); + if (load_dest) { + tcg_gen_ld_i64(t2, cpu_env, dofs + i); + } + fni(t2, t0, t1, c); + tcg_gen_st_i64(t2, cpu_env, dofs + i); + } + tcg_temp_free_i64(t0); + tcg_temp_free_i64(t1); + tcg_temp_free_i64(t2); +} + /* Expand OPSZ bytes worth of three-operand operations using i64 elements.= */ static void expand_4_i64(uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t cofs, uint32_t oprsz, bool write_aofs, @@ -883,6 +929,35 @@ static void expand_3_vec(unsigned vece, uint32_t dofs,= uint32_t aofs, tcg_temp_free_vec(t0); } =20 +/* + * Expand OPSZ bytes worth of three-vector operands and an immediate opera= nd + * using host vectors. + */ +static void expand_3i_vec(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t tysz, + TCGType type, int64_t c, bool load_dest, + void (*fni)(unsigned, TCGv_vec, TCGv_vec, TCGv_v= ec, + int64_t)) +{ + TCGv_vec t0 =3D tcg_temp_new_vec(type); + TCGv_vec t1 =3D tcg_temp_new_vec(type); + TCGv_vec t2 =3D tcg_temp_new_vec(type); + uint32_t i; + + for (i =3D 0; i < oprsz; i +=3D tysz) { + tcg_gen_ld_vec(t0, cpu_env, aofs + i); + tcg_gen_ld_vec(t1, cpu_env, bofs + i); + if (load_dest) { + tcg_gen_ld_vec(t2, cpu_env, dofs + i); + } + fni(vece, t2, t0, t1, c); + tcg_gen_st_vec(t2, cpu_env, dofs + i); + } + tcg_temp_free_vec(t0); + tcg_temp_free_vec(t1); + tcg_temp_free_vec(t2); +} + /* Expand OPSZ bytes worth of four-operand operations using host vectors. = */ static void expand_4_vec(unsigned vece, uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t cofs, uint32_t oprsz, @@ -1174,6 +1249,70 @@ void tcg_gen_gvec_3(uint32_t dofs, uint32_t aofs, ui= nt32_t bofs, } } =20 +/* Expand a vector operation with three vectors and an immediate. */ +void tcg_gen_gvec_3i(uint32_t dofs, uint32_t aofs, uint32_t bofs, + uint32_t oprsz, uint32_t maxsz, int64_t c, + const GVecGen3i *g) +{ + TCGType type; + uint32_t some; + + check_size_align(oprsz, maxsz, dofs | aofs | bofs); + check_overlap_3(dofs, aofs, bofs, maxsz); + + type =3D 0; + if (g->fniv) { + type =3D choose_vector_type(g->opc, g->vece, oprsz, g->prefer_i64); + } + switch (type) { + case TCG_TYPE_V256: + /* + * Recall that ARM SVE allows vector sizes that are not a + * power of 2, but always a multiple of 16. The intent is + * that e.g. size =3D=3D 80 would be expanded with 2x32 + 1x16. + */ + some =3D QEMU_ALIGN_DOWN(oprsz, 32); + expand_3i_vec(g->vece, dofs, aofs, bofs, some, 32, TCG_TYPE_V256, + c, g->load_dest, g->fniv); + if (some =3D=3D oprsz) { + break; + } + dofs +=3D some; + aofs +=3D some; + bofs +=3D some; + oprsz -=3D some; + maxsz -=3D some; + /* fallthru */ + case TCG_TYPE_V128: + expand_3i_vec(g->vece, dofs, aofs, bofs, oprsz, 16, TCG_TYPE_V128, + c, g->load_dest, g->fniv); + break; + case TCG_TYPE_V64: + expand_3i_vec(g->vece, dofs, aofs, bofs, oprsz, 8, TCG_TYPE_V64, + c, g->load_dest, g->fniv); + break; + + case 0: + if (g->fni8 && check_size_impl(oprsz, 8)) { + expand_3i_i64(dofs, aofs, bofs, oprsz, c, g->load_dest, g->fni= 8); + } else if (g->fni4 && check_size_impl(oprsz, 4)) { + expand_3i_i32(dofs, aofs, bofs, oprsz, c, g->load_dest, g->fni= 4); + } else { + assert(g->fno !=3D NULL); + tcg_gen_gvec_3_ool(dofs, aofs, bofs, oprsz, maxsz, c, g->fno); + return; + } + break; + + default: + g_assert_not_reached(); + } + + if (oprsz < maxsz) { + expand_clr(dofs + oprsz, maxsz - oprsz); + } +} + /* Expand a vector four-operand operation. */ void tcg_gen_gvec_4(uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t = cofs, uint32_t oprsz, uint32_t maxsz, const GVecGen4 *g) --=20 2.17.1 From nobody Sat May 4 13:31:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1556949501; cv=none; d=zoho.com; s=zohoarc; b=bjTQZTlPIV6ujOw3ivOcYlbt5iTWdb3o54D1WDYkcXNkTp4Y8jHBQzf5DaZ6ZDz2AkTw7vAhLdd9tmALLciAXpzRs4tjF1OrBFr+ZvqT05N3y1Zb9uTbB8HasLajS+AmIZ0ZFbUpZ9s02qDzct/Zx6EkgUIacDW+0L2q+v1InEM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1556949501; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=I6td3WuBBk5Qpr2iJ7wAnroVlDoSyj0rbd0/PnMjxvM=; b=Ikt9C8v2XNL6bhLHX9kgSi/KvaayyTK/4AH/xzNOtlBawapsAH6vsP1D2gsKqyxcCMx/mRazTrUWgE+KZibCIunktpmP62ibedGWUelIy3PJuUxyMRH/7+CkLkhKn7Z6tsnDx5gkcX2NUcFebxHo3r35O3a9SCX7szh+FRYjJQk= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1556949501130436.20316843770433; Fri, 3 May 2019 22:58:21 -0700 (PDT) Received: from localhost ([127.0.0.1]:51660 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hMngX-0002u1-Qi for importer@patchew.org; Sat, 04 May 2019 01:58:10 -0400 Received: from eggs.gnu.org ([209.51.188.92]:41676) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hMnbj-0007fx-1o for qemu-devel@nongnu.org; Sat, 04 May 2019 01:53:11 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hMnbg-00045w-St for qemu-devel@nongnu.org; Sat, 04 May 2019 01:53:10 -0400 Received: from mail-pg1-x544.google.com ([2607:f8b0:4864:20::544]:45034) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hMnbf-00040g-5e for qemu-devel@nongnu.org; Sat, 04 May 2019 01:53:07 -0400 Received: by mail-pg1-x544.google.com with SMTP id z16so3752275pgv.11 for ; Fri, 03 May 2019 22:53:06 -0700 (PDT) Received: from localhost.localdomain (97-113-189-189.tukw.qwest.net. [97.113.189.189]) by smtp.gmail.com with ESMTPSA id 15sm6680423pfo.117.2019.05.03.22.53.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 03 May 2019 22:53:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=I6td3WuBBk5Qpr2iJ7wAnroVlDoSyj0rbd0/PnMjxvM=; b=j6Ed9zvPVfgFE345UhCgcXLjlK9sxLIcyyLAnWDCg+1hj7E7vFyAVBWGtMCSrxQQ5Y qSuGenvsDm/nzYq5Ecs/vYbeBjM18NGEPyHRAUAgCMsFtxFyddC6xcUsVHzbIWPmXNzt dw90ga+Jemye76G/p5FnfZHonvdt9VHn2BOGgyqfKj9m4pRGr9zvrHJWkxxsRjEj1Lpw ZUgCj6jzuWe6hqyPy+/1Tu72JVfoMyRjfCH+A6O4rF0GkBGXCxSkNpTzIyu7h9VrtY2L ZTJPDUpiniTuhjXTC/UlkpKPDOpfBF3+qvt8HHjGxRD57ZuuiE9uAZ0oOsQjnTYsLCHB GnaQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=I6td3WuBBk5Qpr2iJ7wAnroVlDoSyj0rbd0/PnMjxvM=; b=bDz0HZtLez/U71LsEL/Os0BApdWHFjNgUucS4egiD9igLfuF4XVG+K+FNO1kHilOQN HFwJ+umPR9Wo7RSp/0QzZX0qqfyxZqFPVAdbS+yv2g2DKxMItlw6XbWkMLXblslXwEvQ mCV/3eVG7bSAt7a+URDGc1yd60HtYtQ4r1z7x/9cI/VG0o/UxuDX0XZANtGT2rDCAY2C Hz2hSCRBS/7StOsRWCRIPe5oEuTi1F+voKClwy39GzYMKVUP4++ZygC+LixvvzTdxwAG NIBSFO52m3tLEpKCf66iNmndYVJPifr0VBiYZiA9Eqt4RNSS6rjLRq1umICPPnIqRqtF VuHA== X-Gm-Message-State: APjAAAUs2RT9CP0LScz9s60p2vWR4afeCVryoZK/dFcGFW1ah3ZuKHrN UO1268ynTh+2bZJj7fHjHA2MxVqResg= X-Google-Smtp-Source: APXvYqwWcio4EpkiSMPjPx1V1ZNSIO+XAG+g7d14LmJqRPVzigMuxh3okomSefX6pKNw+EKGhJcUdw== X-Received: by 2002:aa7:86c3:: with SMTP id h3mr16344330pfo.169.1556949185156; Fri, 03 May 2019 22:53:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 3 May 2019 22:52:31 -0700 Message-Id: <20190504055300.18426-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190504055300.18426-1-richard.henderson@linaro.org> References: <20190504055300.18426-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::544 Subject: [Qemu-devel] [PATCH v3 02/31] tcg: Do not recreate INDEX_op_neg_vec unless supported X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Use tcg_can_emit_vec_op instead of just TCG_TARGET_HAS_neg_vec, so that we check the type and vece for the actual operation. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- tcg/optimize.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index 5150c38a25..24faa06260 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -734,9 +734,13 @@ void tcg_optimize(TCGContext *s) } else if (opc =3D=3D INDEX_op_sub_i64) { neg_op =3D INDEX_op_neg_i64; have_neg =3D TCG_TARGET_HAS_neg_i64; - } else { + } else if (TCG_TARGET_HAS_neg_vec) { + TCGType type =3D TCGOP_VECL(op) + TCG_TYPE_V64; + unsigned vece =3D TCGOP_VECE(op); neg_op =3D INDEX_op_neg_vec; - have_neg =3D TCG_TARGET_HAS_neg_vec; + have_neg =3D tcg_can_emit_vec_op(neg_op, type, vece) >= 0; + } else { + break; } if (!have_neg) { break; --=20 2.17.1 From nobody Sat May 4 13:31:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1556949326; cv=none; d=zoho.com; s=zohoarc; b=P051EJvv4yQ8stBvtEaFfhNBpjCpKGqxNB6ytY8ay6UZKzNVQhKYL3U5tTXq3F1dJUWV6OUM31jyguheqwy650oyEzSiDDR4tglgnlgzE0HH+cUX8OX3vcm+vUhjPIlo0mXOighjuuevUhkGaE9DNWEuXJ3BC1MMO02kFrgpChE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1556949326; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=70jMM7lEj32hF5MNi2aYGwLWujNJ8i43oE2DiyUoNSA=; b=khDZ7N98jP5pZvosxLaWJopGasy23+nq1E73lseKlFboi9XMlS90bmAW6A9EZOZQcgxXtET2nxmxBnKtkKz6CIQEEfhrVf2N5nU8zNqUtBq7SYlsWsGtADYKXUb80TRnFwcSXsHz9esJf4PEycdEWwRsinKrxptBapMvZIs8M8w= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1556949326268739.2553777208659; Fri, 3 May 2019 22:55:26 -0700 (PDT) Received: from localhost ([127.0.0.1]:51603 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hMndn-0000Ud-4f for importer@patchew.org; Sat, 04 May 2019 01:55:19 -0400 Received: from eggs.gnu.org ([209.51.188.92]:41675) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hMnbj-0007fw-1h for qemu-devel@nongnu.org; Sat, 04 May 2019 01:53:12 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hMnbh-00046d-4S for qemu-devel@nongnu.org; Sat, 04 May 2019 01:53:10 -0400 Received: from mail-pl1-x641.google.com ([2607:f8b0:4864:20::641]:33471) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hMnbg-00041W-S7 for qemu-devel@nongnu.org; Sat, 04 May 2019 01:53:09 -0400 Received: by mail-pl1-x641.google.com with SMTP id y3so3740134plp.0 for ; Fri, 03 May 2019 22:53:07 -0700 (PDT) Received: from localhost.localdomain (97-113-189-189.tukw.qwest.net. [97.113.189.189]) by smtp.gmail.com with ESMTPSA id 15sm6680423pfo.117.2019.05.03.22.53.05 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 03 May 2019 22:53:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=70jMM7lEj32hF5MNi2aYGwLWujNJ8i43oE2DiyUoNSA=; b=sc9EB6UuNpkDpVrzrzpDZg7hMl7IV+9f4U4dOtk3xfkbCtSAA3HH9nrxhgiI/byQ/4 a0REF/qt7EcANcn4/JV+m1gnF9zygmcqZahBEBt8/hGvNba6eL0Sn4WwbMt7g1iCb/lz 0K7qdJJuwTMXCzLFLIuEI/WotvS5wXI5U9Wo4f3v/uPnCDdCAX4Ft9+tmOd09mns8l5j OQhUPVCnLFXnCJdk+jg4+k/Oa8Ps1y9+Er+9GCGuBKZUOCr7aOVaK6DTecIdR2Xq2aKW 9T48wf/CmHiUT9hY74rR8LccMK3oZ+1BZi4MRujWwMe4TPqszSEhRF3NAd1jqjcLvOSy rvaA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=70jMM7lEj32hF5MNi2aYGwLWujNJ8i43oE2DiyUoNSA=; b=uQTz7M2yjY2V2Iwppc3E9XczLXGXc/TOuL/hJsx7l150orGgXhPyfAzp9XU2p0dpuH 5mp6CVip1wM934j2pIimnH/CPyyOQ9aSp6cXBxNK03Q8TY5+jksQlXrVRC3RNiFnRdf0 jT8lMaT/ymobBy47AgzZE3uf9RBjN1KqqFDUXH4exrojtDyEkxXEmczVTsk5mvNtMoyl NeDZcs+D0FgFjG8Q5rrCTinO7Huv7pmRIthBlCouh9I/VCsc22YwcT3JGk5jllzAm78C RbiPXmRAkMX0jMK0OFU9eihVvzZ8sYIEiHmBhhGMU5qsszCEzi98EPx02QHpZEYvMBjI 49Dg== X-Gm-Message-State: APjAAAVmC82AGPP0hkZBBDbXNVWtoLScyONk7ODsFHByq5JxnpvOsai8 sNRKp6o+k0Jm706at7QxWpcR90H6hrA= X-Google-Smtp-Source: APXvYqw0eWYkmI0YSBqpqSTdi4Em9L/MWvx4eQ0hNYtmWc67jfoXsH+ZHGIzuFtovacV/fSB+GSizg== X-Received: by 2002:a17:902:b582:: with SMTP id a2mr7896788pls.287.1556949186211; Fri, 03 May 2019 22:53:06 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 3 May 2019 22:52:32 -0700 Message-Id: <20190504055300.18426-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190504055300.18426-1-richard.henderson@linaro.org> References: <20190504055300.18426-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::641 Subject: [Qemu-devel] [PATCH v3 03/31] tcg: Allow add_vec, sub_vec, neg_vec, not_vec to be expanded X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Reviewed-by: Alex Benn=C3=A9e Reviewed-by: David Hildenbrand Signed-off-by: Richard Henderson --- tcg/tcg-op-vec.c | 49 ++++++++++++++++++++++++++++++++---------------- 1 file changed, 33 insertions(+), 16 deletions(-) diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c index 27f65600c3..cfb18682b1 100644 --- a/tcg/tcg-op-vec.c +++ b/tcg/tcg-op-vec.c @@ -226,16 +226,6 @@ void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr b, TCGArg o,= TCGType low_type) vec_gen_3(INDEX_op_st_vec, low_type, 0, ri, bi, o); } =20 -void tcg_gen_add_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) -{ - vec_gen_op3(INDEX_op_add_vec, vece, r, a, b); -} - -void tcg_gen_sub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) -{ - vec_gen_op3(INDEX_op_sub_vec, vece, r, a, b); -} - void tcg_gen_and_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) { vec_gen_op3(INDEX_op_and_vec, 0, r, a, b); @@ -296,11 +286,30 @@ void tcg_gen_eqv_vec(unsigned vece, TCGv_vec r, TCGv_= vec a, TCGv_vec b) tcg_gen_not_vec(0, r, r); } =20 +static bool do_op2(unsigned vece, TCGv_vec r, TCGv_vec a, TCGOpcode opc) +{ + TCGTemp *rt =3D tcgv_vec_temp(r); + TCGTemp *at =3D tcgv_vec_temp(a); + TCGArg ri =3D temp_arg(rt); + TCGArg ai =3D temp_arg(at); + TCGType type =3D rt->base_type; + int can; + + tcg_debug_assert(at->base_type >=3D type); + can =3D tcg_can_emit_vec_op(opc, type, vece); + if (can > 0) { + vec_gen_2(opc, type, vece, ri, ai); + } else if (can < 0) { + tcg_expand_vec_op(opc, type, vece, ri, ai); + } else { + return false; + } + return true; +} + void tcg_gen_not_vec(unsigned vece, TCGv_vec r, TCGv_vec a) { - if (TCG_TARGET_HAS_not_vec) { - vec_gen_op2(INDEX_op_not_vec, 0, r, a); - } else { + if (!TCG_TARGET_HAS_not_vec || !do_op2(vece, r, a, INDEX_op_not_vec)) { TCGv_vec t =3D tcg_const_ones_vec_matching(r); tcg_gen_xor_vec(0, r, a, t); tcg_temp_free_vec(t); @@ -309,9 +318,7 @@ void tcg_gen_not_vec(unsigned vece, TCGv_vec r, TCGv_ve= c a) =20 void tcg_gen_neg_vec(unsigned vece, TCGv_vec r, TCGv_vec a) { - if (TCG_TARGET_HAS_neg_vec) { - vec_gen_op2(INDEX_op_neg_vec, vece, r, a); - } else { + if (!TCG_TARGET_HAS_neg_vec || !do_op2(vece, r, a, INDEX_op_neg_vec)) { TCGv_vec t =3D tcg_const_zeros_vec_matching(r); tcg_gen_sub_vec(vece, r, t, a); tcg_temp_free_vec(t); @@ -409,6 +416,16 @@ static void do_op3(unsigned vece, TCGv_vec r, TCGv_vec= a, } } =20 +void tcg_gen_add_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) +{ + do_op3(vece, r, a, b, INDEX_op_add_vec); +} + +void tcg_gen_sub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) +{ + do_op3(vece, r, a, b, INDEX_op_sub_vec); +} + void tcg_gen_mul_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) { do_op3(vece, r, a, b, INDEX_op_mul_vec); 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[97.113.189.189]) by smtp.gmail.com with ESMTPSA id 15sm6680423pfo.117.2019.05.03.22.53.06 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 03 May 2019 22:53:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2Yt9jxfcocc7EEYdmcxBesnYjXMi5ulWqxd6ruvHuEc=; b=VXLbk/LpFqN5rEHQt1UdxZUX+fkm+P9e3EkonQztpw1+NlAoF5Z3DlvF+FdJIrWE1m YitjkTEBE5teZlXvDB0+UKRlwT949seup3vrTVvJ1gJnoSjsdz5Js9i4gTHzWpcJz2BW qHv97Wlq12MFE8hdE0VomAZtzLIUXtBzN4NBt4EK7ap8FV7oao1PsAUaISUChzvtQWrb gtBcfOZXUQs6Y884HJJeIG+wvPKJQ4k3Ginl9M7QHpKVVS3M8QNquhsGw5FLm9I+yfNY v9pFPQ5YLgeOsLSwlaWgCoHb8hmgsCxRcAY2xfNnwWhrPzn5iYMSf5hx+ckQUKTWQXm5 bO9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=2Yt9jxfcocc7EEYdmcxBesnYjXMi5ulWqxd6ruvHuEc=; b=CoT/bkVac1cOymZIP4871Uo0n4pq9Bjk96H6P6HtKoZ4hqseobr/ZgZT6WT/EamsmD VuVexJs0a7IoagI1/O2/KnbKyKto24oogqdEMoQM74BAO+QMpyVbx8+PcldJvIYgyxyD VeP7PBDwANqGNsjM0e1wwJn+BSKg4/Nb/E3v/uRwqX1k7GMBplFeOCMtCewFaYkeRqSr DBZCtbYNpyrEVHMMLHB+1ezgh5gYhJ+U8vCGlDEYaRfBFYBJqg9lpUbT8bo7AOztwFEj PsK63ztcvWV0ePoZb5aNJVfWzFbQ88+iK1KzL+xcNZJSgARlhtFpspVR3okBKS/rJroI aAGA== X-Gm-Message-State: APjAAAXJfuAzTPKXv6tL/vDlKPx0Tkt34wMVxE33fABbKaFGCqUsV7B9 kLLKVq6zIbwmg4j8rgi0ABn1vuVnat0= X-Google-Smtp-Source: APXvYqwwlpE/drGTb3BUh2Tv2faCKD8IGz4G9GXrnp/joZqWPJwpBDXKOK+klB5YTkssM2MYtmvPSA== X-Received: by 2002:a17:902:1d4a:: with SMTP id u10mr11484012plu.272.1556949187534; Fri, 03 May 2019 22:53:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 3 May 2019 22:52:33 -0700 Message-Id: <20190504055300.18426-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190504055300.18426-1-richard.henderson@linaro.org> References: <20190504055300.18426-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 Subject: [Qemu-devel] [PATCH v3 04/31] tcg: Specify optional vector requirements with a list X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Replace the single opcode in .opc with a null-terminated array in .opt_opc. We still require that all opcodes be used with the same .vece. Validate the contents of this list with CONFIG_DEBUG_TCG. All tcg_gen_*_vec functions will check any list active during .fniv expansion. Swap the active list in and out as we expand other opcodes, or take control away from the front-end function. Convert all existing vector aware front ends. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- tcg/tcg-op-gvec.h | 24 +-- tcg/tcg.h | 20 +++ target/arm/translate-sve.c | 9 +- target/arm/translate.c | 123 +++++++++----- target/ppc/translate/vmx-impl.inc.c | 7 +- tcg/tcg-op-gvec.c | 249 ++++++++++++++++------------ tcg/tcg-op-vec.c | 102 ++++++++++++ 7 files changed, 372 insertions(+), 162 deletions(-) diff --git a/tcg/tcg-op-gvec.h b/tcg/tcg-op-gvec.h index c093243c4c..ac744ff7c9 100644 --- a/tcg/tcg-op-gvec.h +++ b/tcg/tcg-op-gvec.h @@ -91,8 +91,8 @@ typedef struct { void (*fniv)(unsigned, TCGv_vec, TCGv_vec); /* Expand out-of-line helper w/descriptor. */ gen_helper_gvec_2 *fno; - /* The opcode, if any, to which this corresponds. */ - TCGOpcode opc; + /* The optional opcodes, if any, utilized by .fniv. */ + const TCGOpcode *opt_opc; /* The data argument to the out-of-line helper. */ int32_t data; /* The vector element size, if applicable. */ @@ -112,8 +112,8 @@ typedef struct { gen_helper_gvec_2 *fno; /* Expand out-of-line helper w/descriptor, data as argument. */ gen_helper_gvec_2i *fnoi; - /* The opcode, if any, to which this corresponds. */ - TCGOpcode opc; + /* The optional opcodes, if any, utilized by .fniv. */ + const TCGOpcode *opt_opc; /* The vector element size, if applicable. */ uint8_t vece; /* Prefer i64 to v64. */ @@ -131,8 +131,8 @@ typedef struct { void (*fniv)(unsigned, TCGv_vec, TCGv_vec, TCGv_vec); /* Expand out-of-line helper w/descriptor. */ gen_helper_gvec_2i *fno; - /* The opcode, if any, to which this corresponds. */ - TCGOpcode opc; + /* The optional opcodes, if any, utilized by .fniv. */ + const TCGOpcode *opt_opc; /* The data argument to the out-of-line helper. */ uint32_t data; /* The vector element size, if applicable. */ @@ -152,8 +152,8 @@ typedef struct { void (*fniv)(unsigned, TCGv_vec, TCGv_vec, TCGv_vec); /* Expand out-of-line helper w/descriptor. */ gen_helper_gvec_3 *fno; - /* The opcode, if any, to which this corresponds. */ - TCGOpcode opc; + /* The optional opcodes, if any, utilized by .fniv. */ + const TCGOpcode *opt_opc; /* The data argument to the out-of-line helper. */ int32_t data; /* The vector element size, if applicable. */ @@ -175,8 +175,8 @@ typedef struct { void (*fniv)(unsigned, TCGv_vec, TCGv_vec, TCGv_vec, int64_t); /* Expand out-of-line helper w/descriptor, data in descriptor. */ gen_helper_gvec_3 *fno; - /* The opcode, if any, to which this corresponds. */ - TCGOpcode opc; + /* The optional opcodes, if any, utilized by .fniv. */ + const TCGOpcode *opt_opc; /* The vector element size, if applicable. */ uint8_t vece; /* Prefer i64 to v64. */ @@ -194,8 +194,8 @@ typedef struct { void (*fniv)(unsigned, TCGv_vec, TCGv_vec, TCGv_vec, TCGv_vec); /* Expand out-of-line helper w/descriptor. */ gen_helper_gvec_4 *fno; - /* The opcode, if any, to which this corresponds. */ - TCGOpcode opc; + /* The optional opcodes, if any, utilized by .fniv. */ + const TCGOpcode *opt_opc; /* The data argument to the out-of-line helper. */ int32_t data; /* The vector element size, if applicable. */ diff --git a/tcg/tcg.h b/tcg/tcg.h index cfc57110a1..2c7315da25 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -692,6 +692,7 @@ struct TCGContext { #ifdef CONFIG_DEBUG_TCG int temps_in_use; int goto_tb_issue_mask; + const TCGOpcode *vecop_list; #endif =20 /* Code generation. Note that we specifically do not use tcg_insn_unit @@ -1492,4 +1493,23 @@ void helper_atomic_sto_le_mmu(CPUArchState *env, tar= get_ulong addr, Int128 val, void helper_atomic_sto_be_mmu(CPUArchState *env, target_ulong addr, Int128= val, TCGMemOpIdx oi, uintptr_t retaddr); =20 +#ifdef CONFIG_DEBUG_TCG +void tcg_assert_listed_vecop(TCGOpcode); +#else +static inline void tcg_assert_listed_vecop(TCGOpcode op) { } +#endif + +static inline const TCGOpcode *tcg_swap_vecop_list(const TCGOpcode *n) +{ +#ifdef CONFIG_DEBUG_TCG + const TCGOpcode *o =3D tcg_ctx->vecop_list; + tcg_ctx->vecop_list =3D n; + return o; +#else + return NULL; +#endif +} + +bool tcg_can_emit_vecop_list(const TCGOpcode *, TCGType, unsigned); + #endif /* TCG_H */ diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 245cd82621..0682c0d32b 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -3302,29 +3302,30 @@ static bool trans_SUB_zzi(DisasContext *s, arg_rri_= esz *a) =20 static bool trans_SUBR_zzi(DisasContext *s, arg_rri_esz *a) { + static const TCGOpcode vecop_list[] =3D { INDEX_op_sub_vec, 0 }; static const GVecGen2s op[4] =3D { { .fni8 =3D tcg_gen_vec_sub8_i64, .fniv =3D tcg_gen_sub_vec, .fno =3D gen_helper_sve_subri_b, - .opc =3D INDEX_op_sub_vec, + .opt_opc =3D vecop_list, .vece =3D MO_8, .scalar_first =3D true }, { .fni8 =3D tcg_gen_vec_sub16_i64, .fniv =3D tcg_gen_sub_vec, .fno =3D gen_helper_sve_subri_h, - .opc =3D INDEX_op_sub_vec, + .opt_opc =3D vecop_list, .vece =3D MO_16, .scalar_first =3D true }, { .fni4 =3D tcg_gen_sub_i32, .fniv =3D tcg_gen_sub_vec, .fno =3D gen_helper_sve_subri_s, - .opc =3D INDEX_op_sub_vec, + .opt_opc =3D vecop_list, .vece =3D MO_32, .scalar_first =3D true }, { .fni8 =3D tcg_gen_sub_i64, .fniv =3D tcg_gen_sub_vec, .fno =3D gen_helper_sve_subri_d, - .opc =3D INDEX_op_sub_vec, + .opt_opc =3D vecop_list, .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, .vece =3D MO_64, .scalar_first =3D true } diff --git a/target/arm/translate.c b/target/arm/translate.c index 10bc53f91c..35bd426a3d 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -5861,27 +5861,31 @@ static void gen_ssra_vec(unsigned vece, TCGv_vec d,= TCGv_vec a, int64_t sh) tcg_gen_add_vec(vece, d, d, a); } =20 +static const TCGOpcode vecop_list_ssra[] =3D { + INDEX_op_sari_vec, INDEX_op_add_vec, 0 +}; + const GVecGen2i ssra_op[4] =3D { { .fni8 =3D gen_ssra8_i64, .fniv =3D gen_ssra_vec, .load_dest =3D true, - .opc =3D INDEX_op_sari_vec, + .opt_opc =3D vecop_list_ssra, .vece =3D MO_8 }, { .fni8 =3D gen_ssra16_i64, .fniv =3D gen_ssra_vec, .load_dest =3D true, - .opc =3D INDEX_op_sari_vec, + .opt_opc =3D vecop_list_ssra, .vece =3D MO_16 }, { .fni4 =3D gen_ssra32_i32, .fniv =3D gen_ssra_vec, .load_dest =3D true, - .opc =3D INDEX_op_sari_vec, + .opt_opc =3D vecop_list_ssra, .vece =3D MO_32 }, { .fni8 =3D gen_ssra64_i64, .fniv =3D gen_ssra_vec, .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .opt_opc =3D vecop_list_ssra, .load_dest =3D true, - .opc =3D INDEX_op_sari_vec, .vece =3D MO_64 }, }; =20 @@ -5915,27 +5919,31 @@ static void gen_usra_vec(unsigned vece, TCGv_vec d,= TCGv_vec a, int64_t sh) tcg_gen_add_vec(vece, d, d, a); } =20 +static const TCGOpcode vecop_list_usra[] =3D { + INDEX_op_shri_vec, INDEX_op_add_vec, 0 +}; + const GVecGen2i usra_op[4] =3D { { .fni8 =3D gen_usra8_i64, .fniv =3D gen_usra_vec, .load_dest =3D true, - .opc =3D INDEX_op_shri_vec, + .opt_opc =3D vecop_list_usra, .vece =3D MO_8, }, { .fni8 =3D gen_usra16_i64, .fniv =3D gen_usra_vec, .load_dest =3D true, - .opc =3D INDEX_op_shri_vec, + .opt_opc =3D vecop_list_usra, .vece =3D MO_16, }, { .fni4 =3D gen_usra32_i32, .fniv =3D gen_usra_vec, .load_dest =3D true, - .opc =3D INDEX_op_shri_vec, + .opt_opc =3D vecop_list_usra, .vece =3D MO_32, }, { .fni8 =3D gen_usra64_i64, .fniv =3D gen_usra_vec, .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, .load_dest =3D true, - .opc =3D INDEX_op_shri_vec, + .opt_opc =3D vecop_list_usra, .vece =3D MO_64, }, }; =20 @@ -5993,27 +6001,29 @@ static void gen_shr_ins_vec(unsigned vece, TCGv_vec= d, TCGv_vec a, int64_t sh) } } =20 +static const TCGOpcode vecop_list_sri[] =3D { INDEX_op_shri_vec, 0 }; + const GVecGen2i sri_op[4] =3D { { .fni8 =3D gen_shr8_ins_i64, .fniv =3D gen_shr_ins_vec, .load_dest =3D true, - .opc =3D INDEX_op_shri_vec, + .opt_opc =3D vecop_list_sri, .vece =3D MO_8 }, { .fni8 =3D gen_shr16_ins_i64, .fniv =3D gen_shr_ins_vec, .load_dest =3D true, - .opc =3D INDEX_op_shri_vec, + .opt_opc =3D vecop_list_sri, .vece =3D MO_16 }, { .fni4 =3D gen_shr32_ins_i32, .fniv =3D gen_shr_ins_vec, .load_dest =3D true, - .opc =3D INDEX_op_shri_vec, + .opt_opc =3D vecop_list_sri, .vece =3D MO_32 }, { .fni8 =3D gen_shr64_ins_i64, .fniv =3D gen_shr_ins_vec, .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, .load_dest =3D true, - .opc =3D INDEX_op_shri_vec, + .opt_opc =3D vecop_list_sri, .vece =3D MO_64 }, }; =20 @@ -6069,27 +6079,29 @@ static void gen_shl_ins_vec(unsigned vece, TCGv_vec= d, TCGv_vec a, int64_t sh) } } =20 +static const TCGOpcode vecop_list_sli[] =3D { INDEX_op_shli_vec, 0 }; + const GVecGen2i sli_op[4] =3D { { .fni8 =3D gen_shl8_ins_i64, .fniv =3D gen_shl_ins_vec, .load_dest =3D true, - .opc =3D INDEX_op_shli_vec, + .opt_opc =3D vecop_list_sli, .vece =3D MO_8 }, { .fni8 =3D gen_shl16_ins_i64, .fniv =3D gen_shl_ins_vec, .load_dest =3D true, - .opc =3D INDEX_op_shli_vec, + .opt_opc =3D vecop_list_sli, .vece =3D MO_16 }, { .fni4 =3D gen_shl32_ins_i32, .fniv =3D gen_shl_ins_vec, .load_dest =3D true, - .opc =3D INDEX_op_shli_vec, + .opt_opc =3D vecop_list_sli, .vece =3D MO_32 }, { .fni8 =3D gen_shl64_ins_i64, .fniv =3D gen_shl_ins_vec, .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, .load_dest =3D true, - .opc =3D INDEX_op_shli_vec, + .opt_opc =3D vecop_list_sli, .vece =3D MO_64 }, }; =20 @@ -6156,51 +6168,60 @@ static void gen_mls_vec(unsigned vece, TCGv_vec d, = TCGv_vec a, TCGv_vec b) /* Note that while NEON does not support VMLA and VMLS as 64-bit ops, * these tables are shared with AArch64 which does support them. */ + +static const TCGOpcode vecop_list_mla[] =3D { + INDEX_op_mul_vec, INDEX_op_add_vec, 0 +}; + +static const TCGOpcode vecop_list_mls[] =3D { + INDEX_op_mul_vec, INDEX_op_sub_vec, 0 +}; + const GVecGen3 mla_op[4] =3D { { .fni4 =3D gen_mla8_i32, .fniv =3D gen_mla_vec, - .opc =3D INDEX_op_mul_vec, .load_dest =3D true, + .opt_opc =3D vecop_list_mla, .vece =3D MO_8 }, { .fni4 =3D gen_mla16_i32, .fniv =3D gen_mla_vec, - .opc =3D INDEX_op_mul_vec, .load_dest =3D true, + .opt_opc =3D vecop_list_mla, .vece =3D MO_16 }, { .fni4 =3D gen_mla32_i32, .fniv =3D gen_mla_vec, - .opc =3D INDEX_op_mul_vec, .load_dest =3D true, + .opt_opc =3D vecop_list_mla, .vece =3D MO_32 }, { .fni8 =3D gen_mla64_i64, .fniv =3D gen_mla_vec, - .opc =3D INDEX_op_mul_vec, .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, .load_dest =3D true, + .opt_opc =3D vecop_list_mla, .vece =3D MO_64 }, }; =20 const GVecGen3 mls_op[4] =3D { { .fni4 =3D gen_mls8_i32, .fniv =3D gen_mls_vec, - .opc =3D INDEX_op_mul_vec, .load_dest =3D true, + .opt_opc =3D vecop_list_mls, .vece =3D MO_8 }, { .fni4 =3D gen_mls16_i32, .fniv =3D gen_mls_vec, - .opc =3D INDEX_op_mul_vec, .load_dest =3D true, + .opt_opc =3D vecop_list_mls, .vece =3D MO_16 }, { .fni4 =3D gen_mls32_i32, .fniv =3D gen_mls_vec, - .opc =3D INDEX_op_mul_vec, .load_dest =3D true, + .opt_opc =3D vecop_list_mls, .vece =3D MO_32 }, { .fni8 =3D gen_mls64_i64, .fniv =3D gen_mls_vec, - .opc =3D INDEX_op_mul_vec, .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, .load_dest =3D true, + .opt_opc =3D vecop_list_mls, .vece =3D MO_64 }, }; =20 @@ -6226,19 +6247,25 @@ static void gen_cmtst_vec(unsigned vece, TCGv_vec d= , TCGv_vec a, TCGv_vec b) tcg_gen_cmp_vec(TCG_COND_NE, vece, d, d, a); } =20 +static const TCGOpcode vecop_list_cmtst[] =3D { INDEX_op_cmp_vec, 0 }; + const GVecGen3 cmtst_op[4] =3D { { .fni4 =3D gen_helper_neon_tst_u8, .fniv =3D gen_cmtst_vec, + .opt_opc =3D vecop_list_cmtst, .vece =3D MO_8 }, { .fni4 =3D gen_helper_neon_tst_u16, .fniv =3D gen_cmtst_vec, + .opt_opc =3D vecop_list_cmtst, .vece =3D MO_16 }, { .fni4 =3D gen_cmtst_i32, .fniv =3D gen_cmtst_vec, + .opt_opc =3D vecop_list_cmtst, .vece =3D MO_32 }, { .fni8 =3D gen_cmtst_i64, .fniv =3D gen_cmtst_vec, .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .opt_opc =3D vecop_list_cmtst, .vece =3D MO_64 }, }; =20 @@ -6253,26 +6280,30 @@ static void gen_uqadd_vec(unsigned vece, TCGv_vec t= , TCGv_vec sat, tcg_temp_free_vec(x); } =20 +static const TCGOpcode vecop_list_uqadd[] =3D { + INDEX_op_usadd_vec, INDEX_op_cmp_vec, INDEX_op_add_vec, 0 +}; + const GVecGen4 uqadd_op[4] =3D { { .fniv =3D gen_uqadd_vec, .fno =3D gen_helper_gvec_uqadd_b, - .opc =3D INDEX_op_usadd_vec, .write_aofs =3D true, + .opt_opc =3D vecop_list_uqadd, .vece =3D MO_8 }, { .fniv =3D gen_uqadd_vec, .fno =3D gen_helper_gvec_uqadd_h, - .opc =3D INDEX_op_usadd_vec, .write_aofs =3D true, + .opt_opc =3D vecop_list_uqadd, .vece =3D MO_16 }, { .fniv =3D gen_uqadd_vec, .fno =3D gen_helper_gvec_uqadd_s, - .opc =3D INDEX_op_usadd_vec, .write_aofs =3D true, + .opt_opc =3D vecop_list_uqadd, .vece =3D MO_32 }, { .fniv =3D gen_uqadd_vec, .fno =3D gen_helper_gvec_uqadd_d, - .opc =3D INDEX_op_usadd_vec, .write_aofs =3D true, + .opt_opc =3D vecop_list_uqadd, .vece =3D MO_64 }, }; =20 @@ -6287,25 +6318,29 @@ static void gen_sqadd_vec(unsigned vece, TCGv_vec t= , TCGv_vec sat, tcg_temp_free_vec(x); } =20 +static const TCGOpcode vecop_list_sqadd[] =3D { + INDEX_op_ssadd_vec, INDEX_op_cmp_vec, INDEX_op_add_vec, 0 +}; + const GVecGen4 sqadd_op[4] =3D { { .fniv =3D gen_sqadd_vec, .fno =3D gen_helper_gvec_sqadd_b, - .opc =3D INDEX_op_ssadd_vec, + .opt_opc =3D vecop_list_sqadd, .write_aofs =3D true, .vece =3D MO_8 }, { .fniv =3D gen_sqadd_vec, .fno =3D gen_helper_gvec_sqadd_h, - .opc =3D INDEX_op_ssadd_vec, + .opt_opc =3D vecop_list_sqadd, .write_aofs =3D true, .vece =3D MO_16 }, { .fniv =3D gen_sqadd_vec, .fno =3D gen_helper_gvec_sqadd_s, - .opc =3D INDEX_op_ssadd_vec, + .opt_opc =3D vecop_list_sqadd, .write_aofs =3D true, .vece =3D MO_32 }, { .fniv =3D gen_sqadd_vec, .fno =3D gen_helper_gvec_sqadd_d, - .opc =3D INDEX_op_ssadd_vec, + .opt_opc =3D vecop_list_sqadd, .write_aofs =3D true, .vece =3D MO_64 }, }; @@ -6321,25 +6356,29 @@ static void gen_uqsub_vec(unsigned vece, TCGv_vec t= , TCGv_vec sat, tcg_temp_free_vec(x); } =20 +static const TCGOpcode vecop_list_uqsub[] =3D { + INDEX_op_ussub_vec, INDEX_op_cmp_vec, INDEX_op_sub_vec, 0 +}; + const GVecGen4 uqsub_op[4] =3D { { .fniv =3D gen_uqsub_vec, .fno =3D gen_helper_gvec_uqsub_b, - .opc =3D INDEX_op_ussub_vec, + .opt_opc =3D vecop_list_uqsub, .write_aofs =3D true, .vece =3D MO_8 }, { .fniv =3D gen_uqsub_vec, .fno =3D gen_helper_gvec_uqsub_h, - .opc =3D INDEX_op_ussub_vec, + .opt_opc =3D vecop_list_uqsub, .write_aofs =3D true, .vece =3D MO_16 }, { .fniv =3D gen_uqsub_vec, .fno =3D gen_helper_gvec_uqsub_s, - .opc =3D INDEX_op_ussub_vec, + .opt_opc =3D vecop_list_uqsub, .write_aofs =3D true, .vece =3D MO_32 }, { .fniv =3D gen_uqsub_vec, .fno =3D gen_helper_gvec_uqsub_d, - .opc =3D INDEX_op_ussub_vec, + .opt_opc =3D vecop_list_uqsub, .write_aofs =3D true, .vece =3D MO_64 }, }; @@ -6355,25 +6394,29 @@ static void gen_sqsub_vec(unsigned vece, TCGv_vec t= , TCGv_vec sat, tcg_temp_free_vec(x); } =20 +static const TCGOpcode vecop_list_sqsub[] =3D { + INDEX_op_sssub_vec, INDEX_op_cmp_vec, INDEX_op_sub_vec, 0 +}; + const GVecGen4 sqsub_op[4] =3D { { .fniv =3D gen_sqsub_vec, .fno =3D gen_helper_gvec_sqsub_b, - .opc =3D INDEX_op_sssub_vec, + .opt_opc =3D vecop_list_sqsub, .write_aofs =3D true, .vece =3D MO_8 }, { .fniv =3D gen_sqsub_vec, .fno =3D gen_helper_gvec_sqsub_h, - .opc =3D INDEX_op_sssub_vec, + .opt_opc =3D vecop_list_sqsub, .write_aofs =3D true, .vece =3D MO_16 }, { .fniv =3D gen_sqsub_vec, .fno =3D gen_helper_gvec_sqsub_s, - .opc =3D INDEX_op_sssub_vec, + .opt_opc =3D vecop_list_sqsub, .write_aofs =3D true, .vece =3D MO_32 }, { .fniv =3D gen_sqsub_vec, .fno =3D gen_helper_gvec_sqsub_d, - .opc =3D INDEX_op_sssub_vec, + .opt_opc =3D vecop_list_sqsub, .write_aofs =3D true, .vece =3D MO_64 }, }; diff --git a/target/ppc/translate/vmx-impl.inc.c b/target/ppc/translate/vmx= -impl.inc.c index bd3ff40e68..6861f4c5b9 100644 --- a/target/ppc/translate/vmx-impl.inc.c +++ b/target/ppc/translate/vmx-impl.inc.c @@ -566,10 +566,15 @@ static void glue(glue(gen_, NAME), _vec)(unsigned vec= e, TCGv_vec t, \ } \ static void glue(gen_, NAME)(DisasContext *ctx) \ { \ + static const TCGOpcode vecop_list[] =3D { \ + glue(glue(INDEX_op_, NORM), _vec), \ + glue(glue(INDEX_op_, SAT), _vec), \ + INDEX_op_cmp_vec, 0 \ + }; \ static const GVecGen4 g =3D { \ .fniv =3D glue(glue(gen_, NAME), _vec), \ .fno =3D glue(gen_helper_, NAME), \ - .opc =3D glue(glue(INDEX_op_, SAT), _vec), \ + .opt_opc =3D vecop_list, \ .write_aofs =3D true, \ .vece =3D VECE, \ }; \ diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c index f831adb4e7..3fcb2352d9 100644 --- a/tcg/tcg-op-gvec.c +++ b/tcg/tcg-op-gvec.c @@ -26,6 +26,13 @@ =20 #define MAX_UNROLL 4 =20 +#ifdef CONFIG_DEBUG_TCG +static const TCGOpcode vecop_list_empty[1] =3D { 0 }; +#else +#define vecop_list_empty NULL +#endif + + /* Verify vector size and alignment rules. OFS should be the OR of all of the operand offsets so that we can check them all at once. */ static void check_size_align(uint32_t oprsz, uint32_t maxsz, uint32_t ofs) @@ -360,31 +367,29 @@ static void gen_dup_i64(unsigned vece, TCGv_i64 out, = TCGv_i64 in) * on elements of size VECE in the selected type. Do not select V64 if * PREFER_I64 is true. Return 0 if no vector type is selected. */ -static TCGType choose_vector_type(TCGOpcode op, unsigned vece, uint32_t si= ze, - bool prefer_i64) +static TCGType choose_vector_type(const TCGOpcode *list, unsigned vece, + uint32_t size, bool prefer_i64) { if (TCG_TARGET_HAS_v256 && check_size_impl(size, 32)) { - if (op =3D=3D 0) { - return TCG_TYPE_V256; - } - /* Recall that ARM SVE allows vector sizes that are not a + /* + * Recall that ARM SVE allows vector sizes that are not a * power of 2, but always a multiple of 16. The intent is * that e.g. size =3D=3D 80 would be expanded with 2x32 + 1x16. * It is hard to imagine a case in which v256 is supported * but v128 is not, but check anyway. */ - if (tcg_can_emit_vec_op(op, TCG_TYPE_V256, vece) + if (tcg_can_emit_vecop_list(list, TCG_TYPE_V256, vece) && (size % 32 =3D=3D 0 - || tcg_can_emit_vec_op(op, TCG_TYPE_V128, vece))) { + || tcg_can_emit_vecop_list(list, TCG_TYPE_V128, vece))) { return TCG_TYPE_V256; } } if (TCG_TARGET_HAS_v128 && check_size_impl(size, 16) - && (op =3D=3D 0 || tcg_can_emit_vec_op(op, TCG_TYPE_V128, vece))) { + && tcg_can_emit_vecop_list(list, TCG_TYPE_V128, vece)) { return TCG_TYPE_V128; } if (TCG_TARGET_HAS_v64 && !prefer_i64 && check_size_impl(size, 8) - && (op =3D=3D 0 || tcg_can_emit_vec_op(op, TCG_TYPE_V64, vece))) { + && tcg_can_emit_vecop_list(list, TCG_TYPE_V64, vece)) { return TCG_TYPE_V64; } return 0; @@ -418,7 +423,7 @@ static void do_dup(unsigned vece, uint32_t dofs, uint32= _t oprsz, /* Implement inline with a vector type, if possible. * Prefer integer when 64-bit host and no variable dup. */ - type =3D choose_vector_type(0, vece, oprsz, + type =3D choose_vector_type(NULL, vece, oprsz, (TCG_TARGET_REG_BITS =3D=3D 64 && in_32 =3D= =3D NULL && (in_64 =3D=3D NULL || vece =3D=3D MO_64)= )); if (type !=3D 0) { @@ -991,6 +996,8 @@ static void expand_4_vec(unsigned vece, uint32_t dofs, = uint32_t aofs, void tcg_gen_gvec_2(uint32_t dofs, uint32_t aofs, uint32_t oprsz, uint32_t maxsz, const GVecGen2 *g) { + const TCGOpcode *this_list =3D g->opt_opc ? : vecop_list_empty; + const TCGOpcode *hold_list =3D tcg_swap_vecop_list(this_list); TCGType type; uint32_t some; =20 @@ -999,7 +1006,7 @@ void tcg_gen_gvec_2(uint32_t dofs, uint32_t aofs, =20 type =3D 0; if (g->fniv) { - type =3D choose_vector_type(g->opc, g->vece, oprsz, g->prefer_i64); + type =3D choose_vector_type(g->opt_opc, g->vece, oprsz, g->prefer_= i64); } switch (type) { case TCG_TYPE_V256: @@ -1032,13 +1039,14 @@ void tcg_gen_gvec_2(uint32_t dofs, uint32_t aofs, } else { assert(g->fno !=3D NULL); tcg_gen_gvec_2_ool(dofs, aofs, oprsz, maxsz, g->data, g->fno); - return; + oprsz =3D maxsz; } break; =20 default: g_assert_not_reached(); } + tcg_swap_vecop_list(hold_list); =20 if (oprsz < maxsz) { expand_clr(dofs + oprsz, maxsz - oprsz); @@ -1049,6 +1057,8 @@ void tcg_gen_gvec_2(uint32_t dofs, uint32_t aofs, void tcg_gen_gvec_2i(uint32_t dofs, uint32_t aofs, uint32_t oprsz, uint32_t maxsz, int64_t c, const GVecGen2i *g) { + const TCGOpcode *this_list =3D g->opt_opc ? : vecop_list_empty; + const TCGOpcode *hold_list =3D tcg_swap_vecop_list(this_list); TCGType type; uint32_t some; =20 @@ -1057,7 +1067,7 @@ void tcg_gen_gvec_2i(uint32_t dofs, uint32_t aofs, ui= nt32_t oprsz, =20 type =3D 0; if (g->fniv) { - type =3D choose_vector_type(g->opc, g->vece, oprsz, g->prefer_i64); + type =3D choose_vector_type(g->opt_opc, g->vece, oprsz, g->prefer_= i64); } switch (type) { case TCG_TYPE_V256: @@ -1099,13 +1109,14 @@ void tcg_gen_gvec_2i(uint32_t dofs, uint32_t aofs, = uint32_t oprsz, maxsz, c, g->fnoi); tcg_temp_free_i64(tcg_c); } - return; + oprsz =3D maxsz; } break; =20 default: g_assert_not_reached(); } + tcg_swap_vecop_list(hold_list); =20 if (oprsz < maxsz) { expand_clr(dofs + oprsz, maxsz - oprsz); @@ -1123,9 +1134,11 @@ void tcg_gen_gvec_2s(uint32_t dofs, uint32_t aofs, u= int32_t oprsz, =20 type =3D 0; if (g->fniv) { - type =3D choose_vector_type(g->opc, g->vece, oprsz, g->prefer_i64); + type =3D choose_vector_type(g->opt_opc, g->vece, oprsz, g->prefer_= i64); } if (type !=3D 0) { + const TCGOpcode *this_list =3D g->opt_opc ? : vecop_list_empty; + const TCGOpcode *hold_list =3D tcg_swap_vecop_list(this_list); TCGv_vec t_vec =3D tcg_temp_new_vec(type); uint32_t some; =20 @@ -1163,6 +1176,7 @@ void tcg_gen_gvec_2s(uint32_t dofs, uint32_t aofs, ui= nt32_t oprsz, g_assert_not_reached(); } tcg_temp_free_vec(t_vec); + tcg_swap_vecop_list(hold_list); } else if (g->fni8 && check_size_impl(oprsz, 8)) { TCGv_i64 t64 =3D tcg_temp_new_i64(); =20 @@ -1190,6 +1204,8 @@ void tcg_gen_gvec_2s(uint32_t dofs, uint32_t aofs, ui= nt32_t oprsz, void tcg_gen_gvec_3(uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t oprsz, uint32_t maxsz, const GVecGen3 *g) { + const TCGOpcode *this_list =3D g->opt_opc ? : vecop_list_empty; + const TCGOpcode *hold_list =3D tcg_swap_vecop_list(this_list); TCGType type; uint32_t some; =20 @@ -1198,7 +1214,7 @@ void tcg_gen_gvec_3(uint32_t dofs, uint32_t aofs, uin= t32_t bofs, =20 type =3D 0; if (g->fniv) { - type =3D choose_vector_type(g->opc, g->vece, oprsz, g->prefer_i64); + type =3D choose_vector_type(g->opt_opc, g->vece, oprsz, g->prefer_= i64); } switch (type) { case TCG_TYPE_V256: @@ -1236,13 +1252,14 @@ void tcg_gen_gvec_3(uint32_t dofs, uint32_t aofs, u= int32_t bofs, assert(g->fno !=3D NULL); tcg_gen_gvec_3_ool(dofs, aofs, bofs, oprsz, maxsz, g->data, g->fno); - return; + oprsz =3D maxsz; } break; =20 default: g_assert_not_reached(); } + tcg_swap_vecop_list(hold_list); =20 if (oprsz < maxsz) { expand_clr(dofs + oprsz, maxsz - oprsz); @@ -1254,6 +1271,8 @@ void tcg_gen_gvec_3i(uint32_t dofs, uint32_t aofs, ui= nt32_t bofs, uint32_t oprsz, uint32_t maxsz, int64_t c, const GVecGen3i *g) { + const TCGOpcode *this_list =3D g->opt_opc ? : vecop_list_empty; + const TCGOpcode *hold_list =3D tcg_swap_vecop_list(this_list); TCGType type; uint32_t some; =20 @@ -1262,7 +1281,7 @@ void tcg_gen_gvec_3i(uint32_t dofs, uint32_t aofs, ui= nt32_t bofs, =20 type =3D 0; if (g->fniv) { - type =3D choose_vector_type(g->opc, g->vece, oprsz, g->prefer_i64); + type =3D choose_vector_type(g->opt_opc, g->vece, oprsz, g->prefer_= i64); } switch (type) { case TCG_TYPE_V256: @@ -1300,13 +1319,14 @@ void tcg_gen_gvec_3i(uint32_t dofs, uint32_t aofs, = uint32_t bofs, } else { assert(g->fno !=3D NULL); tcg_gen_gvec_3_ool(dofs, aofs, bofs, oprsz, maxsz, c, g->fno); - return; + oprsz =3D maxsz; } break; =20 default: g_assert_not_reached(); } + tcg_swap_vecop_list(hold_list); =20 if (oprsz < maxsz) { expand_clr(dofs + oprsz, maxsz - oprsz); @@ -1317,6 +1337,8 @@ void tcg_gen_gvec_3i(uint32_t dofs, uint32_t aofs, ui= nt32_t bofs, void tcg_gen_gvec_4(uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t = cofs, uint32_t oprsz, uint32_t maxsz, const GVecGen4 *g) { + const TCGOpcode *this_list =3D g->opt_opc ? : vecop_list_empty; + const TCGOpcode *hold_list =3D tcg_swap_vecop_list(this_list); TCGType type; uint32_t some; =20 @@ -1325,7 +1347,7 @@ void tcg_gen_gvec_4(uint32_t dofs, uint32_t aofs, uin= t32_t bofs, uint32_t cofs, =20 type =3D 0; if (g->fniv) { - type =3D choose_vector_type(g->opc, g->vece, oprsz, g->prefer_i64); + type =3D choose_vector_type(g->opt_opc, g->vece, oprsz, g->prefer_= i64); } switch (type) { case TCG_TYPE_V256: @@ -1366,13 +1388,14 @@ void tcg_gen_gvec_4(uint32_t dofs, uint32_t aofs, u= int32_t bofs, uint32_t cofs, assert(g->fno !=3D NULL); tcg_gen_gvec_4_ool(dofs, aofs, bofs, cofs, oprsz, maxsz, g->data, g->fno); - return; + oprsz =3D maxsz; } break; =20 default: g_assert_not_reached(); } + tcg_swap_vecop_list(hold_list); =20 if (oprsz < maxsz) { expand_clr(dofs + oprsz, maxsz - oprsz); @@ -1567,6 +1590,8 @@ void tcg_gen_vec_add32_i64(TCGv_i64 d, TCGv_i64 a, TC= Gv_i64 b) tcg_temp_free_i64(t2); } =20 +static const TCGOpcode vecop_list_add[] =3D { INDEX_op_add_vec, 0 }; + void tcg_gen_gvec_add(unsigned vece, uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t oprsz, uint32_t maxsz) { @@ -1574,22 +1599,22 @@ void tcg_gen_gvec_add(unsigned vece, uint32_t dofs,= uint32_t aofs, { .fni8 =3D tcg_gen_vec_add8_i64, .fniv =3D tcg_gen_add_vec, .fno =3D gen_helper_gvec_add8, - .opc =3D INDEX_op_add_vec, + .opt_opc =3D vecop_list_add, .vece =3D MO_8 }, { .fni8 =3D tcg_gen_vec_add16_i64, .fniv =3D tcg_gen_add_vec, .fno =3D gen_helper_gvec_add16, - .opc =3D INDEX_op_add_vec, + .opt_opc =3D vecop_list_add, .vece =3D MO_16 }, { .fni4 =3D tcg_gen_add_i32, .fniv =3D tcg_gen_add_vec, .fno =3D gen_helper_gvec_add32, - .opc =3D INDEX_op_add_vec, + .opt_opc =3D vecop_list_add, .vece =3D MO_32 }, { .fni8 =3D tcg_gen_add_i64, .fniv =3D tcg_gen_add_vec, .fno =3D gen_helper_gvec_add64, - .opc =3D INDEX_op_add_vec, + .opt_opc =3D vecop_list_add, .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, .vece =3D MO_64 }, }; @@ -1605,22 +1630,22 @@ void tcg_gen_gvec_adds(unsigned vece, uint32_t dofs= , uint32_t aofs, { .fni8 =3D tcg_gen_vec_add8_i64, .fniv =3D tcg_gen_add_vec, .fno =3D gen_helper_gvec_adds8, - .opc =3D INDEX_op_add_vec, + .opt_opc =3D vecop_list_add, .vece =3D MO_8 }, { .fni8 =3D tcg_gen_vec_add16_i64, .fniv =3D tcg_gen_add_vec, .fno =3D gen_helper_gvec_adds16, - .opc =3D INDEX_op_add_vec, + .opt_opc =3D vecop_list_add, .vece =3D MO_16 }, { .fni4 =3D tcg_gen_add_i32, .fniv =3D tcg_gen_add_vec, .fno =3D gen_helper_gvec_adds32, - .opc =3D INDEX_op_add_vec, + .opt_opc =3D vecop_list_add, .vece =3D MO_32 }, { .fni8 =3D tcg_gen_add_i64, .fniv =3D tcg_gen_add_vec, .fno =3D gen_helper_gvec_adds64, - .opc =3D INDEX_op_add_vec, + .opt_opc =3D vecop_list_add, .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, .vece =3D MO_64 }, }; @@ -1637,6 +1662,8 @@ void tcg_gen_gvec_addi(unsigned vece, uint32_t dofs, = uint32_t aofs, tcg_temp_free_i64(tmp); } =20 +static const TCGOpcode vecop_list_sub[] =3D { INDEX_op_sub_vec, 0 }; + void tcg_gen_gvec_subs(unsigned vece, uint32_t dofs, uint32_t aofs, TCGv_i64 c, uint32_t oprsz, uint32_t maxsz) { @@ -1644,22 +1671,22 @@ void tcg_gen_gvec_subs(unsigned vece, uint32_t dofs= , uint32_t aofs, { .fni8 =3D tcg_gen_vec_sub8_i64, .fniv =3D tcg_gen_sub_vec, .fno =3D gen_helper_gvec_subs8, - .opc =3D INDEX_op_sub_vec, + .opt_opc =3D vecop_list_sub, .vece =3D MO_8 }, { .fni8 =3D tcg_gen_vec_sub16_i64, .fniv =3D tcg_gen_sub_vec, .fno =3D gen_helper_gvec_subs16, - .opc =3D INDEX_op_sub_vec, + .opt_opc =3D vecop_list_sub, .vece =3D MO_16 }, { .fni4 =3D tcg_gen_sub_i32, .fniv =3D tcg_gen_sub_vec, .fno =3D gen_helper_gvec_subs32, - .opc =3D INDEX_op_sub_vec, + .opt_opc =3D vecop_list_sub, .vece =3D MO_32 }, { .fni8 =3D tcg_gen_sub_i64, .fniv =3D tcg_gen_sub_vec, .fno =3D gen_helper_gvec_subs64, - .opc =3D INDEX_op_sub_vec, + .opt_opc =3D vecop_list_sub, .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, .vece =3D MO_64 }, }; @@ -1723,22 +1750,22 @@ void tcg_gen_gvec_sub(unsigned vece, uint32_t dofs,= uint32_t aofs, { .fni8 =3D tcg_gen_vec_sub8_i64, .fniv =3D tcg_gen_sub_vec, .fno =3D gen_helper_gvec_sub8, - .opc =3D INDEX_op_sub_vec, + .opt_opc =3D vecop_list_sub, .vece =3D MO_8 }, { .fni8 =3D tcg_gen_vec_sub16_i64, .fniv =3D tcg_gen_sub_vec, .fno =3D gen_helper_gvec_sub16, - .opc =3D INDEX_op_sub_vec, + .opt_opc =3D vecop_list_sub, .vece =3D MO_16 }, { .fni4 =3D tcg_gen_sub_i32, .fniv =3D tcg_gen_sub_vec, .fno =3D gen_helper_gvec_sub32, - .opc =3D INDEX_op_sub_vec, + .opt_opc =3D vecop_list_sub, .vece =3D MO_32 }, { .fni8 =3D tcg_gen_sub_i64, .fniv =3D tcg_gen_sub_vec, .fno =3D gen_helper_gvec_sub64, - .opc =3D INDEX_op_sub_vec, + .opt_opc =3D vecop_list_sub, .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, .vece =3D MO_64 }, }; @@ -1747,27 +1774,29 @@ void tcg_gen_gvec_sub(unsigned vece, uint32_t dofs,= uint32_t aofs, tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]); } =20 +static const TCGOpcode vecop_list_mul[] =3D { INDEX_op_mul_vec, 0 }; + void tcg_gen_gvec_mul(unsigned vece, uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t oprsz, uint32_t maxsz) { static const GVecGen3 g[4] =3D { { .fniv =3D tcg_gen_mul_vec, .fno =3D gen_helper_gvec_mul8, - .opc =3D INDEX_op_mul_vec, + .opt_opc =3D vecop_list_mul, .vece =3D MO_8 }, { .fniv =3D tcg_gen_mul_vec, .fno =3D gen_helper_gvec_mul16, - .opc =3D INDEX_op_mul_vec, + .opt_opc =3D vecop_list_mul, .vece =3D MO_16 }, { .fni4 =3D tcg_gen_mul_i32, .fniv =3D tcg_gen_mul_vec, .fno =3D gen_helper_gvec_mul32, - .opc =3D INDEX_op_mul_vec, + .opt_opc =3D vecop_list_mul, .vece =3D MO_32 }, { .fni8 =3D tcg_gen_mul_i64, .fniv =3D tcg_gen_mul_vec, .fno =3D gen_helper_gvec_mul64, - .opc =3D INDEX_op_mul_vec, + .opt_opc =3D vecop_list_mul, .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, .vece =3D MO_64 }, }; @@ -1782,21 +1811,21 @@ void tcg_gen_gvec_muls(unsigned vece, uint32_t dofs= , uint32_t aofs, static const GVecGen2s g[4] =3D { { .fniv =3D tcg_gen_mul_vec, .fno =3D gen_helper_gvec_muls8, - .opc =3D INDEX_op_mul_vec, + .opt_opc =3D vecop_list_mul, .vece =3D MO_8 }, { .fniv =3D tcg_gen_mul_vec, .fno =3D gen_helper_gvec_muls16, - .opc =3D INDEX_op_mul_vec, + .opt_opc =3D vecop_list_mul, .vece =3D MO_16 }, { .fni4 =3D tcg_gen_mul_i32, .fniv =3D tcg_gen_mul_vec, .fno =3D gen_helper_gvec_muls32, - .opc =3D INDEX_op_mul_vec, + .opt_opc =3D vecop_list_mul, .vece =3D MO_32 }, { .fni8 =3D tcg_gen_mul_i64, .fniv =3D tcg_gen_mul_vec, .fno =3D gen_helper_gvec_muls64, - .opc =3D INDEX_op_mul_vec, + .opt_opc =3D vecop_list_mul, .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, .vece =3D MO_64 }, }; @@ -1816,22 +1845,23 @@ void tcg_gen_gvec_muli(unsigned vece, uint32_t dofs= , uint32_t aofs, void tcg_gen_gvec_ssadd(unsigned vece, uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t oprsz, uint32_t maxsz) { + static const TCGOpcode vecop_list[] =3D { INDEX_op_ssadd_vec, 0 }; static const GVecGen3 g[4] =3D { { .fniv =3D tcg_gen_ssadd_vec, .fno =3D gen_helper_gvec_ssadd8, - .opc =3D INDEX_op_ssadd_vec, + .opt_opc =3D vecop_list, .vece =3D MO_8 }, { .fniv =3D tcg_gen_ssadd_vec, .fno =3D gen_helper_gvec_ssadd16, - .opc =3D INDEX_op_ssadd_vec, + .opt_opc =3D vecop_list, .vece =3D MO_16 }, { .fniv =3D tcg_gen_ssadd_vec, .fno =3D gen_helper_gvec_ssadd32, - .opc =3D INDEX_op_ssadd_vec, + .opt_opc =3D vecop_list, .vece =3D MO_32 }, { .fniv =3D tcg_gen_ssadd_vec, .fno =3D gen_helper_gvec_ssadd64, - .opc =3D INDEX_op_ssadd_vec, + .opt_opc =3D vecop_list, .vece =3D MO_64 }, }; tcg_debug_assert(vece <=3D MO_64); @@ -1841,22 +1871,23 @@ void tcg_gen_gvec_ssadd(unsigned vece, uint32_t dof= s, uint32_t aofs, void tcg_gen_gvec_sssub(unsigned vece, uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t oprsz, uint32_t maxsz) { + static const TCGOpcode vecop_list[] =3D { INDEX_op_sssub_vec, 0 }; static const GVecGen3 g[4] =3D { { .fniv =3D tcg_gen_sssub_vec, .fno =3D gen_helper_gvec_sssub8, - .opc =3D INDEX_op_sssub_vec, + .opt_opc =3D vecop_list, .vece =3D MO_8 }, { .fniv =3D tcg_gen_sssub_vec, .fno =3D gen_helper_gvec_sssub16, - .opc =3D INDEX_op_sssub_vec, + .opt_opc =3D vecop_list, .vece =3D MO_16 }, { .fniv =3D tcg_gen_sssub_vec, .fno =3D gen_helper_gvec_sssub32, - .opc =3D INDEX_op_sssub_vec, + .opt_opc =3D vecop_list, .vece =3D MO_32 }, { .fniv =3D tcg_gen_sssub_vec, .fno =3D gen_helper_gvec_sssub64, - .opc =3D INDEX_op_sssub_vec, + .opt_opc =3D vecop_list, .vece =3D MO_64 }, }; tcg_debug_assert(vece <=3D MO_64); @@ -1882,24 +1913,25 @@ static void tcg_gen_usadd_i64(TCGv_i64 d, TCGv_i64 = a, TCGv_i64 b) void tcg_gen_gvec_usadd(unsigned vece, uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t oprsz, uint32_t maxsz) { + static const TCGOpcode vecop_list[] =3D { INDEX_op_usadd_vec, 0 }; static const GVecGen3 g[4] =3D { { .fniv =3D tcg_gen_usadd_vec, .fno =3D gen_helper_gvec_usadd8, - .opc =3D INDEX_op_usadd_vec, + .opt_opc =3D vecop_list, .vece =3D MO_8 }, { .fniv =3D tcg_gen_usadd_vec, .fno =3D gen_helper_gvec_usadd16, - .opc =3D INDEX_op_usadd_vec, + .opt_opc =3D vecop_list, .vece =3D MO_16 }, { .fni4 =3D tcg_gen_usadd_i32, .fniv =3D tcg_gen_usadd_vec, .fno =3D gen_helper_gvec_usadd32, - .opc =3D INDEX_op_usadd_vec, + .opt_opc =3D vecop_list, .vece =3D MO_32 }, { .fni8 =3D tcg_gen_usadd_i64, .fniv =3D tcg_gen_usadd_vec, .fno =3D gen_helper_gvec_usadd64, - .opc =3D INDEX_op_usadd_vec, + .opt_opc =3D vecop_list, .vece =3D MO_64 } }; tcg_debug_assert(vece <=3D MO_64); @@ -1925,24 +1957,25 @@ static void tcg_gen_ussub_i64(TCGv_i64 d, TCGv_i64 = a, TCGv_i64 b) void tcg_gen_gvec_ussub(unsigned vece, uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t oprsz, uint32_t maxsz) { + static const TCGOpcode vecop_list[] =3D { INDEX_op_ussub_vec, 0 }; static const GVecGen3 g[4] =3D { { .fniv =3D tcg_gen_ussub_vec, .fno =3D gen_helper_gvec_ussub8, - .opc =3D INDEX_op_ussub_vec, + .opt_opc =3D vecop_list, .vece =3D MO_8 }, { .fniv =3D tcg_gen_ussub_vec, .fno =3D gen_helper_gvec_ussub16, - .opc =3D INDEX_op_ussub_vec, + .opt_opc =3D vecop_list, .vece =3D MO_16 }, { .fni4 =3D tcg_gen_ussub_i32, .fniv =3D tcg_gen_ussub_vec, .fno =3D gen_helper_gvec_ussub32, - .opc =3D INDEX_op_ussub_vec, + .opt_opc =3D vecop_list, .vece =3D MO_32 }, { .fni8 =3D tcg_gen_ussub_i64, .fniv =3D tcg_gen_ussub_vec, .fno =3D gen_helper_gvec_ussub64, - .opc =3D INDEX_op_ussub_vec, + .opt_opc =3D vecop_list, .vece =3D MO_64 } }; tcg_debug_assert(vece <=3D MO_64); @@ -1952,24 +1985,25 @@ void tcg_gen_gvec_ussub(unsigned vece, uint32_t dof= s, uint32_t aofs, void tcg_gen_gvec_smin(unsigned vece, uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t oprsz, uint32_t maxsz) { + static const TCGOpcode vecop_list[] =3D { INDEX_op_smin_vec, 0 }; static const GVecGen3 g[4] =3D { { .fniv =3D tcg_gen_smin_vec, .fno =3D gen_helper_gvec_smin8, - .opc =3D INDEX_op_smin_vec, + .opt_opc =3D vecop_list, .vece =3D MO_8 }, { .fniv =3D tcg_gen_smin_vec, .fno =3D gen_helper_gvec_smin16, - .opc =3D INDEX_op_smin_vec, + .opt_opc =3D vecop_list, .vece =3D MO_16 }, { .fni4 =3D tcg_gen_smin_i32, .fniv =3D tcg_gen_smin_vec, .fno =3D gen_helper_gvec_smin32, - .opc =3D INDEX_op_smin_vec, + .opt_opc =3D vecop_list, .vece =3D MO_32 }, { .fni8 =3D tcg_gen_smin_i64, .fniv =3D tcg_gen_smin_vec, .fno =3D gen_helper_gvec_smin64, - .opc =3D INDEX_op_smin_vec, + .opt_opc =3D vecop_list, .vece =3D MO_64 } }; tcg_debug_assert(vece <=3D MO_64); @@ -1979,24 +2013,25 @@ void tcg_gen_gvec_smin(unsigned vece, uint32_t dofs= , uint32_t aofs, void tcg_gen_gvec_umin(unsigned vece, uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t oprsz, uint32_t maxsz) { + static const TCGOpcode vecop_list[] =3D { INDEX_op_umin_vec, 0 }; static const GVecGen3 g[4] =3D { { .fniv =3D tcg_gen_umin_vec, .fno =3D gen_helper_gvec_umin8, - .opc =3D INDEX_op_umin_vec, + .opt_opc =3D vecop_list, .vece =3D MO_8 }, { .fniv =3D tcg_gen_umin_vec, .fno =3D gen_helper_gvec_umin16, - .opc =3D INDEX_op_umin_vec, + .opt_opc =3D vecop_list, .vece =3D MO_16 }, { .fni4 =3D tcg_gen_umin_i32, .fniv =3D tcg_gen_umin_vec, .fno =3D gen_helper_gvec_umin32, - .opc =3D INDEX_op_umin_vec, + .opt_opc =3D vecop_list, .vece =3D MO_32 }, { .fni8 =3D tcg_gen_umin_i64, .fniv =3D tcg_gen_umin_vec, .fno =3D gen_helper_gvec_umin64, - .opc =3D INDEX_op_umin_vec, + .opt_opc =3D vecop_list, .vece =3D MO_64 } }; tcg_debug_assert(vece <=3D MO_64); @@ -2006,24 +2041,25 @@ void tcg_gen_gvec_umin(unsigned vece, uint32_t dofs= , uint32_t aofs, void tcg_gen_gvec_smax(unsigned vece, uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t oprsz, uint32_t maxsz) { + static const TCGOpcode vecop_list[] =3D { INDEX_op_smax_vec, 0 }; static const GVecGen3 g[4] =3D { { .fniv =3D tcg_gen_smax_vec, .fno =3D gen_helper_gvec_smax8, - .opc =3D INDEX_op_smax_vec, + .opt_opc =3D vecop_list, .vece =3D MO_8 }, { .fniv =3D tcg_gen_smax_vec, .fno =3D gen_helper_gvec_smax16, - .opc =3D INDEX_op_smax_vec, + .opt_opc =3D vecop_list, .vece =3D MO_16 }, { .fni4 =3D tcg_gen_smax_i32, .fniv =3D tcg_gen_smax_vec, .fno =3D gen_helper_gvec_smax32, - .opc =3D INDEX_op_smax_vec, + .opt_opc =3D vecop_list, .vece =3D MO_32 }, { .fni8 =3D tcg_gen_smax_i64, .fniv =3D tcg_gen_smax_vec, .fno =3D gen_helper_gvec_smax64, - .opc =3D INDEX_op_smax_vec, + .opt_opc =3D vecop_list, .vece =3D MO_64 } }; tcg_debug_assert(vece <=3D MO_64); @@ -2033,24 +2069,25 @@ void tcg_gen_gvec_smax(unsigned vece, uint32_t dofs= , uint32_t aofs, void tcg_gen_gvec_umax(unsigned vece, uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t oprsz, uint32_t maxsz) { + static const TCGOpcode vecop_list[] =3D { INDEX_op_umax_vec, 0 }; static const GVecGen3 g[4] =3D { { .fniv =3D tcg_gen_umax_vec, .fno =3D gen_helper_gvec_umax8, - .opc =3D INDEX_op_umax_vec, + .opt_opc =3D vecop_list, .vece =3D MO_8 }, { .fniv =3D tcg_gen_umax_vec, .fno =3D gen_helper_gvec_umax16, - .opc =3D INDEX_op_umax_vec, + .opt_opc =3D vecop_list, .vece =3D MO_16 }, { .fni4 =3D tcg_gen_umax_i32, .fniv =3D tcg_gen_umax_vec, .fno =3D gen_helper_gvec_umax32, - .opc =3D INDEX_op_umax_vec, + .opt_opc =3D vecop_list, .vece =3D MO_32 }, { .fni8 =3D tcg_gen_umax_i64, .fniv =3D tcg_gen_umax_vec, .fno =3D gen_helper_gvec_umax64, - .opc =3D INDEX_op_umax_vec, + .opt_opc =3D vecop_list, .vece =3D MO_64 } }; tcg_debug_assert(vece <=3D MO_64); @@ -2104,26 +2141,27 @@ void tcg_gen_vec_neg32_i64(TCGv_i64 d, TCGv_i64 b) void tcg_gen_gvec_neg(unsigned vece, uint32_t dofs, uint32_t aofs, uint32_t oprsz, uint32_t maxsz) { + static const TCGOpcode vecop_list[] =3D { INDEX_op_neg_vec, 0 }; static const GVecGen2 g[4] =3D { { .fni8 =3D tcg_gen_vec_neg8_i64, .fniv =3D tcg_gen_neg_vec, .fno =3D gen_helper_gvec_neg8, - .opc =3D INDEX_op_neg_vec, + .opt_opc =3D vecop_list, .vece =3D MO_8 }, { .fni8 =3D tcg_gen_vec_neg16_i64, .fniv =3D tcg_gen_neg_vec, .fno =3D gen_helper_gvec_neg16, - .opc =3D INDEX_op_neg_vec, + .opt_opc =3D vecop_list, .vece =3D MO_16 }, { .fni4 =3D tcg_gen_neg_i32, .fniv =3D tcg_gen_neg_vec, .fno =3D gen_helper_gvec_neg32, - .opc =3D INDEX_op_neg_vec, + .opt_opc =3D vecop_list, .vece =3D MO_32 }, { .fni8 =3D tcg_gen_neg_i64, .fniv =3D tcg_gen_neg_vec, .fno =3D gen_helper_gvec_neg64, - .opc =3D INDEX_op_neg_vec, + .opt_opc =3D vecop_list, .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, .vece =3D MO_64 }, }; @@ -2139,7 +2177,6 @@ void tcg_gen_gvec_and(unsigned vece, uint32_t dofs, u= int32_t aofs, .fni8 =3D tcg_gen_and_i64, .fniv =3D tcg_gen_and_vec, .fno =3D gen_helper_gvec_and, - .opc =3D INDEX_op_and_vec, .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, }; =20 @@ -2157,7 +2194,6 @@ void tcg_gen_gvec_or(unsigned vece, uint32_t dofs, ui= nt32_t aofs, .fni8 =3D tcg_gen_or_i64, .fniv =3D tcg_gen_or_vec, .fno =3D gen_helper_gvec_or, - .opc =3D INDEX_op_or_vec, .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, }; =20 @@ -2175,7 +2211,6 @@ void tcg_gen_gvec_xor(unsigned vece, uint32_t dofs, u= int32_t aofs, .fni8 =3D tcg_gen_xor_i64, .fniv =3D tcg_gen_xor_vec, .fno =3D gen_helper_gvec_xor, - .opc =3D INDEX_op_xor_vec, .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, }; =20 @@ -2193,7 +2228,6 @@ void tcg_gen_gvec_andc(unsigned vece, uint32_t dofs, = uint32_t aofs, .fni8 =3D tcg_gen_andc_i64, .fniv =3D tcg_gen_andc_vec, .fno =3D gen_helper_gvec_andc, - .opc =3D INDEX_op_andc_vec, .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, }; =20 @@ -2211,7 +2245,6 @@ void tcg_gen_gvec_orc(unsigned vece, uint32_t dofs, u= int32_t aofs, .fni8 =3D tcg_gen_orc_i64, .fniv =3D tcg_gen_orc_vec, .fno =3D gen_helper_gvec_orc, - .opc =3D INDEX_op_orc_vec, .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, }; =20 @@ -2277,7 +2310,6 @@ static const GVecGen2s gop_ands =3D { .fni8 =3D tcg_gen_and_i64, .fniv =3D tcg_gen_and_vec, .fno =3D gen_helper_gvec_ands, - .opc =3D INDEX_op_and_vec, .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, .vece =3D MO_64 }; @@ -2303,7 +2335,6 @@ static const GVecGen2s gop_xors =3D { .fni8 =3D tcg_gen_xor_i64, .fniv =3D tcg_gen_xor_vec, .fno =3D gen_helper_gvec_xors, - .opc =3D INDEX_op_xor_vec, .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, .vece =3D MO_64 }; @@ -2329,7 +2360,6 @@ static const GVecGen2s gop_ors =3D { .fni8 =3D tcg_gen_or_i64, .fniv =3D tcg_gen_or_vec, .fno =3D gen_helper_gvec_ors, - .opc =3D INDEX_op_or_vec, .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, .vece =3D MO_64 }; @@ -2368,26 +2398,27 @@ void tcg_gen_vec_shl16i_i64(TCGv_i64 d, TCGv_i64 a,= int64_t c) void tcg_gen_gvec_shli(unsigned vece, uint32_t dofs, uint32_t aofs, int64_t shift, uint32_t oprsz, uint32_t maxsz) { + static const TCGOpcode vecop_list[] =3D { INDEX_op_shli_vec, 0 }; static const GVecGen2i g[4] =3D { { .fni8 =3D tcg_gen_vec_shl8i_i64, .fniv =3D tcg_gen_shli_vec, .fno =3D gen_helper_gvec_shl8i, - .opc =3D INDEX_op_shli_vec, + .opt_opc =3D vecop_list, .vece =3D MO_8 }, { .fni8 =3D tcg_gen_vec_shl16i_i64, .fniv =3D tcg_gen_shli_vec, .fno =3D gen_helper_gvec_shl16i, - .opc =3D INDEX_op_shli_vec, + .opt_opc =3D vecop_list, .vece =3D MO_16 }, { .fni4 =3D tcg_gen_shli_i32, .fniv =3D tcg_gen_shli_vec, .fno =3D gen_helper_gvec_shl32i, - .opc =3D INDEX_op_shli_vec, + .opt_opc =3D vecop_list, .vece =3D MO_32 }, { .fni8 =3D tcg_gen_shli_i64, .fniv =3D tcg_gen_shli_vec, .fno =3D gen_helper_gvec_shl64i, - .opc =3D INDEX_op_shli_vec, + .opt_opc =3D vecop_list, .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, .vece =3D MO_64 }, }; @@ -2418,26 +2449,27 @@ void tcg_gen_vec_shr16i_i64(TCGv_i64 d, TCGv_i64 a,= int64_t c) void tcg_gen_gvec_shri(unsigned vece, uint32_t dofs, uint32_t aofs, int64_t shift, uint32_t oprsz, uint32_t maxsz) { + static const TCGOpcode vecop_list[] =3D { INDEX_op_shri_vec, 0 }; static const GVecGen2i g[4] =3D { { .fni8 =3D tcg_gen_vec_shr8i_i64, .fniv =3D tcg_gen_shri_vec, .fno =3D gen_helper_gvec_shr8i, - .opc =3D INDEX_op_shri_vec, + .opt_opc =3D vecop_list, .vece =3D MO_8 }, { .fni8 =3D tcg_gen_vec_shr16i_i64, .fniv =3D tcg_gen_shri_vec, .fno =3D gen_helper_gvec_shr16i, - .opc =3D INDEX_op_shri_vec, + .opt_opc =3D vecop_list, .vece =3D MO_16 }, { .fni4 =3D tcg_gen_shri_i32, .fniv =3D tcg_gen_shri_vec, .fno =3D gen_helper_gvec_shr32i, - .opc =3D INDEX_op_shri_vec, + .opt_opc =3D vecop_list, .vece =3D MO_32 }, { .fni8 =3D tcg_gen_shri_i64, .fniv =3D tcg_gen_shri_vec, .fno =3D gen_helper_gvec_shr64i, - .opc =3D INDEX_op_shri_vec, + .opt_opc =3D vecop_list, .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, .vece =3D MO_64 }, }; @@ -2482,26 +2514,27 @@ void tcg_gen_vec_sar16i_i64(TCGv_i64 d, TCGv_i64 a,= int64_t c) void tcg_gen_gvec_sari(unsigned vece, uint32_t dofs, uint32_t aofs, int64_t shift, uint32_t oprsz, uint32_t maxsz) { + static const TCGOpcode vecop_list[] =3D { INDEX_op_sari_vec, 0 }; static const GVecGen2i g[4] =3D { { .fni8 =3D tcg_gen_vec_sar8i_i64, .fniv =3D tcg_gen_sari_vec, .fno =3D gen_helper_gvec_sar8i, - .opc =3D INDEX_op_sari_vec, + .opt_opc =3D vecop_list, .vece =3D MO_8 }, { .fni8 =3D tcg_gen_vec_sar16i_i64, .fniv =3D tcg_gen_sari_vec, .fno =3D gen_helper_gvec_sar16i, - .opc =3D INDEX_op_sari_vec, + .opt_opc =3D vecop_list, .vece =3D MO_16 }, { .fni4 =3D tcg_gen_sari_i32, .fniv =3D tcg_gen_sari_vec, .fno =3D gen_helper_gvec_sar32i, - .opc =3D INDEX_op_sari_vec, + .opt_opc =3D vecop_list, .vece =3D MO_32 }, { .fni8 =3D tcg_gen_sari_i64, .fniv =3D tcg_gen_sari_vec, .fno =3D gen_helper_gvec_sar64i, - .opc =3D INDEX_op_sari_vec, + .opt_opc =3D vecop_list, .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, .vece =3D MO_64 }, }; @@ -2574,6 +2607,7 @@ void tcg_gen_gvec_cmp(TCGCond cond, unsigned vece, ui= nt32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t oprsz, uint32_t maxsz) { + static const TCGOpcode cmp_list[] =3D { INDEX_op_cmp_vec, 0 }; static gen_helper_gvec_3 * const eq_fn[4] =3D { gen_helper_gvec_eq8, gen_helper_gvec_eq16, gen_helper_gvec_eq32, gen_helper_gvec_eq64 @@ -2606,6 +2640,8 @@ void tcg_gen_gvec_cmp(TCGCond cond, unsigned vece, ui= nt32_t dofs, [TCG_COND_LTU] =3D ltu_fn, [TCG_COND_LEU] =3D leu_fn, }; + + const TCGOpcode *hold_list; TCGType type; uint32_t some; =20 @@ -2618,10 +2654,12 @@ void tcg_gen_gvec_cmp(TCGCond cond, unsigned vece, = uint32_t dofs, return; } =20 - /* Implement inline with a vector type, if possible. + /* + * Implement inline with a vector type, if possible. * Prefer integer when 64-bit host and 64-bit comparison. */ - type =3D choose_vector_type(INDEX_op_cmp_vec, vece, oprsz, + hold_list =3D tcg_swap_vecop_list(cmp_list); + type =3D choose_vector_type(cmp_list, vece, oprsz, TCG_TARGET_REG_BITS =3D=3D 64 && vece =3D=3D= MO_64); switch (type) { case TCG_TYPE_V256: @@ -2663,13 +2701,14 @@ void tcg_gen_gvec_cmp(TCGCond cond, unsigned vece, = uint32_t dofs, assert(fn !=3D NULL); } tcg_gen_gvec_3_ool(dofs, aofs, bofs, oprsz, maxsz, 0, fn[vece]= ); - return; + oprsz =3D maxsz; } break; =20 default: g_assert_not_reached(); } + tcg_swap_vecop_list(hold_list); =20 if (oprsz < maxsz) { expand_clr(dofs + oprsz, maxsz - oprsz); diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c index cfb18682b1..914fe42b1e 100644 --- a/tcg/tcg-op-vec.c +++ b/tcg/tcg-op-vec.c @@ -34,6 +34,90 @@ extern TCGv_i32 TCGV_HIGH_link_error(TCGv_i64); #define TCGV_HIGH TCGV_HIGH_link_error #endif =20 +/* + * Vector optional opcode tracking. + * Except for the basic logical operations (and, or, xor), and + * data movement (mov, ld, st, dupi), many vector opcodes are + * optional and may not be supported on the host. Thank Intel + * for the irregularity in their instruction set. + * + * The gvec expanders allow custom vector operations to be composed, + * generally via the .fniv callback in the GVecGen* structures. At + * the same time, in deciding whether to use this hook we need to + * know if the host supports the required operations. This is + * presented as an array of opcodes, terminated by 0. Each opcode + * is assumed to be expanded with the given VECE. + * + * For debugging, we want to validate this array. Therefore, when + * tcg_ctx->vec_opt_opc is non-NULL, the tcg_gen_*_vec expanders + * will validate that their opcode is present in the list. + */ +#ifdef CONFIG_DEBUG_TCG +void tcg_assert_listed_vecop(TCGOpcode op) +{ + const TCGOpcode *p =3D tcg_ctx->vecop_list; + if (p) { + for (; *p; ++p) { + if (*p =3D=3D op) { + return; + } + } + g_assert_not_reached(); + } +} +#endif + +bool tcg_can_emit_vecop_list(const TCGOpcode *list, + TCGType type, unsigned vece) +{ + if (list =3D=3D NULL) { + return true; + } + + for (; *list; ++list) { + TCGOpcode opc =3D *list; + +#ifdef CONFIG_DEBUG_TCG + switch (opc) { + case INDEX_op_and_vec: + case INDEX_op_or_vec: + case INDEX_op_xor_vec: + case INDEX_op_mov_vec: + case INDEX_op_dup_vec: + case INDEX_op_dupi_vec: + case INDEX_op_dup2_vec: + case INDEX_op_ld_vec: + case INDEX_op_st_vec: + /* These opcodes are mandatory and should not be listed. */ + g_assert_not_reached(); + default: + break; + } +#endif + + if (tcg_can_emit_vec_op(opc, type, vece)) { + continue; + } + + /* + * The opcode list is created by front ends based on what they + * actually invoke. We must mirror the logic in the routines + * below for generic expansions using other opcodes. + */ + switch (opc) { + case INDEX_op_neg_vec: + if (tcg_can_emit_vec_op(INDEX_op_sub_vec, type, vece)) { + continue; + } + break; + default: + break; + } + return false; + } + return true; +} + void vec_gen_2(TCGOpcode opc, TCGType type, unsigned vece, TCGArg r, TCGAr= g a) { TCGOp *op =3D tcg_emit_op(opc); @@ -296,11 +380,14 @@ static bool do_op2(unsigned vece, TCGv_vec r, TCGv_ve= c a, TCGOpcode opc) int can; =20 tcg_debug_assert(at->base_type >=3D type); + tcg_assert_listed_vecop(opc); can =3D tcg_can_emit_vec_op(opc, type, vece); if (can > 0) { vec_gen_2(opc, type, vece, ri, ai); } else if (can < 0) { + const TCGOpcode *hold_list =3D tcg_swap_vecop_list(NULL); tcg_expand_vec_op(opc, type, vece, ri, ai); + tcg_swap_vecop_list(hold_list); } else { return false; } @@ -318,11 +405,17 @@ void tcg_gen_not_vec(unsigned vece, TCGv_vec r, TCGv_= vec a) =20 void tcg_gen_neg_vec(unsigned vece, TCGv_vec r, TCGv_vec a) { + const TCGOpcode *hold_list; + + tcg_assert_listed_vecop(INDEX_op_neg_vec); + hold_list =3D tcg_swap_vecop_list(NULL); + if (!TCG_TARGET_HAS_neg_vec || !do_op2(vece, r, a, INDEX_op_neg_vec)) { TCGv_vec t =3D tcg_const_zeros_vec_matching(r); tcg_gen_sub_vec(vece, r, t, a); tcg_temp_free_vec(t); } + tcg_swap_vecop_list(hold_list); } =20 static void do_shifti(TCGOpcode opc, unsigned vece, @@ -337,6 +430,7 @@ static void do_shifti(TCGOpcode opc, unsigned vece, =20 tcg_debug_assert(at->base_type =3D=3D type); tcg_debug_assert(i >=3D 0 && i < (8 << vece)); + tcg_assert_listed_vecop(opc); =20 if (i =3D=3D 0) { tcg_gen_mov_vec(r, a); @@ -350,8 +444,10 @@ static void do_shifti(TCGOpcode opc, unsigned vece, /* We leave the choice of expansion via scalar or vector shift to the target. Often, but not always, dupi can feed a vector shift easier than a scalar. */ + const TCGOpcode *hold_list =3D tcg_swap_vecop_list(NULL); tcg_debug_assert(can < 0); tcg_expand_vec_op(opc, type, vece, ri, ai, i); + tcg_swap_vecop_list(hold_list); } } =20 @@ -384,12 +480,15 @@ void tcg_gen_cmp_vec(TCGCond cond, unsigned vece, =20 tcg_debug_assert(at->base_type >=3D type); tcg_debug_assert(bt->base_type >=3D type); + tcg_assert_listed_vecop(INDEX_op_cmp_vec); can =3D tcg_can_emit_vec_op(INDEX_op_cmp_vec, type, vece); if (can > 0) { vec_gen_4(INDEX_op_cmp_vec, type, vece, ri, ai, bi, cond); } else { + const TCGOpcode *hold_list =3D tcg_swap_vecop_list(NULL); tcg_debug_assert(can < 0); tcg_expand_vec_op(INDEX_op_cmp_vec, type, vece, ri, ai, bi, cond); + tcg_swap_vecop_list(hold_list); } } =20 @@ -407,12 +506,15 @@ static void do_op3(unsigned vece, TCGv_vec r, TCGv_ve= c a, =20 tcg_debug_assert(at->base_type >=3D type); tcg_debug_assert(bt->base_type >=3D type); + tcg_assert_listed_vecop(opc); can =3D tcg_can_emit_vec_op(opc, type, vece); if (can > 0) { vec_gen_3(opc, type, vece, ri, ai, bi); } else { + const TCGOpcode *hold_list =3D tcg_swap_vecop_list(NULL); tcg_debug_assert(can < 0); tcg_expand_vec_op(opc, type, vece, ri, ai, bi); + tcg_swap_vecop_list(hold_list); } } =20 --=20 2.17.1 From nobody Sat May 4 13:31:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1556949493; cv=none; d=zoho.com; s=zohoarc; b=oHXEYXb5y43B2CS1aeYulGbSIT0CQlo0GiKKlNQtBxLx9ADhXlqPwmyk4hM342TS3BeaB747jSrP/qRXywSLX0O+5vd5m6PV4olrUT6dCiyDN/D8YwiEEO5Fuu2fICNMU0Ni2fRQ9VwTKOjWkTchRmi+WFakXLKEROs2bT4p9jM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1556949493; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=AEWllDC9QOtFQnoRVEZxCBNwIaVzx46hUstbb9Zao4Q=; b=gsRfXXqWCQPs1xGRsXhFPzPZmJ8K/SHcG0d/j+NzOpNdupfs/hyHRDShz/nJQWK6zUrRV1ak6iseJ3hsRVN94jujGKLAxxVGI+8ODZ6k5MnJiNeAYUDwREt7FwH/hKrEVqiudYiNpS4dSHHyk0K5JUBKX/lhZ/QHgCSBmX+H9t4= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1556949493012730.7405659924874; Fri, 3 May 2019 22:58:13 -0700 (PDT) Received: from localhost ([127.0.0.1]:51658 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hMngX-0002tk-L3 for importer@patchew.org; Sat, 04 May 2019 01:58:09 -0400 Received: from eggs.gnu.org ([209.51.188.92]:41711) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hMnbk-0007hC-Jm for qemu-devel@nongnu.org; Sat, 04 May 2019 01:53:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hMnbj-00049G-7S for qemu-devel@nongnu.org; Sat, 04 May 2019 01:53:12 -0400 Received: from mail-pg1-x541.google.com ([2607:f8b0:4864:20::541]:41225) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hMnbj-00046t-0k for qemu-devel@nongnu.org; Sat, 04 May 2019 01:53:11 -0400 Received: by mail-pg1-x541.google.com with SMTP id z3so59852pgp.8 for ; Fri, 03 May 2019 22:53:09 -0700 (PDT) Received: from localhost.localdomain (97-113-189-189.tukw.qwest.net. [97.113.189.189]) by smtp.gmail.com with ESMTPSA id 15sm6680423pfo.117.2019.05.03.22.53.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 03 May 2019 22:53:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=AEWllDC9QOtFQnoRVEZxCBNwIaVzx46hUstbb9Zao4Q=; b=iZETl0exm2mwe37YJSYauOjqSn2X1yX7gYox/nsBAMwiKJdQ9pM2nw8TjCt0Zqp/dg akRinFecWNg3d7cuAhreaDiKKfc2h4ukjbnJmt5jtIuQ4qzRMsc+MKhwYV6jahXy4/B+ M3dTd5QPc+6ppPJmWKL1HvWk4BWpdXklZvoNrfBu3AplA8KOfAATbO93vu8HF73P6kkt MYgDCr87pn70ZT3nlC8TIQRGrzvuiONNcCWGnu940VZQUAtwFMrd0V/+60rqgKNcKrGI V6+BnsDa0dVIgHHNOiSgIZwlH9D6EVamgXpjtjV1ScqyUhkul93RZPEDB8WxhZNy6X7F rbKw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=AEWllDC9QOtFQnoRVEZxCBNwIaVzx46hUstbb9Zao4Q=; b=YSbIO6z2t46i4MivprlyOgGny5UMKY33bf6gTQQmEcKMQVXolq6QicfFvzP72gYmiu VYEoCcY/Q2Qx5k3jAiYJk2NZzI4683i5g9t2cyTKYzAjQz94QyZ0/MibUZzdTbwkTzb4 EBVkWHGLg1DzHbA5/TYx83e12QB5M2nrFTizKDfyxd3tSYlNRsJDcoFZCmN3mffodu+b leOlvgacdjdxQl7YKld42O5T8mNPLFWGkiSzfvl+rkMvD8IDPQdbqhcfeFd7nNrb/v7o cl9zpArggWcBJFmL021cOHeaoG1J279XYOPt9CTah0/hbBrhGaM8VeGJQ/719YuM7XST efYw== X-Gm-Message-State: APjAAAVRrBqLe75MgUB5ivRNHZTPehYcVvlKdn6MexmRFVebqzl1q6Za DTNx8Bt+iKpAzlevbyLi1IIJVAyG2tA= X-Google-Smtp-Source: APXvYqxyNam82B17U5fIQry01SAviFw62+/q8QdMgU7+zsS6hmAw00m+afLnLZV6XfW13MASfkehZQ== X-Received: by 2002:a62:570a:: with SMTP id l10mr6751866pfb.151.1556949188537; Fri, 03 May 2019 22:53:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 3 May 2019 22:52:34 -0700 Message-Id: <20190504055300.18426-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190504055300.18426-1-richard.henderson@linaro.org> References: <20190504055300.18426-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH v3 05/31] tcg: Assert fixed_reg is read-only X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) The only fixed_reg is cpu_env, and it should not be modified during any TB. Therefore code that tries to special-case moves into a fixed_reg is dead. Remove it. Reviewed-by: Alex Benn=C3=A9e Reviewed-by: David Hildenbrand Signed-off-by: Richard Henderson --- tcg/tcg.c | 87 +++++++++++++++++++++++++------------------------------ 1 file changed, 40 insertions(+), 47 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index f7bef51de8..70ca113c26 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -3274,11 +3274,8 @@ static void tcg_reg_alloc_do_movi(TCGContext *s, TCG= Temp *ots, tcg_target_ulong val, TCGLifeData arg_li= fe, TCGRegSet preferred_regs) { - if (ots->fixed_reg) { - /* For fixed registers, we do not do any constant propagation. */ - tcg_out_movi(s, ots->type, ots->reg, val); - return; - } + /* ENV should not be modified. */ + tcg_debug_assert(!ots->fixed_reg); =20 /* The movi is not explicitly generated here. */ if (ots->val_type =3D=3D TEMP_VAL_REG) { @@ -3314,6 +3311,9 @@ static void tcg_reg_alloc_mov(TCGContext *s, const TC= GOp *op) ots =3D arg_temp(op->args[0]); ts =3D arg_temp(op->args[1]); =20 + /* ENV should not be modified. */ + tcg_debug_assert(!ots->fixed_reg); + /* Note that otype !=3D itype for no-op truncation. */ otype =3D ots->type; itype =3D ts->type; @@ -3338,7 +3338,7 @@ static void tcg_reg_alloc_mov(TCGContext *s, const TC= GOp *op) } =20 tcg_debug_assert(ts->val_type =3D=3D TEMP_VAL_REG); - if (IS_DEAD_ARG(0) && !ots->fixed_reg) { + if (IS_DEAD_ARG(0)) { /* mov to a non-saved dead register makes no sense (even with liveness analysis disabled). */ tcg_debug_assert(NEED_SYNC_ARG(0)); @@ -3351,7 +3351,7 @@ static void tcg_reg_alloc_mov(TCGContext *s, const TC= GOp *op) } temp_dead(s, ots); } else { - if (IS_DEAD_ARG(1) && !ts->fixed_reg && !ots->fixed_reg) { + if (IS_DEAD_ARG(1) && !ts->fixed_reg) { /* the mov can be suppressed */ if (ots->val_type =3D=3D TEMP_VAL_REG) { s->reg_to_temp[ots->reg] =3D NULL; @@ -3504,6 +3504,10 @@ static void tcg_reg_alloc_op(TCGContext *s, const TC= GOp *op) arg =3D op->args[i]; arg_ct =3D &def->args_ct[i]; ts =3D arg_temp(arg); + + /* ENV should not be modified. */ + tcg_debug_assert(!ts->fixed_reg); + if ((arg_ct->ct & TCG_CT_ALIAS) && !const_args[arg_ct->alias_index]) { reg =3D new_args[arg_ct->alias_index]; @@ -3512,29 +3516,21 @@ static void tcg_reg_alloc_op(TCGContext *s, const T= CGOp *op) i_allocated_regs | o_allocated_regs, op->output_pref[k], ts->indirect_base); } else { - /* if fixed register, we try to use it */ - reg =3D ts->reg; - if (ts->fixed_reg && - tcg_regset_test_reg(arg_ct->u.regs, reg)) { - goto oarg_end; - } reg =3D tcg_reg_alloc(s, arg_ct->u.regs, o_allocated_regs, op->output_pref[k], ts->indirect_base); } tcg_regset_set_reg(o_allocated_regs, reg); - /* if a fixed register is used, then a move will be done after= wards */ - if (!ts->fixed_reg) { - if (ts->val_type =3D=3D TEMP_VAL_REG) { - s->reg_to_temp[ts->reg] =3D NULL; - } - ts->val_type =3D TEMP_VAL_REG; - ts->reg =3D reg; - /* temp value is modified, so the value kept in memory is - potentially not the same */ - ts->mem_coherent =3D 0; - s->reg_to_temp[reg] =3D ts; + if (ts->val_type =3D=3D TEMP_VAL_REG) { + s->reg_to_temp[ts->reg] =3D NULL; } - oarg_end: + ts->val_type =3D TEMP_VAL_REG; + ts->reg =3D reg; + /* + * Temp value is modified, so the value kept in memory is + * potentially not the same. + */ + ts->mem_coherent =3D 0; + s->reg_to_temp[reg] =3D ts; new_args[i] =3D reg; } } @@ -3550,10 +3546,10 @@ static void tcg_reg_alloc_op(TCGContext *s, const T= CGOp *op) /* move the outputs in the correct register if needed */ for(i =3D 0; i < nb_oargs; i++) { ts =3D arg_temp(op->args[i]); - reg =3D new_args[i]; - if (ts->fixed_reg && ts->reg !=3D reg) { - tcg_out_mov(s, ts->type, ts->reg, reg); - } + + /* ENV should not be modified. */ + tcg_debug_assert(!ts->fixed_reg); + if (NEED_SYNC_ARG(i)) { temp_sync(s, ts, o_allocated_regs, 0, IS_DEAD_ARG(i)); } else if (IS_DEAD_ARG(i)) { @@ -3674,26 +3670,23 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp= *op) for(i =3D 0; i < nb_oargs; i++) { arg =3D op->args[i]; ts =3D arg_temp(arg); + + /* ENV should not be modified. */ + tcg_debug_assert(!ts->fixed_reg); + reg =3D tcg_target_call_oarg_regs[i]; tcg_debug_assert(s->reg_to_temp[reg] =3D=3D NULL); - - if (ts->fixed_reg) { - if (ts->reg !=3D reg) { - tcg_out_mov(s, ts->type, ts->reg, reg); - } - } else { - if (ts->val_type =3D=3D TEMP_VAL_REG) { - s->reg_to_temp[ts->reg] =3D NULL; - } - ts->val_type =3D TEMP_VAL_REG; - ts->reg =3D reg; - ts->mem_coherent =3D 0; - s->reg_to_temp[reg] =3D ts; - if (NEED_SYNC_ARG(i)) { - temp_sync(s, ts, allocated_regs, 0, IS_DEAD_ARG(i)); - } else if (IS_DEAD_ARG(i)) { - temp_dead(s, ts); - } + if (ts->val_type =3D=3D TEMP_VAL_REG) { + s->reg_to_temp[ts->reg] =3D NULL; + } + ts->val_type =3D TEMP_VAL_REG; + ts->reg =3D reg; + ts->mem_coherent =3D 0; + s->reg_to_temp[reg] =3D ts; + if (NEED_SYNC_ARG(i)) { + temp_sync(s, ts, allocated_regs, 0, IS_DEAD_ARG(i)); + } else if (IS_DEAD_ARG(i)) { + temp_dead(s, ts); } } } --=20 2.17.1 From nobody Sat May 4 13:31:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[97.113.189.189]) by smtp.gmail.com with ESMTPSA id 15sm6680423pfo.117.2019.05.03.22.53.08 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 03 May 2019 22:53:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=eQYUrWBgaVSTGc+XM8Y45frZ2xC0wqtFT2VlLB2AH5Q=; b=hhX/PqE1FuFEYc3EYflwn2g3vvEjqip7NuPeEf3CR6ivyErkHRmeiu5u5epsNio9OW I4AbgN4qQOPh4P4+qCQR8Y5MhbcNfGC+WRG0guA4bon0suv5vGM5MQKLEacimkfXfLHN oUSkS/E7+dnNuKtBR11+2LzTBmQx8TrIGs8E6i/oIluvcJsvLhxyIYB95YFM41fnrF9E fHe0RXABmZwE1g1pL08PB820ekSJMggYSl2ibrCXlLItfh0ftnNkIlqF2R7KMg+yGp54 zLUWPs1Hc/pjXy94m0s00QzR3rC+BGHmkVt6RCPgFjcdC4d5Om9VZV5toPw+D7VksdtI YlMg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=eQYUrWBgaVSTGc+XM8Y45frZ2xC0wqtFT2VlLB2AH5Q=; b=I1pug7PHFz58Xq30Y8LStw/sHKj6Q61kZWuaBszvxrtsrxWIAQJpdqQNYqNnSubokb Ea3X5s5zvGbWoXSmpcF6Th90sjK7rLHWoeHXlIVwBJ1Y2eziElofuz3OFyDlq2DHhSh0 D0UCllhqDuVRFTVAxdncLeZcdVR+03ny9GkBAlsGw+cHe6BoAU5DByafJKshvv5y5K2n RaGj6tDjiGgGpabY8e3tkfsbKEgf7n6hoj4pIT4MN0skXAejuqt0OaJTxb66fOpTBR4B lzCaeGa4c06wwc7h5ySyno7NbmfPGxEVO4tTQ4s7NNE6GVHbIkpIbZrQWD8nKqBtth0R 8KhQ== X-Gm-Message-State: APjAAAVqJJuJWASXj+TlSd2wAFCNvTsGZKioqG0I9/AVgAoIXzoxIU3o NrG/KiwSsprWq88t1X2Q0bqdhja3OXk= X-Google-Smtp-Source: APXvYqxDcWnLvdsGNVzefHM2EjvjnKxoBiSVYLq3CZak99/jxrtJwMBGKz7IRGcFMTEJmvbDmTLJ1g== X-Received: by 2002:a62:56d9:: with SMTP id h86mr6871436pfj.195.1556949189950; Fri, 03 May 2019 22:53:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 3 May 2019 22:52:35 -0700 Message-Id: <20190504055300.18426-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190504055300.18426-1-richard.henderson@linaro.org> References: <20190504055300.18426-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::441 Subject: [Qemu-devel] [PATCH v3 06/31] tcg/arm: Use tcg_out_mov_reg in tcg_out_mov X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We have a function that takes an additional condition parameter over the standard backend interface. It already takes care of eliding no-op moves. Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.inc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c index abf0c444b4..130b6bef1e 100644 --- a/tcg/arm/tcg-target.inc.c +++ b/tcg/arm/tcg-target.inc.c @@ -2267,7 +2267,7 @@ static inline bool tcg_out_sti(TCGContext *s, TCGType= type, TCGArg val, static inline void tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) { - tcg_out_dat_reg(s, COND_AL, ARITH_MOV, ret, 0, arg, SHIFT_IMM_LSL(0)); + tcg_out_mov_reg(s, COND_AL, ret, arg); } =20 static inline void tcg_out_movi(TCGContext *s, TCGType type, --=20 2.17.1 From nobody Sat May 4 13:31:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1556949682; cv=none; d=zoho.com; s=zohoarc; b=jirrJLjWoPRmef2y1VeRk0rrNxczDsDBnS32FwqGdcHFhfou0B3Heaez+cdhQYa7n4OIF5JzpDFKoy2z35PIWkZ/Cb4uniKiKgxVNUvKHf2eMCKNdSP35XI7bf/tSCowRWQeeE1d8sIBLUvEMKsb88ofgqJhSp3qOAYYEUwwNRs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1556949682; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=DVRqREBkCOgKbqofVojwT8Y9Ia/mxWbAuVeJ6nGotn0=; b=W89XjhxcHFwrwWP+ilMRcIt3ZEg7NL2tpmy/y+4uaj5cz8vCmOq0kVondy2GdxkDQ/vjUTD9/nTRsqaE0x1VKhw7k5T745e92SYmBjZmK7pNLRq5oSBuHD84a2I5BLcWoyzjevf9PViU3kj8NrOqnar0fWVSkSynmp5agpggZ+M= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 15569496822271021.6796755974735; Fri, 3 May 2019 23:01:22 -0700 (PDT) Received: from localhost ([127.0.0.1]:51716 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hMnjW-0005H4-TV for importer@patchew.org; Sat, 04 May 2019 02:01:14 -0400 Received: from eggs.gnu.org ([209.51.188.92]:41733) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hMnbm-0007jK-Iw for qemu-devel@nongnu.org; Sat, 04 May 2019 01:53:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hMnbk-0004An-W0 for qemu-devel@nongnu.org; Sat, 04 May 2019 01:53:14 -0400 Received: from mail-pf1-x444.google.com ([2607:f8b0:4864:20::444]:34099) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hMnbk-00049i-O1 for qemu-devel@nongnu.org; Sat, 04 May 2019 01:53:12 -0400 Received: by mail-pf1-x444.google.com with SMTP id b3so3985952pfd.1 for ; Fri, 03 May 2019 22:53:12 -0700 (PDT) Received: from localhost.localdomain (97-113-189-189.tukw.qwest.net. [97.113.189.189]) by smtp.gmail.com with ESMTPSA id 15sm6680423pfo.117.2019.05.03.22.53.10 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 03 May 2019 22:53:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=DVRqREBkCOgKbqofVojwT8Y9Ia/mxWbAuVeJ6nGotn0=; b=WaLfGfPplZa9NItbMHacYES8PkjUcR6zRF1/jXjyyPDLvQAzAd50+5vzDFV7xUECCR tufz7F1yjZ9IJiFtDd16xOT6grg6GgEbWX7Vn8V92Bfp2AEWMean0YnZHCuGIY/xZOv/ fr/sH1hppdXMhObEItMbcdEGMZFLBNQNTQL84J+Y85zHqanhQZfVyaZayaWofGFkMaaN U1ipa8W4iJ/nsEYsAYMzeUc5PE3U3zJNILhZFgO4UHIlnap3x4doJabbLRqGOawChnhI tFrt6gnYntfNZBBmhJqKdDRuebAvqufctsH9bEuQCIElrp3G2qfNnIcsTtCFEhVP40Ni mJzA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=DVRqREBkCOgKbqofVojwT8Y9Ia/mxWbAuVeJ6nGotn0=; b=bnCaQoI0poxQ/zZpaoMVYADO1rysH8H/TpP/qVXoaoIrqx4+Wre5/x5KvVvyrG6cf0 P1lGzYJUn8E2TKpEzeiXWnajYDb8cN0FS3P/fByRGsAgF0xrcIlTCWdfSFZxByj5prbD a4R1VJUmLGLo+ktzT7FUA2I3g+xKbCra4olPCwlx2rBBBodo74oQLasTk0iw55EGTZF4 Ac72W/VeBPUk8Iogpx4wKaS05u0UNQDe3ZUEBrNMJpeijErp6/0DVAPTEiCwYSflDlgo 30qsKmRBnCfP5fJHJyHo1n6yI2BxFmLAnPBLYGYToDj04eLibyyyOErOdL5G4i6JczLq P/Uw== X-Gm-Message-State: APjAAAVVPzGeTRLs7pI+zBYffUExop/Q0q/dF9Vgi0Ux6zLsFPphUAfa EbaMdTbQ3ad/Opu48zYGCkN9u+HUNsE= X-Google-Smtp-Source: APXvYqx9L9I67jakTUr1AhZRRGp3fVlJF6YVVzMX6BoJKTkXlKoPM58M+r36LLWL9oznLkSX+7MABw== X-Received: by 2002:a62:4690:: with SMTP id o16mr16799732pfi.166.1556949191277; Fri, 03 May 2019 22:53:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 3 May 2019 22:52:36 -0700 Message-Id: <20190504055300.18426-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190504055300.18426-1-richard.henderson@linaro.org> References: <20190504055300.18426-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH v3 07/31] tcg: Return bool success from tcg_out_mov X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) This patch merely changes the interface, aborting on all failures, of which there are currently none. Reviewed-by: Alex Benn=C3=A9e Reviewed-by: David Hildenbrand Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: David Gibson Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.inc.c | 5 +++-- tcg/arm/tcg-target.inc.c | 3 ++- tcg/i386/tcg-target.inc.c | 5 +++-- tcg/mips/tcg-target.inc.c | 3 ++- tcg/ppc/tcg-target.inc.c | 3 ++- tcg/riscv/tcg-target.inc.c | 5 +++-- tcg/s390/tcg-target.inc.c | 3 ++- tcg/sparc/tcg-target.inc.c | 3 ++- tcg/tcg.c | 14 ++++++++++---- tcg/tci/tcg-target.inc.c | 3 ++- 10 files changed, 31 insertions(+), 16 deletions(-) diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c index eefa929948..ee89734318 100644 --- a/tcg/aarch64/tcg-target.inc.c +++ b/tcg/aarch64/tcg-target.inc.c @@ -938,10 +938,10 @@ static void tcg_out_ldst(TCGContext *s, AArch64Insn i= nsn, TCGReg rd, tcg_out_ldst_r(s, insn, rd, rn, TCG_TYPE_I64, TCG_REG_TMP); } =20 -static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg ar= g) +static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg ar= g) { if (ret =3D=3D arg) { - return; + return true; } switch (type) { case TCG_TYPE_I32: @@ -970,6 +970,7 @@ static void tcg_out_mov(TCGContext *s, TCGType type, TC= GReg ret, TCGReg arg) default: g_assert_not_reached(); } + return true; } =20 static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c index 130b6bef1e..7316504c9d 100644 --- a/tcg/arm/tcg-target.inc.c +++ b/tcg/arm/tcg-target.inc.c @@ -2264,10 +2264,11 @@ static inline bool tcg_out_sti(TCGContext *s, TCGTy= pe type, TCGArg val, return false; } =20 -static inline void tcg_out_mov(TCGContext *s, TCGType type, +static inline bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) { tcg_out_mov_reg(s, COND_AL, ret, arg); + return true; } =20 static inline void tcg_out_movi(TCGContext *s, TCGType type, diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index d5ed9f1ffd..1198c76392 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -809,12 +809,12 @@ static inline void tgen_arithr(TCGContext *s, int sub= op, int dest, int src) tcg_out_modrm(s, OPC_ARITH_GvEv + (subop << 3) + ext, dest, src); } =20 -static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg ar= g) +static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg ar= g) { int rexw =3D 0; =20 if (arg =3D=3D ret) { - return; + return true; } switch (type) { case TCG_TYPE_I64: @@ -852,6 +852,7 @@ static void tcg_out_mov(TCGContext *s, TCGType type, TC= GReg ret, TCGReg arg) default: g_assert_not_reached(); } + return true; } =20 static void tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c index 412cacdcb9..7cafd4a790 100644 --- a/tcg/mips/tcg-target.inc.c +++ b/tcg/mips/tcg-target.inc.c @@ -558,13 +558,14 @@ static inline void tcg_out_dsra(TCGContext *s, TCGReg= rd, TCGReg rt, TCGArg sa) tcg_out_opc_sa64(s, OPC_DSRA, OPC_DSRA32, rd, rt, sa); } =20 -static inline void tcg_out_mov(TCGContext *s, TCGType type, +static inline bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) { /* Simple reg-reg move, optimising out the 'do nothing' case */ if (ret !=3D arg) { tcg_out_opc_reg(s, OPC_OR, ret, arg, TCG_REG_ZERO); } + return true; } =20 static void tcg_out_movi(TCGContext *s, TCGType type, diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index 36b4791707..30c095d3d5 100644 --- a/tcg/ppc/tcg-target.inc.c +++ b/tcg/ppc/tcg-target.inc.c @@ -559,12 +559,13 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int = type, static void tcg_out_mem_long(TCGContext *s, int opi, int opx, TCGReg rt, TCGReg base, tcg_target_long offset); =20 -static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg ar= g) +static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg ar= g) { tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 64 || type =3D=3D TCG_TYPE= _I32); if (ret !=3D arg) { tcg_out32(s, OR | SAB(arg, ret, arg)); } + return true; } =20 static inline void tcg_out_rld(TCGContext *s, int op, TCGReg ra, TCGReg rs, diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c index 2932505094..6497a4dab2 100644 --- a/tcg/riscv/tcg-target.inc.c +++ b/tcg/riscv/tcg-target.inc.c @@ -515,10 +515,10 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int = type, * TCG intrinsics */ =20 -static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg ar= g) +static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg ar= g) { if (ret =3D=3D arg) { - return; + return true; } switch (type) { case TCG_TYPE_I32: @@ -528,6 +528,7 @@ static void tcg_out_mov(TCGContext *s, TCGType type, TC= GReg ret, TCGReg arg) default: g_assert_not_reached(); } + return true; } =20 static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd, diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c index 3d6150b10e..331d51852c 100644 --- a/tcg/s390/tcg-target.inc.c +++ b/tcg/s390/tcg-target.inc.c @@ -548,7 +548,7 @@ static void tcg_out_sh32(TCGContext* s, S390Opcode op, = TCGReg dest, tcg_out_insn_RS(s, op, dest, sh_reg, 0, sh_imm); } =20 -static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg dst, TCGReg sr= c) +static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg dst, TCGReg sr= c) { if (src !=3D dst) { if (type =3D=3D TCG_TYPE_I32) { @@ -557,6 +557,7 @@ static void tcg_out_mov(TCGContext *s, TCGType type, TC= GReg dst, TCGReg src) tcg_out_insn(s, RRE, LGR, dst, src); } } + return true; } =20 static const S390Opcode lli_insns[4] =3D { diff --git a/tcg/sparc/tcg-target.inc.c b/tcg/sparc/tcg-target.inc.c index 7a61839dc1..83295955a7 100644 --- a/tcg/sparc/tcg-target.inc.c +++ b/tcg/sparc/tcg-target.inc.c @@ -407,12 +407,13 @@ static void tcg_out_arithc(TCGContext *s, TCGReg rd, = TCGReg rs1, | (val2const ? INSN_IMM13(val2) : INSN_RS2(val2))); } =20 -static inline void tcg_out_mov(TCGContext *s, TCGType type, +static inline bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) { if (ret !=3D arg) { tcg_out_arith(s, ret, arg, TCG_REG_G0, ARITH_OR); } + return true; } =20 static inline void tcg_out_sethi(TCGContext *s, TCGReg ret, uint32_t arg) diff --git a/tcg/tcg.c b/tcg/tcg.c index 70ca113c26..8ed7cb8654 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -103,7 +103,7 @@ static const char *target_parse_constraint(TCGArgConstr= aint *ct, const char *ct_str, TCGType typ= e); static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg= 1, intptr_t arg2); -static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg ar= g); +static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg ar= g); static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg ret, tcg_target_long arg); static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, @@ -3367,7 +3367,9 @@ static void tcg_reg_alloc_mov(TCGContext *s, const TC= GOp *op) allocated_regs, preferred_regs, ots->indirect_base); } - tcg_out_mov(s, otype, ots->reg, ts->reg); + if (!tcg_out_mov(s, otype, ots->reg, ts->reg)) { + abort(); + } } ots->val_type =3D TEMP_VAL_REG; ots->mem_coherent =3D 0; @@ -3467,7 +3469,9 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCG= Op *op) i_allocated_regs, 0); reg =3D tcg_reg_alloc(s, arg_ct->u.regs, i_allocated_regs, o_preferred_regs, ts->indirect_base); - tcg_out_mov(s, ts->type, reg, ts->reg); + if (!tcg_out_mov(s, ts->type, reg, ts->reg)) { + abort(); + } } new_args[i] =3D reg; const_args[i] =3D 0; @@ -3626,7 +3630,9 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp *= op) if (ts->val_type =3D=3D TEMP_VAL_REG) { if (ts->reg !=3D reg) { tcg_reg_free(s, reg, allocated_regs); - tcg_out_mov(s, ts->type, reg, ts->reg); + if (!tcg_out_mov(s, ts->type, reg, ts->reg)) { + abort(); + } } } else { TCGRegSet arg_set =3D 0; diff --git a/tcg/tci/tcg-target.inc.c b/tcg/tci/tcg-target.inc.c index 0015a98485..992d50cb1e 100644 --- a/tcg/tci/tcg-target.inc.c +++ b/tcg/tci/tcg-target.inc.c @@ -509,7 +509,7 @@ static void tcg_out_ld(TCGContext *s, TCGType type, TCG= Reg ret, TCGReg arg1, old_code_ptr[1] =3D s->code_ptr - old_code_ptr; } =20 -static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg ar= g) +static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg ar= g) { uint8_t *old_code_ptr =3D s->code_ptr; tcg_debug_assert(ret !=3D arg); @@ -521,6 +521,7 @@ static void tcg_out_mov(TCGContext *s, TCGType type, TC= GReg ret, TCGReg arg) tcg_out_r(s, ret); tcg_out_r(s, arg); old_code_ptr[1] =3D s->code_ptr - old_code_ptr; + return true; } =20 static void tcg_out_movi(TCGContext *s, TCGType type, --=20 2.17.1 From nobody Sat May 4 13:31:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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[97.113.189.189]) by smtp.gmail.com with ESMTPSA id 15sm6680423pfo.117.2019.05.03.22.53.11 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 03 May 2019 22:53:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=jMr4oVpt08WI1vYqrX0gvWFc/UY/0FSsdcwMQYw/C7U=; b=c2h62x35D0tEWBi2wiev0uihBeIGg8XZ+w/BZ1QRezzO7FksJClkwfZqzWhUG0GAEG t2lSdH9/XP/lN0IRV1HvMC1+QA8bJD7yE88NWJ9eonmTqyOcUY4qKjBCSe4VD64LrYms POAb9MxSB4HXGKZAHWlGYtQ+RwRCNNrflpa0uw9yK83FjPg0eid97z2c8xlTvxj8cGDB xcVl0+So2ghcTP5dpMj6uaUNsqNZsed0LPI89+HhsB+Mg5Eh0lFYt7BYYN0jMVtRnG0y 7CpDPq7+3AVAWsXUZt+Ii4MI1PWsvGYJD1mgnzzbtp6JmRlfKqS6xZ1QTpd2nBt2/PsG FxpQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=jMr4oVpt08WI1vYqrX0gvWFc/UY/0FSsdcwMQYw/C7U=; b=pARQgvDlVTp4JHppqeH4L75z2T1rR5wchNKxyNVAvQKm5s6g8yk72zxoJr7SF8rcq2 1CeETSERyqMLLQzAfXCtR2VfIQXWxUBaib/jenUAvpGtTUDrwcH9Mn/rN9yzEBMj12FM gxcXCRHAUvmKLPcDfJEujmHTS4OkYV60I9+DYyfJdnaFTPRY6QmDtSLNCUDyWrTISaPd v0mCvRlTfb0CvJxuR2TSlsOw1aQTmfam6S61OfgwkuMtjSQC9q2vxK22KGeaNNb//sK3 7ghZXT66MP1a75hTRSyz5Er1GdfNZDPyw8BtKCvZOEEdPpXzAwZ4EWrFerIIBthh5Z0x cu+g== X-Gm-Message-State: APjAAAV+8WNRESp72Ds4bsgfJk1MY3KZtMnWtJ67pirGQRxjlhG1vkY+ uRdQpma6wcgeBA+VCeJ3KnJQ2kcYayM= X-Google-Smtp-Source: APXvYqwqOShI7Ak9xrxfANm6sPEq+RWwpCihVPvjBI+XNCFhvfnUkfbJ8nCvGOsJLbhp8dgvyHojmg== X-Received: by 2002:a17:902:820c:: with SMTP id x12mr15656378pln.199.1556949192547; Fri, 03 May 2019 22:53:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 3 May 2019 22:52:37 -0700 Message-Id: <20190504055300.18426-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190504055300.18426-1-richard.henderson@linaro.org> References: <20190504055300.18426-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::644 Subject: [Qemu-devel] [PATCH v3 08/31] tcg: Support cross-class moves without instruction support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" PowerPC Altivec does not support direct moves between vector registers and general registers. So when tcg_out_mov fails, we can use the backing memory for the temporary to perform the move. Acked-by: David Hildenbrand Signed-off-by: Richard Henderson --- tcg/tcg.c | 31 ++++++++++++++++++++++++++++--- 1 file changed, 28 insertions(+), 3 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index 8ed7cb8654..68d86361e2 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -3368,7 +3368,20 @@ static void tcg_reg_alloc_mov(TCGContext *s, const T= CGOp *op) ots->indirect_base); } if (!tcg_out_mov(s, otype, ots->reg, ts->reg)) { - abort(); + /* + * Cross register class move not supported. + * Store the source register into the destination slot + * and leave the destination temp as TEMP_VAL_MEM. + */ + assert(!ots->fixed_reg); + if (!ts->mem_allocated) { + temp_allocate_frame(s, ots); + } + tcg_out_st(s, ts->type, ts->reg, + ots->mem_base->reg, ots->mem_offset); + ots->mem_coherent =3D 1; + temp_free_or_dead(s, ots, -1); + return; } } ots->val_type =3D TEMP_VAL_REG; @@ -3470,7 +3483,13 @@ static void tcg_reg_alloc_op(TCGContext *s, const TC= GOp *op) reg =3D tcg_reg_alloc(s, arg_ct->u.regs, i_allocated_regs, o_preferred_regs, ts->indirect_base); if (!tcg_out_mov(s, ts->type, reg, ts->reg)) { - abort(); + /* + * Cross register class move not supported. Sync the + * temp back to its slot and load from there. + */ + temp_sync(s, ts, i_allocated_regs, 0, 0); + tcg_out_ld(s, ts->type, reg, + ts->mem_base->reg, ts->mem_offset); } } new_args[i] =3D reg; @@ -3631,7 +3650,13 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp = *op) if (ts->reg !=3D reg) { tcg_reg_free(s, reg, allocated_regs); if (!tcg_out_mov(s, ts->type, reg, ts->reg)) { - abort(); + /* + * Cross register class move not supported. Sync = the + * temp back to its slot and load from there. + */ + temp_sync(s, ts, allocated_regs, 0, 0); + tcg_out_ld(s, ts->type, reg, + ts->mem_base->reg, ts->mem_offset); } } } else { --=20 2.17.1 From nobody Sat May 4 13:31:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1556949667; cv=none; d=zoho.com; s=zohoarc; b=F4Dt+0uRKWzm1sW+F9iBnTTohPJWVF2OoZL6/tyWijuQwP5vbhydE0AnQJR4IZB1aWQd9nGeBucrnKqgpIccsPLWDTpB6nm96IaEtEI37K1Gzpndb1EUVnjMRIgj65bh36lFmPb6njtzjyfMjOSbsB8yIwZpX0V2DhFZH82KQac= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1556949667; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=vlsz3mBJLHv925hZ117IYDgBd7E32bASu3EG/5gz9gQ=; b=TaGVC1g/ASHg2f4wP+VjVF1zd0HohZ/2RR0Ltv0yX5u/iAvpisZ1A0ecblTxcBGfuS6FEBoRu44QUrACgDouP6dlglYmaGTlPQEp6x0g1hQhXfX/Wc2/dYnGCsp5Lg0+2vTRLKXYpqmXiS7L1N3M51MyZ+kqbhEK1IoEmpCnqwI= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1556949667237884.3960209903125; Fri, 3 May 2019 23:01:07 -0700 (PDT) Received: from localhost ([127.0.0.1]:51709 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hMnjI-00056J-VI for importer@patchew.org; Sat, 04 May 2019 02:01:01 -0400 Received: from eggs.gnu.org ([209.51.188.92]:41763) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hMnbo-0007kp-6q for qemu-devel@nongnu.org; Sat, 04 May 2019 01:53:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hMnbn-0004C2-1j for qemu-devel@nongnu.org; Sat, 04 May 2019 01:53:16 -0400 Received: from mail-pl1-x642.google.com ([2607:f8b0:4864:20::642]:39679) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hMnbm-0004BP-Rz for qemu-devel@nongnu.org; Sat, 04 May 2019 01:53:14 -0400 Received: by mail-pl1-x642.google.com with SMTP id e92so3730810plb.6 for ; Fri, 03 May 2019 22:53:14 -0700 (PDT) Received: from localhost.localdomain (97-113-189-189.tukw.qwest.net. [97.113.189.189]) by smtp.gmail.com with ESMTPSA id 15sm6680423pfo.117.2019.05.03.22.53.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 03 May 2019 22:53:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vlsz3mBJLHv925hZ117IYDgBd7E32bASu3EG/5gz9gQ=; b=GF6inBISMAYTZATq54aHQ1fUwfGkZ/GsyN0zwUP5vvGvEXqfsraqvNEBGjclTCgKQJ OLPP0FB8iloq2xcpZJnoyrKQ5IlYJmo28tZeb0nM6LqPrsiCsgeCnkjd0BW6OoXpcRuZ ny7axcbZ9x1qN8/tlqCuDnIP9jRL862h0fIIF/F+t2ixIfskuRpwFpayXDDCQ8CBn7E0 eT3/3SS14inU0a3Sz2IfMFV/7rtDaHsvoUbrq8nuTkYQfIzCtttj/X6C09+yLJT3qZOg oekhIVyYJb0yDoyOvyhfuXj77CVJOBDR1t5pNnCxndBG+Z5yc+RYq6PeeiGI1yPl1omS sXpg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vlsz3mBJLHv925hZ117IYDgBd7E32bASu3EG/5gz9gQ=; b=mmcDNHKGJT328IFIlrzJXBqagaCTaPTg3UuzFUF1i88j8QXciy2dzEZzE+Jxr6pP3z dlL5y1O6lmj+OvARL4HYRjMUzokRxQSsvPBv3LRyz4DNwNuxsmvHRWZt377ycDSJBFsH EK7aR6KDDYrK88T3NVMB4fUtpIsm/3KRufQoB+g5Mgnis+Jcb3buoBiU5W4jt4n2NNMZ Tx9R3HoU7Ru535KM40Kk5ebnK02t2lOR5bC2tvtKoC+NIKQT2poyVy0qyN8sNc0UiUzS RzLA7Lj+jS8vGLhwFzXCtCh0tUDm/AJpcf8w1VWpNh+zO7v6cvN4SHWu98lf95tNmbsY M7/A== X-Gm-Message-State: APjAAAVkY+rJg03RifKhoS02ukYT5hmpTk2dxeIMWtDfGfG88rU90QLx zpzzNotYU5oJeLS7A34mjwUFaOfq1ys= X-Google-Smtp-Source: APXvYqwz6a8VSuBJwfgp3UCA+13gjM/Y9NRsptcgqlXymRNUYunG3aBZAQhiMZ9Ch2w/wioTodvzZQ== X-Received: by 2002:a17:902:42a5:: with SMTP id h34mr10507298pld.146.1556949193550; Fri, 03 May 2019 22:53:13 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 3 May 2019 22:52:38 -0700 Message-Id: <20190504055300.18426-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190504055300.18426-1-richard.henderson@linaro.org> References: <20190504055300.18426-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::642 Subject: [Qemu-devel] [PATCH v3 09/31] tcg: Promote tcg_out_{dup, dupi}_vec to backend interface X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) The i386 backend already has these functions, and the aarch64 backend could easily split out one. Nothing is done with these functions yet, but this will aid register allocation of INDEX_op_dup_vec in a later patch. Adjust the aarch64 tcg_out_dupi_vec signature to match the new interface. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.inc.c | 12 ++++++++++-- tcg/i386/tcg-target.inc.c | 3 ++- tcg/tcg.c | 14 ++++++++++++++ 3 files changed, 26 insertions(+), 3 deletions(-) diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c index ee89734318..e443b5df23 100644 --- a/tcg/aarch64/tcg-target.inc.c +++ b/tcg/aarch64/tcg-target.inc.c @@ -799,7 +799,7 @@ static void tcg_out_logicali(TCGContext *s, AArch64Insn= insn, TCGType ext, } =20 static void tcg_out_dupi_vec(TCGContext *s, TCGType type, - TCGReg rd, uint64_t v64) + TCGReg rd, tcg_target_long v64) { int op, cmode, imm8; =20 @@ -814,6 +814,14 @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType ty= pe, } } =20 +static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, + TCGReg rd, TCGReg rs) +{ + int is_q =3D type - TCG_TYPE_V64; + tcg_out_insn(s, 3605, DUP, is_q, rd, rs, 1 << vece, 0); + return true; +} + static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd, tcg_target_long value) { @@ -2201,7 +2209,7 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode o= pc, tcg_out_insn(s, 3617, NOT, is_q, 0, a0, a1); break; case INDEX_op_dup_vec: - tcg_out_insn(s, 3605, DUP, is_q, a0, a1, 1 << vece, 0); + tcg_out_dup_vec(s, type, vece, a0, a1); break; case INDEX_op_shli_vec: tcg_out_insn(s, 3614, SHL, is_q, a0, a1, a2 + (8 << vece)); diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index 1198c76392..0d621670c7 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -855,7 +855,7 @@ static bool tcg_out_mov(TCGContext *s, TCGType type, TC= GReg ret, TCGReg arg) return true; } =20 -static void tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, +static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, TCGReg r, TCGReg a) { if (have_avx2) { @@ -888,6 +888,7 @@ static void tcg_out_dup_vec(TCGContext *s, TCGType type= , unsigned vece, g_assert_not_reached(); } } + return true; } =20 static void tcg_out_dupi_vec(TCGContext *s, TCGType type, diff --git a/tcg/tcg.c b/tcg/tcg.c index 68d86361e2..3ef4d3478d 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -109,10 +109,24 @@ static void tcg_out_movi(TCGContext *s, TCGType type, static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, const int *const_args); #if TCG_TARGET_MAYBE_vec +static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, + TCGReg dst, TCGReg src); +static void tcg_out_dupi_vec(TCGContext *s, TCGType type, + TCGReg dst, tcg_target_long arg); static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, unsigned vecl, unsigned vece, const TCGArg *args, const int *const_args); #else +static inline bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned v= ece, + TCGReg dst, TCGReg src) +{ + g_assert_not_reached(); +} +static inline void tcg_out_dupi_vec(TCGContext *s, TCGType type, + TCGReg dst, tcg_target_long arg) +{ + g_assert_not_reached(); +} static inline void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, unsigned v= ecl, unsigned vece, const TCGArg *args, const int *const_args) --=20 2.17.1 From nobody Sat May 4 13:31:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[97.113.189.189]) by smtp.gmail.com with ESMTPSA id 15sm6680423pfo.117.2019.05.03.22.53.13 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 03 May 2019 22:53:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=0NdT1vVANH/LILN+5zIlMLc6x66kLizQd46/eOmSl1E=; b=h1SQu/m1hNKn0yLNsK3U5VqM8oyjONTGcTpIwAjl6JeKWTJ1ate7bfqpwqBq3dx7Vc Ft1f6MMG2iA/11aYuTvGLKk+eZgyBQc0SJr6wJJ+JKS0mM1mfadxnU8DnTmA6lJ5ZiQu +/zHF+mZ9usD5q0ZP/fpJLxYizyBA5kYvD7L8RDYbYgAn0mMEoBVR8wByrLFINk9U7qx cBh/TcRLbeuo6/n/oF2Nzr8R/ZSgo1g43tNs5zsHdOIfISyVD7VDVzD+nQvPFuLHwxzG xI4CL/7w+PHt5kvsYpzZD9BHGLpJQZQUPlZt4V8AHw4MNg9O/vw1tWgYO3S60ZWIgkAB bS0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=0NdT1vVANH/LILN+5zIlMLc6x66kLizQd46/eOmSl1E=; b=bjduMTvOuSXNGwZk0lr3Qdri0UFZTZ60dnb3SfmIiZ5F3oLMQktbOqF5doYCPNNeXp l74DYNu6IxtazBq7aUJdi40IuLISyEspI4XU0mAxK/dsWwLopvZZ2whLoNmQl9L22dKs lWbaIXQ2UECYKlA5KwF4XR8ZlG4aFCBTyaJGpOhBng+GL8PurFhVNSjXZIR+PgPk7uQT mfUFLHjiyek6rkatdT6JUooIK+dOy+FSD8NHD2+Cnt8WsrvIfZMdt0vfMSH8gwk1wavq 3/nfAPdZyli95s+t4cM/Vf/ZeQClSCLILYDn1mtV5C7SVy084o/K2xKbQlIrWC5DugIQ yt0A== X-Gm-Message-State: APjAAAUdWbTOBLWezDGX1GWVjxX2p37blnEJyHea+wC6uBOFrPBABRBK Kp8qB1j2961fhM9KcksCQCznd2RVcFQ= X-Google-Smtp-Source: APXvYqzRYAIheGB1pcsnTQWS8YyA0ajYl49d1Fex5K4ZbLsy7zYQe8K69AQbTnpquq3HZccmKk4+tw== X-Received: by 2002:a17:902:8ec8:: with SMTP id x8mr16053421plo.21.1556949194695; Fri, 03 May 2019 22:53:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 3 May 2019 22:52:39 -0700 Message-Id: <20190504055300.18426-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190504055300.18426-1-richard.henderson@linaro.org> References: <20190504055300.18426-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::630 Subject: [Qemu-devel] [PATCH v3 10/31] tcg: Manually expand INDEX_op_dup_vec X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This case is similar to INDEX_op_mov_* in that we need to do different things depending on the current location of the source. Signed-off-by: Richard Henderson --- v3: Added some commentary to the tcg_reg_alloc_* functions. --- tcg/aarch64/tcg-target.inc.c | 9 ++- tcg/i386/tcg-target.inc.c | 8 +-- tcg/tcg.c | 111 +++++++++++++++++++++++++++++++++++ 3 files changed, 118 insertions(+), 10 deletions(-) diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c index e443b5df23..3cefdd1e43 100644 --- a/tcg/aarch64/tcg-target.inc.c +++ b/tcg/aarch64/tcg-target.inc.c @@ -2108,10 +2108,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, =20 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ case INDEX_op_mov_i64: - case INDEX_op_mov_vec: case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */ case INDEX_op_movi_i64: - case INDEX_op_dupi_vec: case INDEX_op_call: /* Always emitted via tcg_out_call. */ default: g_assert_not_reached(); @@ -2208,9 +2206,6 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode o= pc, case INDEX_op_not_vec: tcg_out_insn(s, 3617, NOT, is_q, 0, a0, a1); break; - case INDEX_op_dup_vec: - tcg_out_dup_vec(s, type, vece, a0, a1); - break; case INDEX_op_shli_vec: tcg_out_insn(s, 3614, SHL, is_q, a0, a1, a2 + (8 << vece)); break; @@ -2254,6 +2249,10 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, } } break; + + case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */ + case INDEX_op_dupi_vec: /* Always emitted via tcg_out_movi. */ + case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */ default: g_assert_not_reached(); } diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index 0d621670c7..3c8229d413 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -2603,10 +2603,8 @@ static inline void tcg_out_op(TCGContext *s, TCGOpco= de opc, break; case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ case INDEX_op_mov_i64: - case INDEX_op_mov_vec: case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */ case INDEX_op_movi_i64: - case INDEX_op_dupi_vec: case INDEX_op_call: /* Always emitted via tcg_out_call. */ default: tcg_abort(); @@ -2795,9 +2793,6 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode o= pc, case INDEX_op_st_vec: tcg_out_st(s, type, a0, a1, a2); break; - case INDEX_op_dup_vec: - tcg_out_dup_vec(s, type, vece, a0, a1); - break; =20 case INDEX_op_x86_shufps_vec: insn =3D OPC_SHUFPS; @@ -2839,6 +2834,9 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode o= pc, tcg_out8(s, a2); break; =20 + case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */ + case INDEX_op_dupi_vec: /* Always emitted via tcg_out_movi. */ + case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */ default: g_assert_not_reached(); } diff --git a/tcg/tcg.c b/tcg/tcg.c index 3ef4d3478d..2b715bf099 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -3284,6 +3284,9 @@ static void tcg_reg_alloc_bb_end(TCGContext *s, TCGRe= gSet allocated_regs) save_globals(s, allocated_regs); } =20 +/* + * Specialized code generation for INDEX_op_movi_*. + */ static void tcg_reg_alloc_do_movi(TCGContext *s, TCGTemp *ots, tcg_target_ulong val, TCGLifeData arg_li= fe, TCGRegSet preferred_regs) @@ -3313,6 +3316,9 @@ static void tcg_reg_alloc_movi(TCGContext *s, const T= CGOp *op) tcg_reg_alloc_do_movi(s, ots, val, op->life, op->output_pref[0]); } =20 +/* + * Specialized code generation for INDEX_op_mov_*. + */ static void tcg_reg_alloc_mov(TCGContext *s, const TCGOp *op) { const TCGLifeData arg_life =3D op->life; @@ -3407,6 +3413,108 @@ static void tcg_reg_alloc_mov(TCGContext *s, const = TCGOp *op) } } =20 +/* + * Specialized code generation for INDEX_op_dup_vec. + */ +static void tcg_reg_alloc_dup(TCGContext *s, const TCGOp *op) +{ + const TCGLifeData arg_life =3D op->life; + TCGRegSet dup_out_regs, dup_in_regs; + TCGTemp *its, *ots; + TCGType itype, vtype; + unsigned vece; + bool ok; + + ots =3D arg_temp(op->args[0]); + its =3D arg_temp(op->args[1]); + + /* ENV should not be modified. */ + tcg_debug_assert(!ots->fixed_reg); + + itype =3D its->type; + vece =3D TCGOP_VECE(op); + vtype =3D TCGOP_VECL(op) + TCG_TYPE_V64; + + if (its->val_type =3D=3D TEMP_VAL_CONST) { + /* Propagate constant via movi -> dupi. */ + tcg_target_ulong val =3D its->val; + if (IS_DEAD_ARG(1)) { + temp_dead(s, its); + } + tcg_reg_alloc_do_movi(s, ots, val, arg_life, op->output_pref[0]); + return; + } + + dup_out_regs =3D tcg_op_defs[INDEX_op_dup_vec].args_ct[0].u.regs; + dup_in_regs =3D tcg_op_defs[INDEX_op_dup_vec].args_ct[1].u.regs; + + /* Allocate the output register now. */ + if (ots->val_type !=3D TEMP_VAL_REG) { + TCGRegSet allocated_regs =3D s->reserved_regs; + + if (!IS_DEAD_ARG(1) && its->val_type =3D=3D TEMP_VAL_REG) { + /* Make sure to not spill the input register. */ + tcg_regset_set_reg(allocated_regs, its->reg); + } + ots->reg =3D tcg_reg_alloc(s, dup_out_regs, allocated_regs, + op->output_pref[0], ots->indirect_base); + ots->val_type =3D TEMP_VAL_REG; + ots->mem_coherent =3D 0; + s->reg_to_temp[ots->reg] =3D ots; + } + + switch (its->val_type) { + case TEMP_VAL_REG: + /* + * The dup constriaints must be broad, covering all possible VECE. + * However, tcg_op_dup_vec() gets to see the VECE and we allow it + * to fail, indicating that extra moves are required for that case. + */ + if (tcg_regset_test_reg(dup_in_regs, its->reg)) { + if (tcg_out_dup_vec(s, vtype, vece, ots->reg, its->reg)) { + goto done; + } + /* Try again from memory or a vector input register. */ + } + if (!its->mem_coherent) { + /* + * The input register is not synced, and so an extra store + * would be required to use memory. Attempt an integer-vector + * register move first. We do not have a TCGRegSet for this. + */ + if (tcg_out_mov(s, itype, ots->reg, its->reg)) { + break; + } + /* Sync the temp back to its slot and load from there. */ + temp_sync(s, its, s->reserved_regs, 0, 0); + } + /* fall through */ + + case TEMP_VAL_MEM: + /* TODO: dup from memory */ + tcg_out_ld(s, itype, ots->reg, its->mem_base->reg, its->mem_offset= ); + break; + + default: + g_assert_not_reached(); + } + + /* We now have a vector input register, so dup must succeed. */ + ok =3D tcg_out_dup_vec(s, vtype, vece, ots->reg, ots->reg); + tcg_debug_assert(ok); + + done: + if (IS_DEAD_ARG(1)) { + temp_dead(s, its); + } + if (NEED_SYNC_ARG(0)) { + temp_sync(s, ots, s->reserved_regs, 0, 0); + } + if (IS_DEAD_ARG(0)) { + temp_dead(s, ots); + } +} + static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op) { const TCGLifeData arg_life =3D op->life; @@ -3981,6 +4089,9 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) case INDEX_op_dupi_vec: tcg_reg_alloc_movi(s, op); break; + case INDEX_op_dup_vec: + tcg_reg_alloc_dup(s, op); + break; case INDEX_op_insn_start: if (num_insns >=3D 0) { size_t off =3D tcg_current_code_size(s); --=20 2.17.1 From nobody Sat May 4 13:31:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1556949850; cv=none; d=zoho.com; s=zohoarc; b=allK369EsLeBEoClOuEYeQ7rN2H6ZkFJ0EnaDvAum0IjdabOCZpZXc0CHdgmp3mC+APuKPZdzmEVnZznxLrP+rr3M9mXa4a7nU9CFw8XFk2ydLlZZE7Wbq1qCkyaR8FVNqbPiX8EReL1XcDAvqzZnb+9yS+SodOjig6OKetsfDU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1556949850; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=yjaWcvw9UbJX/NgPrNoAKyN+ZZwbI4Jl9YPntsAKSX4=; b=kSGIG7ogVYoLjwYHUjxk+9QZhpYnOvT+kzfwILeafMN4FFGSBvAPJQzIVnHMUHFtafwbMYKmpgZRtu3CEt6q6NoBYQMIWRP4hbzHOZ3vZAgdLC28/iXxPxp0AbLC+8J/287H8/WwU7b8/FlTGkTk5Bq4UhUWOPPD/7gic3M0l8E= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1556949849976490.58440233230544; Fri, 3 May 2019 23:04:09 -0700 (PDT) Received: from localhost ([127.0.0.1]:51745 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hMnmF-0007Yu-Ow for importer@patchew.org; Sat, 04 May 2019 02:04:03 -0400 Received: from eggs.gnu.org ([209.51.188.92]:41786) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hMnbq-0007mR-6D for qemu-devel@nongnu.org; Sat, 04 May 2019 01:53:20 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hMnbp-0004Et-3q for qemu-devel@nongnu.org; Sat, 04 May 2019 01:53:18 -0400 Received: from mail-pl1-x643.google.com ([2607:f8b0:4864:20::643]:43265) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hMnbo-0004EX-UD for qemu-devel@nongnu.org; Sat, 04 May 2019 01:53:17 -0400 Received: by mail-pl1-x643.google.com with SMTP id n8so3723863plp.10 for ; Fri, 03 May 2019 22:53:16 -0700 (PDT) Received: from localhost.localdomain (97-113-189-189.tukw.qwest.net. [97.113.189.189]) by smtp.gmail.com with ESMTPSA id 15sm6680423pfo.117.2019.05.03.22.53.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 03 May 2019 22:53:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=yjaWcvw9UbJX/NgPrNoAKyN+ZZwbI4Jl9YPntsAKSX4=; b=Pz3g8Bl5GlOK0uwydAsWCYeYWC4KXpsFIrBDgck9hqexVJzxjQdxiZRIg9AeofZhlI wTq5sXhsVEeuU4S2iMaUOPFu/BGBRHqtVexRT5jGr4W4sxf8SXS/ie6CvDQK6vgf+iXI /yQYbDzorhvKB9919zp2x4XQ+FVBaESiK8iPqtLHLY2nqTCbHCiYpKRfwKcYTJIYrcVJ ZgFKqSFXtraEDq7o67zyuyAfWUgKTU+nSq/BYKm6XhvimIoJxJVEfYBo+iH53lwRaB8J Aq2FXASGaBP+jfT9QFxObwIjUKnEQkpTEygDLutgd62x7T7NeVcI1tTaR0zjB1WARknB P9mw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=yjaWcvw9UbJX/NgPrNoAKyN+ZZwbI4Jl9YPntsAKSX4=; b=Gg1ZyNQ4+tkECQJ8kAHkbdlGhbJqIaCrssY16XXVKCU7UejgZVAwmGlYJ+6hUSIyrS vNlGUdwMkxVaWafhw9QbU/vKUDk8RtpPRx5lp+m7qq+wHd/z91llV5wdpkxTyoy8bbhE Ldw6zj8cpXKCUbME6PvNSls9W8bWm4OzlipZSMsv+s1RzIAVgF/fSyjTUkMZdbopDSLh NfQ4pbURO7+7ub70pIqdNBlz0NNxPdX6u0l3edEHIOvWcLzMcC1Zzd2ndFXYPBuQ92xq Zg22WFXChLkDdzsDnFDgRwfuVpdZVhVToO+lwxqpVErjWkAWU2E2LDPwn72NY4PoZLSD fb2g== X-Gm-Message-State: APjAAAXX4hDx7xu/4JOtg8efVx0dSZE3BAG0RmnzrjnRw2uZeY06fhz9 0p4R2+ECjQjfnGhV2ElEKty0Khefn1s= X-Google-Smtp-Source: APXvYqxFU7KvjqpPEOXfiIgIk86AhJpKIaCSJKUi6JuVk/u9s4rSwiC3v1b8epbZOlcNgEJf8BhS2A== X-Received: by 2002:a17:902:521:: with SMTP id 30mr15799157plf.248.1556949195769; Fri, 03 May 2019 22:53:15 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 3 May 2019 22:52:40 -0700 Message-Id: <20190504055300.18426-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190504055300.18426-1-richard.henderson@linaro.org> References: <20190504055300.18426-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 Subject: [Qemu-devel] [PATCH v3 11/31] tcg: Add tcg_out_dupm_vec to the backend interface X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Currently stubbed out in all backends that support vectors. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.inc.c | 6 ++++++ tcg/i386/tcg-target.inc.c | 7 +++++++ tcg/tcg.c | 19 ++++++++++++++++++- 3 files changed, 31 insertions(+), 1 deletion(-) diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c index 3cefdd1e43..4a3cfa778a 100644 --- a/tcg/aarch64/tcg-target.inc.c +++ b/tcg/aarch64/tcg-target.inc.c @@ -822,6 +822,12 @@ static bool tcg_out_dup_vec(TCGContext *s, TCGType typ= e, unsigned vece, return true; } =20 +static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, + TCGReg r, TCGReg base, intptr_t offset) +{ + return false; +} + static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd, tcg_target_long value) { diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index 3c8229d413..f04933bc19 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -891,6 +891,13 @@ static bool tcg_out_dup_vec(TCGContext *s, TCGType typ= e, unsigned vece, return true; } =20 +static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, + TCGReg r, TCGReg base, intptr_t offset) +{ + return false; +} + + static void tcg_out_dupi_vec(TCGContext *s, TCGType type, TCGReg ret, tcg_target_long arg) { diff --git a/tcg/tcg.c b/tcg/tcg.c index 2b715bf099..b9945794c4 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -111,6 +111,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, co= nst TCGArg *args, #if TCG_TARGET_MAYBE_vec static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, TCGReg dst, TCGReg src); +static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, + TCGReg dst, TCGReg base, intptr_t offset); static void tcg_out_dupi_vec(TCGContext *s, TCGType type, TCGReg dst, tcg_target_long arg); static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, unsigned vecl, @@ -122,6 +124,11 @@ static inline bool tcg_out_dup_vec(TCGContext *s, TCGT= ype type, unsigned vece, { g_assert_not_reached(); } +static inline bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned = vece, + TCGReg dst, TCGReg base, intptr_t offs= et) +{ + g_assert_not_reached(); +} static inline void tcg_out_dupi_vec(TCGContext *s, TCGType type, TCGReg dst, tcg_target_long arg) { @@ -3422,6 +3429,7 @@ static void tcg_reg_alloc_dup(TCGContext *s, const TC= GOp *op) TCGRegSet dup_out_regs, dup_in_regs; TCGTemp *its, *ots; TCGType itype, vtype; + intptr_t endian_fixup; unsigned vece; bool ok; =20 @@ -3491,7 +3499,16 @@ static void tcg_reg_alloc_dup(TCGContext *s, const T= CGOp *op) /* fall through */ =20 case TEMP_VAL_MEM: - /* TODO: dup from memory */ +#ifdef HOST_WORDS_BIGENDIAN + endian_fixup =3D itype =3D=3D TCG_TYPE_I32 ? 4 : 8; + endian_fixup -=3D 1 << vece; +#else + endian_fixup =3D 0; +#endif + if (tcg_out_dupm_vec(s, vtype, vece, ots->reg, its->mem_base->reg, + its->mem_offset + endian_fixup)) { + goto done; + } tcg_out_ld(s, itype, ots->reg, its->mem_base->reg, its->mem_offset= ); break; =20 --=20 2.17.1 From nobody Sat May 4 13:31:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1556950029; cv=none; d=zoho.com; s=zohoarc; b=bUdXnGUZ04z2SJkTClZyGbnQ5i7ETcb8V9hae2pcl4I/L81q5xdOPqDnhNGsD88ZVYxChVt7Euz8tYWMfzzpzgxZqfHlhaIFTWBZH9pqhT8SaekL2C5MjXG/GxlsmV+GxRQeCn3AbdNsVMgVCPy0KstYBvAYkqRz5l12ioWR1Qk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1556950029; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=4qREfMgDOvDIZnxD8mHxrlGbKtAgS56ZNj2GB4ImDXs=; b=KCnnkr+o6sgh2Q5aTx92+NdJWSIZ7J3bJtekchWRhacuHyFlXMi228Xewl4Kf6Rdj41RGwLz8oGHQdYp17RxQjt79X4rbEOUtdr74bo1xWpLmX+B+GvjgJFAL7uagLo6f941QcVRm8yTk1oGcfbg0hRpxZn66b9DXVZYO65nZHM= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1556950029768722.674202242842; Fri, 3 May 2019 23:07:09 -0700 (PDT) Received: from localhost ([127.0.0.1]:51796 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hMnp9-0001WL-IR for importer@patchew.org; Sat, 04 May 2019 02:07:03 -0400 Received: from eggs.gnu.org ([209.51.188.92]:41804) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hMnbr-0007nN-C5 for qemu-devel@nongnu.org; Sat, 04 May 2019 01:53:20 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hMnbq-0004Hf-8l for qemu-devel@nongnu.org; Sat, 04 May 2019 01:53:19 -0400 Received: from mail-pl1-x643.google.com ([2607:f8b0:4864:20::643]:37789) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hMnbq-0004F5-2e for qemu-devel@nongnu.org; Sat, 04 May 2019 01:53:18 -0400 Received: by mail-pl1-x643.google.com with SMTP id z8so3737565pln.4 for ; Fri, 03 May 2019 22:53:18 -0700 (PDT) Received: from localhost.localdomain (97-113-189-189.tukw.qwest.net. [97.113.189.189]) by smtp.gmail.com with ESMTPSA id 15sm6680423pfo.117.2019.05.03.22.53.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 03 May 2019 22:53:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=4qREfMgDOvDIZnxD8mHxrlGbKtAgS56ZNj2GB4ImDXs=; b=uHcom7lbdbAHTa7Uh7NSEvhxxrGz9AHCDKPqv2B7ogzinWA2Ru5bFDpWi6WhqoJvNH F6guMw0RH+pFbWjjmSTU5vFsxsA5BbfMOTfBKou+roZoBePMfjiejkVxK7h0Mrskje4d uZ3G9/LD3omJ/E01aup2gVXOnBG1bF1r6lSH+HZNNZtylFg5V/vTOjFWxFAQyFVdpS+S wmKOSlM8dSC4f7Sy8O4efZ9RLBrM0SeszcMdEJnanyahFUaXBxGqq74iwAQsoZatU7+Y 023QXn+FvWZjN0ni7ajX1Fqwsm9J9psSerupuOWKYzAKTQA8gUfgEmxH34DA8rJS64j+ iUIw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=4qREfMgDOvDIZnxD8mHxrlGbKtAgS56ZNj2GB4ImDXs=; b=D6FKE7IcHiV1F0CCDeWz3GgMjXIbOVAlu43+M2L+hf++gZOu44be4jJNSNcwDQExua z8ecfJpYpusWXOk2Iqn68fHWSO4cfuvjVgamtgRzl03LENDVTgFkeBB8xbu5DvZ+EArb HV87xgZGIwIESyfjbYoXncKfrh2Z4otb6YHbK4bcfZRi0WwnSLSPym5+Af5F0tHTttcH 3KXZdlRWX41wxFBrtGCbFDX3RIWomxQ/vgq+j9bAGHkgpMu3v4hP9o/nUWZ72MRQxZFL MJZQXq8EYTz2vb5uBRldc7aK7WDSQ1OL6PGRMz8MMv1YwYUF35j6oH5o1W04s9mYXORj RrJQ== X-Gm-Message-State: APjAAAXjsIGsgswlMmUh6gBhLkHTsgzWhvAAVOrJG9XltcMbwRiRnlA0 4zAkqlzsn6Ov4gW/BR73lXC9yNLBj9U= X-Google-Smtp-Source: APXvYqw5hcWA4hzYx6Qh/odviPSA2cAk1pjC9Pe26TtNzMuHq9xREEnzDWWKbLfXYUAg8p3Ho0Gnng== X-Received: by 2002:a17:902:7590:: with SMTP id j16mr16519061pll.296.1556949196878; Fri, 03 May 2019 22:53:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 3 May 2019 22:52:41 -0700 Message-Id: <20190504055300.18426-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190504055300.18426-1-richard.henderson@linaro.org> References: <20190504055300.18426-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 Subject: [Qemu-devel] [PATCH v3 12/31] tcg/i386: Implement tcg_out_dupm_vec X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" At the same time, improve tcg_out_dupi_vec wrt broadcast from the constant pool. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.inc.c | 57 +++++++++++++++++++++++++++++---------- 1 file changed, 43 insertions(+), 14 deletions(-) diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index f04933bc19..f4bd00e24f 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -358,7 +358,6 @@ static inline int tcg_target_const_match(tcg_target_lon= g val, TCGType type, #define OPC_MOVBE_MyGy (0xf1 | P_EXT38) #define OPC_MOVD_VyEy (0x6e | P_EXT | P_DATA16) #define OPC_MOVD_EyVy (0x7e | P_EXT | P_DATA16) -#define OPC_MOVDDUP (0x12 | P_EXT | P_SIMDF2) #define OPC_MOVDQA_VxWx (0x6f | P_EXT | P_DATA16) #define OPC_MOVDQA_WxVx (0x7f | P_EXT | P_DATA16) #define OPC_MOVDQU_VxWx (0x6f | P_EXT | P_SIMDF3) @@ -458,6 +457,10 @@ static inline int tcg_target_const_match(tcg_target_lo= ng val, TCGType type, #define OPC_UD2 (0x0b | P_EXT) #define OPC_VPBLENDD (0x02 | P_EXT3A | P_DATA16) #define OPC_VPBLENDVB (0x4c | P_EXT3A | P_DATA16) +#define OPC_VPINSRB (0x20 | P_EXT3A | P_DATA16) +#define OPC_VPINSRW (0xc4 | P_EXT | P_DATA16) +#define OPC_VBROADCASTSS (0x18 | P_EXT38 | P_DATA16) +#define OPC_VBROADCASTSD (0x19 | P_EXT38 | P_DATA16) #define OPC_VPBROADCASTB (0x78 | P_EXT38 | P_DATA16) #define OPC_VPBROADCASTW (0x79 | P_EXT38 | P_DATA16) #define OPC_VPBROADCASTD (0x58 | P_EXT38 | P_DATA16) @@ -855,16 +858,17 @@ static bool tcg_out_mov(TCGContext *s, TCGType type, = TCGReg ret, TCGReg arg) return true; } =20 +static const int avx2_dup_insn[4] =3D { + OPC_VPBROADCASTB, OPC_VPBROADCASTW, + OPC_VPBROADCASTD, OPC_VPBROADCASTQ, +}; + static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, TCGReg r, TCGReg a) { if (have_avx2) { - static const int dup_insn[4] =3D { - OPC_VPBROADCASTB, OPC_VPBROADCASTW, - OPC_VPBROADCASTD, OPC_VPBROADCASTQ, - }; int vex_l =3D (type =3D=3D TCG_TYPE_V256 ? P_VEXL : 0); - tcg_out_vex_modrm(s, dup_insn[vece] + vex_l, r, 0, a); + tcg_out_vex_modrm(s, avx2_dup_insn[vece] + vex_l, r, 0, a); } else { switch (vece) { case MO_8: @@ -894,10 +898,35 @@ static bool tcg_out_dup_vec(TCGContext *s, TCGType ty= pe, unsigned vece, static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, TCGReg r, TCGReg base, intptr_t offset) { - return false; + if (have_avx2) { + int vex_l =3D (type =3D=3D TCG_TYPE_V256 ? P_VEXL : 0); + tcg_out_vex_modrm_offset(s, avx2_dup_insn[vece] + vex_l, + r, 0, base, offset); + } else { + switch (vece) { + case MO_64: + tcg_out_vex_modrm_offset(s, OPC_VBROADCASTSD, r, 0, base, offs= et); + break; + case MO_32: + tcg_out_vex_modrm_offset(s, OPC_VBROADCASTSS, r, 0, base, offs= et); + break; + case MO_16: + tcg_out_vex_modrm_offset(s, OPC_VPINSRW, r, r, base, offset); + tcg_out8(s, 0); /* imm8 */ + tcg_out_dup_vec(s, type, vece, r, r); + break; + case MO_8: + tcg_out_vex_modrm_offset(s, OPC_VPINSRB, r, r, base, offset); + tcg_out8(s, 0); /* imm8 */ + tcg_out_dup_vec(s, type, vece, r, r); + break; + default: + g_assert_not_reached(); + } + } + return true; } =20 - static void tcg_out_dupi_vec(TCGContext *s, TCGType type, TCGReg ret, tcg_target_long arg) { @@ -918,16 +947,16 @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType t= ype, } else if (have_avx2) { tcg_out_vex_modrm_pool(s, OPC_VPBROADCASTQ + vex_l, ret); } else { - tcg_out_vex_modrm_pool(s, OPC_MOVDDUP, ret); + tcg_out_vex_modrm_pool(s, OPC_VBROADCASTSD, ret); } new_pool_label(s, arg, R_386_PC32, s->code_ptr - 4, -4); - } else if (have_avx2) { - tcg_out_vex_modrm_pool(s, OPC_VPBROADCASTD + vex_l, ret); - new_pool_label(s, arg, R_386_32, s->code_ptr - 4, 0); } else { - tcg_out_vex_modrm_pool(s, OPC_MOVD_VyEy, ret); + if (have_avx2) { + tcg_out_vex_modrm_pool(s, OPC_VBROADCASTSD + vex_l, ret); + } else { + tcg_out_vex_modrm_pool(s, OPC_VBROADCASTSS, ret); + } new_pool_label(s, arg, R_386_32, s->code_ptr - 4, 0); - tcg_out_dup_vec(s, type, MO_32, ret, ret); } } =20 --=20 2.17.1 From nobody Sat May 4 13:31:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1556950122; cv=none; d=zoho.com; s=zohoarc; b=ELNaYzi7ugyKLovt4I2Ovf6qNlJq7xEoFHjP0B3mNvmJg/v1FbkYE0ad7ZD4NYtZmj3cpiJX7RmHKmoNbK62hrqCbSL4PerBIBsdJKK2TwRQSHrHhSmH7DP6lvWKdeN3pErCN1/0I/IakHuPTilaU2Kt3Cabtb9ZFfbUcKU8vBE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1556950122; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=6HfRdIIOg5JaMDEH2+axpi9/LlfDFn1av6lWaEWwguc=; b=k55JgWu+25qgjWcuxGIfsWxp23fm1cTiwZfPOvZxh8djIQQHM5SRMdtGTIX7dZCWp08rRi/CLwKd4yuOU2E2mKIpZSuD984VLiV7c9Sphge0X26p/XThrpf+pTdRVAYfhp54dQ1Q/aHSW4t7U86cJsfHo/MwNMuQtUAEeJOn5EU= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1556950122651964.3756620746549; Fri, 3 May 2019 23:08:42 -0700 (PDT) Received: from localhost ([127.0.0.1]:51812 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hMnqg-0002rL-FM for importer@patchew.org; Sat, 04 May 2019 02:08:38 -0400 Received: from eggs.gnu.org ([209.51.188.92]:41820) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hMnbs-0007nO-DJ for qemu-devel@nongnu.org; Sat, 04 May 2019 01:53:21 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hMnbr-0004JF-Ef for qemu-devel@nongnu.org; Sat, 04 May 2019 01:53:20 -0400 Received: from mail-pg1-x542.google.com ([2607:f8b0:4864:20::542]:41226) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hMnbr-0004IS-8d for qemu-devel@nongnu.org; Sat, 04 May 2019 01:53:19 -0400 Received: by mail-pg1-x542.google.com with SMTP id z3so59981pgp.8 for ; Fri, 03 May 2019 22:53:19 -0700 (PDT) Received: from localhost.localdomain (97-113-189-189.tukw.qwest.net. [97.113.189.189]) by smtp.gmail.com with ESMTPSA id 15sm6680423pfo.117.2019.05.03.22.53.16 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 03 May 2019 22:53:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=6HfRdIIOg5JaMDEH2+axpi9/LlfDFn1av6lWaEWwguc=; b=NZHOFS8XL83XUlNnyhAf37j8XiHQd7sgTb3xADe6zItsKBtF2ijJa9Sa3xbLGL1Pfb 8+XyWzY3w92wKhrxZWVnYITglNfmtfl7wkYKwOMNcSKWqMGLdeYcZg+eWmUuvj1ryvQN d5hYDuOx/2J4iJRszl2+RxJqDpaYO2VMSYjNBA03+VytkMbz5p4rOQJK4Gl6UaBy+r3Q 7OlNyuRwUq6ZPusklelcyuAh+51i0f6qQelodzYHAknLcbrWlkDnFYbu/NZwTLLu4zeK T46uttT1/kH7DsI3hV6r7ACV5gokjnFuwBuXjgs39L0HEE78vqquEoo1GFhl+0FzNtZb hZGg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=6HfRdIIOg5JaMDEH2+axpi9/LlfDFn1av6lWaEWwguc=; b=j1oCBbAmkOuxSPYaFVtWDTwbnt/cOAG6v4yhDaqyWxU8QvZLans8j2YPfyIwBIMeal UX2Q3L5tUE59Km9BYYF78FuYzgy9ZOVgnYWr2B2juAKc02PwzV5HsnEx3mZsddcNpfiD MENnApqt0eU/43aCaS6hXuye7FJW43kXXOxS6FBtkZszuyIWLYfSBtOLYmjZOCyM47XY Z/XBd5WddgGeL96Dfjc3PmcEZcJ1sBZIPl+IuiKQK+g5s+QFYelVeKd2mEix/Xi9M0FQ sYrPGceJas1rteDeLrE/QWVD/cnxNNE66kL9wKhHC/UTXszjzIvLccjtgVr5/UiL4OSl osgA== X-Gm-Message-State: APjAAAVIPgDJhNF1V/D0D8w9/Jm+vSjLIlMMdH8Sk5UWCT5gFCDhvS/2 +/OmSqOmmq5okrEuccV8drHjjOK6l8o= X-Google-Smtp-Source: APXvYqyr3Yx91bgd6467tRxh/+/6vSrvJtlT/XhbkQD+OAHB9K1zYxqhdjVvmebc2PV9Xe492rKfRQ== X-Received: by 2002:a63:4ce:: with SMTP id 197mr16170912pge.309.1556949197939; Fri, 03 May 2019 22:53:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 3 May 2019 22:52:42 -0700 Message-Id: <20190504055300.18426-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190504055300.18426-1-richard.henderson@linaro.org> References: <20190504055300.18426-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::542 Subject: [Qemu-devel] [PATCH v3 13/31] tcg/aarch64: Implement tcg_out_dupm_vec X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.inc.c | 36 ++++++++++++++++++++++++++++++++++-- 1 file changed, 34 insertions(+), 2 deletions(-) diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c index 4a3cfa778a..e8cf4e4044 100644 --- a/tcg/aarch64/tcg-target.inc.c +++ b/tcg/aarch64/tcg-target.inc.c @@ -381,6 +381,9 @@ typedef enum { I3207_BLR =3D 0xd63f0000, I3207_RET =3D 0xd65f0000, =20 + /* AdvSIMD load/store single structure. */ + I3303_LD1R =3D 0x0d40c000, + /* Load literal for loading the address at pc-relative offset */ I3305_LDR =3D 0x58000000, I3305_LDR_v64 =3D 0x5c000000, @@ -566,7 +569,14 @@ static inline uint32_t tcg_in32(TCGContext *s) #define tcg_out_insn(S, FMT, OP, ...) \ glue(tcg_out_insn_,FMT)(S, glue(glue(glue(I,FMT),_),OP), ## __VA_ARGS_= _) =20 -static void tcg_out_insn_3305(TCGContext *s, AArch64Insn insn, int imm19, = TCGReg rt) +static void tcg_out_insn_3303(TCGContext *s, AArch64Insn insn, bool q, + TCGReg rt, TCGReg rn, unsigned size) +{ + tcg_out32(s, insn | (rt & 0x1f) | (rn << 5) | (size << 10) | (q << 30)= ); +} + +static void tcg_out_insn_3305(TCGContext *s, AArch64Insn insn, + int imm19, TCGReg rt) { tcg_out32(s, insn | (imm19 & 0x7ffff) << 5 | rt); } @@ -825,7 +835,29 @@ static bool tcg_out_dup_vec(TCGContext *s, TCGType typ= e, unsigned vece, static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, TCGReg r, TCGReg base, intptr_t offset) { - return false; + if (offset !=3D 0) { + AArch64Insn add_insn =3D I3401_ADDI; + TCGReg temp =3D TCG_REG_TMP; + + if (offset < 0) { + add_insn =3D I3401_SUBI; + offset =3D -offset; + } + if (offset <=3D 0xfff) { + tcg_out_insn_3401(s, add_insn, 1, temp, base, offset); + } else if (offset <=3D 0xffffff) { + tcg_out_insn_3401(s, add_insn, 1, temp, base, offset & 0xfff00= 0); + if (offset & 0xfff) { + tcg_out_insn_3401(s, add_insn, 1, temp, base, offset & 0xf= ff); + } + } else { + tcg_out_movi(s, TCG_TYPE_PTR, temp, offset); + tcg_out_insn(s, 3502, ADD, 1, temp, temp, base); + } + base =3D temp; + } + tcg_out_insn(s, 3303, LD1R, type =3D=3D TCG_TYPE_V128, r, base, vece); + return true; } =20 static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd, --=20 2.17.1 From nobody Sat May 4 13:31:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1556949507; cv=none; d=zoho.com; s=zohoarc; b=HDqB5jzTcgYK5ij1cMxKdGOF/Nio3i6m8VsI79mFb/k24NM2cBueL3aHCbIZ0GUnybat37yfAKAyjG4aDFAwhx9/ox9yUujHrWgevcrknjTRTTjGSWf0rMrhkBbI8TY6VfzXG91Nboma3PhWzBYgfGqn0PToSL7/cxRz4g1WPXM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1556949507; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; 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[97.113.189.189]) by smtp.gmail.com with ESMTPSA id 15sm6680423pfo.117.2019.05.03.22.53.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 03 May 2019 22:53:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=iouNpek1sIbhwxlou+KBXfVhlak4Z8ReZcZPt+6ibqU=; b=FPEk4/84IQVPCqtjmvcJ9RkEa7VQOP6w42UmidMfL82CXidGe0C1W1HZJ1uWrt3Of2 rSTxud8O89uqDVOUQsUU5YBUw13L28r5MnDNkKswP1K3y7Qy7wL4nXi54EuyuNcR6Tc9 rzmdchd2ZiNpj+I9ks+6oO3ISV2ttxoBVLienOggSHMLeUo/YAHkioirzlkDPFfzKm2i oyPDNnMdHrUpSwnQvD7U93lbgSFAxPLvATCoBG5Rmixpa2ctC/pNR3oBlLt4GO7iDbO7 7WU5q8RvXXh5LtxOcUNkuz89Z1mRkE5ptAPYcOMvrytu69vvjo3MUJrJXFKJG4792K5T j3iQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=iouNpek1sIbhwxlou+KBXfVhlak4Z8ReZcZPt+6ibqU=; b=DEcyj+/QLDDXPPkb1SlacEZYZXXrpHkG0jDBMCQ8478Db7C7Uur443Qilk/gQZOPtm BA18hbY8RJb4vu5XGGRDK51xbjxHQfRiJ065hFIsGCtXa+DvCf4FZTtzc8qerVZqsFoS cCMCNwZQsdsv4KYPgtBsnkdy9EEPen6FbaZIuAbonbLEHxpXqzn+8PqAXO7A7TMaVXAc vLup8xjbyvutus+nSNWIKqaXN8GgicA+b3Zelbd5vMGFJqFH89AYbg8SdmpDX79gjI/b PLoQVa+TidDecirBEyczB5icvglKv5Je1DqQtfed6pak19+9pRfUYk+qku3ZQfVO4Gkw UTMA== X-Gm-Message-State: APjAAAXtffP6+py+ZZlYgbVSz5UBmYdbLgWTFPFgpj+UcUJYhDJKeXf5 E78/fxFR4CS09aulk2Gg/jVTB+pNA6s= X-Google-Smtp-Source: APXvYqxrAIYHTR8bLc6aWxOFsGFPJD2ecJ8IYdx3jKmsUM5ETdRmUS44A6D6RuVCupH1EVtlPj9tOQ== X-Received: by 2002:a63:d343:: with SMTP id u3mr16266311pgi.285.1556949199160; Fri, 03 May 2019 22:53:19 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 3 May 2019 22:52:43 -0700 Message-Id: <20190504055300.18426-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190504055300.18426-1-richard.henderson@linaro.org> References: <20190504055300.18426-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::544 Subject: [Qemu-devel] [PATCH v3 14/31] tcg: Add INDEX_op_dupm_vec X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Allow the backend to expand dup from memory directly, instead of forcing the value into a temp first. This is especially important if integer/vector register moves do not exist. Note that officially tcg_out_dupm_vec is allowed to fail. If it did, we could fix this up relatively easily: VECE =3D=3D 32/64: Load the value into a vector register, then dup. Both of these must work. VECE =3D=3D 8/16: If the value happens to be at an offset such that an aligned load would place the desired value in the least significant end of the register, go ahead and load w/garbage in high bits. Load the value w/INDEX_op_ld{8,16}_i32. Attempt a move directly to vector reg, which may fail. Store the value into the backing store for OTS. Load the value into the vector reg w/TCG_TYPE_I32, which must work. Duplicate from the vector reg into itself, which must work. All of which is well and good, except that all supported hosts can support dupm for all vece, so all of the failure paths would be dead code and untestable. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- tcg/tcg-op.h | 1 + tcg/tcg-opc.h | 1 + tcg/aarch64/tcg-target.inc.c | 4 ++ tcg/i386/tcg-target.inc.c | 4 ++ tcg/tcg-op-gvec.c | 89 +++++++++++++++++++----------------- tcg/tcg-op-vec.c | 11 +++++ tcg/tcg.c | 1 + 7 files changed, 70 insertions(+), 41 deletions(-) diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h index 1f1824c30a..9fff9864f6 100644 --- a/tcg/tcg-op.h +++ b/tcg/tcg-op.h @@ -954,6 +954,7 @@ void tcg_gen_atomic_umax_fetch_i64(TCGv_i64, TCGv, TCGv= _i64, TCGArg, TCGMemOp); void tcg_gen_mov_vec(TCGv_vec, TCGv_vec); void tcg_gen_dup_i32_vec(unsigned vece, TCGv_vec, TCGv_i32); void tcg_gen_dup_i64_vec(unsigned vece, TCGv_vec, TCGv_i64); +void tcg_gen_dup_mem_vec(unsigned vece, TCGv_vec, TCGv_ptr, tcg_target_lon= g); void tcg_gen_dup8i_vec(TCGv_vec, uint32_t); void tcg_gen_dup16i_vec(TCGv_vec, uint32_t); void tcg_gen_dup32i_vec(TCGv_vec, uint32_t); diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h index 1bad6e4208..4bf71f261f 100644 --- a/tcg/tcg-opc.h +++ b/tcg/tcg-opc.h @@ -219,6 +219,7 @@ DEF(dup2_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_REG_BI= TS =3D=3D 32)) =20 DEF(ld_vec, 1, 1, 1, IMPLVEC) DEF(st_vec, 0, 2, 1, IMPLVEC) +DEF(dupm_vec, 1, 1, 1, IMPLVEC) =20 DEF(add_vec, 1, 2, 0, IMPLVEC) DEF(sub_vec, 1, 2, 0, IMPLVEC) diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c index e8cf4e4044..15ab35adf7 100644 --- a/tcg/aarch64/tcg-target.inc.c +++ b/tcg/aarch64/tcg-target.inc.c @@ -2190,6 +2190,9 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode o= pc, case INDEX_op_st_vec: tcg_out_st(s, type, a0, a1, a2); break; + case INDEX_op_dupm_vec: + tcg_out_dupm_vec(s, type, vece, a0, a1, a2); + break; case INDEX_op_add_vec: tcg_out_insn(s, 3616, ADD, is_q, vece, a0, a1, a2); break; @@ -2522,6 +2525,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) return &w_w; case INDEX_op_ld_vec: case INDEX_op_st_vec: + case INDEX_op_dupm_vec: return &w_r; case INDEX_op_dup_vec: return &w_wr; diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index f4bd00e24f..5b33bbd99b 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -2829,6 +2829,9 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode o= pc, case INDEX_op_st_vec: tcg_out_st(s, type, a0, a1, a2); break; + case INDEX_op_dupm_vec: + tcg_out_dupm_vec(s, type, vece, a0, a1, a2); + break; =20 case INDEX_op_x86_shufps_vec: insn =3D OPC_SHUFPS; @@ -3115,6 +3118,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) =20 case INDEX_op_ld_vec: case INDEX_op_st_vec: + case INDEX_op_dupm_vec: return &x_r; =20 case INDEX_op_add_vec: diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c index 3fcb2352d9..35ebc5a201 100644 --- a/tcg/tcg-op-gvec.c +++ b/tcg/tcg-op-gvec.c @@ -395,6 +395,41 @@ static TCGType choose_vector_type(const TCGOpcode *lis= t, unsigned vece, return 0; } =20 +static void do_dup_store(TCGType type, uint32_t dofs, uint32_t oprsz, + uint32_t maxsz, TCGv_vec t_vec) +{ + uint32_t i =3D 0; + + switch (type) { + case TCG_TYPE_V256: + /* + * Recall that ARM SVE allows vector sizes that are not a + * power of 2, but always a multiple of 16. The intent is + * that e.g. size =3D=3D 80 would be expanded with 2x32 + 1x16. + */ + for (; i + 32 <=3D oprsz; i +=3D 32) { + tcg_gen_stl_vec(t_vec, cpu_env, dofs + i, TCG_TYPE_V256); + } + /* fallthru */ + case TCG_TYPE_V128: + for (; i + 16 <=3D oprsz; i +=3D 16) { + tcg_gen_stl_vec(t_vec, cpu_env, dofs + i, TCG_TYPE_V128); + } + break; + case TCG_TYPE_V64: + for (; i < oprsz; i +=3D 8) { + tcg_gen_stl_vec(t_vec, cpu_env, dofs + i, TCG_TYPE_V64); + } + break; + default: + g_assert_not_reached(); + } + + if (oprsz < maxsz) { + expand_clr(dofs + oprsz, maxsz - oprsz); + } +} + /* Set OPRSZ bytes at DOFS to replications of IN_32, IN_64 or IN_C. * Only one of IN_32 or IN_64 may be set; * IN_C is used if IN_32 and IN_64 are unset. @@ -434,49 +469,11 @@ static void do_dup(unsigned vece, uint32_t dofs, uint= 32_t oprsz, } else if (in_64) { tcg_gen_dup_i64_vec(vece, t_vec, in_64); } else { - switch (vece) { - case MO_8: - tcg_gen_dup8i_vec(t_vec, in_c); - break; - case MO_16: - tcg_gen_dup16i_vec(t_vec, in_c); - break; - case MO_32: - tcg_gen_dup32i_vec(t_vec, in_c); - break; - default: - tcg_gen_dup64i_vec(t_vec, in_c); - break; - } + tcg_gen_dupi_vec(vece, t_vec, in_c); } - - i =3D 0; - switch (type) { - case TCG_TYPE_V256: - /* Recall that ARM SVE allows vector sizes that are not a - * power of 2, but always a multiple of 16. The intent is - * that e.g. size =3D=3D 80 would be expanded with 2x32 + 1x16. - */ - for (; i + 32 <=3D oprsz; i +=3D 32) { - tcg_gen_stl_vec(t_vec, cpu_env, dofs + i, TCG_TYPE_V256); - } - /* fallthru */ - case TCG_TYPE_V128: - for (; i + 16 <=3D oprsz; i +=3D 16) { - tcg_gen_stl_vec(t_vec, cpu_env, dofs + i, TCG_TYPE_V128); - } - break; - case TCG_TYPE_V64: - for (; i < oprsz; i +=3D 8) { - tcg_gen_stl_vec(t_vec, cpu_env, dofs + i, TCG_TYPE_V64); - } - break; - default: - g_assert_not_reached(); - } - + do_dup_store(type, dofs, oprsz, maxsz, t_vec); tcg_temp_free_vec(t_vec); - goto done; + return; } =20 /* Otherwise, inline with an integer type, unless "large". */ @@ -1449,6 +1446,16 @@ void tcg_gen_gvec_dup_i64(unsigned vece, uint32_t do= fs, uint32_t oprsz, void tcg_gen_gvec_dup_mem(unsigned vece, uint32_t dofs, uint32_t aofs, uint32_t oprsz, uint32_t maxsz) { + if (vece <=3D MO_64) { + TCGType type =3D choose_vector_type(0, vece, oprsz, 0); + if (type !=3D 0) { + TCGv_vec t_vec =3D tcg_temp_new_vec(type); + tcg_gen_dup_mem_vec(vece, t_vec, cpu_env, aofs); + do_dup_store(type, dofs, oprsz, maxsz, t_vec); + tcg_temp_free_vec(t_vec); + return; + } + } if (vece <=3D MO_32) { TCGv_i32 in =3D tcg_temp_new_i32(); switch (vece) { diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c index 914fe42b1e..213d2e22aa 100644 --- a/tcg/tcg-op-vec.c +++ b/tcg/tcg-op-vec.c @@ -278,6 +278,17 @@ void tcg_gen_dup_i32_vec(unsigned vece, TCGv_vec r, TC= Gv_i32 a) vec_gen_2(INDEX_op_dup_vec, type, vece, ri, ai); } =20 +void tcg_gen_dup_mem_vec(unsigned vece, TCGv_vec r, TCGv_ptr b, + tcg_target_long ofs) +{ + TCGArg ri =3D tcgv_vec_arg(r); + TCGArg bi =3D tcgv_ptr_arg(b); + TCGTemp *rt =3D arg_temp(ri); + TCGType type =3D rt->base_type; + + vec_gen_3(INDEX_op_dupm_vec, type, vece, ri, bi, ofs); +} + static void vec_gen_ldst(TCGOpcode opc, TCGv_vec r, TCGv_ptr b, TCGArg o) { TCGArg ri =3D tcgv_vec_arg(r); diff --git a/tcg/tcg.c b/tcg/tcg.c index b9945794c4..3b80feb344 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1600,6 +1600,7 @@ bool tcg_op_supported(TCGOpcode op) case INDEX_op_mov_vec: case INDEX_op_dup_vec: case INDEX_op_dupi_vec: + case INDEX_op_dupm_vec: case INDEX_op_ld_vec: case INDEX_op_st_vec: case INDEX_op_add_vec: --=20 2.17.1 From nobody Sat May 4 13:31:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1556949693; cv=none; d=zoho.com; s=zohoarc; b=bWMor9ESHwfV/6KYKocC8736Rg34dfgiN0rfDzYQgs2UOaM3WEeuXE1edYBM8cqivkRgvEtwEytGP7oCVkW3f2O1q78QuRv04rNbRP0wE2PX1T96Q81H45+d5C0MkRXq5iSRe0+SxbL9eEet7Ub2uEzkX0EtuV7R5f62qtn0G7w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1556949693; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=a9OtYY/L3tjcYNcnftsoHy1MvDzVKoGmvUT84hy5Bno=; b=V13zumdx5lNsdCFS3wB8/S6bvxHXbRPEkjoiWjfLMIr9wKeJvK9m0bE1wwFgG0tNe161E8QYE4R8fbPOgPqKmbX0VAvl9KOJP4nI/nThb6nsBNASMGW10mvYbGqaPwC8T3aqE0Q8w1OMjj5HAswyZAr405RQLOP1VAleaz6I8wM= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1556949693114947.3427007037641; Fri, 3 May 2019 23:01:33 -0700 (PDT) Received: from localhost ([127.0.0.1]:51720 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hMnjl-0005aQ-UI for importer@patchew.org; Sat, 04 May 2019 02:01:29 -0400 Received: from eggs.gnu.org ([209.51.188.92]:41879) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hMnbw-0007sR-6f for qemu-devel@nongnu.org; Sat, 04 May 2019 01:53:26 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hMnbu-0004Kf-19 for qemu-devel@nongnu.org; Sat, 04 May 2019 01:53:24 -0400 Received: from mail-pl1-x644.google.com ([2607:f8b0:4864:20::644]:40426) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hMnbt-0004KQ-PH for qemu-devel@nongnu.org; Sat, 04 May 2019 01:53:21 -0400 Received: by mail-pl1-x644.google.com with SMTP id b3so3722595plr.7 for ; Fri, 03 May 2019 22:53:21 -0700 (PDT) Received: from localhost.localdomain (97-113-189-189.tukw.qwest.net. [97.113.189.189]) by smtp.gmail.com with ESMTPSA id 15sm6680423pfo.117.2019.05.03.22.53.19 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 03 May 2019 22:53:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=a9OtYY/L3tjcYNcnftsoHy1MvDzVKoGmvUT84hy5Bno=; b=WvwqxxSjapvqE3pY7wV0QetbnPoS8VkJaBRw4I6yVnQGuYuML31Woc5PjJdz1bGPks JxVb3M8nAqk+VhWyw4u0g6SSXlXnwX2W5K+r0oKyyORi57laehPH+I+6RDz1rLx2tk9u I5MZ3qdq6HiYkbEFJcsSrkFGlcyzLpU38nHqG2AKbIMD+SUJTE4UscCmpsbl00FJpyVS RALXT/5j1hs8LOJyjcl1L5H/NMsfuM2irfD1mFcraNIuRU55psm/DRner+Jd9djnFYyG jMfePzsXOmqY2mUosycI1UIY1RvtE+C/XUKJYKg9gSkJCena4fUpWJzKT8ZSQQ7pqLS1 Zjgw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=a9OtYY/L3tjcYNcnftsoHy1MvDzVKoGmvUT84hy5Bno=; b=k7LX3UT1m5775AaBY9WOELeVpl9XK77Rp5vzFFicKwm5zj22lS5j7ECk7nwHWsQCuu edJOY7J2FSU+3LbMpa+Xzq0Qh9jELyUFhgQ2xfTyfzO8jfJwlIE3tOaDxdHo0mwXlG7O ud7Cb8HqOg140wcO9fSN2fQqrkv1wXKHGQr076A5TjQ0H6qdkLtP84yhh4nRD41DnIhK zeS9wl1azhVy3hyrXCu4bCb3s7QKEADl8IgJrJyXnnyI71+WiIgetEzas8dyDS1mk606 Iyk7XOlN2XSA9gb9u5s2rIEHKo/yHgngG2Qx7yg9FBH4rJ9TnhmQiYoC9UDKihoSuece Cn9w== X-Gm-Message-State: APjAAAXDwLUYI0rf84yp1gokd9It8BrTg5OunLHu3BNbkv6MHcJZJw5o cj3THmb49x3Kmnqs69+mbfv57k0WBRY= X-Google-Smtp-Source: APXvYqwm26niIb+qtWCZEuqoL38PlsqqE1mriNSJCrEUd/hmu/q2d1UuW10Mzr2JaUCYmhObWvbt+Q== X-Received: by 2002:a17:902:12f:: with SMTP id 44mr16312122plb.193.1556949200495; Fri, 03 May 2019 22:53:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 3 May 2019 22:52:44 -0700 Message-Id: <20190504055300.18426-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190504055300.18426-1-richard.henderson@linaro.org> References: <20190504055300.18426-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::644 Subject: [Qemu-devel] [PATCH v3 15/31] tcg: Add gvec expanders for variable shift X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) The gvec expanders perform a modulo on the shift count. If the target requires alternate behaviour, then it cannot use the generic gvec expanders anyway, and will have to have its own custom code. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- accel/tcg/tcg-runtime.h | 15 +++ tcg/tcg-op-gvec.h | 11 ++ tcg/tcg-op.h | 4 + accel/tcg/tcg-runtime-gvec.c | 144 ++++++++++++++++++++++++++ tcg/tcg-op-gvec.c | 195 +++++++++++++++++++++++++++++++++++ tcg/tcg-op-vec.c | 15 +++ 6 files changed, 384 insertions(+) diff --git a/accel/tcg/tcg-runtime.h b/accel/tcg/tcg-runtime.h index dfe325625c..ed3ce5fd91 100644 --- a/accel/tcg/tcg-runtime.h +++ b/accel/tcg/tcg-runtime.h @@ -254,6 +254,21 @@ DEF_HELPER_FLAGS_3(gvec_sar16i, TCG_CALL_NO_RWG, void,= ptr, ptr, i32) DEF_HELPER_FLAGS_3(gvec_sar32i, TCG_CALL_NO_RWG, void, ptr, ptr, i32) DEF_HELPER_FLAGS_3(gvec_sar64i, TCG_CALL_NO_RWG, void, ptr, ptr, i32) =20 +DEF_HELPER_FLAGS_4(gvec_shl8v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_shl16v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_shl32v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_shl64v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(gvec_shr8v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_shr16v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_shr32v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_shr64v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(gvec_sar8v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_sar16v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_sar32v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_sar64v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + DEF_HELPER_FLAGS_4(gvec_eq8, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_eq16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_eq32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) diff --git a/tcg/tcg-op-gvec.h b/tcg/tcg-op-gvec.h index ac744ff7c9..84a6247b16 100644 --- a/tcg/tcg-op-gvec.h +++ b/tcg/tcg-op-gvec.h @@ -318,6 +318,17 @@ void tcg_gen_gvec_shri(unsigned vece, uint32_t dofs, u= int32_t aofs, void tcg_gen_gvec_sari(unsigned vece, uint32_t dofs, uint32_t aofs, int64_t shift, uint32_t oprsz, uint32_t maxsz); =20 +/* + * Perform vector shift by vector element, modulo the element size. + * E.g. D[i] =3D A[i] << (B[i] % (8 << vece)). + */ +void tcg_gen_gvec_shlv(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_shrv(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_sarv(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz); + void tcg_gen_gvec_cmp(TCGCond cond, unsigned vece, uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t oprsz, uint32_t maxsz); diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h index 9fff9864f6..833c6330b5 100644 --- a/tcg/tcg-op.h +++ b/tcg/tcg-op.h @@ -986,6 +986,10 @@ void tcg_gen_shli_vec(unsigned vece, TCGv_vec r, TCGv_= vec a, int64_t i); void tcg_gen_shri_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i); void tcg_gen_sari_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i); =20 +void tcg_gen_shlv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s); +void tcg_gen_shrv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s); +void tcg_gen_sarv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s); + void tcg_gen_cmp_vec(TCGCond cond, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); =20 diff --git a/accel/tcg/tcg-runtime-gvec.c b/accel/tcg/tcg-runtime-gvec.c index e2c6f24262..2152fb6903 100644 --- a/accel/tcg/tcg-runtime-gvec.c +++ b/accel/tcg/tcg-runtime-gvec.c @@ -725,6 +725,150 @@ void HELPER(gvec_sar64i)(void *d, void *a, uint32_t d= esc) clear_high(d, oprsz, desc); } =20 +void HELPER(gvec_shl8v)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz =3D simd_oprsz(desc); + intptr_t i; + + for (i =3D 0; i < oprsz; i +=3D sizeof(uint8_t)) { + uint8_t sh =3D *(uint8_t *)(b + i) & 7; + *(uint8_t *)(d + i) =3D *(uint8_t *)(a + i) << sh; + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_shl16v)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz =3D simd_oprsz(desc); + intptr_t i; + + for (i =3D 0; i < oprsz; i +=3D sizeof(uint16_t)) { + uint8_t sh =3D *(uint16_t *)(b + i) & 15; + *(uint16_t *)(d + i) =3D *(uint16_t *)(a + i) << sh; + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_shl32v)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz =3D simd_oprsz(desc); + intptr_t i; + + for (i =3D 0; i < oprsz; i +=3D sizeof(uint32_t)) { + uint8_t sh =3D *(uint32_t *)(b + i) & 31; + *(uint32_t *)(d + i) =3D *(uint32_t *)(a + i) << sh; + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_shl64v)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz =3D simd_oprsz(desc); + intptr_t i; + + for (i =3D 0; i < oprsz; i +=3D sizeof(uint64_t)) { + uint8_t sh =3D *(uint64_t *)(b + i) & 63; + *(uint64_t *)(d + i) =3D *(uint64_t *)(a + i) << sh; + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_shr8v)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz =3D simd_oprsz(desc); + intptr_t i; + + for (i =3D 0; i < oprsz; i +=3D sizeof(uint8_t)) { + uint8_t sh =3D *(uint8_t *)(b + i) & 7; + *(uint8_t *)(d + i) =3D *(uint8_t *)(a + i) >> sh; + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_shr16v)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz =3D simd_oprsz(desc); + intptr_t i; + + for (i =3D 0; i < oprsz; i +=3D sizeof(uint16_t)) { + uint8_t sh =3D *(uint16_t *)(b + i) & 15; + *(uint16_t *)(d + i) =3D *(uint16_t *)(a + i) >> sh; + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_shr32v)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz =3D simd_oprsz(desc); + intptr_t i; + + for (i =3D 0; i < oprsz; i +=3D sizeof(uint32_t)) { + uint8_t sh =3D *(uint32_t *)(b + i) & 31; + *(uint32_t *)(d + i) =3D *(uint32_t *)(a + i) >> sh; + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_shr64v)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz =3D simd_oprsz(desc); + intptr_t i; + + for (i =3D 0; i < oprsz; i +=3D sizeof(uint64_t)) { + uint8_t sh =3D *(uint64_t *)(b + i) & 63; + *(uint64_t *)(d + i) =3D *(uint64_t *)(a + i) >> sh; + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_sar8v)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz =3D simd_oprsz(desc); + intptr_t i; + + for (i =3D 0; i < oprsz; i +=3D sizeof(vec8)) { + uint8_t sh =3D *(uint8_t *)(b + i) & 7; + *(int8_t *)(d + i) =3D *(int8_t *)(a + i) >> sh; + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_sar16v)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz =3D simd_oprsz(desc); + intptr_t i; + + for (i =3D 0; i < oprsz; i +=3D sizeof(int16_t)) { + uint8_t sh =3D *(uint16_t *)(b + i) & 15; + *(int16_t *)(d + i) =3D *(int16_t *)(a + i) >> sh; + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_sar32v)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz =3D simd_oprsz(desc); + intptr_t i; + + for (i =3D 0; i < oprsz; i +=3D sizeof(vec32)) { + uint8_t sh =3D *(uint32_t *)(b + i) & 31; + *(int32_t *)(d + i) =3D *(int32_t *)(a + i) >> sh; + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_sar64v)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz =3D simd_oprsz(desc); + intptr_t i; + + for (i =3D 0; i < oprsz; i +=3D sizeof(vec64)) { + uint8_t sh =3D *(uint64_t *)(b + i) & 63; + *(int64_t *)(d + i) =3D *(int64_t *)(a + i) >> sh; + } + clear_high(d, oprsz, desc); +} + /* If vectors are enabled, the compiler fills in -1 for true. Otherwise, we must take care of this by hand. */ #ifdef CONFIG_VECTOR16 diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c index 35ebc5a201..061ef329f1 100644 --- a/tcg/tcg-op-gvec.c +++ b/tcg/tcg-op-gvec.c @@ -2555,6 +2555,201 @@ void tcg_gen_gvec_sari(unsigned vece, uint32_t dofs= , uint32_t aofs, } } =20 +/* + * Expand D =3D A << (B % element bits) + * + * Unlike scalar shifts, where it is easy for the target front end + * to include the modulo as part of the expansion. If the target + * naturally includes the modulo as part of the operation, great! + * If the target has some other behaviour from out-of-range shifts, + * then it could not use this function anyway, and would need to + * do it's own expansion with custom functions. + */ +static void tcg_gen_shlv_mod_vec(unsigned vece, TCGv_vec d, + TCGv_vec a, TCGv_vec b) +{ + TCGv_vec t =3D tcg_temp_new_vec_matching(d); + + tcg_gen_dupi_vec(vece, t, (8 << vece) - 1); + tcg_gen_and_vec(vece, t, t, b); + tcg_gen_shlv_vec(vece, d, a, t); + tcg_temp_free_vec(t); +} + +static void tcg_gen_shl_mod_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) +{ + TCGv_i32 t =3D tcg_temp_new_i32(); + + tcg_gen_andi_i32(t, b, 31); + tcg_gen_shl_i32(d, a, t); + tcg_temp_free_i32(t); +} + +static void tcg_gen_shl_mod_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) +{ + TCGv_i64 t =3D tcg_temp_new_i64(); + + tcg_gen_andi_i64(t, b, 63); + tcg_gen_shl_i64(d, a, t); + tcg_temp_free_i64(t); +} + +void tcg_gen_gvec_shlv(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz) +{ + static const TCGOpcode vecop_list[] =3D { INDEX_op_shlv_vec, 0 }; + static const GVecGen3 g[4] =3D { + { .fniv =3D tcg_gen_shlv_mod_vec, + .fno =3D gen_helper_gvec_shl8v, + .opt_opc =3D vecop_list, + .vece =3D MO_8 }, + { .fniv =3D tcg_gen_shlv_mod_vec, + .fno =3D gen_helper_gvec_shl16v, + .opt_opc =3D vecop_list, + .vece =3D MO_16 }, + { .fni4 =3D tcg_gen_shl_mod_i32, + .fniv =3D tcg_gen_shlv_mod_vec, + .fno =3D gen_helper_gvec_shl32v, + .opt_opc =3D vecop_list, + .vece =3D MO_32 }, + { .fni8 =3D tcg_gen_shl_mod_i64, + .fniv =3D tcg_gen_shlv_mod_vec, + .fno =3D gen_helper_gvec_shl64v, + .opt_opc =3D vecop_list, + .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .vece =3D MO_64 }, + }; + + tcg_debug_assert(vece <=3D MO_64); + tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]); +} + +/* + * Similarly for logical right shifts. + */ + +static void tcg_gen_shrv_mod_vec(unsigned vece, TCGv_vec d, + TCGv_vec a, TCGv_vec b) +{ + TCGv_vec t =3D tcg_temp_new_vec_matching(d); + + tcg_gen_dupi_vec(vece, t, (8 << vece) - 1); + tcg_gen_and_vec(vece, t, t, b); + tcg_gen_shrv_vec(vece, d, a, t); + tcg_temp_free_vec(t); +} + +static void tcg_gen_shr_mod_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) +{ + TCGv_i32 t =3D tcg_temp_new_i32(); + + tcg_gen_andi_i32(t, b, 31); + tcg_gen_shr_i32(d, a, t); + tcg_temp_free_i32(t); +} + +static void tcg_gen_shr_mod_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) +{ + TCGv_i64 t =3D tcg_temp_new_i64(); + + tcg_gen_andi_i64(t, b, 63); + tcg_gen_shr_i64(d, a, t); + tcg_temp_free_i64(t); +} + +void tcg_gen_gvec_shrv(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz) +{ + static const TCGOpcode vecop_list[] =3D { INDEX_op_shrv_vec, 0 }; + static const GVecGen3 g[4] =3D { + { .fniv =3D tcg_gen_shrv_mod_vec, + .fno =3D gen_helper_gvec_shr8v, + .opt_opc =3D vecop_list, + .vece =3D MO_8 }, + { .fniv =3D tcg_gen_shrv_mod_vec, + .fno =3D gen_helper_gvec_shr16v, + .opt_opc =3D vecop_list, + .vece =3D MO_16 }, + { .fni4 =3D tcg_gen_shr_mod_i32, + .fniv =3D tcg_gen_shrv_mod_vec, + .fno =3D gen_helper_gvec_shr32v, + .opt_opc =3D vecop_list, + .vece =3D MO_32 }, + { .fni8 =3D tcg_gen_shr_mod_i64, + .fniv =3D tcg_gen_shrv_mod_vec, + .fno =3D gen_helper_gvec_shr64v, + .opt_opc =3D vecop_list, + .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .vece =3D MO_64 }, + }; + + tcg_debug_assert(vece <=3D MO_64); + tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]); +} + +/* + * Similarly for arithmetic right shifts. + */ + +static void tcg_gen_sarv_mod_vec(unsigned vece, TCGv_vec d, + TCGv_vec a, TCGv_vec b) +{ + TCGv_vec t =3D tcg_temp_new_vec_matching(d); + + tcg_gen_dupi_vec(vece, t, (8 << vece) - 1); + tcg_gen_and_vec(vece, t, t, b); + tcg_gen_sarv_vec(vece, d, a, t); + tcg_temp_free_vec(t); +} + +static void tcg_gen_sar_mod_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) +{ + TCGv_i32 t =3D tcg_temp_new_i32(); + + tcg_gen_andi_i32(t, b, 31); + tcg_gen_sar_i32(d, a, t); + tcg_temp_free_i32(t); +} + +static void tcg_gen_sar_mod_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) +{ + TCGv_i64 t =3D tcg_temp_new_i64(); + + tcg_gen_andi_i64(t, b, 63); + tcg_gen_sar_i64(d, a, t); + tcg_temp_free_i64(t); +} + +void tcg_gen_gvec_sarv(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz) +{ + static const TCGOpcode vecop_list[] =3D { INDEX_op_sarv_vec, 0 }; + static const GVecGen3 g[4] =3D { + { .fniv =3D tcg_gen_sarv_mod_vec, + .fno =3D gen_helper_gvec_sar8v, + .opt_opc =3D vecop_list, + .vece =3D MO_8 }, + { .fniv =3D tcg_gen_sarv_mod_vec, + .fno =3D gen_helper_gvec_sar16v, + .opt_opc =3D vecop_list, + .vece =3D MO_16 }, + { .fni4 =3D tcg_gen_sar_mod_i32, + .fniv =3D tcg_gen_sarv_mod_vec, + .fno =3D gen_helper_gvec_sar32v, + .opt_opc =3D vecop_list, + .vece =3D MO_32 }, + { .fni8 =3D tcg_gen_sar_mod_i64, + .fniv =3D tcg_gen_sarv_mod_vec, + .fno =3D gen_helper_gvec_sar64v, + .opt_opc =3D vecop_list, + .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .vece =3D MO_64 }, + }; + + tcg_debug_assert(vece <=3D MO_64); + tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]); +} + /* Expand OPSZ bytes worth of three-operand operations using i32 elements.= */ static void expand_cmp_i32(uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t oprsz, TCGCond cond) diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c index 213d2e22aa..96317dbd10 100644 --- a/tcg/tcg-op-vec.c +++ b/tcg/tcg-op-vec.c @@ -583,3 +583,18 @@ void tcg_gen_umax_vec(unsigned vece, TCGv_vec r, TCGv_= vec a, TCGv_vec b) { do_op3(vece, r, a, b, INDEX_op_umax_vec); } + +void tcg_gen_shlv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) +{ + do_op3(vece, r, a, b, INDEX_op_shlv_vec); +} + +void tcg_gen_shrv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) +{ + do_op3(vece, r, a, b, INDEX_op_shrv_vec); +} + +void tcg_gen_sarv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) +{ + do_op3(vece, r, a, b, INDEX_op_sarv_vec); +} --=20 2.17.1 From nobody Sat May 4 13:31:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1556950295; cv=none; d=zoho.com; s=zohoarc; b=j34FE4MUjCwhB31lQE1fSM2fV675e+f9TtlHgYMIrM+UVB+VE7QqNZ9TpAkZZqG9I5n/5oYOq3nzZqBzhau0qbdQxyZ+FZjoGCZapXTaS/BMJd6LTnrFd2gbMjTlUR/+/Myxe0VZT+Y9sq+qgjzlrvdaCdBJioEbg6w4BndUWdM= ARC-Message-Signature: i=1; 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[97.113.189.189]) by smtp.gmail.com with ESMTPSA id 15sm6680423pfo.117.2019.05.03.22.53.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 03 May 2019 22:53:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=+vy3D5n9NVcZ5Oj9MBgVyI+mUUxTaLSYcOmzMokmrqg=; b=XV1nax+FMF84Szf8k89MeWYtZmaWr9uyOFZZ9IuYA1+nkqwnpUFkELNoXVbj2kduCt qmppro2+SFBMwaoFbyrUKZOmR7gRmVxfhYEcb3y4p1y2FRUnVffgXct0X90ljFi8BtVw SNBpCp0bzft70F70CCRZfLvKLIstPrS2IU0F1bje8CYkuoHl/m5GzVMhDq63Y+JZm22o RBBuHVrueq8e+CM1tNSmlvBrw+nJXs7ygvY1Sy+phTCceINesoZpNckTrEZiZ0OwVHrA MRyPiJXe2CBOqydbceXWrymy0gYk+DIodFtjLrJtZIzK/w13q9ihpmBdWGmSdc/4C+qM E1ig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=+vy3D5n9NVcZ5Oj9MBgVyI+mUUxTaLSYcOmzMokmrqg=; b=WRme8G9oG3mZge4DJv+7ShPzaRsBjv+5Wes46NDZpRd5EoBMHJJ/O1HNSg7VEyBjRB DE+V6nf9EGSAdu46ZZCK8/i0IeSTGJhAgLo6ZjiI18n75XzpR15ccqAUoqYl8IcRxUmW en4nd6Pu1m3LBFbVqXfatSlCgOVhwfPSyOKVqjUCCasjuVpcbGaCkR+4jWnb1gl0fI+J cbn2JpLTzAF9d207ST5JYPOO99tHl89qTIvZ+4rMwaWDnuVeujfSOqRTpcmcBiahqP+u aPhyVhzqzm5NqE1VOb6qxXO2q9rvErZDqNHvLpJUJH5iu0A81CJ4L5HF1LfnLIvFxHSo Kn1g== X-Gm-Message-State: APjAAAU7+qajZ7KFkasrMXtqQ3F7jWkNye8RI1XCcXtjygFvdi6bROua 0GYxxVn10nPd/mCbdJwU/9I8+lsYhcs= X-Google-Smtp-Source: APXvYqzHMF+nUyH8tG47XgiXyws7E4YWMzyDwuPvksVQp6+9X1iR6+37fOPkDHoW1bKPaUWgCH2PqQ== X-Received: by 2002:a17:902:2702:: with SMTP id c2mr15980098plb.277.1556949201625; Fri, 03 May 2019 22:53:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 3 May 2019 22:52:45 -0700 Message-Id: <20190504055300.18426-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190504055300.18426-1-richard.henderson@linaro.org> References: <20190504055300.18426-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::62d Subject: [Qemu-devel] [PATCH v3 16/31] tcg/i386: Support vector variable shift opcodes X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.h | 2 +- tcg/i386/tcg-target.inc.c | 35 +++++++++++++++++++++++++++++++++++ 2 files changed, 36 insertions(+), 1 deletion(-) diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 241bf19413..b240633455 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -184,7 +184,7 @@ extern bool have_avx2; #define TCG_TARGET_HAS_neg_vec 0 #define TCG_TARGET_HAS_shi_vec 1 #define TCG_TARGET_HAS_shs_vec 0 -#define TCG_TARGET_HAS_shv_vec 0 +#define TCG_TARGET_HAS_shv_vec have_avx2 #define TCG_TARGET_HAS_cmp_vec 1 #define TCG_TARGET_HAS_mul_vec 1 #define TCG_TARGET_HAS_sat_vec 1 diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index 5b33bbd99b..c9448b6d84 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -467,6 +467,11 @@ static inline int tcg_target_const_match(tcg_target_lo= ng val, TCGType type, #define OPC_VPBROADCASTQ (0x59 | P_EXT38 | P_DATA16) #define OPC_VPERMQ (0x00 | P_EXT3A | P_DATA16 | P_REXW) #define OPC_VPERM2I128 (0x46 | P_EXT3A | P_DATA16 | P_VEXL) +#define OPC_VPSLLVD (0x47 | P_EXT38 | P_DATA16) +#define OPC_VPSLLVQ (0x47 | P_EXT38 | P_DATA16 | P_REXW) +#define OPC_VPSRAVD (0x46 | P_EXT38 | P_DATA16) +#define OPC_VPSRLVD (0x45 | P_EXT38 | P_DATA16) +#define OPC_VPSRLVQ (0x45 | P_EXT38 | P_DATA16 | P_REXW) #define OPC_VZEROUPPER (0x77 | P_EXT) #define OPC_XCHG_ax_r32 (0x90) =20 @@ -2707,6 +2712,18 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, static int const umax_insn[4] =3D { OPC_PMAXUB, OPC_PMAXUW, OPC_PMAXUD, OPC_UD2 }; + static int const shlv_insn[4] =3D { + /* TODO: AVX512 adds support for MO_16. */ + OPC_UD2, OPC_UD2, OPC_VPSLLVD, OPC_VPSLLVQ + }; + static int const shrv_insn[4] =3D { + /* TODO: AVX512 adds support for MO_16. */ + OPC_UD2, OPC_UD2, OPC_VPSRLVD, OPC_VPSRLVQ + }; + static int const sarv_insn[4] =3D { + /* TODO: AVX512 adds support for MO_16, MO_64. */ + OPC_UD2, OPC_UD2, OPC_VPSRAVD, OPC_UD2 + }; =20 TCGType type =3D vecl + TCG_TYPE_V64; int insn, sub; @@ -2759,6 +2776,15 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, case INDEX_op_umax_vec: insn =3D umax_insn[vece]; goto gen_simd; + case INDEX_op_shlv_vec: + insn =3D shlv_insn[vece]; + goto gen_simd; + case INDEX_op_shrv_vec: + insn =3D shrv_insn[vece]; + goto gen_simd; + case INDEX_op_sarv_vec: + insn =3D sarv_insn[vece]; + goto gen_simd; case INDEX_op_x86_punpckl_vec: insn =3D punpckl_insn[vece]; goto gen_simd; @@ -3136,6 +3162,9 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) case INDEX_op_umin_vec: case INDEX_op_smax_vec: case INDEX_op_umax_vec: + case INDEX_op_shlv_vec: + case INDEX_op_shrv_vec: + case INDEX_op_sarv_vec: case INDEX_op_cmp_vec: case INDEX_op_x86_shufps_vec: case INDEX_op_x86_blend_vec: @@ -3193,6 +3222,12 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type,= unsigned vece) } return 1; =20 + case INDEX_op_shlv_vec: + case INDEX_op_shrv_vec: + return have_avx2 && vece >=3D MO_32; + case INDEX_op_sarv_vec: + return have_avx2 && vece =3D=3D MO_32; + case INDEX_op_mul_vec: if (vece =3D=3D MO_8) { /* We can expand the operation for MO_8. */ --=20 2.17.1 From nobody Sat May 4 13:31:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1556950439; cv=none; d=zoho.com; s=zohoarc; b=BBoYwvHVu66Nl4HYL3vrKF+ROLkJ1DlEwLUpdcle0yuLU8an3pJ9I4mpkdlq7pt1twMPee/RXDUIWUZN25j9bqY06Yhwi4HIx2MPHQS647dudb97G0aOio+SV4M1SsRX808ABWFqnEw8P+PIYm+Q2Q856B24W616C22mjnGvnP0= ARC-Message-Signature: i=1; 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X-Received-From: 2607:f8b0:4864:20::642 Subject: [Qemu-devel] [PATCH v3 17/31] tcg/aarch64: Support vector variable shift opcodes X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.h | 2 +- tcg/aarch64/tcg-target.opc.h | 2 ++ tcg/aarch64/tcg-target.inc.c | 42 ++++++++++++++++++++++++++++++++++++ 3 files changed, 45 insertions(+), 1 deletion(-) diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index ce2bb1f90b..f5640a229b 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -134,7 +134,7 @@ typedef enum { #define TCG_TARGET_HAS_neg_vec 1 #define TCG_TARGET_HAS_shi_vec 1 #define TCG_TARGET_HAS_shs_vec 0 -#define TCG_TARGET_HAS_shv_vec 0 +#define TCG_TARGET_HAS_shv_vec 1 #define TCG_TARGET_HAS_cmp_vec 1 #define TCG_TARGET_HAS_mul_vec 1 #define TCG_TARGET_HAS_sat_vec 1 diff --git a/tcg/aarch64/tcg-target.opc.h b/tcg/aarch64/tcg-target.opc.h index 4816a6c3d4..59e1d3f7f7 100644 --- a/tcg/aarch64/tcg-target.opc.h +++ b/tcg/aarch64/tcg-target.opc.h @@ -1,3 +1,5 @@ /* Target-specific opcodes for host vector expansion. These will be emitted by tcg_expand_vec_op. For those familiar with GCC internals, consider these to be UNSPEC with names. */ + +DEF(aa64_sshl_vec, 1, 2, 0, IMPLVEC) diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c index 15ab35adf7..7d842cad47 100644 --- a/tcg/aarch64/tcg-target.inc.c +++ b/tcg/aarch64/tcg-target.inc.c @@ -536,12 +536,14 @@ typedef enum { I3616_CMEQ =3D 0x2e208c00, I3616_SMAX =3D 0x0e206400, I3616_SMIN =3D 0x0e206c00, + I3616_SSHL =3D 0x0e204400, I3616_SQADD =3D 0x0e200c00, I3616_SQSUB =3D 0x0e202c00, I3616_UMAX =3D 0x2e206400, I3616_UMIN =3D 0x2e206c00, I3616_UQADD =3D 0x2e200c00, I3616_UQSUB =3D 0x2e202c00, + I3616_USHL =3D 0x2e204400, =20 /* AdvSIMD two-reg misc. */ I3617_CMGT0 =3D 0x0e208800, @@ -2256,6 +2258,12 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, case INDEX_op_sari_vec: tcg_out_insn(s, 3614, SSHR, is_q, a0, a1, (16 << vece) - a2); break; + case INDEX_op_shlv_vec: + tcg_out_insn(s, 3616, USHL, is_q, vece, a0, a1, a2); + break; + case INDEX_op_aa64_sshl_vec: + tcg_out_insn(s, 3616, SSHL, is_q, vece, a0, a1, a2); + break; case INDEX_op_cmp_vec: { TCGCond cond =3D args[3]; @@ -2323,7 +2331,11 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type,= unsigned vece) case INDEX_op_smin_vec: case INDEX_op_umax_vec: case INDEX_op_umin_vec: + case INDEX_op_shlv_vec: return 1; + case INDEX_op_shrv_vec: + case INDEX_op_sarv_vec: + return -1; case INDEX_op_mul_vec: return vece < MO_64; =20 @@ -2335,6 +2347,32 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type,= unsigned vece) void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, TCGArg a0, ...) { + va_list va; + TCGv_vec v0, v1, v2, t1; + + va_start(va, a0); + v0 =3D temp_tcgv_vec(arg_temp(a0)); + v1 =3D temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); + v2 =3D temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); + + switch (opc) { + case INDEX_op_shrv_vec: + case INDEX_op_sarv_vec: + /* Right shifts are negative left shifts for AArch64. */ + t1 =3D tcg_temp_new_vec(type); + tcg_gen_neg_vec(vece, t1, v2); + opc =3D (opc =3D=3D INDEX_op_shrv_vec + ? INDEX_op_shlv_vec : INDEX_op_aa64_sshl_vec); + vec_gen_3(opc, type, vece, tcgv_vec_arg(v0), + tcgv_vec_arg(v1), tcgv_vec_arg(t1)); + tcg_temp_free_vec(t1); + break; + + default: + g_assert_not_reached(); + } + + va_end(va); } =20 static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) @@ -2516,6 +2554,10 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOp= code op) case INDEX_op_smin_vec: case INDEX_op_umax_vec: case INDEX_op_umin_vec: + case INDEX_op_shlv_vec: + case INDEX_op_shrv_vec: + case INDEX_op_sarv_vec: + case INDEX_op_aa64_sshl_vec: return &w_w_w; case INDEX_op_not_vec: case INDEX_op_neg_vec: --=20 2.17.1 From nobody Sat May 4 13:31:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1556949881; cv=none; d=zoho.com; s=zohoarc; b=OVbAr3AZb7TnK/7ddXPeVrPBflFnLoUGgzvsrbHTLaiE+D/qhF4mziJ/MHyaXmQAAZLN2WlwI+hS2ZFlTmQ/S434qbwZ5fSfrFaoO1zrAvW3MyHRjs05nLgdO0CXo/cVk/vSTe5WBENbTmipkVwmuyR6y5UQ0n1vB7qgGW49xLw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1556949881; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=qw9asg7SRqxlX27WylYo/55gkKhhqIWBrKFJgQwUqqc=; b=M0uLktw91VDz4c+cFrTm/Snnn7BWgdCiYdxTkIe54wenwUJ0kqZf3/wrEv6OsXW9fGccoGQT3368s+zQxnGV5ulYf4Wi1YY76+5MNKtgGHs5NzxbosmMAAHuIboyni4JPKaxhXQqDIwEKfDLpS0QQdCLfZaiSsWROhaG96dNOfY= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 155694988177510.68158197824414; Fri, 3 May 2019 23:04:41 -0700 (PDT) Received: from localhost ([127.0.0.1]:51749 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hMnmo-0007xX-Hf for importer@patchew.org; Sat, 04 May 2019 02:04:38 -0400 Received: from eggs.gnu.org ([209.51.188.92]:41925) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hMnbz-0007vz-6Y for qemu-devel@nongnu.org; Sat, 04 May 2019 01:53:28 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hMnbx-0004Mu-Fw for qemu-devel@nongnu.org; Sat, 04 May 2019 01:53:27 -0400 Received: from mail-pg1-x543.google.com ([2607:f8b0:4864:20::543]:35880) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hMnbx-0004MM-7D for qemu-devel@nongnu.org; Sat, 04 May 2019 01:53:25 -0400 Received: by mail-pg1-x543.google.com with SMTP id 85so3768775pgc.3 for ; Fri, 03 May 2019 22:53:25 -0700 (PDT) Received: from localhost.localdomain (97-113-189-189.tukw.qwest.net. [97.113.189.189]) by smtp.gmail.com with ESMTPSA id 15sm6680423pfo.117.2019.05.03.22.53.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 03 May 2019 22:53:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=qw9asg7SRqxlX27WylYo/55gkKhhqIWBrKFJgQwUqqc=; b=zPk2iiood4zQAFE1p4nOun9WlPhRYe8X6DtHXn5W6MYTuMExnWYESrUaCUWrJ/Kbfk c28ZqEok11BepA1OuUQ3DQWnLaRooZs7R1jdUxs6SHjzmVPjDTqBVrGJWLxniAj0pZOa 863/ZtPOMVACz+IdP7rf3jGiBHnDnlcl5jGXicSgOmtrpohWHv+6DA75eGF7xmpn47KB HxclW12I8undTphfohAfeoAGqf4UrvwmgOOCplnAYz2+mQ9AqG9yY1rFiBQnSzdxki/G 1+EsV7Ng4TSJYEJyX9tlXGQvsYcDfapvgztdrCQfb2855xST6hv92iZJhPGsZnfJLx7v EVdQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=qw9asg7SRqxlX27WylYo/55gkKhhqIWBrKFJgQwUqqc=; b=ClQ/YNkS6vpOsbokieYt4HxAD/fQ8X8XuYgcsU6sxhd9KPl0N5Ttu09UwZnxYJRaty mL3nKRRDav9rFgLDZ+EVcjbRJ9WSVG6Dzlu/dXU2WT3nIlHoeYs7cX16Xr19ZdHcUfnW XUR4rXmLGMQjBKqDAA2mNnGwdsRSxYQ0JTkKpAVY0Z9bnFz152pZmzM92AIq7VXcoAXu vgKy3TDVnBU4IiuYqZ9tgwvAyUBqGvKf0uKuUDV9NhHwaoXQukbVol2tIMBiG3MTZfhv yGeIUld3FGvMY9IRZX1r84PBR9KW1bt32PMU8EQKjBTzFKqYBJUT8smsP5F7q0xocjLv gdyw== X-Gm-Message-State: APjAAAWlZRmcI9F8GrQqhTXhIolUPIMbDQi1GiYHuXx9TLBtEIVySZeu KqK4Srf6EDfzLLAgsNFxU5dXQAD2RVg= X-Google-Smtp-Source: APXvYqwnjEP+HvA2asahCxUb4GtCfdwVj/iqqBk7YB3SRBvlLyu7D/PTb9Nxd/ZDOVAaZ21JuZxMkw== X-Received: by 2002:a63:550c:: with SMTP id j12mr15945016pgb.450.1556949203762; Fri, 03 May 2019 22:53:23 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 3 May 2019 22:52:47 -0700 Message-Id: <20190504055300.18426-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190504055300.18426-1-richard.henderson@linaro.org> References: <20190504055300.18426-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 Subject: [Qemu-devel] [PATCH v3 18/31] tcg: Add gvec expanders for vector shift by scalar X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Allow expansion either via shift by scalar or by replicating the scalar for shift by vector. Signed-off-by: Richard Henderson --- v3: Use a private structure for do_gvec_shifts. --- tcg/tcg-op-gvec.h | 7 ++ tcg/tcg-op.h | 4 + tcg/tcg-op-gvec.c | 214 ++++++++++++++++++++++++++++++++++++++++++++++ tcg/tcg-op-vec.c | 54 ++++++++++++ 4 files changed, 279 insertions(+) diff --git a/tcg/tcg-op-gvec.h b/tcg/tcg-op-gvec.h index 84a6247b16..6ee98f3378 100644 --- a/tcg/tcg-op-gvec.h +++ b/tcg/tcg-op-gvec.h @@ -318,6 +318,13 @@ void tcg_gen_gvec_shri(unsigned vece, uint32_t dofs, u= int32_t aofs, void tcg_gen_gvec_sari(unsigned vece, uint32_t dofs, uint32_t aofs, int64_t shift, uint32_t oprsz, uint32_t maxsz); =20 +void tcg_gen_gvec_shls(unsigned vece, uint32_t dofs, uint32_t aofs, + TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_shrs(unsigned vece, uint32_t dofs, uint32_t aofs, + TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_sars(unsigned vece, uint32_t dofs, uint32_t aofs, + TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz); + /* * Perform vector shift by vector element, modulo the element size. * E.g. D[i] =3D A[i] << (B[i] % (8 << vece)). diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h index 833c6330b5..472b73cb38 100644 --- a/tcg/tcg-op.h +++ b/tcg/tcg-op.h @@ -986,6 +986,10 @@ void tcg_gen_shli_vec(unsigned vece, TCGv_vec r, TCGv_= vec a, int64_t i); void tcg_gen_shri_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i); void tcg_gen_sari_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i); =20 +void tcg_gen_shls_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s); +void tcg_gen_shrs_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s); +void tcg_gen_sars_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s); + void tcg_gen_shlv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s); void tcg_gen_shrv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s); void tcg_gen_sarv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s); diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c index 061ef329f1..c69c7960b8 100644 --- a/tcg/tcg-op-gvec.c +++ b/tcg/tcg-op-gvec.c @@ -2555,6 +2555,220 @@ void tcg_gen_gvec_sari(unsigned vece, uint32_t dofs= , uint32_t aofs, } } =20 +/* + * Specialized generation vector shifts by a non-constant scalar. + */ + +typedef struct { + void (*fni4)(TCGv_i32, TCGv_i32, TCGv_i32); + void (*fni8)(TCGv_i64, TCGv_i64, TCGv_i64); + void (*fniv_s)(unsigned, TCGv_vec, TCGv_vec, TCGv_i32); + void (*fniv_v)(unsigned, TCGv_vec, TCGv_vec, TCGv_vec); + gen_helper_gvec_2 *fno[4]; + TCGOpcode s_list[2]; + TCGOpcode v_list[2]; +} GVecGen2sh; + +static void expand_2sh_vec(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t oprsz, uint32_t tysz, TCGType type, + TCGv_i32 shift, + void (*fni)(unsigned, TCGv_vec, TCGv_vec, TCGv_= i32)) +{ + TCGv_vec t0 =3D tcg_temp_new_vec(type); + uint32_t i; + + for (i =3D 0; i < oprsz; i +=3D tysz) { + tcg_gen_ld_vec(t0, cpu_env, aofs + i); + fni(vece, t0, t0, shift); + tcg_gen_st_vec(t0, cpu_env, dofs + i); + } + tcg_temp_free_vec(t0); +} + +static void +do_gvec_shifts(unsigned vece, uint32_t dofs, uint32_t aofs, TCGv_i32 shift, + uint32_t oprsz, uint32_t maxsz, const GVecGen2sh *g) +{ + TCGType type; + uint32_t some; + + check_size_align(oprsz, maxsz, dofs | aofs); + check_overlap_2(dofs, aofs, maxsz); + + /* If the backend has a scalar expansion, great. */ + type =3D choose_vector_type(g->s_list, vece, oprsz, vece =3D=3D MO_64); + if (type) { + const TCGOpcode *hold_list =3D tcg_swap_vecop_list(NULL); + switch (type) { + case TCG_TYPE_V256: + some =3D QEMU_ALIGN_DOWN(oprsz, 32); + expand_2sh_vec(vece, dofs, aofs, some, 32, + TCG_TYPE_V256, shift, g->fniv_s); + if (some =3D=3D oprsz) { + break; + } + dofs +=3D some; + aofs +=3D some; + oprsz -=3D some; + maxsz -=3D some; + /* fallthru */ + case TCG_TYPE_V128: + expand_2sh_vec(vece, dofs, aofs, oprsz, 16, + TCG_TYPE_V128, shift, g->fniv_s); + break; + case TCG_TYPE_V64: + expand_2sh_vec(vece, dofs, aofs, oprsz, 8, + TCG_TYPE_V64, shift, g->fniv_s); + break; + default: + g_assert_not_reached(); + } + tcg_swap_vecop_list(hold_list); + goto clear_tail; + } + + /* If the backend supports variable vector shifts, also cool. */ + type =3D choose_vector_type(g->v_list, vece, oprsz, vece =3D=3D MO_64); + if (type) { + const TCGOpcode *hold_list =3D tcg_swap_vecop_list(NULL); + TCGv_vec v_shift =3D tcg_temp_new_vec(type); + + if (vece =3D=3D MO_64) { + TCGv_i64 sh64 =3D tcg_temp_new_i64(); + tcg_gen_extu_i32_i64(sh64, shift); + tcg_gen_dup_i64_vec(MO_64, v_shift, sh64); + tcg_temp_free_i64(sh64); + } else { + tcg_gen_dup_i32_vec(vece, v_shift, shift); + } + + switch (type) { + case TCG_TYPE_V256: + some =3D QEMU_ALIGN_DOWN(oprsz, 32); + expand_2s_vec(vece, dofs, aofs, some, 32, TCG_TYPE_V256, + v_shift, false, g->fniv_v); + if (some =3D=3D oprsz) { + break; + } + dofs +=3D some; + aofs +=3D some; + oprsz -=3D some; + maxsz -=3D some; + /* fallthru */ + case TCG_TYPE_V128: + expand_2s_vec(vece, dofs, aofs, oprsz, 16, TCG_TYPE_V128, + v_shift, false, g->fniv_v); + break; + case TCG_TYPE_V64: + expand_2s_vec(vece, dofs, aofs, oprsz, 8, TCG_TYPE_V64, + v_shift, false, g->fniv_v); + break; + default: + g_assert_not_reached(); + } + tcg_temp_free_vec(v_shift); + tcg_swap_vecop_list(hold_list); + goto clear_tail; + } + + /* Otherwise fall back to integral... */ + if (vece =3D=3D MO_32 && check_size_impl(oprsz, 4)) { + expand_2s_i32(dofs, aofs, oprsz, shift, false, g->fni4); + } else if (vece =3D=3D MO_64 && check_size_impl(oprsz, 8)) { + TCGv_i64 sh64 =3D tcg_temp_new_i64(); + tcg_gen_extu_i32_i64(sh64, shift); + expand_2s_i64(dofs, aofs, oprsz, sh64, false, g->fni8); + tcg_temp_free_i64(sh64); + } else { + TCGv_ptr a0 =3D tcg_temp_new_ptr(); + TCGv_ptr a1 =3D tcg_temp_new_ptr(); + TCGv_i32 desc =3D tcg_temp_new_i32(); + + tcg_gen_shli_i32(desc, shift, SIMD_DATA_SHIFT); + tcg_gen_ori_i32(desc, desc, simd_desc(oprsz, maxsz, 0)); + tcg_gen_addi_ptr(a0, cpu_env, dofs); + tcg_gen_addi_ptr(a1, cpu_env, aofs); + + g->fno[vece](a0, a1, desc); + + tcg_temp_free_ptr(a0); + tcg_temp_free_ptr(a1); + tcg_temp_free_i32(desc); + return; + } + + clear_tail: + if (oprsz < maxsz) { + expand_clr(dofs + oprsz, maxsz - oprsz); + } +} + +void tcg_gen_gvec_shls(unsigned vece, uint32_t dofs, uint32_t aofs, + TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz) +{ + static const GVecGen2sh g =3D { + .fni4 =3D tcg_gen_shl_i32, + .fni8 =3D tcg_gen_shl_i64, + .fniv_s =3D tcg_gen_shls_vec, + .fniv_v =3D tcg_gen_shlv_vec, + .fno =3D { + gen_helper_gvec_shl8i, + gen_helper_gvec_shl16i, + gen_helper_gvec_shl32i, + gen_helper_gvec_shl64i, + }, + .s_list =3D { INDEX_op_shls_vec, 0 }, + .v_list =3D { INDEX_op_shlv_vec, 0 }, + }; + + tcg_debug_assert(vece <=3D MO_64); + do_gvec_shifts(vece, dofs, aofs, shift, oprsz, maxsz, &g); +} + +void tcg_gen_gvec_shrs(unsigned vece, uint32_t dofs, uint32_t aofs, + TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz) +{ + static const GVecGen2sh g =3D { + .fni4 =3D tcg_gen_shr_i32, + .fni8 =3D tcg_gen_shr_i64, + .fniv_s =3D tcg_gen_shrs_vec, + .fniv_v =3D tcg_gen_shrv_vec, + .fno =3D { + gen_helper_gvec_shr8i, + gen_helper_gvec_shr16i, + gen_helper_gvec_shr32i, + gen_helper_gvec_shr64i, + }, + .s_list =3D { INDEX_op_shrs_vec, 0 }, + .v_list =3D { INDEX_op_shrv_vec, 0 }, + }; + + tcg_debug_assert(vece <=3D MO_64); + do_gvec_shifts(vece, dofs, aofs, shift, oprsz, maxsz, &g); +} + +void tcg_gen_gvec_sars(unsigned vece, uint32_t dofs, uint32_t aofs, + TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz) +{ + static const GVecGen2sh g =3D { + .fni4 =3D tcg_gen_sar_i32, + .fni8 =3D tcg_gen_sar_i64, + .fniv_s =3D tcg_gen_sars_vec, + .fniv_v =3D tcg_gen_sarv_vec, + .fno =3D { + gen_helper_gvec_sar8i, + gen_helper_gvec_sar16i, + gen_helper_gvec_sar32i, + gen_helper_gvec_sar64i, + }, + .s_list =3D { INDEX_op_sars_vec, 0 }, + .v_list =3D { INDEX_op_sarv_vec, 0 }, + }; + + tcg_debug_assert(vece <=3D MO_64); + do_gvec_shifts(vece, dofs, aofs, shift, oprsz, maxsz, &g); +} + /* * Expand D =3D A << (B % element bits) * diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c index 96317dbd10..16062f5995 100644 --- a/tcg/tcg-op-vec.c +++ b/tcg/tcg-op-vec.c @@ -598,3 +598,57 @@ void tcg_gen_sarv_vec(unsigned vece, TCGv_vec r, TCGv_= vec a, TCGv_vec b) { do_op3(vece, r, a, b, INDEX_op_sarv_vec); } + +static void do_shifts(unsigned vece, TCGv_vec r, TCGv_vec a, + TCGv_i32 s, TCGOpcode opc_s, TCGOpcode opc_v) +{ + TCGTemp *rt =3D tcgv_vec_temp(r); + TCGTemp *at =3D tcgv_vec_temp(a); + TCGTemp *st =3D tcgv_i32_temp(s); + TCGArg ri =3D temp_arg(rt); + TCGArg ai =3D temp_arg(at); + TCGArg si =3D temp_arg(st); + TCGType type =3D rt->base_type; + const TCGOpcode *hold_list; + int can; + + tcg_debug_assert(at->base_type >=3D type); + tcg_assert_listed_vecop(opc_s); + hold_list =3D tcg_swap_vecop_list(NULL); + + can =3D tcg_can_emit_vec_op(opc_s, type, vece); + if (can > 0) { + vec_gen_3(opc_s, type, vece, ri, ai, si); + } else if (can < 0) { + tcg_expand_vec_op(opc_s, type, vece, ri, ai, si); + } else { + TCGv_vec vec_s =3D tcg_temp_new_vec(type); + + if (vece =3D=3D MO_64) { + TCGv_i64 s64 =3D tcg_temp_new_i64(); + tcg_gen_extu_i32_i64(s64, s); + tcg_gen_dup_i64_vec(MO_64, vec_s, s64); + tcg_temp_free_i64(s64); + } else { + tcg_gen_dup_i32_vec(vece, vec_s, s); + } + do_op3(vece, r, a, vec_s, opc_v); + tcg_temp_free_vec(vec_s); + } + tcg_swap_vecop_list(hold_list); +} + +void tcg_gen_shls_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 b) +{ + do_shifts(vece, r, a, b, INDEX_op_shls_vec, INDEX_op_shlv_vec); +} + +void tcg_gen_shrs_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 b) +{ + do_shifts(vece, r, a, b, INDEX_op_shrs_vec, INDEX_op_shrv_vec); +} + +void tcg_gen_sars_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 b) +{ + do_shifts(vece, r, a, b, INDEX_op_sars_vec, INDEX_op_sarv_vec); +} --=20 2.17.1 From nobody Sat May 4 13:31:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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X-Received-From: 2607:f8b0:4864:20::633 Subject: [Qemu-devel] [PATCH v3 19/31] tcg/i386: Support vector scalar shift opcodes X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.h | 2 +- tcg/i386/tcg-target.inc.c | 35 +++++++++++++++++++++++++++++++++++ 2 files changed, 36 insertions(+), 1 deletion(-) diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index b240633455..618aa520d2 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -183,7 +183,7 @@ extern bool have_avx2; #define TCG_TARGET_HAS_not_vec 0 #define TCG_TARGET_HAS_neg_vec 0 #define TCG_TARGET_HAS_shi_vec 1 -#define TCG_TARGET_HAS_shs_vec 0 +#define TCG_TARGET_HAS_shs_vec 1 #define TCG_TARGET_HAS_shv_vec have_avx2 #define TCG_TARGET_HAS_cmp_vec 1 #define TCG_TARGET_HAS_mul_vec 1 diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index c9448b6d84..0ba1587da4 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -420,6 +420,14 @@ static inline int tcg_target_const_match(tcg_target_lo= ng val, TCGType type, #define OPC_PSHIFTW_Ib (0x71 | P_EXT | P_DATA16) /* /2 /6 /4 */ #define OPC_PSHIFTD_Ib (0x72 | P_EXT | P_DATA16) /* /2 /6 /4 */ #define OPC_PSHIFTQ_Ib (0x73 | P_EXT | P_DATA16) /* /2 /6 /4 */ +#define OPC_PSLLW (0xf1 | P_EXT | P_DATA16) +#define OPC_PSLLD (0xf2 | P_EXT | P_DATA16) +#define OPC_PSLLQ (0xf3 | P_EXT | P_DATA16) +#define OPC_PSRAW (0xe1 | P_EXT | P_DATA16) +#define OPC_PSRAD (0xe2 | P_EXT | P_DATA16) +#define OPC_PSRLW (0xd1 | P_EXT | P_DATA16) +#define OPC_PSRLD (0xd2 | P_EXT | P_DATA16) +#define OPC_PSRLQ (0xd3 | P_EXT | P_DATA16) #define OPC_PSUBB (0xf8 | P_EXT | P_DATA16) #define OPC_PSUBW (0xf9 | P_EXT | P_DATA16) #define OPC_PSUBD (0xfa | P_EXT | P_DATA16) @@ -2724,6 +2732,15 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, /* TODO: AVX512 adds support for MO_16, MO_64. */ OPC_UD2, OPC_UD2, OPC_VPSRAVD, OPC_UD2 }; + static int const shls_insn[4] =3D { + OPC_UD2, OPC_PSLLW, OPC_PSLLD, OPC_PSLLQ + }; + static int const shrs_insn[4] =3D { + OPC_UD2, OPC_PSRLW, OPC_PSRLD, OPC_PSRLQ + }; + static int const sars_insn[4] =3D { + OPC_UD2, OPC_PSRAW, OPC_PSRAD, OPC_UD2 + }; =20 TCGType type =3D vecl + TCG_TYPE_V64; int insn, sub; @@ -2785,6 +2802,15 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, case INDEX_op_sarv_vec: insn =3D sarv_insn[vece]; goto gen_simd; + case INDEX_op_shls_vec: + insn =3D shls_insn[vece]; + goto gen_simd; + case INDEX_op_shrs_vec: + insn =3D shrs_insn[vece]; + goto gen_simd; + case INDEX_op_sars_vec: + insn =3D sars_insn[vece]; + goto gen_simd; case INDEX_op_x86_punpckl_vec: insn =3D punpckl_insn[vece]; goto gen_simd; @@ -3165,6 +3191,9 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) case INDEX_op_shlv_vec: case INDEX_op_shrv_vec: case INDEX_op_sarv_vec: + case INDEX_op_shls_vec: + case INDEX_op_shrs_vec: + case INDEX_op_sars_vec: case INDEX_op_cmp_vec: case INDEX_op_x86_shufps_vec: case INDEX_op_x86_blend_vec: @@ -3222,6 +3251,12 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type,= unsigned vece) } return 1; =20 + case INDEX_op_shls_vec: + case INDEX_op_shrs_vec: + return vece >=3D MO_16; + case INDEX_op_sars_vec: + return vece >=3D MO_16 && vece <=3D MO_32; + case INDEX_op_shlv_vec: case INDEX_op_shrv_vec: return have_avx2 && vece >=3D MO_32; --=20 2.17.1 From nobody Sat May 4 13:31:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1556950557; cv=none; d=zoho.com; s=zohoarc; b=SYEzuQFWNtF4Lx8ANk+/2IoRpFQLBgyfq4p8g/jyPaJsadkbL+l3HUDnoT+X0zrGZ1R03cLv3KCMMi/7UZXvM3QSGq8wcmm/Wjnd4X7mDJiwhfoy6X8FHiEBDM1gdy/xShWRp1AAAvbICEAMDFQxaq+5CBf1nuZdYQcGhwS9XUU= ARC-Message-Signature: i=1; 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[97.113.189.189]) by smtp.gmail.com with ESMTPSA id 15sm6680423pfo.117.2019.05.03.22.53.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 03 May 2019 22:53:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=oB7VP5ATUZChOLMjOlpdWPN1IctJhwYBQQIlaCDVjkw=; b=ZN3z0+Wx4Ckd7Bz+92mm0xR6ZEmC12+z4/YNmrctazoL3a90rBrP0Cd+qNl3CRl0bA FAeg9xS0Atv0zhsd4R4Yd8gEhbZt6qykz5yObK6GlhzpbCtN5cxZ2OishmX5UDGlm2CP d/eYVi1rbbTfaZ0l750kF/okdLqJjZflNUaikeXv6pRHLmgO9/RKffgZOqi2SJoVGPi2 E5UDwmVhoLPthGkgAT0h+xy2ybEY17/pSqPa+ajSaoAQiZQHgd9k8RlhrnEKDU7tx+zU GFjxGxOLj0MWRcKZg0Jfamkr0ls8u8FfiFu5Ygc4DnmM6WyJ2myDULzsBNjIO86Tx0HV 951Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=oB7VP5ATUZChOLMjOlpdWPN1IctJhwYBQQIlaCDVjkw=; b=Nf8lQiL2umXwyDCgT+TRtEdV/qPGQxxMrR4AVHdFNhrTIsC38i2Y3unK66qtWUKH4S z6GKlqO6TuRrzOc04x5TELYldpCM8Mn6EVy6xBgNo3fXAooI1VSTvpF5ohUGVwXuyrkq fIOIyRRNcUkbEdnCZGA/t3hDK0RUgL0LUNo9SJKv9u/WZXwCqVsNgbjiioCPw1A1FIRz k9A1H4JVFSrrXEUI5vr8zirMr7Fuv/nCIodiQfS+k56lqKvwUz24sOyU+MYNadkFlPpp 4mw63OZI7+yYyY5TQZ87n9R64H04hZcPwAHhbXIYBxktw8GT9tAMeZKhoIXRKZhv7dM7 RZXg== X-Gm-Message-State: APjAAAXo9XSGbQKTNQpHamhcl7VNvfuM5YIcGF+nd20VErhEmFY9cfUE /5m/8r5k02F1M9iIDAX8yWta/QL3i7g= X-Google-Smtp-Source: APXvYqzWLetqo1I/alzsuBBa8zDNfOUEAf2LbjwEvVKFnP5kg/QG1eIFdcLIPfW/khiNpRq5D55GYQ== X-Received: by 2002:a63:d016:: with SMTP id z22mr16343866pgf.116.1556949205972; Fri, 03 May 2019 22:53:25 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 3 May 2019 22:52:49 -0700 Message-Id: <20190504055300.18426-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190504055300.18426-1-richard.henderson@linaro.org> References: <20190504055300.18426-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 Subject: [Qemu-devel] [PATCH v3 20/31] tcg: Add support for integer absolute value X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Remove a function of the same name from target/arm/. Use a branchless implementation of abs gleaned from gcc. Reviewed-by: Alex Benn=C3=A9e Reviewed-by: David Hildenbrand Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/tcg-op.h | 5 +++++ target/arm/translate.c | 10 ---------- tcg/tcg-op.c | 20 ++++++++++++++++++++ 3 files changed, 25 insertions(+), 10 deletions(-) diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h index 472b73cb38..660fe205d0 100644 --- a/tcg/tcg-op.h +++ b/tcg/tcg-op.h @@ -335,6 +335,7 @@ void tcg_gen_smin_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32= arg2); void tcg_gen_smax_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_umin_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_umax_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2); +void tcg_gen_abs_i32(TCGv_i32, TCGv_i32); =20 static inline void tcg_gen_discard_i32(TCGv_i32 arg) { @@ -534,6 +535,7 @@ void tcg_gen_smin_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64= arg2); void tcg_gen_smax_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_umin_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_umax_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2); +void tcg_gen_abs_i64(TCGv_i64, TCGv_i64); =20 #if TCG_TARGET_REG_BITS =3D=3D 64 static inline void tcg_gen_discard_i64(TCGv_i64 arg) @@ -973,6 +975,7 @@ void tcg_gen_nor_vec(unsigned vece, TCGv_vec r, TCGv_ve= c a, TCGv_vec b); void tcg_gen_eqv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); void tcg_gen_not_vec(unsigned vece, TCGv_vec r, TCGv_vec a); void tcg_gen_neg_vec(unsigned vece, TCGv_vec r, TCGv_vec a); +void tcg_gen_abs_vec(unsigned vece, TCGv_vec r, TCGv_vec a); void tcg_gen_ssadd_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); void tcg_gen_usadd_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); void tcg_gen_sssub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); @@ -1019,6 +1022,7 @@ void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr base, TCGAr= g offset, TCGType t); #define tcg_gen_addi_tl tcg_gen_addi_i64 #define tcg_gen_sub_tl tcg_gen_sub_i64 #define tcg_gen_neg_tl tcg_gen_neg_i64 +#define tcg_gen_abs_tl tcg_gen_abs_i64 #define tcg_gen_subfi_tl tcg_gen_subfi_i64 #define tcg_gen_subi_tl tcg_gen_subi_i64 #define tcg_gen_and_tl tcg_gen_and_i64 @@ -1131,6 +1135,7 @@ void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr base, TCGAr= g offset, TCGType t); #define tcg_gen_addi_tl tcg_gen_addi_i32 #define tcg_gen_sub_tl tcg_gen_sub_i32 #define tcg_gen_neg_tl tcg_gen_neg_i32 +#define tcg_gen_abs_tl tcg_gen_abs_i32 #define tcg_gen_subfi_tl tcg_gen_subfi_i32 #define tcg_gen_subi_tl tcg_gen_subi_i32 #define tcg_gen_and_tl tcg_gen_and_i32 diff --git a/target/arm/translate.c b/target/arm/translate.c index 35bd426a3d..b25781554f 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -604,16 +604,6 @@ static void gen_sar(TCGv_i32 dest, TCGv_i32 t0, TCGv_i= 32 t1) tcg_temp_free_i32(tmp1); } =20 -static void tcg_gen_abs_i32(TCGv_i32 dest, TCGv_i32 src) -{ - TCGv_i32 c0 =3D tcg_const_i32(0); - TCGv_i32 tmp =3D tcg_temp_new_i32(); - tcg_gen_neg_i32(tmp, src); - tcg_gen_movcond_i32(TCG_COND_GT, dest, src, c0, src, tmp); - tcg_temp_free_i32(c0); - tcg_temp_free_i32(tmp); -} - static void shifter_out_im(TCGv_i32 var, int shift) { if (shift =3D=3D 0) { diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index a00d1df37e..0ac291f1c4 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -1091,6 +1091,16 @@ void tcg_gen_umax_i32(TCGv_i32 ret, TCGv_i32 a, TCGv= _i32 b) tcg_gen_movcond_i32(TCG_COND_LTU, ret, a, b, b, a); } =20 +void tcg_gen_abs_i32(TCGv_i32 ret, TCGv_i32 a) +{ + TCGv_i32 t =3D tcg_temp_new_i32(); + + tcg_gen_sari_i32(t, a, 31); + tcg_gen_xor_i32(ret, a, t); + tcg_gen_sub_i32(ret, ret, t); + tcg_temp_free_i32(t); +} + /* 64-bit ops */ =20 #if TCG_TARGET_REG_BITS =3D=3D 32 @@ -2548,6 +2558,16 @@ void tcg_gen_umax_i64(TCGv_i64 ret, TCGv_i64 a, TCGv= _i64 b) tcg_gen_movcond_i64(TCG_COND_LTU, ret, a, b, b, a); } =20 +void tcg_gen_abs_i64(TCGv_i64 ret, TCGv_i64 a) +{ + TCGv_i64 t =3D tcg_temp_new_i64(); + + tcg_gen_sari_i64(t, a, 63); + tcg_gen_xor_i64(ret, a, t); + tcg_gen_sub_i64(ret, ret, t); + tcg_temp_free_i64(t); +} + /* Size changing operations. */ =20 void tcg_gen_extrl_i64_i32(TCGv_i32 ret, TCGv_i64 arg) --=20 2.17.1 From nobody Sat May 4 13:31:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; 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X-Received-From: 2607:f8b0:4864:20::530 Subject: [Qemu-devel] [PATCH v3 21/31] tcg: Add support for vector absolute value X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- accel/tcg/tcg-runtime.h | 5 +++ tcg/aarch64/tcg-target.h | 1 + tcg/i386/tcg-target.h | 1 + tcg/tcg-op-gvec.h | 2 ++ tcg/tcg-opc.h | 1 + tcg/tcg.h | 1 + accel/tcg/tcg-runtime-gvec.c | 48 +++++++++++++++++++++++++++ tcg/tcg-op-gvec.c | 63 ++++++++++++++++++++++++++++++++++++ tcg/tcg-op-vec.c | 39 ++++++++++++++++++++++ tcg/tcg.c | 2 ++ tcg/README | 4 +++ 11 files changed, 167 insertions(+) diff --git a/accel/tcg/tcg-runtime.h b/accel/tcg/tcg-runtime.h index ed3ce5fd91..6d73dc2d65 100644 --- a/accel/tcg/tcg-runtime.h +++ b/accel/tcg/tcg-runtime.h @@ -225,6 +225,11 @@ DEF_HELPER_FLAGS_3(gvec_neg16, TCG_CALL_NO_RWG, void, = ptr, ptr, i32) DEF_HELPER_FLAGS_3(gvec_neg32, TCG_CALL_NO_RWG, void, ptr, ptr, i32) DEF_HELPER_FLAGS_3(gvec_neg64, TCG_CALL_NO_RWG, void, ptr, ptr, i32) =20 +DEF_HELPER_FLAGS_3(gvec_abs8, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(gvec_abs16, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(gvec_abs32, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(gvec_abs64, TCG_CALL_NO_RWG, void, ptr, ptr, i32) + DEF_HELPER_FLAGS_3(gvec_not, TCG_CALL_NO_RWG, void, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_and, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_or, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index f5640a229b..21d06d928c 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -132,6 +132,7 @@ typedef enum { #define TCG_TARGET_HAS_orc_vec 1 #define TCG_TARGET_HAS_not_vec 1 #define TCG_TARGET_HAS_neg_vec 1 +#define TCG_TARGET_HAS_abs_vec 0 #define TCG_TARGET_HAS_shi_vec 1 #define TCG_TARGET_HAS_shs_vec 0 #define TCG_TARGET_HAS_shv_vec 1 diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 618aa520d2..7445f05885 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -182,6 +182,7 @@ extern bool have_avx2; #define TCG_TARGET_HAS_orc_vec 0 #define TCG_TARGET_HAS_not_vec 0 #define TCG_TARGET_HAS_neg_vec 0 +#define TCG_TARGET_HAS_abs_vec 0 #define TCG_TARGET_HAS_shi_vec 1 #define TCG_TARGET_HAS_shs_vec 1 #define TCG_TARGET_HAS_shv_vec have_avx2 diff --git a/tcg/tcg-op-gvec.h b/tcg/tcg-op-gvec.h index 6ee98f3378..52a398c190 100644 --- a/tcg/tcg-op-gvec.h +++ b/tcg/tcg-op-gvec.h @@ -228,6 +228,8 @@ void tcg_gen_gvec_not(unsigned vece, uint32_t dofs, uin= t32_t aofs, uint32_t oprsz, uint32_t maxsz); void tcg_gen_gvec_neg(unsigned vece, uint32_t dofs, uint32_t aofs, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_abs(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t oprsz, uint32_t maxsz); =20 void tcg_gen_gvec_add(unsigned vece, uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t oprsz, uint32_t maxsz); diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h index 4bf71f261f..4a2dd116eb 100644 --- a/tcg/tcg-opc.h +++ b/tcg/tcg-opc.h @@ -225,6 +225,7 @@ DEF(add_vec, 1, 2, 0, IMPLVEC) DEF(sub_vec, 1, 2, 0, IMPLVEC) DEF(mul_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_mul_vec)) DEF(neg_vec, 1, 1, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_neg_vec)) +DEF(abs_vec, 1, 1, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_abs_vec)) DEF(ssadd_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_sat_vec)) DEF(usadd_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_sat_vec)) DEF(sssub_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_sat_vec)) diff --git a/tcg/tcg.h b/tcg/tcg.h index 2c7315da25..0e01a70d66 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -176,6 +176,7 @@ typedef uint64_t TCGRegSet; && !defined(TCG_TARGET_HAS_v128) \ && !defined(TCG_TARGET_HAS_v256) #define TCG_TARGET_MAYBE_vec 0 +#define TCG_TARGET_HAS_abs_vec 0 #define TCG_TARGET_HAS_neg_vec 0 #define TCG_TARGET_HAS_not_vec 0 #define TCG_TARGET_HAS_andc_vec 0 diff --git a/accel/tcg/tcg-runtime-gvec.c b/accel/tcg/tcg-runtime-gvec.c index 2152fb6903..0f09e0ef38 100644 --- a/accel/tcg/tcg-runtime-gvec.c +++ b/accel/tcg/tcg-runtime-gvec.c @@ -398,6 +398,54 @@ void HELPER(gvec_neg64)(void *d, void *a, uint32_t des= c) clear_high(d, oprsz, desc); } =20 +void HELPER(gvec_abs8)(void *d, void *a, uint32_t desc) +{ + intptr_t oprsz =3D simd_oprsz(desc); + intptr_t i; + + for (i =3D 0; i < oprsz; i +=3D sizeof(int8_t)) { + int8_t aa =3D *(int8_t *)(a + i); + *(int8_t *)(d + i) =3D aa < 0 ? -aa : aa; + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_abs16)(void *d, void *a, uint32_t desc) +{ + intptr_t oprsz =3D simd_oprsz(desc); + intptr_t i; + + for (i =3D 0; i < oprsz; i +=3D sizeof(int16_t)) { + int16_t aa =3D *(int16_t *)(a + i); + *(int16_t *)(d + i) =3D aa < 0 ? -aa : aa; + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_abs32)(void *d, void *a, uint32_t desc) +{ + intptr_t oprsz =3D simd_oprsz(desc); + intptr_t i; + + for (i =3D 0; i < oprsz; i +=3D sizeof(int32_t)) { + int32_t aa =3D *(int32_t *)(a + i); + *(int32_t *)(d + i) =3D aa < 0 ? -aa : aa; + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_abs64)(void *d, void *a, uint32_t desc) +{ + intptr_t oprsz =3D simd_oprsz(desc); + intptr_t i; + + for (i =3D 0; i < oprsz; i +=3D sizeof(int64_t)) { + int64_t aa =3D *(int64_t *)(a + i); + *(int64_t *)(d + i) =3D aa < 0 ? -aa : aa; + } + clear_high(d, oprsz, desc); +} + void HELPER(gvec_mov)(void *d, void *a, uint32_t desc) { intptr_t oprsz =3D simd_oprsz(desc); diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c index c69c7960b8..338ddd9d9e 100644 --- a/tcg/tcg-op-gvec.c +++ b/tcg/tcg-op-gvec.c @@ -2177,6 +2177,69 @@ void tcg_gen_gvec_neg(unsigned vece, uint32_t dofs, = uint32_t aofs, tcg_gen_gvec_2(dofs, aofs, oprsz, maxsz, &g[vece]); } =20 +static void gen_absv_mask(TCGv_i64 d, TCGv_i64 b, unsigned vece) +{ + TCGv_i64 t =3D tcg_temp_new_i64(); + int nbit =3D 8 << vece; + + /* Create -1 for each negative element. */ + tcg_gen_shri_i64(t, b, nbit - 1); + tcg_gen_andi_i64(t, t, dup_const(vece, 1)); + tcg_gen_muli_i64(t, t, (1 << nbit) - 1); + + /* + * Invert (via xor -1) and add one (via sub -1). + * Because of the ordering the msb is cleared, + * so we never have carry into the next element. + */ + tcg_gen_xor_i64(d, b, t); + tcg_gen_sub_i64(d, d, t); + + tcg_temp_free_i64(t); +} + +static void tcg_gen_vec_abs8_i64(TCGv_i64 d, TCGv_i64 b) +{ + gen_absv_mask(d, b, MO_8); +} + +static void tcg_gen_vec_abs16_i64(TCGv_i64 d, TCGv_i64 b) +{ + gen_absv_mask(d, b, MO_16); +} + +void tcg_gen_gvec_abs(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t oprsz, uint32_t maxsz) +{ + static const TCGOpcode vecop_list[] =3D { INDEX_op_abs_vec, 0 }; + static const GVecGen2 g[4] =3D { + { .fni8 =3D tcg_gen_vec_abs8_i64, + .fniv =3D tcg_gen_abs_vec, + .fno =3D gen_helper_gvec_abs8, + .opt_opc =3D vecop_list, + .vece =3D MO_8 }, + { .fni8 =3D tcg_gen_vec_abs16_i64, + .fniv =3D tcg_gen_abs_vec, + .fno =3D gen_helper_gvec_abs16, + .opt_opc =3D vecop_list, + .vece =3D MO_16 }, + { .fni4 =3D tcg_gen_abs_i32, + .fniv =3D tcg_gen_abs_vec, + .fno =3D gen_helper_gvec_abs32, + .opt_opc =3D vecop_list, + .vece =3D MO_32 }, + { .fni8 =3D tcg_gen_abs_i64, + .fniv =3D tcg_gen_abs_vec, + .fno =3D gen_helper_gvec_abs64, + .opt_opc =3D vecop_list, + .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .vece =3D MO_64 }, + }; + + tcg_debug_assert(vece <=3D MO_64); + tcg_gen_gvec_2(dofs, aofs, oprsz, maxsz, &g[vece]); +} + void tcg_gen_gvec_and(unsigned vece, uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t oprsz, uint32_t maxsz) { diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c index 16062f5995..543508d545 100644 --- a/tcg/tcg-op-vec.c +++ b/tcg/tcg-op-vec.c @@ -110,6 +110,14 @@ bool tcg_can_emit_vecop_list(const TCGOpcode *list, continue; } break; + case INDEX_op_abs_vec: + if (tcg_can_emit_vec_op(INDEX_op_sub_vec, type, vece) + && (tcg_can_emit_vec_op(INDEX_op_smax_vec, type, vece) > 0 + || tcg_can_emit_vec_op(INDEX_op_sari_vec, type, vece) = > 0 + || tcg_can_emit_vec_op(INDEX_op_cmp_vec, type, vece)))= { + continue; + } + break; default: break; } @@ -429,6 +437,37 @@ void tcg_gen_neg_vec(unsigned vece, TCGv_vec r, TCGv_v= ec a) tcg_swap_vecop_list(hold_list); } =20 +void tcg_gen_abs_vec(unsigned vece, TCGv_vec r, TCGv_vec a) +{ + const TCGOpcode *hold_list; + + tcg_assert_listed_vecop(INDEX_op_abs_vec); + hold_list =3D tcg_swap_vecop_list(NULL); + + if (!do_op2(vece, r, a, INDEX_op_abs_vec)) { + TCGType type =3D tcgv_vec_temp(r)->base_type; + TCGv_vec t =3D tcg_temp_new_vec(type); + + tcg_debug_assert(tcg_can_emit_vec_op(INDEX_op_sub_vec, type, vece)= ); + if (tcg_can_emit_vec_op(INDEX_op_smax_vec, type, vece) > 0) { + tcg_gen_neg_vec(vece, t, a); + tcg_gen_smax_vec(vece, r, a, t); + } else { + if (tcg_can_emit_vec_op(INDEX_op_sari_vec, type, vece) > 0) { + tcg_gen_sari_vec(vece, t, a, (8 << vece) - 1); + } else { + do_dupi_vec(t, MO_REG, 0); + tcg_gen_cmp_vec(TCG_COND_LT, vece, t, a, t); + } + tcg_gen_xor_vec(vece, r, a, t); + tcg_gen_sub_vec(vece, r, r, t); + } + + tcg_temp_free_vec(t); + } + tcg_swap_vecop_list(hold_list); +} + static void do_shifti(TCGOpcode opc, unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i) { diff --git a/tcg/tcg.c b/tcg/tcg.c index 3b80feb344..24083b8c00 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1616,6 +1616,8 @@ bool tcg_op_supported(TCGOpcode op) return have_vec && TCG_TARGET_HAS_not_vec; case INDEX_op_neg_vec: return have_vec && TCG_TARGET_HAS_neg_vec; + case INDEX_op_abs_vec: + return have_vec && TCG_TARGET_HAS_abs_vec; case INDEX_op_andc_vec: return have_vec && TCG_TARGET_HAS_andc_vec; case INDEX_op_orc_vec: diff --git a/tcg/README b/tcg/README index c30e5418a6..cbdfd3b6bc 100644 --- a/tcg/README +++ b/tcg/README @@ -561,6 +561,10 @@ E.g. VECL=3D1 -> 64 << 1 -> v128, and VECE=3D2 -> 1 <<= 2 -> i32. =20 Similarly, v0 =3D -v1. =20 +* abs_vec v0, v1 + + Similarly, v0 =3D v1 < 0 ? -v1 : v1, in elements across the vector. + * smin_vec: * umin_vec: =20 --=20 2.17.1 From nobody Sat May 4 13:31:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1556950040; cv=none; d=zoho.com; s=zohoarc; b=Oh7lTLuTlt9Z1YA8wgZRhob1n3s8hDsKrl8sKQOS97REnly3ZezfXzvF9iVL0duIehX5EWo0lIMySN+c0auz7lhLIbyLNoW5mH8HfAytWqoSHYiICyu/3wiSwW6orNEaz6/zx/uk1PNo8cNF1H9E2vzljGKJw/Nxft5SsyP7LVU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1556950040; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=4RamRVLS6CpSQqwq41FPx2oK0CgrkzF+uLuaNa5g2S4=; b=jDlNTZEGRdGyOYqE1Ab0Y4xsg5X0Em2qfXGEw66IEeedU11BviAxzniQJgRUsGB8t3fbAUkatrw8BhTHuxqx1f4TP0VJmsngo/AE85V83uJOTQk5xdJ2TYPihdqjLKKHkj+YURr2tMam7yyZm+UMGRXXPFKysDiZ438gLqJg8uE= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1556950040033104.7165337274912; Fri, 3 May 2019 23:07:20 -0700 (PDT) Received: from localhost ([127.0.0.1]:51800 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hMnpI-0001ec-KV for importer@patchew.org; Sat, 04 May 2019 02:07:12 -0400 Received: from eggs.gnu.org ([209.51.188.92]:41977) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hMnc3-00081I-E8 for qemu-devel@nongnu.org; Sat, 04 May 2019 01:53:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hMnc2-0004R2-De for qemu-devel@nongnu.org; Sat, 04 May 2019 01:53:31 -0400 Received: from mail-pf1-x435.google.com ([2607:f8b0:4864:20::435]:45108) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hMnc2-0004P3-6z for qemu-devel@nongnu.org; Sat, 04 May 2019 01:53:30 -0400 Received: by mail-pf1-x435.google.com with SMTP id e24so3956563pfi.12 for ; Fri, 03 May 2019 22:53:30 -0700 (PDT) Received: from localhost.localdomain (97-113-189-189.tukw.qwest.net. [97.113.189.189]) by smtp.gmail.com with ESMTPSA id 15sm6680423pfo.117.2019.05.03.22.53.27 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 03 May 2019 22:53:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=4RamRVLS6CpSQqwq41FPx2oK0CgrkzF+uLuaNa5g2S4=; b=mxDjQCt37mE5J5Cvzs64RuNxY5zDhXZ3MIuN5y3PUi5nR5boLTrL0qW6YrH++IjGvZ QkuAUtbaqGMRK/31fbornlNW91M5vFI9+5a1nznsE1jF9Va6XFa17EpPNvqA6/lv/BvX VQmC1Ifc88lMAtucCyMS80eIz5Qya5EE/Ybvk2zX+xH24fLj02avXdmuehwEjJ0bzwNe /l5U2jKA+KX2uAuw0Yw88kpD/DcFbIYKusEnkqUE+ZZEEA06O5hxz0jDs+T+SObhhqRs b+aG3Bs+aJMPlrdb2uTY/JX3PWQBgoCurlOgmbPnGwh9U6nkfUOKc3rtiY/oM/nmqiBS XCSw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=4RamRVLS6CpSQqwq41FPx2oK0CgrkzF+uLuaNa5g2S4=; b=d/1pGY3JnA9UjyMRGzFUPA6IivZVsc1DAiYsOFfvQ2Ri0WFw0XOf9HnoUP7ywYJKvq rfKxbMxqXJwcAHp3KvPz5z/m8EXGkWI0LUVOL7B2KyJo4R9owEvw4TQzfSuweOuYo5nl 3RZw06hVFXZuwCkAFMzSvJ3kT3lZlcnjXm1Gx3LZJyb9PJj6G2xIuOd6q2pvS8cgOclE 8FKaJxByD2R9PlSL4B+80Ok1llhRligNcsA/fVE9/NPPoC/46h3g+bLVILnp2i0NJT+b i5JDl5Jyy0X8wAtk7KfhOrJKAw+fa69TsrXqwAHDqmkgzjB8+XCiWqb/z2FQ0L0oUnH8 HzYg== X-Gm-Message-State: APjAAAX4JGLbnb/zgEU3MSRiQDQmUfhcp2komIq1XLsOgp+R/P+ZAN4H VSdX00Bsfe3PbS6cTZFHw0I4Jydv7RQ= X-Google-Smtp-Source: APXvYqwj2eqALYh/e7Jzd6LUS8iB8p8RcP0KHc4R8tcLbEQDEjsk0yDSjKMwmo3qRRpaI5zljO6htQ== X-Received: by 2002:a63:6849:: with SMTP id d70mr15670892pgc.21.1556949208817; Fri, 03 May 2019 22:53:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 3 May 2019 22:52:51 -0700 Message-Id: <20190504055300.18426-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190504055300.18426-1-richard.henderson@linaro.org> References: <20190504055300.18426-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::435 Subject: [Qemu-devel] [PATCH v3 22/31] tcg/i386: Support vector absolute value X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.h | 2 +- tcg/i386/tcg-target.inc.c | 15 +++++++++++++++ 2 files changed, 16 insertions(+), 1 deletion(-) diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 7445f05885..66f16fbe3c 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -182,7 +182,7 @@ extern bool have_avx2; #define TCG_TARGET_HAS_orc_vec 0 #define TCG_TARGET_HAS_not_vec 0 #define TCG_TARGET_HAS_neg_vec 0 -#define TCG_TARGET_HAS_abs_vec 0 +#define TCG_TARGET_HAS_abs_vec 1 #define TCG_TARGET_HAS_shi_vec 1 #define TCG_TARGET_HAS_shs_vec 1 #define TCG_TARGET_HAS_shv_vec have_avx2 diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index 0ba1587da4..aafd01cb49 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -369,6 +369,9 @@ static inline int tcg_target_const_match(tcg_target_lon= g val, TCGType type, #define OPC_MOVSLQ (0x63 | P_REXW) #define OPC_MOVZBL (0xb6 | P_EXT) #define OPC_MOVZWL (0xb7 | P_EXT) +#define OPC_PABSB (0x1c | P_EXT38 | P_DATA16) +#define OPC_PABSW (0x1d | P_EXT38 | P_DATA16) +#define OPC_PABSD (0x1e | P_EXT38 | P_DATA16) #define OPC_PACKSSDW (0x6b | P_EXT | P_DATA16) #define OPC_PACKSSWB (0x63 | P_EXT | P_DATA16) #define OPC_PACKUSDW (0x2b | P_EXT38 | P_DATA16) @@ -2741,6 +2744,10 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, static int const sars_insn[4] =3D { OPC_UD2, OPC_PSRAW, OPC_PSRAD, OPC_UD2 }; + static int const abs_insn[4] =3D { + /* TODO: AVX512 adds support for MO_64. */ + OPC_PABSB, OPC_PABSW, OPC_PABSD, OPC_UD2 + }; =20 TCGType type =3D vecl + TCG_TYPE_V64; int insn, sub; @@ -2829,6 +2836,11 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, insn =3D OPC_PUNPCKLDQ; goto gen_simd; #endif + case INDEX_op_abs_vec: + insn =3D abs_insn[vece]; + a2 =3D a1; + a1 =3D 0; + goto gen_simd; gen_simd: tcg_debug_assert(insn !=3D OPC_UD2); if (type =3D=3D TCG_TYPE_V256) { @@ -3206,6 +3218,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) case INDEX_op_dup2_vec: #endif return &x_x_x; + case INDEX_op_abs_vec: case INDEX_op_dup_vec: case INDEX_op_shli_vec: case INDEX_op_shri_vec: @@ -3283,6 +3296,8 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, = unsigned vece) case INDEX_op_umin_vec: case INDEX_op_umax_vec: return vece <=3D MO_32 ? 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X-Received-From: 2607:f8b0:4864:20::543 Subject: [Qemu-devel] [PATCH v3 23/31] tcg/aarch64: Support vector absolute value X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.h | 2 +- tcg/aarch64/tcg-target.inc.c | 6 ++++++ 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index 21d06d928c..e43554c3c7 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -132,7 +132,7 @@ typedef enum { #define TCG_TARGET_HAS_orc_vec 1 #define TCG_TARGET_HAS_not_vec 1 #define TCG_TARGET_HAS_neg_vec 1 -#define TCG_TARGET_HAS_abs_vec 0 +#define TCG_TARGET_HAS_abs_vec 1 #define TCG_TARGET_HAS_shi_vec 1 #define TCG_TARGET_HAS_shs_vec 0 #define TCG_TARGET_HAS_shv_vec 1 diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c index 7d842cad47..5684b39e1f 100644 --- a/tcg/aarch64/tcg-target.inc.c +++ b/tcg/aarch64/tcg-target.inc.c @@ -552,6 +552,7 @@ typedef enum { I3617_CMGE0 =3D 0x2e208800, I3617_CMLE0 =3D 0x2e20a800, I3617_NOT =3D 0x2e205800, + I3617_ABS =3D 0x0e20b800, I3617_NEG =3D 0x2e20b800, =20 /* System instructions. */ @@ -2207,6 +2208,9 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode o= pc, case INDEX_op_neg_vec: tcg_out_insn(s, 3617, NEG, is_q, vece, a0, a1); break; + case INDEX_op_abs_vec: + tcg_out_insn(s, 3617, ABS, is_q, vece, a0, a1); + break; case INDEX_op_and_vec: tcg_out_insn(s, 3616, AND, is_q, 0, a0, a1, a2); break; @@ -2318,6 +2322,7 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, = unsigned vece) case INDEX_op_andc_vec: case INDEX_op_orc_vec: case INDEX_op_neg_vec: + case INDEX_op_abs_vec: case INDEX_op_not_vec: case INDEX_op_cmp_vec: case INDEX_op_shli_vec: @@ -2561,6 +2566,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) return &w_w_w; case INDEX_op_not_vec: case INDEX_op_neg_vec: + case INDEX_op_abs_vec: case INDEX_op_shli_vec: case INDEX_op_shri_vec: case INDEX_op_sari_vec: --=20 2.17.1 From nobody Sat May 4 13:31:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; 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X-Received-From: 2607:f8b0:4864:20::42b Subject: [Qemu-devel] [PATCH v3 24/31] target/arm: Use tcg_gen_abs_i64 and tcg_gen_gvec_abs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- target/arm/helper.h | 2 -- target/arm/neon_helper.c | 5 ----- target/arm/translate-a64.c | 41 +++++--------------------------------- target/arm/translate.c | 11 +++------- 4 files changed, 8 insertions(+), 51 deletions(-) diff --git a/target/arm/helper.h b/target/arm/helper.h index 50cb036378..132aa1682e 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -352,8 +352,6 @@ DEF_HELPER_2(neon_ceq_u8, i32, i32, i32) DEF_HELPER_2(neon_ceq_u16, i32, i32, i32) DEF_HELPER_2(neon_ceq_u32, i32, i32, i32) =20 -DEF_HELPER_1(neon_abs_s8, i32, i32) -DEF_HELPER_1(neon_abs_s16, i32, i32) DEF_HELPER_1(neon_clz_u8, i32, i32) DEF_HELPER_1(neon_clz_u16, i32, i32) DEF_HELPER_1(neon_cls_s8, i32, i32) diff --git a/target/arm/neon_helper.c b/target/arm/neon_helper.c index ed1c6fc41c..4259056723 100644 --- a/target/arm/neon_helper.c +++ b/target/arm/neon_helper.c @@ -1228,11 +1228,6 @@ NEON_VOP(ceq_u16, neon_u16, 2) NEON_VOP(ceq_u32, neon_u32, 1) #undef NEON_FN =20 -#define NEON_FN(dest, src, dummy) dest =3D (src < 0) ? -src : src -NEON_VOP1(abs_s8, neon_s8, 4) -NEON_VOP1(abs_s16, neon_s16, 2) -#undef NEON_FN - /* Count Leading Sign/Zero Bits. */ static inline int do_clz8(uint8_t x) { diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 9dcc5ff3a3..b7c5a928b4 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -9468,11 +9468,7 @@ static void handle_2misc_64(DisasContext *s, int opc= ode, bool u, if (u) { tcg_gen_neg_i64(tcg_rd, tcg_rn); } else { - TCGv_i64 tcg_zero =3D tcg_const_i64(0); - tcg_gen_neg_i64(tcg_rd, tcg_rn); - tcg_gen_movcond_i64(TCG_COND_GT, tcg_rd, tcg_rn, tcg_zero, - tcg_rn, tcg_rd); - tcg_temp_free_i64(tcg_zero); + tcg_gen_abs_i64(tcg_rd, tcg_rn); } break; case 0x2f: /* FABS */ @@ -12366,11 +12362,12 @@ static void disas_simd_two_reg_misc(DisasContext = *s, uint32_t insn) } break; case 0xb: - if (u) { /* NEG */ + if (u) { /* ABS, NEG */ gen_gvec_fn2(s, is_q, rd, rn, tcg_gen_gvec_neg, size); - return; + } else { + gen_gvec_fn2(s, is_q, rd, rn, tcg_gen_gvec_abs, size); } - break; + return; } =20 if (size =3D=3D 3) { @@ -12438,17 +12435,6 @@ static void disas_simd_two_reg_misc(DisasContext *= s, uint32_t insn) gen_helper_neon_qabs_s32(tcg_res, cpu_env, tcg_op); } break; - case 0xb: /* ABS, NEG */ - if (u) { - tcg_gen_neg_i32(tcg_res, tcg_op); - } else { - TCGv_i32 tcg_zero =3D tcg_const_i32(0); - tcg_gen_neg_i32(tcg_res, tcg_op); - tcg_gen_movcond_i32(TCG_COND_GT, tcg_res, tcg_op, - tcg_zero, tcg_op, tcg_res); - tcg_temp_free_i32(tcg_zero); - } - break; case 0x2f: /* FABS */ gen_helper_vfp_abss(tcg_res, tcg_op); break; @@ -12561,23 +12547,6 @@ static void disas_simd_two_reg_misc(DisasContext *= s, uint32_t insn) tcg_temp_free_i32(tcg_zero); break; } - case 0xb: /* ABS, NEG */ - if (u) { - TCGv_i32 tcg_zero =3D tcg_const_i32(0); - if (size) { - gen_helper_neon_sub_u16(tcg_res, tcg_zero, tcg= _op); - } else { - gen_helper_neon_sub_u8(tcg_res, tcg_zero, tcg_= op); - } - tcg_temp_free_i32(tcg_zero); - } else { - if (size) { - gen_helper_neon_abs_s16(tcg_res, tcg_op); - } else { - gen_helper_neon_abs_s8(tcg_res, tcg_op); - } - } - break; case 0x4: /* CLS, CLZ */ if (u) { if (size =3D=3D 0) { diff --git a/target/arm/translate.c b/target/arm/translate.c index b25781554f..dd053c80d6 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8120,6 +8120,9 @@ static int disas_neon_data_insn(DisasContext *s, uint= 32_t insn) case NEON_2RM_VNEG: tcg_gen_gvec_neg(size, rd_ofs, rm_ofs, vec_size, vec_s= ize); break; + case NEON_2RM_VABS: + tcg_gen_gvec_abs(size, rd_ofs, rm_ofs, vec_size, vec_s= ize); + break; =20 default: elementwise: @@ -8225,14 +8228,6 @@ static int disas_neon_data_insn(DisasContext *s, uin= t32_t insn) } tcg_temp_free_i32(tmp2); break; - case NEON_2RM_VABS: - switch(size) { - case 0: gen_helper_neon_abs_s8(tmp, tmp); brea= k; - case 1: gen_helper_neon_abs_s16(tmp, tmp); bre= ak; - case 2: tcg_gen_abs_i32(tmp, tmp); break; - default: abort(); - } - break; case NEON_2RM_VCGT0_F: { TCGv_ptr fpstatus =3D get_fpstatus_ptr(1); --=20 2.17.1 From nobody Sat May 4 13:31:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[97.113.189.189]) by smtp.gmail.com with ESMTPSA id 15sm6680423pfo.117.2019.05.03.22.53.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 03 May 2019 22:53:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=njZylfJYYv8BcxCOaRQsx2/xRladRXvgAJ8dZdaUUo4=; b=c68dW8uTjhOrYNSajL/NL7Ypw9kvNpq4F8rO8AJWJxD+JrnvY1VqEN8hyVyjVD4sJh oikgrddzh/mFpXvlnijlsDpjIXCvnPXqWkY0jySsVWG3QVcIyS4QWPzyoiaZG1LFUt7L 6YRxphKIkf8n/l9ovZFnn3xxV7RPp3+M6iGdNQG+TxcPAcLmvZTGEiSXUtCAvDJj0108 CgxHeocsbSWkQ55VyF5TzlzT3OdwDTtjnxJAEWJ5eL8BeOGkEx9/j1Y151gRNBBBpuSg HaiiVeT2h91h+5dqAnMPT1kiZ242b03Gs1qcjSKgeWEz3cmoEr9W1wuG7unB/h5h512K srDg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=njZylfJYYv8BcxCOaRQsx2/xRladRXvgAJ8dZdaUUo4=; b=bh3djOOEIF042BcY77XMJoCBpvOWRl5vTv48mr07o0swD9yUQRbyU2TLYGtUzG6xxd xmb1+c1aKMyjOPe6j0SI8B/SNfC3TodP/b9paWoZq1k8yZ5PENtp1naDRSjsQ1P6RRnJ UtqNn1VmWPiYySYGmm2S0ofpAHgCtcmwdy190IfgbkY+9tZhiyZIKoFdkdS1iDoH3FiO RC/9ReEPcLJ3lLEIZ94/mWjTkhV3VXzhLjnmKslCfrBf20gzSHHDse4pkV4BsTB7LmPg rTbpBXBL2iGlTTl53/QSii3DNjRjMt7noC/EYpGojhPuJ20u4v1wK6qw4J5kEWBCyThw 04uA== X-Gm-Message-State: APjAAAWK3N3OEG9g0NDnSQlqtTtA1yxLUi6fIyk5f2OAuKRJ4vgYdVzT 7y0zDCslFO6iWKlIIuyRwvgvBcRHgM4= X-Google-Smtp-Source: APXvYqzNjj0I3XArr18UmrbdCrRAWs6NBMqrAW3LsgmKhXQSPP8eHRfi6ZD9G78loQwVhxRfJmJq8Q== X-Received: by 2002:a63:5443:: with SMTP id e3mr15950418pgm.265.1556949212426; Fri, 03 May 2019 22:53:32 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 3 May 2019 22:52:54 -0700 Message-Id: <20190504055300.18426-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190504055300.18426-1-richard.henderson@linaro.org> References: <20190504055300.18426-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::443 Subject: [Qemu-devel] [PATCH v3 25/31] target/cris: Use tcg_gen_abs_tl X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: David Hildenbrand --- target/cris/translate.c | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/target/cris/translate.c b/target/cris/translate.c index b005a5c20e..31b40a57f9 100644 --- a/target/cris/translate.c +++ b/target/cris/translate.c @@ -1686,18 +1686,11 @@ static int dec_cmp_r(CPUCRISState *env, DisasContex= t *dc) =20 static int dec_abs_r(CPUCRISState *env, DisasContext *dc) { - TCGv t0; - LOG_DIS("abs $r%u, $r%u\n", dc->op1, dc->op2); cris_cc_mask(dc, CC_MASK_NZ); =20 - t0 =3D tcg_temp_new(); - tcg_gen_sari_tl(t0, cpu_R[dc->op1], 31); - tcg_gen_xor_tl(cpu_R[dc->op2], cpu_R[dc->op1], t0); - tcg_gen_sub_tl(cpu_R[dc->op2], cpu_R[dc->op2], t0); - tcg_temp_free(t0); - + tcg_gen_abs_tl(cpu_R[dc->op2], cpu_R[dc->op1]); cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op2], 4); return 2; --=20 2.17.1 From nobody Sat May 4 13:31:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1556950666; cv=none; d=zoho.com; s=zohoarc; b=j1LoZuSiHNx5ZbLXZqCYzzOUpCSLL/jD32JFiJm4gaMVxwyJaN2bU6tVyYpKP5+yFGEf1RilaQvIx2KWYKDWS9KeReUK9jSFt5nU8g4aAvhFgfvL2QFkuM2pFIFDSyUxD2KJvfCHc9GmlqlLsNPF5jmS5kfY+jNhiKBXvlYvD64= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1556950666; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=FH8HIUisgKxx/wO5rpgn7QNUU9WJqnDYvJ4xHC9+spw=; b=UbautXyuM9g6W5h/NfTB3L4UuldyKW6WQc/uRjEMtDr7LACYOlsaFv6hsQHMQRhtkkEboORU8fFmas75aj6vziGuuuBhBMZRui3RwgMWxO0BQnIhDvKFae06f6hI7A+tS25EmjQowSlWIxNKLzvp7GdvR+0nZMuETNhbo7OJmQg= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1556950666224824.2199413873799; Fri, 3 May 2019 23:17:46 -0700 (PDT) Received: from localhost ([127.0.0.1]:51959 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hMnzQ-0003yx-7h for importer@patchew.org; Sat, 04 May 2019 02:17:40 -0400 Received: from eggs.gnu.org ([209.51.188.92]:42045) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hMnc7-00086N-Tq for qemu-devel@nongnu.org; Sat, 04 May 2019 01:53:36 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hMnc7-0004Zs-0A for qemu-devel@nongnu.org; Sat, 04 May 2019 01:53:35 -0400 Received: from mail-pg1-x543.google.com ([2607:f8b0:4864:20::543]:39960) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hMnc6-0004ZR-NX for qemu-devel@nongnu.org; Sat, 04 May 2019 01:53:34 -0400 Received: by mail-pg1-x543.google.com with SMTP id d31so3761378pgl.7 for ; Fri, 03 May 2019 22:53:34 -0700 (PDT) Received: from localhost.localdomain (97-113-189-189.tukw.qwest.net. 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X-Received-From: 2607:f8b0:4864:20::543 Subject: [Qemu-devel] [PATCH v3 26/31] target/ppc: Use tcg_gen_abs_i32 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20190423102145.14812-2-f4bug@amsat.org> Signed-off-by: Richard Henderson --- target/ppc/translate/spe-impl.inc.c | 14 +------------- 1 file changed, 1 insertion(+), 13 deletions(-) diff --git a/target/ppc/translate/spe-impl.inc.c b/target/ppc/translate/spe= -impl.inc.c index 7ab0a29b5f..36b4d5654d 100644 --- a/target/ppc/translate/spe-impl.inc.c +++ b/target/ppc/translate/spe-impl.inc.c @@ -126,19 +126,7 @@ static inline void gen_##name(DisasContext *ctx) = \ tcg_temp_free_i32(t0); = \ } =20 -static inline void gen_op_evabs(TCGv_i32 ret, TCGv_i32 arg1) -{ - TCGLabel *l1 =3D gen_new_label(); - TCGLabel *l2 =3D gen_new_label(); - - tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1); - tcg_gen_neg_i32(ret, arg1); - tcg_gen_br(l2); - gen_set_label(l1); - tcg_gen_mov_i32(ret, arg1); - gen_set_label(l2); -} -GEN_SPEOP_ARITH1(evabs, gen_op_evabs); +GEN_SPEOP_ARITH1(evabs, tcg_gen_abs_i32); GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32); GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32); GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32); --=20 2.17.1 From nobody Sat May 4 13:31:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1556950370; cv=none; d=zoho.com; s=zohoarc; b=h3+Ynby1u2LjNRTT0UqT5xwniIo52NBL3PWHXVGqT/euBEsNi3KwpcKUG9NJn62g1uOcudTeJhKVkKKezi8xM5iSBD539j66tEt7hEZEmdy770wigP+b1ABdi2hF4D185dC+Eseu99ynZx1XVLhIjDnPqh69hrrgEoX6TW/gxJg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1556950370; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=sLhzMGGDR1ZhuOEjkMPl9rWAydAxNvaV/cqSFAgz/Lc=; b=P711oLZzARQefFtDWP/wDp3EFqtRx7OPBjTviiKQtzMUQLaCFKtjb+DIAgqNtQ545y+SCqVemWAWPbp/WfKxs41Q8rttNRmFWTe3I7ZFhpv2A91uU1FPLhbVPSBRFk9Oih7Xbb0anNo5mJJtaiZ/Nk4z3zx3C+CvNexCTcT7PdM= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1556950370265550.3711011219484; Fri, 3 May 2019 23:12:50 -0700 (PDT) Received: from localhost ([127.0.0.1]:51880 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hMnuh-0007sO-4F for importer@patchew.org; Sat, 04 May 2019 02:12:47 -0400 Received: from eggs.gnu.org ([209.51.188.92]:42060) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hMnc9-00087Z-0Z for qemu-devel@nongnu.org; Sat, 04 May 2019 01:53:38 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hMnc7-0004aJ-TA for qemu-devel@nongnu.org; Sat, 04 May 2019 01:53:36 -0400 Received: from mail-pf1-x441.google.com ([2607:f8b0:4864:20::441]:37245) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hMnc7-0004a0-Mm for qemu-devel@nongnu.org; Sat, 04 May 2019 01:53:35 -0400 Received: by mail-pf1-x441.google.com with SMTP id g3so3975798pfi.4 for ; Fri, 03 May 2019 22:53:35 -0700 (PDT) Received: from localhost.localdomain (97-113-189-189.tukw.qwest.net. [97.113.189.189]) by smtp.gmail.com with ESMTPSA id 15sm6680423pfo.117.2019.05.03.22.53.33 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 03 May 2019 22:53:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=sLhzMGGDR1ZhuOEjkMPl9rWAydAxNvaV/cqSFAgz/Lc=; b=OXbI95IVET/MEyrfHbeMzCG8LiGf9O1EJzXSaZK5vhQ7iImliEW3rJq787eWSlpcYy LKdbnv1wIEfTJc2pP1/DLLn9LKnem03MnmG6Q2lwMbp3Wg7sYr94sKGZtIAW1ypAB4D+ nLKUQG5CSVFkov65+/3/J273IbdinuJH+GZr14dzsfEzlrCodOcLUWb7QvJzcElNbObZ haFbfwiH87fDQHV9OeLo5SK2XqZgdEDjaPCKIf7lmJQd3B13hrtRrVz2espU+qHb4u5I RyVLpR9edov1lOC+V04Bp1oHPgHoRpm7Eaf2ZuAW5d6mDEozDjbhG3l3RVeaFoeUn6GR 8SFA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=sLhzMGGDR1ZhuOEjkMPl9rWAydAxNvaV/cqSFAgz/Lc=; b=ed38oUncH+1YXVb3kJz37U987wgDKSna+idCtjLWYeCzxvU233ZAhu2dES2VUtRan/ 4eWFZLB6MjqVfegq5mlVhTK9JjmLqngN5Ym7Ww19NXDWgIzsJLuxDC+WkOr7EfVbNcjS dRFxZWKzzwrh6kBl96k9qxUNWAsbnT4PComP9QoVQzrytqk03w3l6P+LbftRCjd062gl ZCrecWDZavdHVTYQJGJWXUHjRi0mzYgjX3P1j/NlhlP4pbjOdpIpev1xBjYYSC7DPink P5JeD3lC1nz4pRdxATPvtarSfCLD2/jxTYzr6FfN1xYrsn8gXgfcKIFSX0MDU6l2F3GH a7qg== X-Gm-Message-State: APjAAAWjt1HpGo3aQXauJ6TFlHHvOCYeE/uLBzBPgZw40EWn/grRCGcV UnhDn+nqP2WvXuvZNnY/lZUYUM0irDY= X-Google-Smtp-Source: APXvYqwhQmIm2stQ00CWajbJBWq4D1Mfv4XqJYjxBRG42M67y4IdT+tq3pRWJIMSNwSxcdkT9LKleA== X-Received: by 2002:a65:528b:: with SMTP id y11mr5097163pgp.341.1556949214547; Fri, 03 May 2019 22:53:34 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 3 May 2019 22:52:56 -0700 Message-Id: <20190504055300.18426-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190504055300.18426-1-richard.henderson@linaro.org> References: <20190504055300.18426-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::441 Subject: [Qemu-devel] [PATCH v3 27/31] target/ppc: Use tcg_gen_abs_tl X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/ppc/translate.c | 68 +++++++++++++++--------------------------- 1 file changed, 24 insertions(+), 44 deletions(-) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 8d08625c33..b5217f632f 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -5075,40 +5075,26 @@ static void gen_ecowx(DisasContext *ctx) /* abs - abs. */ static void gen_abs(DisasContext *ctx) { - TCGLabel *l1 =3D gen_new_label(); - TCGLabel *l2 =3D gen_new_label(); - tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1); - tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); - tcg_gen_br(l2); - gen_set_label(l1); - tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); - gen_set_label(l2); + TCGv d =3D cpu_gpr[rD(ctx->opcode)]; + TCGv a =3D cpu_gpr[rA(ctx->opcode)]; + + tcg_gen_abs_tl(d, a); if (unlikely(Rc(ctx->opcode) !=3D 0)) { - gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); + gen_set_Rc0(ctx, d); } } =20 /* abso - abso. */ static void gen_abso(DisasContext *ctx) { - TCGLabel *l1 =3D gen_new_label(); - TCGLabel *l2 =3D gen_new_label(); - TCGLabel *l3 =3D gen_new_label(); - /* Start with XER OV disabled, the most likely case */ - tcg_gen_movi_tl(cpu_ov, 0); - tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2); - tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, = l1); - tcg_gen_movi_tl(cpu_ov, 1); - tcg_gen_movi_tl(cpu_so, 1); - tcg_gen_br(l2); - gen_set_label(l1); - tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); - tcg_gen_br(l3); - gen_set_label(l2); - tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); - gen_set_label(l3); + TCGv d =3D cpu_gpr[rD(ctx->opcode)]; + TCGv a =3D cpu_gpr[rA(ctx->opcode)]; + + tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_ov, a, 0x80000000); + tcg_gen_abs_tl(d, a); + tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); if (unlikely(Rc(ctx->opcode) !=3D 0)) { - gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); + gen_set_Rc0(ctx, d); } } =20 @@ -5344,34 +5330,28 @@ static void gen_mulo(DisasContext *ctx) /* nabs - nabs. */ static void gen_nabs(DisasContext *ctx) { - TCGLabel *l1 =3D gen_new_label(); - TCGLabel *l2 =3D gen_new_label(); - tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1); - tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); - tcg_gen_br(l2); - gen_set_label(l1); - tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); - gen_set_label(l2); + TCGv d =3D cpu_gpr[rD(ctx->opcode)]; + TCGv a =3D cpu_gpr[rA(ctx->opcode)]; + + tcg_gen_abs_tl(d, a); + tcg_gen_neg_tl(d, d); if (unlikely(Rc(ctx->opcode) !=3D 0)) { - gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); + gen_set_Rc0(ctx, d); } } =20 /* nabso - nabso. */ static void gen_nabso(DisasContext *ctx) { - TCGLabel *l1 =3D gen_new_label(); - TCGLabel *l2 =3D gen_new_label(); - tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1); - tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); - tcg_gen_br(l2); - gen_set_label(l1); - tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); - gen_set_label(l2); + TCGv d =3D cpu_gpr[rD(ctx->opcode)]; + TCGv a =3D cpu_gpr[rA(ctx->opcode)]; + + tcg_gen_abs_tl(d, a); + tcg_gen_neg_tl(d, d); /* nabs never overflows */ tcg_gen_movi_tl(cpu_ov, 0); if (unlikely(Rc(ctx->opcode) !=3D 0)) { - gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); + gen_set_Rc0(ctx, d); } } =20 --=20 2.17.1 From nobody Sat May 4 13:31:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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X-Received-From: 2607:f8b0:4864:20::543 Subject: [Qemu-devel] [PATCH v3 28/31] target/s390x: Use tcg_gen_abs_i64 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: David Hildenbrand Signed-off-by: Richard Henderson --- target/s390x/translate.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/target/s390x/translate.c b/target/s390x/translate.c index d4951836ad..e8e8a79b7d 100644 --- a/target/s390x/translate.c +++ b/target/s390x/translate.c @@ -1407,13 +1407,7 @@ static DisasJumpType help_branch(DisasContext *s, Di= sasCompare *c, =20 static DisasJumpType op_abs(DisasContext *s, DisasOps *o) { - TCGv_i64 z, n; - z =3D tcg_const_i64(0); - n =3D tcg_temp_new_i64(); - tcg_gen_neg_i64(n, o->in2); - tcg_gen_movcond_i64(TCG_COND_LT, o->out, o->in2, z, n, o->in2); - tcg_temp_free_i64(n); - tcg_temp_free_i64(z); + tcg_gen_abs_i64(o->out, o->in2); return DISAS_NEXT; } =20 --=20 2.17.1 From nobody Sat May 4 13:31:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1556950826; cv=none; d=zoho.com; s=zohoarc; b=bcYcveAaBa9OGEilabxM39Mom36EkBC2MhfkZ5HQC8mRJykrrMlYcdVtB87A1DlyHxn/LVylgnYFDCwzJMhA6KDa+5F94vhjvrHMOTXYRi1dICQHN/RZb+Ht3zWFrko6JZq/SxqdCPTwPRIIS3YbkWjSQtFPwUZThmnE1xIqEpI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1556950826; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=NPRvgVGg8Y/3Ni/kBR6Hw8ovXKBKiDD4+leXLS3F/ik=; b=NIRKZtC99nBfs+33hNIxhojUuL4eRHkGGJrXUGG+urvSOmMvaYJCfROJSlhdU212m6Sb599ONZ02cL49+A2H8eUzl8V+QL4/6VXWl07d8J17KW+pur57gSx03UhI79U/FMlrJAlNYikpcAjeBF/i9c1mHKCpwwYl5c1KvHN9iOA= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1556950826357396.8138304074904; Fri, 3 May 2019 23:20:26 -0700 (PDT) Received: from localhost ([127.0.0.1]:51971 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hMo20-0005MF-8v for importer@patchew.org; Sat, 04 May 2019 02:20:20 -0400 Received: from eggs.gnu.org ([209.51.188.92]:42110) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hMncB-0008AS-Up for qemu-devel@nongnu.org; Sat, 04 May 2019 01:53:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hMncA-0004fT-NT for qemu-devel@nongnu.org; Sat, 04 May 2019 01:53:39 -0400 Received: from mail-pg1-x535.google.com ([2607:f8b0:4864:20::535]:35225) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hMncA-0004eD-HR for qemu-devel@nongnu.org; Sat, 04 May 2019 01:53:38 -0400 Received: by mail-pg1-x535.google.com with SMTP id h1so3773918pgs.2 for ; Fri, 03 May 2019 22:53:38 -0700 (PDT) Received: from localhost.localdomain (97-113-189-189.tukw.qwest.net. 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X-Received-From: 2607:f8b0:4864:20::535 Subject: [Qemu-devel] [PATCH v3 29/31] target/tricore: Use tcg_gen_abs_tl X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Bastian Koppelmann Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20190423102145.14812-3-f4bug@amsat.org> Signed-off-by: Richard Henderson --- target/tricore/translate.c | 27 +++++---------------------- 1 file changed, 5 insertions(+), 22 deletions(-) diff --git a/target/tricore/translate.c b/target/tricore/translate.c index 8f6416144e..06c4485e55 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -2415,11 +2415,7 @@ gen_msubadr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3= , uint32_t n, uint32_t mode) =20 static inline void gen_abs(TCGv ret, TCGv r1) { - TCGv temp =3D tcg_temp_new(); - TCGv t0 =3D tcg_const_i32(0); - - tcg_gen_neg_tl(temp, r1); - tcg_gen_movcond_tl(TCG_COND_GE, ret, r1, t0, r1, temp); + tcg_gen_abs_tl(ret, r1); /* overflow can only happen, if r1 =3D 0x80000000 */ tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, r1, 0x80000000); tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); @@ -2430,9 +2426,6 @@ static inline void gen_abs(TCGv ret, TCGv r1) tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV); /* calc SAV bit */ tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); - - tcg_temp_free(temp); - tcg_temp_free(t0); } =20 static inline void gen_absdif(TCGv ret, TCGv r1, TCGv r2) @@ -6617,13 +6610,8 @@ static void decode_rr_divide(CPUTriCoreState *env, D= isasContext *ctx) tcg_gen_movi_tl(cpu_PSW_AV, 0); if (!tricore_feature(env, TRICORE_FEATURE_131)) { /* overflow =3D (abs(D[r3+1]) >=3D abs(D[r2])) */ - tcg_gen_neg_tl(temp, temp3); - /* use cpu_PSW_AV to compare against 0 */ - tcg_gen_movcond_tl(TCG_COND_LT, temp, temp3, cpu_PSW_AV, - temp, temp3); - tcg_gen_neg_tl(temp2, cpu_gpr_d[r2]); - tcg_gen_movcond_tl(TCG_COND_LT, temp2, cpu_gpr_d[r2], cpu_PSW_= AV, - temp2, cpu_gpr_d[r2]); + tcg_gen_abs_tl(temp, temp3); + tcg_gen_abs_tl(temp2, cpu_gpr_d[r2]); tcg_gen_setcond_tl(TCG_COND_GE, cpu_PSW_V, temp, temp2); } else { /* overflow =3D (D[b] =3D=3D 0) */ @@ -6655,13 +6643,8 @@ static void decode_rr_divide(CPUTriCoreState *env, D= isasContext *ctx) tcg_gen_movi_tl(cpu_PSW_AV, 0); if (!tricore_feature(env, TRICORE_FEATURE_131)) { /* overflow =3D (abs(D[r3+1]) >=3D abs(D[r2])) */ - tcg_gen_neg_tl(temp, temp3); - /* use cpu_PSW_AV to compare against 0 */ - tcg_gen_movcond_tl(TCG_COND_LT, temp, temp3, cpu_PSW_AV, - temp, temp3); - tcg_gen_neg_tl(temp2, cpu_gpr_d[r2]); - tcg_gen_movcond_tl(TCG_COND_LT, temp2, cpu_gpr_d[r2], cpu_PSW_= AV, - temp2, cpu_gpr_d[r2]); + tcg_gen_abs_tl(temp, temp3); + tcg_gen_abs_tl(temp2, cpu_gpr_d[r2]); tcg_gen_setcond_tl(TCG_COND_GE, cpu_PSW_V, temp, temp2); } else { /* overflow =3D (D[b] =3D=3D 0) */ --=20 2.17.1 From nobody Sat May 4 13:31:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[97.113.189.189]) by smtp.gmail.com with ESMTPSA id 15sm6680423pfo.117.2019.05.03.22.53.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 03 May 2019 22:53:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=noj71OX2nBmtjQYQqqpKzc/I+BY/kKSngSA5N+1PwXo=; b=f10gAB5VruJnZW4D3xDGE4DyPtMaj1mtYWNggF1S3KEb1aq5nyVdBqBsGu8Un1P0XS 7MzyGe7FkYoU69kLTfL/iP3fMsX0ReTrpKF5fFQtim63X8M4uKoFgT1F/0zJ6OB25iMb iN73RGMrMgDqD/gdHnjAtm6caZrnAbf18VdwqBRO9zMUowKbraaY019YLWITgsStBN1o SXpzSFhd+X2DKjv2vO/FFo5c1i3/6JLeI3F7+R2yntnvRZNY2r0JfyYEuAnGLYcJAKH4 KQ34SmpNqrU3Zr6JA6vcdXNcDQ9AHomA1bk562G5jelWCRU9I6LWkdKh8POb17GNelU+ OTTQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=noj71OX2nBmtjQYQqqpKzc/I+BY/kKSngSA5N+1PwXo=; b=I/PxDaBWBQ++I1hl7AEjYWGAVuglo2D5hi9F+fvC/ZVfJenNwGLoeCC3Bj2BtlGlXL TwwKopVRSn0xep5eAx4LhQae6OCH+8zJZzNGRUB1j3zcnrkHC7npw1hkeNGJwSNBA2XX h+VsKk/CD2Sdzu51w+MUUbH2yR9Pyr3Aeu87pA8yYX8XdAhUQFHCek0/rJ4y85QOmS3s OzrjJChur7GN/Iw06YZrvbm8084RyINUV2nWovsrPt86tHDfALpaFOd3exrbu3hp++OG 1aPHXpqLb3KXmXZKPlZtRaUA1Vj7GvkC3rWml4jDQFNuTNC9Y4Qzg/yJEKWPineGwQln j2iw== X-Gm-Message-State: APjAAAWIJWG8/Xj8VLQC6adcc5nnyLheEode1mqpKvA4+cnNf7IRcoeh G+7HRzZ7ZMiuiNIrR4ZUEz1qzQHNXOc= X-Google-Smtp-Source: APXvYqx6jhL7i1+WbDlLV+qfPO2XKKJ+qXpBCapixxI0xnp7D4kc2HVg9dPgo9HwKoIF1DsHlhGoaQ== X-Received: by 2002:a65:584f:: with SMTP id s15mr12608825pgr.171.1556949218632; Fri, 03 May 2019 22:53:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 3 May 2019 22:52:59 -0700 Message-Id: <20190504055300.18426-31-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190504055300.18426-1-richard.henderson@linaro.org> References: <20190504055300.18426-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::544 Subject: [Qemu-devel] [PATCH v3 30/31] target/xtensa: Use tcg_gen_abs_i32 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Acked-by: Max Filippov Signed-off-by: Richard Henderson --- target/xtensa/translate.c | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index 301c8e3161..b063fa85f2 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -1709,14 +1709,7 @@ void restore_state_to_opc(CPUXtensaState *env, Trans= lationBlock *tb, static void translate_abs(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - TCGv_i32 zero =3D tcg_const_i32(0); - TCGv_i32 neg =3D tcg_temp_new_i32(); - - tcg_gen_neg_i32(neg, arg[1].in); - tcg_gen_movcond_i32(TCG_COND_GE, arg[0].out, - arg[1].in, zero, arg[1].in, neg); - tcg_temp_free(neg); - tcg_temp_free(zero); + tcg_gen_abs_i32(arg[0].out, arg[1].in); } =20 static void translate_add(DisasContext *dc, const OpcodeArg arg[], --=20 2.17.1 From nobody Sat May 4 13:31:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1556950908; cv=none; d=zoho.com; s=zohoarc; b=AawUKlmEXLASvEieQ4NI8eZPXPA9Cv+3CqfBU4fxKJuikQozVk0wgtVUVLIlkdHQZrumvflYxCjIal4KMipmRCXa9ULtz/60ia+dTRVlw/+7lABOpkK9uPXvkAStwH4j0ji5JSzyEt9ah7dqcqUeYoRPoziCOFVE+97snEkIu6Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1556950908; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=tIygHdppWS7z7SV8q8qHfD/88HKRxXbhxr5Q11UfKw4=; b=JDR9h0X27BfzugqrXJntn4Arfqlgdmhns6Cj+1Tdlkwf+OpHthkT73HaEDdqyyFhdCfP24ti+s0+P+7PrXWlvl0+JY5m2fq+WyUGyMzMaXhWJ1LOr001coZumJ3EZt5nhsXiNvq5bAkHWxUTnSxG/9CFPjkQ/2ShIII3BUlt3Ic= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 155695090815126.19423036805415; Fri, 3 May 2019 23:21:48 -0700 (PDT) Received: from localhost ([127.0.0.1]:52010 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hMo3K-0006qU-4i for importer@patchew.org; Sat, 04 May 2019 02:21:42 -0400 Received: from eggs.gnu.org ([209.51.188.92]:42154) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hMncE-0008AW-7u for qemu-devel@nongnu.org; Sat, 04 May 2019 01:53:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hMncD-0004ic-Bj for qemu-devel@nongnu.org; Sat, 04 May 2019 01:53:42 -0400 Received: from mail-pf1-x442.google.com ([2607:f8b0:4864:20::442]:36051) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hMncD-0004hs-5y for qemu-devel@nongnu.org; Sat, 04 May 2019 01:53:41 -0400 Received: by mail-pf1-x442.google.com with SMTP id v80so3978159pfa.3 for ; Fri, 03 May 2019 22:53:41 -0700 (PDT) Received: from localhost.localdomain (97-113-189-189.tukw.qwest.net. [97.113.189.189]) by smtp.gmail.com with ESMTPSA id 15sm6680423pfo.117.2019.05.03.22.53.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 03 May 2019 22:53:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=tIygHdppWS7z7SV8q8qHfD/88HKRxXbhxr5Q11UfKw4=; b=YzwRBDUYyI+7OdmU7QWnzA4M4wRPWQyiLe2O8wSSwfTw8LxY76XYNpjWlY9BkmfwU1 cLy8SeYKaaJIzj99LMDkUi+2QhQkffw6SupnlwL7pZ96OxuriY/geZ1S87s/tPdAryKl /n1EuKMP1I1VCJB6pvWAvBkruTHt3zd27pRnUXUmjQXMxbUW7q6afQn5FkK3WcVfajsY FjuchkqNJyuTvw+XXUV/CQVO5lMgJKiNUqgGNfA3eEoPxnOjD8Faf5K59yJFXNA8/G02 cuJ48NO6Zq3heGCYQ9yGGmkGdDi9jkuQGkEoVdnRUO01JIpu7ssk1NodBA2ygZq1ach7 mC4Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=tIygHdppWS7z7SV8q8qHfD/88HKRxXbhxr5Q11UfKw4=; b=bsis/6pV//bQ9hJzMNVMlUKytyaNpCP1W1tTGMcomNC5PGAbHHW3dYIWcEnvYgkvn2 KZud5AMT8gD7OuOW/Yjt0JZ1j0jV0L8Q+LUM4s2wcdgE2qLNy7JkDsxaegZuV1pjT+WM KuYC14T6bdFYqoe3fRNeo1RyBf5uNeDUbY0q1rQpPDQKkgfcpDbKphYCx3CFYyhsmr6c GdBhueU3oE40zgCwWJaWp2no69QKnKoibnWgy1dDmCCbD+1HzabgXbOpemv9/VXythrn z7Z+MyAOw65Si530YBYldm4dVEjTa6x8TpzZh1A2ERhZO8WwoQLBnJVj0jeqpXFHrW37 4idA== X-Gm-Message-State: APjAAAUqLxzIVvVF2VNbBND/d0Jj+Ko+iLuIFbyNNJamwTbkLfrOO+5B 83sq+KSPG5g5lBrVhIEASB7AMVergN0= X-Google-Smtp-Source: APXvYqxh19wuvR6rP7psaInMqUXBHZgKd6YuAJ9tXLJzRzhl9Q0RkI1LvKeZQvS8Sq8UHN0D+HCrxw== X-Received: by 2002:a63:e004:: with SMTP id e4mr16248223pgh.344.1556949219880; Fri, 03 May 2019 22:53:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 3 May 2019 22:53:00 -0700 Message-Id: <20190504055300.18426-32-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190504055300.18426-1-richard.henderson@linaro.org> References: <20190504055300.18426-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH v3 31/31] tcg/aarch64: Do not advertise minmax for MO_64 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The min/max instructions are not available for 64-bit elements. Fixes: 93f332a50371 Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.inc.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c index 5684b39e1f..e13960711d 100644 --- a/tcg/aarch64/tcg-target.inc.c +++ b/tcg/aarch64/tcg-target.inc.c @@ -2332,16 +2332,16 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type= , unsigned vece) case INDEX_op_sssub_vec: case INDEX_op_usadd_vec: case INDEX_op_ussub_vec: - case INDEX_op_smax_vec: - case INDEX_op_smin_vec: - case INDEX_op_umax_vec: - case INDEX_op_umin_vec: case INDEX_op_shlv_vec: return 1; case INDEX_op_shrv_vec: case INDEX_op_sarv_vec: return -1; case INDEX_op_mul_vec: + case INDEX_op_smax_vec: + case INDEX_op_smin_vec: + case INDEX_op_umax_vec: + case INDEX_op_umin_vec: return vece < MO_64; =20 default: --=20 2.17.1