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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Date: Mon, 29 Apr 2019 18:00:17 +0100
Message-Id: <20190429170030.11323-30-peter.maydell@linaro.org>
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Subject: [Qemu-devel] [PULL 29/42] target/arm: Enable FPU for Cortex-M4 and
Cortex-M33
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Enable the FPU by default for the Cortex-M4 and Cortex-M33.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190416125744.27770-27-peter.maydell@linaro.org
---
target/arm/cpu.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 7deccda2404..a181fa8dc1a 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1493,8 +1493,12 @@ static void cortex_m4_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_M);
set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
+ set_feature(&cpu->env, ARM_FEATURE_VFP4);
cpu->midr =3D 0x410fc240; /* r0p0 */
cpu->pmsav7_dregion =3D 8;
+ cpu->isar.mvfr0 =3D 0x10110021;
+ cpu->isar.mvfr1 =3D 0x11000011;
+ cpu->isar.mvfr2 =3D 0x00000000;
cpu->id_pfr0 =3D 0x00000030;
cpu->id_pfr1 =3D 0x00000200;
cpu->id_dfr0 =3D 0x00100000;
@@ -1521,9 +1525,13 @@ static void cortex_m33_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
set_feature(&cpu->env, ARM_FEATURE_M_SECURITY);
set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
+ set_feature(&cpu->env, ARM_FEATURE_VFP4);
cpu->midr =3D 0x410fd213; /* r0p3 */
cpu->pmsav7_dregion =3D 16;
cpu->sau_sregion =3D 8;
+ cpu->isar.mvfr0 =3D 0x10110021;
+ cpu->isar.mvfr1 =3D 0x11000011;
+ cpu->isar.mvfr2 =3D 0x00000040;
cpu->id_pfr0 =3D 0x00000030;
cpu->id_pfr1 =3D 0x00000210;
cpu->id_dfr0 =3D 0x00200000;
--=20
2.20.1