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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Date: Mon, 29 Apr 2019 18:00:16 +0100
Message-Id: <20190429170030.11323-29-peter.maydell@linaro.org>
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Subject: [Qemu-devel] [PULL 28/42] target/arm: Implement VLLDM for v7M CPUs
with an FPU
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Implement the VLLDM instruction for v7M for the FPU present cas.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190416125744.27770-26-peter.maydell@linaro.org
---
target/arm/helper.h | 1 +
target/arm/helper.c | 54 ++++++++++++++++++++++++++++++++++++++++++
target/arm/translate.c | 2 +-
3 files changed, 56 insertions(+), 1 deletion(-)
diff --git a/target/arm/helper.h b/target/arm/helper.h
index 62051ae6d51..50cb036378b 100644
--- a/target/arm/helper.h
+++ b/target/arm/helper.h
@@ -72,6 +72,7 @@ DEF_HELPER_3(v7m_tt, i32, env, i32, i32)
DEF_HELPER_1(v7m_preserve_fp_state, void, env)
=20
DEF_HELPER_2(v7m_vlstm, void, env, i32)
+DEF_HELPER_2(v7m_vlldm, void, env, i32)
=20
DEF_HELPER_2(v8m_stackcheck, void, env, i32)
=20
diff --git a/target/arm/helper.c b/target/arm/helper.c
index b821037c3b6..81a92ab4911 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -7390,6 +7390,12 @@ void HELPER(v7m_vlstm)(CPUARMState *env, uint32_t fp=
tr)
g_assert_not_reached();
}
=20
+void HELPER(v7m_vlldm)(CPUARMState *env, uint32_t fptr)
+{
+ /* translate.c should never generate calls here in user-only mode */
+ g_assert_not_reached();
+}
+
uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op)
{
/* The TT instructions can be used by unprivileged code, but in
@@ -8474,6 +8480,54 @@ void HELPER(v7m_vlstm)(CPUARMState *env, uint32_t fp=
tr)
env->v7m.control[M_REG_S] &=3D ~R_V7M_CONTROL_FPCA_MASK;
}
=20
+void HELPER(v7m_vlldm)(CPUARMState *env, uint32_t fptr)
+{
+ /* fptr is the value of Rn, the frame pointer we load the FP regs from=
*/
+ assert(env->v7m.secure);
+
+ if (!(env->v7m.control[M_REG_S] & R_V7M_CONTROL_SFPA_MASK)) {
+ return;
+ }
+
+ /* Check access to the coprocessor is permitted */
+ if (!v7m_cpacr_pass(env, true, arm_current_el(env) !=3D 0)) {
+ raise_exception_ra(env, EXCP_NOCP, 0, 1, GETPC());
+ }
+
+ if (env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_LSPACT_MASK) {
+ /* State in FP is still valid */
+ env->v7m.fpccr[M_REG_S] &=3D ~R_V7M_FPCCR_LSPACT_MASK;
+ } else {
+ bool ts =3D env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_TS_MASK;
+ int i;
+ uint32_t fpscr;
+
+ if (fptr & 7) {
+ raise_exception_ra(env, EXCP_UNALIGNED, 0, 1, GETPC());
+ }
+
+ for (i =3D 0; i < (ts ? 32 : 16); i +=3D 2) {
+ uint32_t slo, shi;
+ uint64_t dn;
+ uint32_t faddr =3D fptr + 4 * i;
+
+ if (i >=3D 16) {
+ faddr +=3D 8; /* skip the slot for the FPSCR */
+ }
+
+ slo =3D cpu_ldl_data(env, faddr);
+ shi =3D cpu_ldl_data(env, faddr + 4);
+
+ dn =3D (uint64_t) shi << 32 | slo;
+ *aa32_vfp_dreg(env, i / 2) =3D dn;
+ }
+ fpscr =3D cpu_ldl_data(env, fptr + 0x40);
+ vfp_set_fpscr(env, fpscr);
+ }
+
+ env->v7m.control[M_REG_S] |=3D R_V7M_CONTROL_FPCA_MASK;
+}
+
static bool v7m_push_stack(ARMCPU *cpu)
{
/* Do the "set up stack frame" part of exception entry,
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 99b38dd5f2b..10bc53f91c6 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -11823,7 +11823,7 @@ static void disas_thumb2_insn(DisasContext *s, uint=
32_t insn)
TCGv_i32 fptr =3D load_reg(s, rn);
=20
if (extract32(insn, 20, 1)) {
- /* VLLDM */
+ gen_helper_v7m_vlldm(cpu_env, fptr);
} else {
gen_helper_v7m_vlstm(cpu_env, fptr);
}
--=20
2.20.1