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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Date: Mon, 29 Apr 2019 18:00:13 +0100
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Subject: [Qemu-devel] [PULL 25/42] target/arm: Add lazy-FP-stacking support
to v7m_stack_write()
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Pushing registers to the stack for v7M needs to handle three cases:
* the "normal" case where we pend exceptions
* an "ignore faults" case where we set FSR bits but
do not pend exceptions (this is used when we are
handling some kinds of derived exception on exception entry)
* a "lazy FP stacking" case, where different FSR bits
are set and the exception is pended differently
Implement this by changing the existing flag argument that
tells us whether to ignore faults or not into an enum that
specifies which of the 3 modes we should handle.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190416125744.27770-23-peter.maydell@linaro.org
---
target/arm/helper.c | 118 +++++++++++++++++++++++++++++---------------
1 file changed, 79 insertions(+), 39 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 1ed5f1a2513..41531390853 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -7575,8 +7575,18 @@ static bool v7m_cpacr_pass(CPUARMState *env, bool is=
_secure, bool is_priv)
}
}
=20
+/*
+ * What kind of stack write are we doing? This affects how exceptions
+ * generated during the stacking are treated.
+ */
+typedef enum StackingMode {
+ STACK_NORMAL,
+ STACK_IGNFAULTS,
+ STACK_LAZYFP,
+} StackingMode;
+
static bool v7m_stack_write(ARMCPU *cpu, uint32_t addr, uint32_t value,
- ARMMMUIdx mmu_idx, bool ignfault)
+ ARMMMUIdx mmu_idx, StackingMode mode)
{
CPUState *cs =3D CPU(cpu);
CPUARMState *env =3D &cpu->env;
@@ -7594,15 +7604,31 @@ static bool v7m_stack_write(ARMCPU *cpu, uint32_t a=
ddr, uint32_t value,
&attrs, &prot, &page_size, &fi, NULL)) {
/* MPU/SAU lookup failed */
if (fi.type =3D=3D ARMFault_QEMU_SFault) {
- qemu_log_mask(CPU_LOG_INT,
- "...SecureFault with SFSR.AUVIOL during stacking=
\n");
- env->v7m.sfsr |=3D R_V7M_SFSR_AUVIOL_MASK | R_V7M_SFSR_SFARVAL=
ID_MASK;
+ if (mode =3D=3D STACK_LAZYFP) {
+ qemu_log_mask(CPU_LOG_INT,
+ "...SecureFault with SFSR.LSPERR "
+ "during lazy stacking\n");
+ env->v7m.sfsr |=3D R_V7M_SFSR_LSPERR_MASK;
+ } else {
+ qemu_log_mask(CPU_LOG_INT,
+ "...SecureFault with SFSR.AUVIOL "
+ "during stacking\n");
+ env->v7m.sfsr |=3D R_V7M_SFSR_AUVIOL_MASK;
+ }
+ env->v7m.sfsr |=3D R_V7M_SFSR_SFARVALID_MASK;
env->v7m.sfar =3D addr;
exc =3D ARMV7M_EXCP_SECURE;
exc_secure =3D false;
} else {
- qemu_log_mask(CPU_LOG_INT, "...MemManageFault with CFSR.MSTKER=
R\n");
- env->v7m.cfsr[secure] |=3D R_V7M_CFSR_MSTKERR_MASK;
+ if (mode =3D=3D STACK_LAZYFP) {
+ qemu_log_mask(CPU_LOG_INT,
+ "...MemManageFault with CFSR.MLSPERR\n");
+ env->v7m.cfsr[secure] |=3D R_V7M_CFSR_MLSPERR_MASK;
+ } else {
+ qemu_log_mask(CPU_LOG_INT,
+ "...MemManageFault with CFSR.MSTKERR\n");
+ env->v7m.cfsr[secure] |=3D R_V7M_CFSR_MSTKERR_MASK;
+ }
exc =3D ARMV7M_EXCP_MEM;
exc_secure =3D secure;
}
@@ -7612,8 +7638,13 @@ static bool v7m_stack_write(ARMCPU *cpu, uint32_t ad=
dr, uint32_t value,
attrs, &txres);
if (txres !=3D MEMTX_OK) {
/* BusFault trying to write the data */
- qemu_log_mask(CPU_LOG_INT, "...BusFault with BFSR.STKERR\n");
- env->v7m.cfsr[M_REG_NS] |=3D R_V7M_CFSR_STKERR_MASK;
+ if (mode =3D=3D STACK_LAZYFP) {
+ qemu_log_mask(CPU_LOG_INT, "...BusFault with BFSR.LSPERR\n");
+ env->v7m.cfsr[M_REG_NS] |=3D R_V7M_CFSR_LSPERR_MASK;
+ } else {
+ qemu_log_mask(CPU_LOG_INT, "...BusFault with BFSR.STKERR\n");
+ env->v7m.cfsr[M_REG_NS] |=3D R_V7M_CFSR_STKERR_MASK;
+ }
exc =3D ARMV7M_EXCP_BUS;
exc_secure =3D false;
goto pend_fault;
@@ -7628,11 +7659,19 @@ pend_fault:
* later if we have two derived exceptions.
* The only case when we must not pend the exception but instead
* throw it away is if we are doing the push of the callee registers
- * and we've already generated a derived exception. Even in this
- * case we will still update the fault status registers.
+ * and we've already generated a derived exception (this is indicated
+ * by the caller passing STACK_IGNFAULTS). Even in this case we will
+ * still update the fault status registers.
*/
- if (!ignfault) {
+ switch (mode) {
+ case STACK_NORMAL:
armv7m_nvic_set_pending_derived(env->nvic, exc, exc_secure);
+ break;
+ case STACK_LAZYFP:
+ armv7m_nvic_set_pending_lazyfp(env->nvic, exc, exc_secure);
+ break;
+ case STACK_IGNFAULTS:
+ break;
}
return false;
}
@@ -8009,6 +8048,7 @@ static bool v7m_push_callee_stack(ARMCPU *cpu, uint32=
_t lr, bool dotailchain,
uint32_t limit;
bool want_psp;
uint32_t sig;
+ StackingMode smode =3D ignore_faults ? STACK_IGNFAULTS : STACK_NORMAL;
=20
if (dotailchain) {
bool mode =3D lr & R_V7M_EXCRET_MODE_MASK;
@@ -8052,23 +8092,15 @@ static bool v7m_push_callee_stack(ARMCPU *cpu, uint=
32_t lr, bool dotailchain,
*/
sig =3D v7m_integrity_sig(env, lr);
stacked_ok =3D
- v7m_stack_write(cpu, frameptr, sig, mmu_idx, ignore_faults) &&
- v7m_stack_write(cpu, frameptr + 0x8, env->regs[4], mmu_idx,
- ignore_faults) &&
- v7m_stack_write(cpu, frameptr + 0xc, env->regs[5], mmu_idx,
- ignore_faults) &&
- v7m_stack_write(cpu, frameptr + 0x10, env->regs[6], mmu_idx,
- ignore_faults) &&
- v7m_stack_write(cpu, frameptr + 0x14, env->regs[7], mmu_idx,
- ignore_faults) &&
- v7m_stack_write(cpu, frameptr + 0x18, env->regs[8], mmu_idx,
- ignore_faults) &&
- v7m_stack_write(cpu, frameptr + 0x1c, env->regs[9], mmu_idx,
- ignore_faults) &&
- v7m_stack_write(cpu, frameptr + 0x20, env->regs[10], mmu_idx,
- ignore_faults) &&
- v7m_stack_write(cpu, frameptr + 0x24, env->regs[11], mmu_idx,
- ignore_faults);
+ v7m_stack_write(cpu, frameptr, sig, mmu_idx, smode) &&
+ v7m_stack_write(cpu, frameptr + 0x8, env->regs[4], mmu_idx, smode)=
&&
+ v7m_stack_write(cpu, frameptr + 0xc, env->regs[5], mmu_idx, smode)=
&&
+ v7m_stack_write(cpu, frameptr + 0x10, env->regs[6], mmu_idx, smode=
) &&
+ v7m_stack_write(cpu, frameptr + 0x14, env->regs[7], mmu_idx, smode=
) &&
+ v7m_stack_write(cpu, frameptr + 0x18, env->regs[8], mmu_idx, smode=
) &&
+ v7m_stack_write(cpu, frameptr + 0x1c, env->regs[9], mmu_idx, smode=
) &&
+ v7m_stack_write(cpu, frameptr + 0x20, env->regs[10], mmu_idx, smod=
e) &&
+ v7m_stack_write(cpu, frameptr + 0x24, env->regs[11], mmu_idx, smod=
e);
=20
/* Update SP regardless of whether any of the stack accesses failed. */
*frame_sp_p =3D frameptr;
@@ -8347,14 +8379,20 @@ static bool v7m_push_stack(ARMCPU *cpu)
* if it has higher priority).
*/
stacked_ok =3D stacked_ok &&
- v7m_stack_write(cpu, frameptr, env->regs[0], mmu_idx, false) &&
- v7m_stack_write(cpu, frameptr + 4, env->regs[1], mmu_idx, false) &&
- v7m_stack_write(cpu, frameptr + 8, env->regs[2], mmu_idx, false) &&
- v7m_stack_write(cpu, frameptr + 12, env->regs[3], mmu_idx, false) =
&&
- v7m_stack_write(cpu, frameptr + 16, env->regs[12], mmu_idx, false)=
&&
- v7m_stack_write(cpu, frameptr + 20, env->regs[14], mmu_idx, false)=
&&
- v7m_stack_write(cpu, frameptr + 24, env->regs[15], mmu_idx, false)=
&&
- v7m_stack_write(cpu, frameptr + 28, xpsr, mmu_idx, false);
+ v7m_stack_write(cpu, frameptr, env->regs[0], mmu_idx, STACK_NORMAL=
) &&
+ v7m_stack_write(cpu, frameptr + 4, env->regs[1],
+ mmu_idx, STACK_NORMAL) &&
+ v7m_stack_write(cpu, frameptr + 8, env->regs[2],
+ mmu_idx, STACK_NORMAL) &&
+ v7m_stack_write(cpu, frameptr + 12, env->regs[3],
+ mmu_idx, STACK_NORMAL) &&
+ v7m_stack_write(cpu, frameptr + 16, env->regs[12],
+ mmu_idx, STACK_NORMAL) &&
+ v7m_stack_write(cpu, frameptr + 20, env->regs[14],
+ mmu_idx, STACK_NORMAL) &&
+ v7m_stack_write(cpu, frameptr + 24, env->regs[15],
+ mmu_idx, STACK_NORMAL) &&
+ v7m_stack_write(cpu, frameptr + 28, xpsr, mmu_idx, STACK_NORMAL);
=20
if (env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK) {
/* FPU is active, try to save its registers */
@@ -8404,12 +8442,14 @@ static bool v7m_push_stack(ARMCPU *cpu)
faddr +=3D 8; /* skip the slot for the FPSCR */
}
stacked_ok =3D stacked_ok &&
- v7m_stack_write(cpu, faddr, slo, mmu_idx, false) &&
- v7m_stack_write(cpu, faddr + 4, shi, mmu_idx, fals=
e);
+ v7m_stack_write(cpu, faddr, slo,
+ mmu_idx, STACK_NORMAL) &&
+ v7m_stack_write(cpu, faddr + 4, shi,
+ mmu_idx, STACK_NORMAL);
}
stacked_ok =3D stacked_ok &&
v7m_stack_write(cpu, frameptr + 0x60,
- vfp_get_fpscr(env), mmu_idx, false);
+ vfp_get_fpscr(env), mmu_idx, STACK_NOR=
MAL);
if (cpacr_pass) {
for (i =3D 0; i < ((framesize =3D=3D 0xa8) ? 32 : 16);=
i +=3D 2) {
*aa32_vfp_dreg(env, i / 2) =3D 0;
--=20
2.20.1