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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Date: Mon, 29 Apr 2019 18:00:11 +0100
Message-Id: <20190429170030.11323-24-peter.maydell@linaro.org>
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Subject: [Qemu-devel] [PULL 23/42] target/arm: New helper function
arm_v7m_mmu_idx_all()
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Add a new helper function which returns the MMU index to use
for v7M, where the caller specifies all of the security
state, privilege level and whether the execution priority
is negative, and reimplement the existing
arm_v7m_mmu_idx_for_secstate_and_priv() in terms of it.
We are going to need this for the lazy-FP-stacking code.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190416125744.27770-21-peter.maydell@linaro.org
---
target/arm/cpu.h | 7 +++++++
target/arm/helper.c | 14 +++++++++++---
2 files changed, 18 insertions(+), 3 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index d4996a4d204..920cf367020 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -2911,6 +2911,13 @@ static inline int arm_mmu_idx_to_el(ARMMMUIdx mmu_id=
x)
}
}
=20
+/*
+ * Return the MMU index for a v7M CPU with all relevant information
+ * manually specified.
+ */
+ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env,
+ bool secstate, bool priv, bool negpri);
+
/* Return the MMU index for a v7M CPU in the specified security and
* privilege state.
*/
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 84e3790a9de..1ed5f1a2513 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -13230,8 +13230,8 @@ int fp_exception_el(CPUARMState *env, int cur_el)
return 0;
}
=20
-ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env,
- bool secstate, bool priv)
+ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env,
+ bool secstate, bool priv, bool negpri)
{
ARMMMUIdx mmu_idx =3D ARM_MMU_IDX_M;
=20
@@ -13239,7 +13239,7 @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPU=
ARMState *env,
mmu_idx |=3D ARM_MMU_IDX_M_PRIV;
}
=20
- if (armv7m_nvic_neg_prio_requested(env->nvic, secstate)) {
+ if (negpri) {
mmu_idx |=3D ARM_MMU_IDX_M_NEGPRI;
}
=20
@@ -13250,6 +13250,14 @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CP=
UARMState *env,
return mmu_idx;
}
=20
+ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env,
+ bool secstate, bool priv)
+{
+ bool negpri =3D armv7m_nvic_neg_prio_requested(env->nvic, secstate);
+
+ return arm_v7m_mmu_idx_all(env, secstate, priv, negpri);
+}
+
/* Return the MMU index for a v7M CPU in the specified security state */
ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate)
{
--=20
2.20.1