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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Date: Mon, 29 Apr 2019 18:00:10 +0100
Message-Id: <20190429170030.11323-23-peter.maydell@linaro.org>
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Subject: [Qemu-devel] [PULL 22/42] target/arm: Activate M-profile floating
point context when FPCCR.ASPEN is set
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The M-profile FPCCR.ASPEN bit indicates that automatic floating-point
context preservation is enabled. Before executing any floating-point
instruction, if FPCCR.ASPEN is set and the CONTROL FPCA/SFPA bits
indicate that there is no active floating point context then we
must create a new context (by initializing FPSCR and setting
FPCA/SFPA to indicate that the context is now active). In the
pseudocode this is handled by ExecuteFPCheck().
Implement this with a new TB flag which tracks whether we
need to create a new FP context.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190416125744.27770-20-peter.maydell@linaro.org
---
target/arm/cpu.h | 2 ++
target/arm/translate.h | 1 +
target/arm/helper.c | 13 +++++++++++++
target/arm/translate.c | 29 +++++++++++++++++++++++++++++
4 files changed, 45 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index a2cf9aae3a1..d4996a4d204 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3153,6 +3153,8 @@ FIELD(TBFLAG_A32, NS, 6, 1)
FIELD(TBFLAG_A32, VFPEN, 7, 1)
FIELD(TBFLAG_A32, CONDEXEC, 8, 8)
FIELD(TBFLAG_A32, SCTLR_B, 16, 1)
+/* For M profile only, set if we must create a new FP context */
+FIELD(TBFLAG_A32, NEW_FP_CTXT_NEEDED, 19, 1)
/* For M profile only, set if FPCCR.S does not match current security stat=
e */
FIELD(TBFLAG_A32, FPCCR_S_WRONG, 20, 1)
/* For M profile only, Handler (ie not Thread) mode */
diff --git a/target/arm/translate.h b/target/arm/translate.h
index 93abff645ad..ed8ae2e7e3b 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -41,6 +41,7 @@ typedef struct DisasContext {
bool v8m_secure; /* true if v8M and we're in Secure mode */
bool v8m_stackcheck; /* true if we need to perform v8M stack limit che=
cks */
bool v8m_fpccr_s_wrong; /* true if v8M FPCCR.S !=3D v8m_secure */
+ bool v7m_new_fp_ctxt_needed; /* ASPEN set but no active FP context */
/* Immediate value in AArch32 SVC insn; must be set if is_jmp =3D=3D D=
ISAS_SWI
* so that top level loop can generate correct syndrome information.
*/
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 8290f56c658..84e3790a9de 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -13422,6 +13422,19 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target=
_ulong *pc,
flags =3D FIELD_DP32(flags, TBFLAG_A32, FPCCR_S_WRONG, 1);
}
=20
+ if (arm_feature(env, ARM_FEATURE_M) &&
+ (env->v7m.fpccr[env->v7m.secure] & R_V7M_FPCCR_ASPEN_MASK) &&
+ (!(env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK) ||
+ (env->v7m.secure &&
+ !(env->v7m.control[M_REG_S] & R_V7M_CONTROL_SFPA_MASK)))) {
+ /*
+ * ASPEN is set, but FPCA/SFPA indicate that there is no active
+ * FP context; we must create a new FP context before executing
+ * any FP insn.
+ */
+ flags =3D FIELD_DP32(flags, TBFLAG_A32, NEW_FP_CTXT_NEEDED, 1);
+ }
+
*pflags =3D flags;
*cs_base =3D 0;
}
diff --git a/target/arm/translate.c b/target/arm/translate.c
index f0332ac19ec..edb66e7be8e 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -3438,6 +3438,33 @@ static int disas_vfp_insn(DisasContext *s, uint32_t =
insn)
/* Don't need to do this for any further FP insns in this TB */
s->v8m_fpccr_s_wrong =3D false;
}
+
+ if (s->v7m_new_fp_ctxt_needed) {
+ /*
+ * Create new FP context by updating CONTROL.FPCA, CONTROL.SFPA
+ * and the FPSCR.
+ */
+ TCGv_i32 control, fpscr;
+ uint32_t bits =3D R_V7M_CONTROL_FPCA_MASK;
+
+ fpscr =3D load_cpu_field(v7m.fpdscr[s->v8m_secure]);
+ gen_helper_vfp_set_fpscr(cpu_env, fpscr);
+ tcg_temp_free_i32(fpscr);
+ /*
+ * We don't need to arrange to end the TB, because the only
+ * parts of FPSCR which we cache in the TB flags are the VECLEN
+ * and VECSTRIDE, and those don't exist for M-profile.
+ */
+
+ if (s->v8m_secure) {
+ bits |=3D R_V7M_CONTROL_SFPA_MASK;
+ }
+ control =3D load_cpu_field(v7m.control[M_REG_S]);
+ tcg_gen_ori_i32(control, control, bits);
+ store_cpu_field(control, v7m.control[M_REG_S]);
+ /* Don't need to do this for any further FP insns in this TB */
+ s->v7m_new_fp_ctxt_needed =3D false;
+ }
}
=20
if (extract32(insn, 28, 4) =3D=3D 0xf) {
@@ -13361,6 +13388,8 @@ static void arm_tr_init_disas_context(DisasContextB=
ase *dcbase, CPUState *cs)
regime_is_secure(env, dc->mmu_idx);
dc->v8m_stackcheck =3D FIELD_EX32(tb_flags, TBFLAG_A32, STACKCHECK);
dc->v8m_fpccr_s_wrong =3D FIELD_EX32(tb_flags, TBFLAG_A32, FPCCR_S_WRO=
NG);
+ dc->v7m_new_fp_ctxt_needed =3D
+ FIELD_EX32(tb_flags, TBFLAG_A32, NEW_FP_CTXT_NEEDED);
dc->cp_regs =3D cpu->cp_regs;
dc->features =3D env->features;
=20
--=20
2.20.1