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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Date: Mon, 29 Apr 2019 18:00:09 +0100
Message-Id: <20190429170030.11323-22-peter.maydell@linaro.org>
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Subject: [Qemu-devel] [PULL 21/42] target/arm: Set FPCCR.S when executing
M-profile floating point insns
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The M-profile FPCCR.S bit indicates the security status of
the floating point context. In the pseudocode ExecuteFPCheck()
function it is unconditionally set to match the current
security state whenever a floating point instruction is
executed.
Implement this by adding a new TB flag which tracks whether
FPCCR.S is different from the current security state, so
that we only need to emit the code to update it in the
less-common case when it is not already set correctly.
Note that we will add the handling for the other work done
by ExecuteFPCheck() in later commits.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190416125744.27770-19-peter.maydell@linaro.org
---
target/arm/cpu.h | 2 ++
target/arm/translate.h | 1 +
target/arm/helper.c | 5 +++++
target/arm/translate.c | 20 ++++++++++++++++++++
4 files changed, 28 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 99ccb4824d4..a2cf9aae3a1 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3153,6 +3153,8 @@ FIELD(TBFLAG_A32, NS, 6, 1)
FIELD(TBFLAG_A32, VFPEN, 7, 1)
FIELD(TBFLAG_A32, CONDEXEC, 8, 8)
FIELD(TBFLAG_A32, SCTLR_B, 16, 1)
+/* For M profile only, set if FPCCR.S does not match current security stat=
e */
+FIELD(TBFLAG_A32, FPCCR_S_WRONG, 20, 1)
/* For M profile only, Handler (ie not Thread) mode */
FIELD(TBFLAG_A32, HANDLER, 21, 1)
/* For M profile only, whether we should generate stack-limit checks */
diff --git a/target/arm/translate.h b/target/arm/translate.h
index 984617786d6..93abff645ad 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -40,6 +40,7 @@ typedef struct DisasContext {
bool v7m_handler_mode;
bool v8m_secure; /* true if v8M and we're in Secure mode */
bool v8m_stackcheck; /* true if we need to perform v8M stack limit che=
cks */
+ bool v8m_fpccr_s_wrong; /* true if v8M FPCCR.S !=3D v8m_secure */
/* Immediate value in AArch32 SVC insn; must be set if is_jmp =3D=3D D=
ISAS_SWI
* so that top level loop can generate correct syndrome information.
*/
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 9be5fe581df..8290f56c658 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -13417,6 +13417,11 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target=
_ulong *pc,
flags =3D FIELD_DP32(flags, TBFLAG_A32, STACKCHECK, 1);
}
=20
+ if (arm_feature(env, ARM_FEATURE_M_SECURITY) &&
+ FIELD_EX32(env->v7m.fpccr[M_REG_S], V7M_FPCCR, S) !=3D env->v7m.se=
cure) {
+ flags =3D FIELD_DP32(flags, TBFLAG_A32, FPCCR_S_WRONG, 1);
+ }
+
*pflags =3D flags;
*cs_base =3D 0;
}
diff --git a/target/arm/translate.c b/target/arm/translate.c
index ffaa4f1e095..f0332ac19ec 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -3421,6 +3421,25 @@ static int disas_vfp_insn(DisasContext *s, uint32_t =
insn)
}
}
=20
+ if (arm_dc_feature(s, ARM_FEATURE_M)) {
+ /* Handle M-profile lazy FP state mechanics */
+
+ /* Update ownership of FP context: set FPCCR.S to match current st=
ate */
+ if (s->v8m_fpccr_s_wrong) {
+ TCGv_i32 tmp;
+
+ tmp =3D load_cpu_field(v7m.fpccr[M_REG_S]);
+ if (s->v8m_secure) {
+ tcg_gen_ori_i32(tmp, tmp, R_V7M_FPCCR_S_MASK);
+ } else {
+ tcg_gen_andi_i32(tmp, tmp, ~R_V7M_FPCCR_S_MASK);
+ }
+ store_cpu_field(tmp, v7m.fpccr[M_REG_S]);
+ /* Don't need to do this for any further FP insns in this TB */
+ s->v8m_fpccr_s_wrong =3D false;
+ }
+ }
+
if (extract32(insn, 28, 4) =3D=3D 0xf) {
/*
* Encodings with T=3D1 (Thumb) or unconditional (ARM):
@@ -13341,6 +13360,7 @@ static void arm_tr_init_disas_context(DisasContextB=
ase *dcbase, CPUState *cs)
dc->v8m_secure =3D arm_feature(env, ARM_FEATURE_M_SECURITY) &&
regime_is_secure(env, dc->mmu_idx);
dc->v8m_stackcheck =3D FIELD_EX32(tb_flags, TBFLAG_A32, STACKCHECK);
+ dc->v8m_fpccr_s_wrong =3D FIELD_EX32(tb_flags, TBFLAG_A32, FPCCR_S_WRO=
NG);
dc->cp_regs =3D cpu->cp_regs;
dc->features =3D env->features;
=20
--=20
2.20.1