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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Date: Mon, 29 Apr 2019 18:00:08 +0100
Message-Id: <20190429170030.11323-21-peter.maydell@linaro.org>
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Subject: [Qemu-devel] [PULL 20/42] target/arm: Overlap VECSTRIDE and
XSCALE_CPAR TB flags
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We are close to running out of TB flags for AArch32; we could
start using the cs_base word, but before we do that we can
economise on our usage by sharing the same bits for the VFP
VECSTRIDE field and the XScale XSCALE_CPAR field. This
works because no XScale CPU ever had VFP.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190416125744.27770-18-peter.maydell@linaro.org
---
target/arm/cpu.h | 10 ++++++----
target/arm/cpu.c | 7 +++++++
target/arm/helper.c | 6 +++++-
target/arm/translate.c | 9 +++++++--
4 files changed, 25 insertions(+), 7 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 0ea448034b3..99ccb4824d4 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3138,6 +3138,12 @@ FIELD(TBFLAG_ANY, BE_DATA, 23, 1)
FIELD(TBFLAG_A32, THUMB, 0, 1)
FIELD(TBFLAG_A32, VECLEN, 1, 3)
FIELD(TBFLAG_A32, VECSTRIDE, 4, 2)
+/*
+ * We store the bottom two bits of the CPAR as TB flags and handle
+ * checks on the other bits at runtime. This shares the same bits as
+ * VECSTRIDE, which is OK as no XScale CPU has VFP.
+ */
+FIELD(TBFLAG_A32, XSCALE_CPAR, 4, 2)
/*
* Indicates whether cp register reads and writes by guest code should acc=
ess
* the secure or nonsecure bank of banked registers; note that this is not
@@ -3147,10 +3153,6 @@ FIELD(TBFLAG_A32, NS, 6, 1)
FIELD(TBFLAG_A32, VFPEN, 7, 1)
FIELD(TBFLAG_A32, CONDEXEC, 8, 8)
FIELD(TBFLAG_A32, SCTLR_B, 16, 1)
-/* We store the bottom two bits of the CPAR as TB flags and handle
- * checks on the other bits at runtime
- */
-FIELD(TBFLAG_A32, XSCALE_CPAR, 17, 2)
/* For M profile only, Handler (ie not Thread) mode */
FIELD(TBFLAG_A32, HANDLER, 21, 1)
/* For M profile only, whether we should generate stack-limit checks */
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index be81e197ee9..7deccda2404 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1034,6 +1034,13 @@ static void arm_cpu_realizefn(DeviceState *dev, Erro=
r **errp)
set_feature(env, ARM_FEATURE_THUMB_DSP);
}
=20
+ /*
+ * We rely on no XScale CPU having VFP so we can use the same bits in =
the
+ * TB flags field for VECSTRIDE and XSCALE_CPAR.
+ */
+ assert(!(arm_feature(env, ARM_FEATURE_VFP) &&
+ arm_feature(env, ARM_FEATURE_XSCALE)));
+
if (arm_feature(env, ARM_FEATURE_V7) &&
!arm_feature(env, ARM_FEATURE_M) &&
!arm_feature(env, ARM_FEATURE_PMSA)) {
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 14604f49a4c..9be5fe581df 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -13370,7 +13370,11 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target=
_ulong *pc,
|| arm_el_is_aa64(env, 1) || arm_feature(env, ARM_FEATURE_M)) {
flags =3D FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1);
}
- flags =3D FIELD_DP32(flags, TBFLAG_A32, XSCALE_CPAR, env->cp15.c15=
_cpar);
+ /* Note that XSCALE_CPAR shares bits with VECSTRIDE */
+ if (arm_feature(env, ARM_FEATURE_XSCALE)) {
+ flags =3D FIELD_DP32(flags, TBFLAG_A32,
+ XSCALE_CPAR, env->cp15.c15_cpar);
+ }
}
=20
flags =3D FIELD_DP32(flags, TBFLAG_ANY, MMUIDX, arm_to_core_mmu_idx(mm=
u_idx));
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 0747f7847a9..ffaa4f1e095 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -13330,8 +13330,13 @@ static void arm_tr_init_disas_context(DisasContext=
Base *dcbase, CPUState *cs)
dc->fp_excp_el =3D FIELD_EX32(tb_flags, TBFLAG_ANY, FPEXC_EL);
dc->vfp_enabled =3D FIELD_EX32(tb_flags, TBFLAG_A32, VFPEN);
dc->vec_len =3D FIELD_EX32(tb_flags, TBFLAG_A32, VECLEN);
- dc->vec_stride =3D FIELD_EX32(tb_flags, TBFLAG_A32, VECSTRIDE);
- dc->c15_cpar =3D FIELD_EX32(tb_flags, TBFLAG_A32, XSCALE_CPAR);
+ if (arm_feature(env, ARM_FEATURE_XSCALE)) {
+ dc->c15_cpar =3D FIELD_EX32(tb_flags, TBFLAG_A32, XSCALE_CPAR);
+ dc->vec_stride =3D 0;
+ } else {
+ dc->vec_stride =3D FIELD_EX32(tb_flags, TBFLAG_A32, VECSTRIDE);
+ dc->c15_cpar =3D 0;
+ }
dc->v7m_handler_mode =3D FIELD_EX32(tb_flags, TBFLAG_A32, HANDLER);
dc->v8m_secure =3D arm_feature(env, ARM_FEATURE_M_SECURITY) &&
regime_is_secure(env, dc->mmu_idx);
--=20
2.20.1