From nobody Wed May 7 04:44:42 2025
Delivered-To: importer@patchew.org
Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as
permitted sender) client-ip=209.51.188.17;
envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org;
helo=lists.gnu.org;
Authentication-Results: mx.zohomail.com;
dkim=fail;
spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted
sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org;
dmarc=fail(p=none dis=none) header.from=linaro.org
ARC-Seal: i=1; a=rsa-sha256; t=1556558774; cv=none;
d=zoho.com; s=zohoarc;
b=L07/pPhZcvP/eZTpaZbOEt7++5i5JHtsm6gyRIQXXG/drXWcteNvYx01BdqEVr+KExb7L07n/jwVr/wzUuJcjUcpLOJ43GMW3+ghXsT69feYMSgW+Hc7MHOkzGCodsZa6O2/n5NKX+TDImf4hFohcBeP2mrwfovfH7sMHBQXTcw=
ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com;
s=zohoarc;
t=1556558774;
h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results;
bh=aRW2k9Bx9SmwGykwzikVBcj0TPSJbJZ0vG2+ZFO8UMs=;
b=P+dqbIYsfnfW5JLY1X+ttCjw4LfyigBXsGu7LDpzaeDVz5iqtJmZMdU551bGfcK9rWTWhwCGrSB87oRna3US5g2Aoro7MM4Iq5W/A0QnqtSB8q6VmqK4SfJcv4K2aY9fGsn51b+a1co2hdLqcoSlkuJGUEp1vbyqtO+08ZxYkmI=
ARC-Authentication-Results: i=1; mx.zoho.com;
dkim=fail;
spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted
sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org;
dmarc=fail header.from=<peter.maydell@linaro.org> (p=none dis=none)
header.from=<peter.maydell@linaro.org>
Return-Path: <qemu-devel-bounces+importer=patchew.org@nongnu.org>
Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by
mx.zohomail.com
with SMTPS id 1556558774029152.8072661343292;
Mon, 29 Apr 2019 10:26:14 -0700 (PDT)
Received: from localhost ([127.0.0.1]:60962 helo=lists.gnu.org)
by lists.gnu.org with esmtp (Exim 4.71)
(envelope-from <qemu-devel-bounces+importer=patchew.org@nongnu.org>)
id 1hLA2e-0000Pl-NI
for importer@patchew.org; Mon, 29 Apr 2019 13:26:12 -0400
Received: from eggs.gnu.org ([209.51.188.92]:34377)
by lists.gnu.org with esmtp (Exim 4.71)
(envelope-from <peter.maydell@linaro.org>) id 1hL9er-0004rg-Hk
for qemu-devel@nongnu.org; Mon, 29 Apr 2019 13:01:38 -0400
Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)
(envelope-from <peter.maydell@linaro.org>) id 1hL9eo-0006kd-Gr
for qemu-devel@nongnu.org; Mon, 29 Apr 2019 13:01:36 -0400
Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]:51172)
by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16)
(Exim 4.71) (envelope-from <peter.maydell@linaro.org>)
id 1hL9eo-0006NL-1h
for qemu-devel@nongnu.org; Mon, 29 Apr 2019 13:01:34 -0400
Received: by mail-wm1-x32b.google.com with SMTP id p21so186402wmc.0
for <qemu-devel@nongnu.org>; Mon, 29 Apr 2019 10:00:47 -0700 (PDT)
Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148])
by smtp.gmail.com with ESMTPSA id a13sm36896wmj.39.2019.04.29.10.00.45
for <qemu-devel@nongnu.org>
(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);
Mon, 29 Apr 2019 10:00:45 -0700 (PDT)
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google;
h=from:to:subject:date:message-id:in-reply-to:references:mime-version
:content-transfer-encoding;
bh=aRW2k9Bx9SmwGykwzikVBcj0TPSJbJZ0vG2+ZFO8UMs=;
b=wLLvNVonfMOdE5NK01+FeJefR2LEdhlmaHSblf/41ORtcHH2wIU7LiI19j1r15NOc+
Vckz6RbsacvtlHEjY0ZtRqktYWSkZOxOHcfjpEYj0i+G4U0XRcGxrt7GKUhB/r2mnWg2
FsxlzWqwq2C9qWTjq1Ku1vG+IvmIB6ihEZX+RLv/IgGnRmrdTusoxQhz+ezNnCsDCs5q
C4g2wsghmYNLD+R3K1+NfByhp3yIf65ERfrLwerU44yNv1HYwvdFQDmh6dWMHmrKgQ2/
bErIEYe7amlyDkBv0DP2jWn1cYyvmDMTvluflcRMp+rFLuSGzDGvlr0X2krVx/9HnJfk
HL+A==
X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed;
d=1e100.net; s=20161025;
h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to
:references:mime-version:content-transfer-encoding;
bh=aRW2k9Bx9SmwGykwzikVBcj0TPSJbJZ0vG2+ZFO8UMs=;
b=qoOHGtrdMMWOFpvQ8ZErVzeC5rVwyf3SLtCFRPdipT1Rg9QWPXcpI165qMR6oZVZ0D
HR8Kro1lBiSbvuhZeLBzrwTugLZvbiI4DWD21jliUswutBpipNAw0bLVCOoT3nw1NsxK
cHEiEB5EIOntRCvkB5hrRkuDtlsg1PNS5gYuMlA1BsImrMfMk0yLpuCCd+sHVN5sTlTS
EfU4Xe8ld+EaG227zTZMswfweMf+RGoawTrQJ94QxTE2uli/DZRGqpCf+j/Q3uNO2N0F
WCaEjj0W2qhEjLcykFD5LhquPl7ffLkzzv4lxeoE0j/jXdcMsUBZxP3aOMnb50+6Ezoh
WGcA==
X-Gm-Message-State: APjAAAXPKpAWaJaMRWGUkiE1iIiEmcamc1ey9DRTzhBEiETaKFQbEh1e
zSsCf1UZos5Frz9HCveGzvmAxokX8GQ=
X-Google-Smtp-Source:
APXvYqyT2bc8/CokJXAb3SzQ8KNXk8rd1XS7VRaLkY7fyfQ3Zbtgq+wBVlDxG09t0TdTxsT+E/NBIQ==
X-Received: by 2002:a1c:dc84:: with SMTP id t126mr15391wmg.143.1556557246599;
Mon, 29 Apr 2019 10:00:46 -0700 (PDT)
From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Date: Mon, 29 Apr 2019 17:59:59 +0100
Message-Id: <20190429170030.11323-12-peter.maydell@linaro.org>
X-Mailer: git-send-email 2.20.1
In-Reply-To: <20190429170030.11323-1-peter.maydell@linaro.org>
References: <20190429170030.11323-1-peter.maydell@linaro.org>
MIME-Version: 1.0
Content-Transfer-Encoding: quoted-printable
X-detected-operating-system: by eggs.gnu.org: Genre and OS details not
recognized.
X-Received-From: 2a00:1450:4864:20::32b
Subject: [Qemu-devel] [PULL 11/42] target/arm: Handle SFPA and FPCA bits in
reads and writes of CONTROL
X-BeenThere: qemu-devel@nongnu.org
X-Mailman-Version: 2.1.21
Precedence: list
List-Id: <qemu-devel.nongnu.org>
List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>,
<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>
List-Archive: <http://lists.nongnu.org/archive/html/qemu-devel/>
List-Post: <mailto:qemu-devel@nongnu.org>
List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help>
List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>,
<mailto:qemu-devel-request@nongnu.org?subject=subscribe>
Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org
Sender: "Qemu-devel" <qemu-devel-bounces+importer=patchew.org@nongnu.org>
X-ZohoMail-DKIM: fail (Header signature does not verify)
Content-Type: text/plain; charset="utf-8"
The M-profile CONTROL register has two bits -- SFPA and FPCA --
which relate to floating-point support, and should be RES0 otherwise.
Handle them correctly in the MSR/MRS register access code.
Neither is banked between security states, so they are stored
in v7m.control[M_REG_S] regardless of current security state.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190416125744.27770-9-peter.maydell@linaro.org
---
target/arm/helper.c | 57 ++++++++++++++++++++++++++++++++++++++-------
1 file changed, 49 insertions(+), 8 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 45a9d92e505..e801744673f 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -12027,7 +12027,14 @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_=
t reg)
return xpsr_read(env) & mask;
break;
case 20: /* CONTROL */
- return env->v7m.control[env->v7m.secure];
+ {
+ uint32_t value =3D env->v7m.control[env->v7m.secure];
+ if (!env->v7m.secure) {
+ /* SFPA is RAZ/WI from NS; FPCA is stored in the M_REG_S bank =
*/
+ value |=3D env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK;
+ }
+ return value;
+ }
case 0x94: /* CONTROL_NS */
/* We have to handle this here because unprivileged Secure code
* can read the NS CONTROL register.
@@ -12035,7 +12042,8 @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t=
reg)
if (!env->v7m.secure) {
return 0;
}
- return env->v7m.control[M_REG_NS];
+ return env->v7m.control[M_REG_NS] |
+ (env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK);
}
=20
if (el =3D=3D 0) {
@@ -12141,9 +12149,13 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t ma=
skreg, uint32_t val)
*/
uint32_t mask =3D extract32(maskreg, 8, 4);
uint32_t reg =3D extract32(maskreg, 0, 8);
+ int cur_el =3D arm_current_el(env);
=20
- if (arm_current_el(env) =3D=3D 0 && reg > 7) {
- /* only xPSR sub-fields may be written by unprivileged */
+ if (cur_el =3D=3D 0 && reg > 7 && reg !=3D 20) {
+ /*
+ * only xPSR sub-fields and CONTROL.SFPA may be written by
+ * unprivileged code
+ */
return;
}
=20
@@ -12202,6 +12214,15 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t ma=
skreg, uint32_t val)
env->v7m.control[M_REG_NS] &=3D ~R_V7M_CONTROL_NPRIV_MASK;
env->v7m.control[M_REG_NS] |=3D val & R_V7M_CONTROL_NPRIV_=
MASK;
}
+ /*
+ * SFPA is RAZ/WI from NS. FPCA is RO if NSACR.CP10 =3D=3D 0,
+ * RES0 if the FPU is not present, and is stored in the S bank
+ */
+ if (arm_feature(env, ARM_FEATURE_VFP) &&
+ extract32(env->v7m.nsacr, 10, 1)) {
+ env->v7m.control[M_REG_S] &=3D ~R_V7M_CONTROL_FPCA_MASK;
+ env->v7m.control[M_REG_S] |=3D val & R_V7M_CONTROL_FPCA_MA=
SK;
+ }
return;
case 0x98: /* SP_NS */
{
@@ -12304,21 +12325,41 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t m=
askreg, uint32_t val)
env->v7m.faultmask[env->v7m.secure] =3D val & 1;
break;
case 20: /* CONTROL */
- /* Writing to the SPSEL bit only has an effect if we are in
+ /*
+ * Writing to the SPSEL bit only has an effect if we are in
* thread mode; other bits can be updated by any privileged code.
* write_v7m_control_spsel() deals with updating the SPSEL bit in
* env->v7m.control, so we only need update the others.
* For v7M, we must just ignore explicit writes to SPSEL in handler
* mode; for v8M the write is permitted but will have no effect.
+ * All these bits are writes-ignored from non-privileged code,
+ * except for SFPA.
*/
- if (arm_feature(env, ARM_FEATURE_V8) ||
- !arm_v7m_is_handler_mode(env)) {
+ if (cur_el > 0 && (arm_feature(env, ARM_FEATURE_V8) ||
+ !arm_v7m_is_handler_mode(env))) {
write_v7m_control_spsel(env, (val & R_V7M_CONTROL_SPSEL_MASK) =
!=3D 0);
}
- if (arm_feature(env, ARM_FEATURE_M_MAIN)) {
+ if (cur_el > 0 && arm_feature(env, ARM_FEATURE_M_MAIN)) {
env->v7m.control[env->v7m.secure] &=3D ~R_V7M_CONTROL_NPRIV_MA=
SK;
env->v7m.control[env->v7m.secure] |=3D val & R_V7M_CONTROL_NPR=
IV_MASK;
}
+ if (arm_feature(env, ARM_FEATURE_VFP)) {
+ /*
+ * SFPA is RAZ/WI from NS or if no FPU.
+ * FPCA is RO if NSACR.CP10 =3D=3D 0, RES0 if the FPU is not p=
resent.
+ * Both are stored in the S bank.
+ */
+ if (env->v7m.secure) {
+ env->v7m.control[M_REG_S] &=3D ~R_V7M_CONTROL_SFPA_MASK;
+ env->v7m.control[M_REG_S] |=3D val & R_V7M_CONTROL_SFPA_MA=
SK;
+ }
+ if (cur_el > 0 &&
+ (env->v7m.secure || !arm_feature(env, ARM_FEATURE_M_SECURI=
TY) ||
+ extract32(env->v7m.nsacr, 10, 1))) {
+ env->v7m.control[M_REG_S] &=3D ~R_V7M_CONTROL_FPCA_MASK;
+ env->v7m.control[M_REG_S] |=3D val & R_V7M_CONTROL_FPCA_MA=
SK;
+ }
+ }
break;
default:
bad_reg:
--=20
2.20.1