From nobody Mon Feb 9 02:36:09 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1556550585; cv=none; d=zoho.com; s=zohoarc; b=aIaGAaEnUDz0P12L3pFpdz/VHcCoupaKOm3Jur5mv8j6hlqy+4or4qB2xKwaQyV64n+/to/lO6pNad7svhZZ50qPdM/R8QCoMvnJo337Ill9L9JnI1ChVeGQjQuru3Ve4tsUQPuTdU+vE23EE2ARkMm6TWYD9/FzAG6b061qeJ8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1556550585; h=Content-Type:Content-Transfer-Encoding:Date:From:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:To:ARC-Authentication-Results; bh=UXAbUgkZk1QwQMjJq6cf0VxASrDg5cTDGQ21e4E72XY=; b=ZJWVJuYYE7t+4FkaHVOFZG7W/bDfT/6Zx4Bho422JtTuD+Zk9DGIMIEV60+3NRQk7QrcJzg9l81wNrWhKvjnAvyEJZLifmnTgpG7AE/1Eovy0/S/WHK0+JSYa7/p9FGhsxOPS2b/hJakoWImbMovZTZlI7OW4wzbJo0lg9g2/Qk= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1556550585831840.2054940360933; Mon, 29 Apr 2019 08:09:45 -0700 (PDT) Received: from localhost ([127.0.0.1]:58944 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hL7uV-0006TJ-Rd for importer@patchew.org; Mon, 29 Apr 2019 11:09:39 -0400 Received: from eggs.gnu.org ([209.51.188.92]:38041) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hL094-0007eR-8q for qemu-devel@nongnu.org; Mon, 29 Apr 2019 02:52:11 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hL093-0005AQ-9z for qemu-devel@nongnu.org; Mon, 29 Apr 2019 02:52:10 -0400 Received: from szxga06-in.huawei.com ([45.249.212.32]:37822 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hL092-00056G-W7 for qemu-devel@nongnu.org; Mon, 29 Apr 2019 02:52:09 -0400 Received: from DGGEMS402-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id E8C37CE312D4E3B86315 for ; Mon, 29 Apr 2019 14:51:57 +0800 (CST) Received: from huawei.com (10.143.28.114) by DGGEMS402-HUB.china.huawei.com (10.3.19.202) with Microsoft SMTP Server id 14.3.439.0; Mon, 29 Apr 2019 14:51:57 +0800 From: Yang Chuanlong To: Date: Mon, 29 Apr 2019 14:48:30 +0800 Message-ID: <20190429064830.12213-1-yangchuanlong@huawei.com> X-Mailer: git-send-email 2.21.0 MIME-Version: 1.0 X-Originating-IP: [10.143.28.114] X-CFilter-Loop: Reflected Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 45.249.212.32 X-Mailman-Approved-At: Mon, 29 Apr 2019 11:06:13 -0400 Subject: [Qemu-devel] [PATCH v1] target/arm/arm-powerctl: mask the cpuid with affinity bits when get cpu X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Currently, the cpuid passed from the device tree may still contain non-affinity fields, which will cause arm_set_cpu_on failure. Therefore, we mask the cpuid with affinity fields here to improve qemu compatibility. Signed-off-by: Yang Chuanlong --- target/arm/arm-powerctl.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/target/arm/arm-powerctl.c b/target/arm/arm-powerctl.c index f77a950db6..ef9fec0b4d 100644 --- a/target/arm/arm-powerctl.c +++ b/target/arm/arm-powerctl.c @@ -31,7 +31,13 @@ CPUState *arm_get_cpu_by_id(uint64_t id) { CPUState *cpu; =20 - DPRINTF("cpu %" PRId64 "\n", id); +#ifdef TARGET_AARCH64 + id &=3D ARM64_AFFINITY_MASK; +#else + id &=3D ARM32_AFFINITY_MASK; +#endif + + DPRINTF("cpu %" PRId64 " after mask affinity\n", id); =20 CPU_FOREACH(cpu) { ARMCPU *armcpu =3D ARM_CPU(cpu); --=20 2.21.0