From nobody Tue Feb 10 23:14:00 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1556462695; cv=none; d=zoho.com; s=zohoarc; b=mV78vF0wSWAUVdBn27kjqdpuSQa3ZUGp4ulHkhkYxp4zFuHizPOtCZwqCWV3nlx+8t3hZxZhUpE1lQwTDMZFEk4Ihd6TPAFDutEyY1eSt7tw/7wThy5haMTL6LJeW+XnLKTZ3qNrERrZNrK2GxDELB4HOw/EpzKngoQyilQ312A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1556462695; h=Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=piKidJYy0ULw2oMeqRlqa6S/OVKJoP0aMpfUsooxpj0=; b=XS2qxeQIcSZgpSe4df0NzJK/BXZAcEFsLXDlzQLqROPD8b84WSggPsM0wahvjbnP3v3aobT8Mkm6FjaBac1DIlOoKwq3AQzDl7Dzv2i4p10c/Qyv8XRzd120USwHxCLWhyFtCekBZuq/1Sa/vIM/WiHmThYYSHpsqPe6wB1Qc/U= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1556462695400576.8890658685011; Sun, 28 Apr 2019 07:44:55 -0700 (PDT) Received: from localhost ([127.0.0.1]:44946 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hKl2w-0007BJ-65 for importer@patchew.org; Sun, 28 Apr 2019 10:44:50 -0400 Received: from eggs.gnu.org ([209.51.188.92]:58713) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hKl0q-000608-Mb for qemu-devel@nongnu.org; Sun, 28 Apr 2019 10:42:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hKl0p-00055R-Jm for qemu-devel@nongnu.org; Sun, 28 Apr 2019 10:42:40 -0400 Received: from mail.ilande.co.uk ([46.43.2.167]:52902 helo=mail.default.ilande.uk0.bigv.io) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hKl0p-0004bG-E8; Sun, 28 Apr 2019 10:42:39 -0400 Received: from host86-175-31-255.range86-175.btcentralplus.com ([86.175.31.255] helo=kentang.home) by mail.default.ilande.uk0.bigv.io with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.89) (envelope-from ) id 1hKkxE-0005tp-Td; Sun, 28 Apr 2019 15:38:57 +0100 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, rth@twiddle.net, gkurz@kaod.org Date: Sun, 28 Apr 2019 15:38:33 +0100 Message-Id: <20190428143845.11810-3-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190428143845.11810-1-mark.cave-ayland@ilande.co.uk> References: <20190428143845.11810-1-mark.cave-ayland@ilande.co.uk> X-SA-Exim-Connect-IP: 86.175.31.255 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Tue, 02 Aug 2016 21:08:31 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.uk0.bigv.io) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 46.43.2.167 Subject: [Qemu-devel] [PATCH 02/14] target/ppc: remove getVSR()/putVSR() from mem_helper.c X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Since commit 8a14d31b00 "target/ppc: switch fpr/vsrl registers so all VSX registers are in host endian order" functions getVSR() and putVSR() which u= sed to convert the VSR registers into host endian order are no longer required. Signed-off-by: Mark Cave-Ayland --- target/ppc/mem_helper.c | 24 +++++++++++------------- target/ppc/translate/vsx-impl.inc.c | 8 +++++--- 2 files changed, 16 insertions(+), 16 deletions(-) diff --git a/target/ppc/mem_helper.c b/target/ppc/mem_helper.c index 5b0f9ee50d..4dfa7ee23f 100644 --- a/target/ppc/mem_helper.c +++ b/target/ppc/mem_helper.c @@ -415,28 +415,27 @@ STVE(stvewx, cpu_stl_data_ra, bswap32, u32) =20 #define VSX_LXVL(name, lj) \ void helper_##name(CPUPPCState *env, target_ulong addr, \ - target_ulong xt_num, target_ulong rb) \ + target_ulong xt, target_ulong rb) \ { \ + ppc_vsr_t *r =3D &env->vsr[xt]; \ + int nb =3D GET_NB(env->gpr[rb]); \ int i; \ - ppc_vsr_t xt; \ - uint64_t nb =3D GET_NB(rb); \ \ - xt.s128 =3D int128_zero(); \ + r->s128 =3D int128_zero(); \ if (nb) { \ nb =3D (nb >=3D 16) ? 16 : nb; = \ if (msr_le && !lj) { \ for (i =3D 16; i > 16 - nb; i--) { \ - xt.VsrB(i - 1) =3D cpu_ldub_data_ra(env, addr, GETPC()); \ + r->VsrB(i - 1) =3D cpu_ldub_data_ra(env, addr, GETPC()); \ addr =3D addr_add(env, addr, 1); \ } \ } else { \ for (i =3D 0; i < nb; i++) { \ - xt.VsrB(i) =3D cpu_ldub_data_ra(env, addr, GETPC()); \ + r->VsrB(i) =3D cpu_ldub_data_ra(env, addr, GETPC()); \ addr =3D addr_add(env, addr, 1); \ } \ } \ } \ - putVSR(xt_num, &xt, env); \ } =20 VSX_LXVL(lxvl, 0) @@ -445,25 +444,24 @@ VSX_LXVL(lxvll, 1) =20 #define VSX_STXVL(name, lj) \ void helper_##name(CPUPPCState *env, target_ulong addr, \ - target_ulong xt_num, target_ulong rb) \ + target_ulong xt, target_ulong rb) \ { \ + ppc_vsr_t *r =3D &env->vsr[xt]; \ + int nb =3D GET_NB(env->gpr[rb]); \ int i; \ - ppc_vsr_t xt; \ - target_ulong nb =3D GET_NB(rb); \ \ if (!nb) { \ return; \ } \ - getVSR(xt_num, &xt, env); \ nb =3D (nb >=3D 16) ? 16 : nb; \ if (msr_le && !lj) { \ for (i =3D 16; i > 16 - nb; i--) { \ - cpu_stb_data_ra(env, addr, xt.VsrB(i - 1), GETPC()); \ + cpu_stb_data_ra(env, addr, r->VsrB(i - 1), GETPC()); \ addr =3D addr_add(env, addr, 1); \ } \ } else { \ for (i =3D 0; i < nb; i++) { \ - cpu_stb_data_ra(env, addr, xt.VsrB(i), GETPC()); \ + cpu_stb_data_ra(env, addr, r->VsrB(i), GETPC()); \ addr =3D addr_add(env, addr, 1); \ } \ } \ diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx= -impl.inc.c index 11d9b75d01..c776d50ddc 100644 --- a/target/ppc/translate/vsx-impl.inc.c +++ b/target/ppc/translate/vsx-impl.inc.c @@ -290,7 +290,7 @@ VSX_VECTOR_LOAD_STORE(stxvx, st_i64, 1) #define VSX_VECTOR_LOAD_STORE_LENGTH(name) \ static void gen_##name(DisasContext *ctx) \ { \ - TCGv EA, xt; \ + TCGv EA, xt, rb; \ \ if (xT(ctx->opcode) < 32) { \ if (unlikely(!ctx->vsx_enabled)) { \ @@ -304,12 +304,14 @@ static void gen_##name(DisasContext *ctx) = \ } \ } \ EA =3D tcg_temp_new(); \ - xt =3D tcg_const_tl(xT(ctx->opcode)); \ gen_set_access_type(ctx, ACCESS_INT); \ gen_addr_register(ctx, EA); \ - gen_helper_##name(cpu_env, EA, xt, cpu_gpr[rB(ctx->opcode)]); \ + xt =3D tcg_const_tl(xT(ctx->opcode)); \ + rb =3D tcg_const_tl(rB(ctx->opcode)); \ + gen_helper_##name(cpu_env, EA, xt, rb); \ tcg_temp_free(EA); \ tcg_temp_free(xt); \ + tcg_temp_free(rb); \ } =20 VSX_VECTOR_LOAD_STORE_LENGTH(lxvl) --=20 2.11.0