From nobody Mon Feb 9 10:38:33 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1556326463; cv=none; d=zoho.com; s=zohoarc; b=awvOuMWHCi5KXUHLfx6xMtv1CJJche6RSDSeBviXHpA9TvgjiWsB0W54WEjdpiKNs9o9NVsEQNeoVFQlrz+BKkfaTf5BVFXBFv66nTdXHs/5gY+IoMUqPIIIKyV8ikTK1CsCo6XGWyT15sZAl2Li6abTxsetCrNne+My8/zia8Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1556326463; h=Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=yR3SBCBXYUmKX63niTZceDYrt1W/+HQOJtz/bKyhTGI=; b=UIlX9Zw9By3CSC4IYFq4rLpTxMmZEOhpgcNdBN/R58ynq0F9RPkMRa3TUqIxNioDN3rFI8pmxFrYra3TtYtH3iLydHsT6YYjPsMcoywCCTpNYzhI9qjS7w0o/ZjS0du7Cq71GfJROCkWqcLt513BbIBCjotP8umfW5JnlmLMo04= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1556326463031986.7536055708191; Fri, 26 Apr 2019 17:54:23 -0700 (PDT) Received: from localhost ([127.0.0.1]:53832 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hKBbW-0006DO-Uh for importer@patchew.org; Fri, 26 Apr 2019 20:54:11 -0400 Received: from eggs.gnu.org ([209.51.188.92]:41304) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hKBZs-0005He-1T for qemu-devel@nongnu.org; Fri, 26 Apr 2019 20:52:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hKBYv-0000zx-9C for qemu-devel@nongnu.org; Fri, 26 Apr 2019 20:51:30 -0400 Received: from mail-pf1-x441.google.com ([2607:f8b0:4864:20::441]:33929) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hKBYv-0000zY-2X for qemu-devel@nongnu.org; Fri, 26 Apr 2019 20:51:29 -0400 Received: by mail-pf1-x441.google.com with SMTP id b3so2494108pfd.1 for ; Fri, 26 Apr 2019 17:51:28 -0700 (PDT) Received: from localhost.localdomain (97-113-179-147.tukw.qwest.net. [97.113.179.147]) by smtp.gmail.com with ESMTPSA id b20sm5301745pff.118.2019.04.26.17.51.26 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 26 Apr 2019 17:51:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=yR3SBCBXYUmKX63niTZceDYrt1W/+HQOJtz/bKyhTGI=; b=LXz5eCQtDQIJUGDa1TZ4LI5N5lpwRVeXEwyAdwmnaWnx8+JEaexsoQQtlDJPZRErp7 ZQyYYvBVwdE4TUjOMkufgS80A/pju5hY908Oy9agv9M44KPODu9GgWJN6gHtqPyhI5O0 VTOt13063mLlb5k46KYGQ4iBP+Yb10rfsev+jwhK2aEhWb9emYBx36qOvZk8Hw5KZRlm 31Ze6W8YJHxe4ZoJUopbnBCiElHSEQ9rGRP9JzX4dwPwMUtxTSz/HPDHGii3gtw/VkOp M3uvM1+5L783RjmpUan+I6LuRs9xDh1+Rka8onEFxEyfNZPKyi/rLvGOIEoF8JMxj57J IFpg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=yR3SBCBXYUmKX63niTZceDYrt1W/+HQOJtz/bKyhTGI=; b=bng0EB9nMxLDgAMzo/EeisNkmNqjSmsa4AJbLXRssdhL1ys+ecfq5ZiPJWGpxOq69n MBe4A+Kzdqao6CWZ7N6QP8L2wys/eoIxAc2Wq3bo215HsDRb548/WMzKD1UmYPsfEs0i 9gmvXbCC21gNQQ31k/BDt4ZNYVKRJGW+eGcf1nBODS/3KY+WgclBOh0cBEQh0b22xmbQ f5QZ1Rh0fg7hCGiGeRy3BO5AtIcFxnVKTKq6zDl5jKLGPLvCvK9sZzzvswH6qj3PH3o5 X4agTriP1E+Ui9yRq0MXx1Cz2AB8swTJAYT6H0M1EswH+EGH5m65fa6vQDp1qaBgL5aK lJXQ== X-Gm-Message-State: APjAAAVciusX5c92zjoSkbHyCyOM6u/2LcAQ4wCPpsRr5rJGPHsz4VdS b+pHuX3jPruJqeYabirQ+cSFow6LmXI= X-Google-Smtp-Source: APXvYqy+v8+g3XgYrUNjmI9PD+v3+ueopiowWLRTtOnGBt5YtyBfrUprsdDF5TTzNUEodPlCDvlOSg== X-Received: by 2002:aa7:938b:: with SMTP id t11mr50145807pfe.67.1556326287334; Fri, 26 Apr 2019 17:51:27 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 26 Apr 2019 17:51:23 -0700 Message-Id: <20190427005124.12756-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190427005124.12756-1-richard.henderson@linaro.org> References: <20190427005124.12756-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::441 Subject: [Qemu-devel] [PATCH 1/2] target/alpha: Clean up alpha_cpu_dump_state X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Drop the "RI" and "FIR" prefixes; use only the normal linux names. Add the FPCR to the dump. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 --- target/alpha/helper.c | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/target/alpha/helper.c b/target/alpha/helper.c index 7201576aae..31de9593b6 100644 --- a/target/alpha/helper.c +++ b/target/alpha/helper.c @@ -429,32 +429,33 @@ bool alpha_cpu_exec_interrupt(CPUState *cs, int inter= rupt_request) =20 void alpha_cpu_dump_state(CPUState *cs, FILE *f, int flags) { - static const char *linux_reg_names[] =3D { - "v0 ", "t0 ", "t1 ", "t2 ", "t3 ", "t4 ", "t5 ", "t6 ", - "t7 ", "s0 ", "s1 ", "s2 ", "s3 ", "s4 ", "s5 ", "fp ", - "a0 ", "a1 ", "a2 ", "a3 ", "a4 ", "a5 ", "t8 ", "t9 ", - "t10", "t11", "ra ", "t12", "at ", "gp ", "sp ", "zero", + static const char linux_reg_names[31][4] =3D { + "v0", "t0", "t1", "t2", "t3", "t4", "t5", "t6", + "t7", "s0", "s1", "s2", "s3", "s4", "s5", "fp", + "a0", "a1", "a2", "a3", "a4", "a5", "t8", "t9", + "t10", "t11", "ra", "t12", "at", "gp", "sp" }; AlphaCPU *cpu =3D ALPHA_CPU(cs); CPUAlphaState *env =3D &cpu->env; int i; =20 - qemu_fprintf(f, " PC " TARGET_FMT_lx " PS %02x\n", + qemu_fprintf(f, "PC " TARGET_FMT_lx " PS %02x\n", env->pc, extract32(env->flags, ENV_FLAG_PS_SHIFT, 8)); for (i =3D 0; i < 31; i++) { - qemu_fprintf(f, "IR%02d %s " TARGET_FMT_lx "%c", i, + qemu_fprintf(f, "%-8s" TARGET_FMT_lx "%c", linux_reg_names[i], cpu_alpha_load_gr(env, i), (i % 3) =3D=3D 2 ? '\n' : ' '); } =20 - qemu_fprintf(f, "lock_a " TARGET_FMT_lx " lock_v " TARGET_FMT_lx "= \n", + qemu_fprintf(f, "lock_a " TARGET_FMT_lx " lock_v " TARGET_FMT_lx "\n= ", env->lock_addr, env->lock_value); =20 if (flags & CPU_DUMP_FPU) { for (i =3D 0; i < 31; i++) { - qemu_fprintf(f, "FIR%02d %016" PRIx64 "%c", i, env->fir[i], + qemu_fprintf(f, "f%-7d%016" PRIx64 "%c", i, env->fir[i], (i % 3) =3D=3D 2 ? '\n' : ' '); } + qemu_fprintf(f, "fpcr %016" PRIx64 "\n", cpu_alpha_load_fpcr(en= v)); } qemu_fprintf(f, "\n"); } --=20 2.17.1 From nobody Mon Feb 9 10:38:33 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1556326457; cv=none; d=zoho.com; s=zohoarc; b=JRgfB1BBnhGc4seBZ0FxNogmuMjHvY1BhII6QOFNwS1p1cGDmrYwi0ychFVfcpdGAy61azCR1YNEIohI2SDkebJSPtC8/hb2ovGHR6GqKfcxxfMsP7zYqqvHvOR0laFI1JlGWjTYgL8WwjHnlQeA7bv5KT75ChpnpDXCqENGOlE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1556326457; h=Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=tj3s4+mU5PKa2WhEAxXILWeOt/wWMt3OHwjOwYf7Zes=; b=k3cWP5csIrzHYfyXXrK3sdsA8bWWJE2EpdGkH1kUwBwSZOJxqppmJ5qDmvCBdOEgJCWCb8VO8HsIaaf/RPM3xtDGxi+DLuDHF4sEMIP26F2Eu7OvXZhUqOIxn227UjSmasgYybDkKUnvDnDBKnKdunCepyqDe8pUyC03CVjnrTw= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1556326457794875.8747330851863; Fri, 26 Apr 2019 17:54:17 -0700 (PDT) Received: from localhost ([127.0.0.1]:53830 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hKBbU-0006B4-3u for importer@patchew.org; Fri, 26 Apr 2019 20:54:08 -0400 Received: from eggs.gnu.org ([209.51.188.92]:41304) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hKBZq-0005He-6v for qemu-devel@nongnu.org; Fri, 26 Apr 2019 20:52:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hKBYw-00010g-Al for qemu-devel@nongnu.org; Fri, 26 Apr 2019 20:51:31 -0400 Received: from mail-pg1-x541.google.com ([2607:f8b0:4864:20::541]:42672) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hKBYw-00010E-2G for qemu-devel@nongnu.org; Fri, 26 Apr 2019 20:51:30 -0400 Received: by mail-pg1-x541.google.com with SMTP id p6so2351526pgh.9 for ; Fri, 26 Apr 2019 17:51:30 -0700 (PDT) Received: from localhost.localdomain (97-113-179-147.tukw.qwest.net. [97.113.179.147]) by smtp.gmail.com with ESMTPSA id b20sm5301745pff.118.2019.04.26.17.51.27 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 26 Apr 2019 17:51:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=tj3s4+mU5PKa2WhEAxXILWeOt/wWMt3OHwjOwYf7Zes=; b=omf1lLaPemC3PlaVoM35C8UHl4DXojOrRfMCzV7QGv1v877wVDkaHUr1e3xWztJvBT X3g9DPbwUYu4jcfuckqid8VXBbAhoeAX59v3/xlDxmsLqV57o+S43HYqC3hd57g/AM6W DVRSeh6z68EuIVOzIgw9LAML6jAZ2UzXMG6SdQXQbJINOJvxvXALqrV7ZApCS5UvfyyR hQVgEkk/5Ek/qWe6f5VjLyj04YUwOwKbXXCzaMbFY45dF4o9I5YY4Stl11QVpMK5MnJE 8u88c0eIVHIVopbocD2R/4NQNhRq7t7R3WHTY4EKNpYNbceN+9O5a1KH2eonzcK+jGRl Q3mw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=tj3s4+mU5PKa2WhEAxXILWeOt/wWMt3OHwjOwYf7Zes=; b=I2uUwOBbMvxgyF8zVgVAw1+QMOpULjdCSRYzecEOP7zFSI09U8WNlZD70RQ3IsL3dj LaCuybxbxzpcOmSUwob5FBY4rjjgK5eC1Uunms+YQtJedpgnu8TuJSCcYmfk2lP5nlG7 nqrkR5vU83Xpv5gwCGkgDisagPRqJi6S/H1P5R+MAEI/aM45IXgltGd1O+ZxEcUGsOT/ uRMZIf/bNcaK8X69agUQE9Bub2rxuswjyvqHoQS+jbH5Nva9VIdXHk2uX/W1ueVCZiBk v9pKEVLGuk9XpprZc4Rp70+2fxcZue/UbM+MRBCtbM1pHTh+eUN66sz9HDirPaKem9AJ fKjQ== X-Gm-Message-State: APjAAAVY3DtKKpIL3UgKK54+AZ33GoWHsEPAxu42wjxC7MdphgXEOKJZ wLV5vR2rceGutd6Guh7bHMj4rV3ACJI= X-Google-Smtp-Source: APXvYqw57zPRSvczGH5CKrTidFlWDgEaz9VDhJWplAuA3NstpTU7EPHS8aOQ2oF+4HsJntOlz//TaQ== X-Received: by 2002:a63:f147:: with SMTP id o7mr47144348pgk.197.1556326288848; Fri, 26 Apr 2019 17:51:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 26 Apr 2019 17:51:24 -0700 Message-Id: <20190427005124.12756-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190427005124.12756-1-richard.henderson@linaro.org> References: <20190427005124.12756-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH 2/2] target/alpha: Fix user-only floating-point exceptions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Record the software fp control register, as set by the osf_setsysinfo syscall. Add those masked exceptions to fpcr_exc_enable. Do not raise a signal for masked fp exceptions. Signed-off-by: Richard Henderson --- linux-user/syscall_defs.h | 3 +- target/alpha/cpu.h | 42 +++++++++++++++ linux-user/syscall.c | 104 ++++++++++++++++++-------------------- target/alpha/fpu_helper.c | 21 ++++++-- target/alpha/helper.c | 20 +++++++- 5 files changed, 130 insertions(+), 60 deletions(-) diff --git a/linux-user/syscall_defs.h b/linux-user/syscall_defs.h index 12c8407144..1f5b2d18db 100644 --- a/linux-user/syscall_defs.h +++ b/linux-user/syscall_defs.h @@ -635,7 +635,8 @@ typedef struct target_siginfo { #define TARGET_FPE_FLTRES (6) /* floating point inexact result */ #define TARGET_FPE_FLTINV (7) /* floating point invalid operation */ #define TARGET_FPE_FLTSUB (8) /* subscript out of range */ -#define TARGET_NSIGFPE 8 +#define TARGET_FPE_FLTUNK (14) /* undiagnosed fp exception */ +#define TARGET_NSIGFPE 15 =20 /* * SIGSEGV si_codes diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index 63bf3618ff..d8edb86642 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -198,6 +198,8 @@ enum { #define SWCR_STATUS_DNO (1U << 22) #define SWCR_STATUS_MASK ((1U << 23) - (1U << 17)) =20 +#define SWCR_STATUS_TO_EXCSUM_SHIFT 16 + #define SWCR_MASK (SWCR_TRAP_ENABLE_MASK | SWCR_MAP_MASK | SWCR_STATUS_MA= SK) =20 /* MMU modes definitions */ @@ -235,6 +237,9 @@ struct CPUAlphaState { =20 /* The FPCR, and disassembled portions thereof. */ uint32_t fpcr; +#ifdef CONFIG_USER_ONLY + uint32_t swcr; +#endif uint32_t fpcr_exc_enable; float_status fp_status; uint8_t fpcr_dyn_round; @@ -500,4 +505,41 @@ static inline void cpu_get_tb_cpu_state(CPUAlphaState = *env, target_ulong *pc, *pflags =3D env->flags & ENV_FLAG_TB_MASK; } =20 +#ifdef CONFIG_USER_ONLY +/* Copied from linux ieee_swcr_to_fpcr. */ +static inline uint64_t alpha_ieee_swcr_to_fpcr(uint64_t swcr) +{ + uint64_t fpcr =3D 0; + + fpcr |=3D (swcr & SWCR_STATUS_MASK) << 35; + fpcr |=3D (swcr & SWCR_MAP_DMZ) << 36; + fpcr |=3D (~swcr & (SWCR_TRAP_ENABLE_INV + | SWCR_TRAP_ENABLE_DZE + | SWCR_TRAP_ENABLE_OVF)) << 48; + fpcr |=3D (~swcr & (SWCR_TRAP_ENABLE_UNF + | SWCR_TRAP_ENABLE_INE)) << 57; + fpcr |=3D (swcr & SWCR_MAP_UMZ ? FPCR_UNDZ | FPCR_UNFD : 0); + fpcr |=3D (~swcr & SWCR_TRAP_ENABLE_DNO) << 41; + + return fpcr; +} + +/* Copied from linux ieee_fpcr_to_swcr. */ +static inline uint64_t alpha_ieee_fpcr_to_swcr(uint64_t fpcr) +{ + uint64_t swcr =3D 0; + + swcr |=3D (fpcr >> 35) & SWCR_STATUS_MASK; + swcr |=3D (fpcr >> 36) & SWCR_MAP_DMZ; + swcr |=3D (~fpcr >> 48) & (SWCR_TRAP_ENABLE_INV + | SWCR_TRAP_ENABLE_DZE + | SWCR_TRAP_ENABLE_OVF); + swcr |=3D (~fpcr >> 57) & (SWCR_TRAP_ENABLE_UNF | SWCR_TRAP_ENABLE_INE= ); + swcr |=3D (fpcr >> 47) & SWCR_MAP_UMZ; + swcr |=3D (~fpcr >> 41) & SWCR_TRAP_ENABLE_DNO; + + return swcr; +} +#endif /* CONFIG_USER_ONLY */ + #endif /* ALPHA_CPU_H */ diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 96cd4bf86d..a33eb2be82 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -10182,18 +10182,11 @@ static abi_long do_syscall1(void *cpu_env, int nu= m, abi_long arg1, switch (arg1) { case TARGET_GSI_IEEE_FP_CONTROL: { - uint64_t swcr, fpcr =3D cpu_alpha_load_fpcr (cpu_env); + uint64_t fpcr =3D cpu_alpha_load_fpcr(cpu_env); + uint64_t swcr =3D ((CPUAlphaState *)cpu_env)->swcr; =20 - /* Copied from linux ieee_fpcr_to_swcr. */ - swcr =3D (fpcr >> 35) & SWCR_STATUS_MASK; - swcr |=3D (fpcr >> 36) & SWCR_MAP_DMZ; - swcr |=3D (~fpcr >> 48) & (SWCR_TRAP_ENABLE_INV - | SWCR_TRAP_ENABLE_DZE - | SWCR_TRAP_ENABLE_OVF); - swcr |=3D (~fpcr >> 57) & (SWCR_TRAP_ENABLE_UNF - | SWCR_TRAP_ENABLE_INE); - swcr |=3D (fpcr >> 47) & SWCR_MAP_UMZ; - swcr |=3D (~fpcr >> 41) & SWCR_TRAP_ENABLE_DNO; + swcr &=3D ~SWCR_STATUS_MASK; + swcr |=3D (fpcr >> 35) & SWCR_STATUS_MASK; =20 if (put_user_u64 (swcr, arg2)) return -TARGET_EFAULT; @@ -10220,25 +10213,24 @@ static abi_long do_syscall1(void *cpu_env, int nu= m, abi_long arg1, switch (arg1) { case TARGET_SSI_IEEE_FP_CONTROL: { - uint64_t swcr, fpcr, orig_fpcr; + uint64_t swcr, fpcr; =20 if (get_user_u64 (swcr, arg2)) { return -TARGET_EFAULT; } - orig_fpcr =3D cpu_alpha_load_fpcr(cpu_env); - fpcr =3D orig_fpcr & FPCR_DYN_MASK; =20 - /* Copied from linux ieee_swcr_to_fpcr. */ - fpcr |=3D (swcr & SWCR_STATUS_MASK) << 35; - fpcr |=3D (swcr & SWCR_MAP_DMZ) << 36; - fpcr |=3D (~swcr & (SWCR_TRAP_ENABLE_INV - | SWCR_TRAP_ENABLE_DZE - | SWCR_TRAP_ENABLE_OVF)) << 48; - fpcr |=3D (~swcr & (SWCR_TRAP_ENABLE_UNF - | SWCR_TRAP_ENABLE_INE)) << 57; - fpcr |=3D (swcr & SWCR_MAP_UMZ ? FPCR_UNDZ | FPCR_UNFD : 0= ); - fpcr |=3D (~swcr & SWCR_TRAP_ENABLE_DNO) << 41; + /* + * The kernel calls swcr_update_status to update the + * status bits from the fpcr at every point that it + * could be queried. Therefore, we store the status + * bits only in FPCR. + */ + ((CPUAlphaState *)cpu_env)->swcr + =3D swcr & (SWCR_TRAP_ENABLE_MASK | SWCR_MAP_MASK); =20 + fpcr =3D cpu_alpha_load_fpcr(cpu_env); + fpcr &=3D ((uint64_t)FPCR_DYN_MASK << 32); + fpcr |=3D alpha_ieee_swcr_to_fpcr(swcr); cpu_alpha_store_fpcr(cpu_env, fpcr); ret =3D 0; } @@ -10246,44 +10238,47 @@ static abi_long do_syscall1(void *cpu_env, int nu= m, abi_long arg1, =20 case TARGET_SSI_IEEE_RAISE_EXCEPTION: { - uint64_t exc, fpcr, orig_fpcr; - int si_code; + uint64_t exc, fpcr, fex; =20 if (get_user_u64(exc, arg2)) { return -TARGET_EFAULT; } - - orig_fpcr =3D cpu_alpha_load_fpcr(cpu_env); - - /* We only add to the exception status here. */ - fpcr =3D orig_fpcr | ((exc & SWCR_STATUS_MASK) << 35); - - cpu_alpha_store_fpcr(cpu_env, fpcr); - ret =3D 0; + exc &=3D SWCR_STATUS_MASK; + fpcr =3D cpu_alpha_load_fpcr(cpu_env); =20 /* Old exceptions are not signaled. */ - fpcr &=3D ~(orig_fpcr & FPCR_STATUS_MASK); + fex =3D alpha_ieee_fpcr_to_swcr(fpcr); + fex =3D exc & ~fex; + fex >>=3D SWCR_STATUS_TO_EXCSUM_SHIFT; + fex &=3D ((CPUArchState *)cpu_env)->swcr; =20 - /* If any exceptions set by this call, - and are unmasked, send a signal. */ - si_code =3D 0; - if ((fpcr & (FPCR_INE | FPCR_INED)) =3D=3D FPCR_INE) { - si_code =3D TARGET_FPE_FLTRES; - } - if ((fpcr & (FPCR_UNF | FPCR_UNFD)) =3D=3D FPCR_UNF) { - si_code =3D TARGET_FPE_FLTUND; - } - if ((fpcr & (FPCR_OVF | FPCR_OVFD)) =3D=3D FPCR_OVF) { - si_code =3D TARGET_FPE_FLTOVF; - } - if ((fpcr & (FPCR_DZE | FPCR_DZED)) =3D=3D FPCR_DZE) { - si_code =3D TARGET_FPE_FLTDIV; - } - if ((fpcr & (FPCR_INV | FPCR_INVD)) =3D=3D FPCR_INV) { - si_code =3D TARGET_FPE_FLTINV; - } - if (si_code !=3D 0) { + /* Update the hardware fpcr. */ + fpcr |=3D alpha_ieee_swcr_to_fpcr(exc); + cpu_alpha_store_fpcr(cpu_env, fpcr); + + if (fex) { + int si_code =3D TARGET_FPE_FLTUNK; target_siginfo_t info; + + if (fex & SWCR_TRAP_ENABLE_DNO) { + si_code =3D TARGET_FPE_FLTUND; + } + if (fex & SWCR_TRAP_ENABLE_INE) { + si_code =3D TARGET_FPE_FLTRES; + } + if (fex & SWCR_TRAP_ENABLE_UNF) { + si_code =3D TARGET_FPE_FLTUND; + } + if (fex & SWCR_TRAP_ENABLE_OVF) { + si_code =3D TARGET_FPE_FLTOVF; + } + if (fex & SWCR_TRAP_ENABLE_DZE) { + si_code =3D TARGET_FPE_FLTDIV; + } + if (fex & SWCR_TRAP_ENABLE_INV) { + si_code =3D TARGET_FPE_FLTINV; + } + info.si_signo =3D SIGFPE; info.si_errno =3D 0; info.si_code =3D si_code; @@ -10292,6 +10287,7 @@ static abi_long do_syscall1(void *cpu_env, int num,= abi_long arg1, queue_signal((CPUArchState *)cpu_env, info.si_signo, QEMU_SI_FAULT, &info); } + ret =3D 0; } break; =20 diff --git a/target/alpha/fpu_helper.c b/target/alpha/fpu_helper.c index 9645978aaa..62a066d902 100644 --- a/target/alpha/fpu_helper.c +++ b/target/alpha/fpu_helper.c @@ -91,10 +91,25 @@ void helper_fp_exc_raise_s(CPUAlphaState *env, uint32_t= ignore, uint32_t regno) if (exc) { env->fpcr |=3D exc; exc &=3D ~ignore; - if (exc) { - exc &=3D env->fpcr_exc_enable; - fp_exc_raise1(env, GETPC(), exc, regno, EXC_M_SWC); +#ifdef CONFIG_USER_ONLY + /* + * In user mode, the kernel's software handler only + * delivers a signal if the exception is enabled. + */ + if (!(exc & env->fpcr_exc_enable)) { + return; } +#else + /* + * In system mode, the software handler gets invoked + * for any non-ignored exception. + */ + if (!exc) { + return; + } +#endif + exc &=3D env->fpcr_exc_enable; + fp_exc_raise1(env, GETPC(), exc, regno, EXC_M_SWC); } } =20 diff --git a/target/alpha/helper.c b/target/alpha/helper.c index 31de9593b6..42d59d09e8 100644 --- a/target/alpha/helper.c +++ b/target/alpha/helper.c @@ -29,12 +29,12 @@ #define CONVERT_BIT(X, SRC, DST) \ (SRC > DST ? (X) / (SRC / DST) & (DST) : ((X) & SRC) * (DST / SRC)) =20 -uint64_t cpu_alpha_load_fpcr (CPUAlphaState *env) +uint64_t cpu_alpha_load_fpcr(CPUAlphaState *env) { return (uint64_t)env->fpcr << 32; } =20 -void cpu_alpha_store_fpcr (CPUAlphaState *env, uint64_t val) +void cpu_alpha_store_fpcr(CPUAlphaState *env, uint64_t val) { uint32_t fpcr =3D val >> 32; uint32_t t =3D 0; @@ -67,6 +67,22 @@ void cpu_alpha_store_fpcr (CPUAlphaState *env, uint64_t = val) =20 env->fpcr_flush_to_zero =3D (fpcr & FPCR_UNFD) && (fpcr & FPCR_UNDZ); env->fp_status.flush_inputs_to_zero =3D (fpcr & FPCR_DNZ) !=3D 0; + +#ifdef CONFIG_USER_ONLY + /* + * Override some of these bits with the contents of ENV->SWCR. + * In system mode, some of these would trap to the kernel, at + * which point the kernel's handler would emulate and apply + * the software exception mask. + */ + if (env->swcr & SWCR_MAP_DMZ) { + env->fp_status.flush_inputs_to_zero =3D 1; + } + if (env->swcr & SWCR_MAP_UMZ) { + env->fp_status.flush_to_zero =3D 1; + } + env->fpcr_exc_enable &=3D ~(alpha_ieee_swcr_to_fpcr(env->swcr) >> 32); +#endif } =20 uint64_t helper_load_fpcr(CPUAlphaState *env) --=20 2.17.1