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[97.113.179.147]) by smtp.gmail.com with ESMTPSA id j5sm7901762pfg.186.2019.04.26.10.24.23 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 26 Apr 2019 10:24:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ttC6fl6fwWNP1yc7/CG0jAts66wPZDS8qpyi15deS9k=; b=S8cewnN1aH16vqnqdoeeU3kRenXtU02RlOrVXpN2fChpnGBu7Bz+wUu205hgC4jxKE 1aB1mKoWzPaysPiYl2dw7yZtGs1dfpkBmi9ZQ1tyuK8NKUMUI+eXkN0js/OqtPIZsdMm MIIHu53fjqR5qcVx/+0UJJVdH7EthAIq1dfOmwdd+zn6bDpf4B5H2ssPY6yy52Z1NBUD tiGyY8KRKCcDS/vKPyJzcQXQlAB41cMQcDHxGR10A6X6yXh6OjFVhOeAmSgP6FrUOf4h 8ud2GKHXzWYCNfKoV6TWMMD2h2eKTisAlkzQWAPBbTmWp7Rx3rxEaDgKaYEnd+BMDSYY GxvA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ttC6fl6fwWNP1yc7/CG0jAts66wPZDS8qpyi15deS9k=; b=GKsnKdX54zZbX1oFRRZimgyHICkTEM6/uEoNVNVbl3/QE5E1aPSe7I7vWDO4divKd8 5KVKUIntOGwDpKZmY9Ov3HoCnKDS8j8XorKPm2m45Gg8Sm4jmrh9MaOrzuzMH/nLXQQN OkHXDh6lb47G8lZ/wnRvja4u62AheG9678DuzP6D6uWqSDDaGYKF844xXN8awM3Euz0/ XpJLv6ad/G+u9HmxxY7QGE23bPcMSolvYmd28saThJoiU1CWiJocb1DTQ9uSXYc2Zh7F AHy46LhvQkov3BXKM3m11irtyvLv2ayMQ1H9oUS2iC1LKMx3WC7pCfpcJgUqodxmxyeR uQ/w== X-Gm-Message-State: APjAAAXHL6F9XBym2Yu9KCYZee+UVgpxA2xHfeLZAf/EhOhbCMoySaDw 42gLGlHyy7VuDFbfbTZSahJfgowfS7E= X-Google-Smtp-Source: APXvYqyf0qQem+4VWTzykxblVHHRJehgl6VT+6WjUd3j5wB0h+ceBheRFfH6taOPHAaIy8oH4mdvpQ== X-Received: by 2002:a63:6849:: with SMTP id d70mr43407174pgc.21.1556299464851; Fri, 26 Apr 2019 10:24:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 26 Apr 2019 10:24:07 -0700 Message-Id: <20190426172421.27133-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190426172421.27133-1-richard.henderson@linaro.org> References: <20190426172421.27133-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::52b Subject: [Qemu-devel] [PULL 01/15] tcg: Implement tcg_gen_extract2_{i32, i64} X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, David Hildenbrand Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: David Hildenbrand Will be helpful for s390x. Input 128 bit and output 64 bit only, which is sufficient for now. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Signed-off-by: David Hildenbrand Message-Id: <20190225154204.26751-1-david@redhat.com> [rth: Add matching tcg_gen_extract2_i32.] Signed-off-by: Richard Henderson --- tcg/tcg-op.h | 6 ++++++ tcg/tcg-op.c | 44 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 50 insertions(+) diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h index d3e51b15af..1f1824c30a 100644 --- a/tcg/tcg-op.h +++ b/tcg/tcg-op.h @@ -308,6 +308,8 @@ void tcg_gen_extract_i32(TCGv_i32 ret, TCGv_i32 arg, unsigned int ofs, unsigned int len); void tcg_gen_sextract_i32(TCGv_i32 ret, TCGv_i32 arg, unsigned int ofs, unsigned int len); +void tcg_gen_extract2_i32(TCGv_i32 ret, TCGv_i32 al, TCGv_i32 ah, + unsigned int ofs); void tcg_gen_brcond_i32(TCGCond cond, TCGv_i32 arg1, TCGv_i32 arg2, TCGLab= el *); void tcg_gen_brcondi_i32(TCGCond cond, TCGv_i32 arg1, int32_t arg2, TCGLab= el *); void tcg_gen_setcond_i32(TCGCond cond, TCGv_i32 ret, @@ -501,6 +503,8 @@ void tcg_gen_extract_i64(TCGv_i64 ret, TCGv_i64 arg, unsigned int ofs, unsigned int len); void tcg_gen_sextract_i64(TCGv_i64 ret, TCGv_i64 arg, unsigned int ofs, unsigned int len); +void tcg_gen_extract2_i64(TCGv_i64 ret, TCGv_i64 al, TCGv_i64 ah, + unsigned int ofs); void tcg_gen_brcond_i64(TCGCond cond, TCGv_i64 arg1, TCGv_i64 arg2, TCGLab= el *); void tcg_gen_brcondi_i64(TCGCond cond, TCGv_i64 arg1, int64_t arg2, TCGLab= el *); void tcg_gen_setcond_i64(TCGCond cond, TCGv_i64 ret, @@ -1068,6 +1072,7 @@ void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr base, TCGAr= g offset, TCGType t); #define tcg_gen_deposit_z_tl tcg_gen_deposit_z_i64 #define tcg_gen_extract_tl tcg_gen_extract_i64 #define tcg_gen_sextract_tl tcg_gen_sextract_i64 +#define tcg_gen_extract2_tl tcg_gen_extract2_i64 #define tcg_const_tl tcg_const_i64 #define tcg_const_local_tl tcg_const_local_i64 #define tcg_gen_movcond_tl tcg_gen_movcond_i64 @@ -1178,6 +1183,7 @@ void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr base, TCGAr= g offset, TCGType t); #define tcg_gen_deposit_z_tl tcg_gen_deposit_z_i32 #define tcg_gen_extract_tl tcg_gen_extract_i32 #define tcg_gen_sextract_tl tcg_gen_sextract_i32 +#define tcg_gen_extract2_tl tcg_gen_extract2_i32 #define tcg_const_tl tcg_const_i32 #define tcg_const_local_tl tcg_const_local_i32 #define tcg_gen_movcond_tl tcg_gen_movcond_i32 diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 1bd7ef24af..7c56c92c8e 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -809,6 +809,28 @@ void tcg_gen_sextract_i32(TCGv_i32 ret, TCGv_i32 arg, tcg_gen_sari_i32(ret, ret, 32 - len); } =20 +/* + * Extract 32-bits from a 64-bit input, ah:al, starting from ofs. + * Unlike tcg_gen_extract_i32 above, len is fixed at 32. + */ +void tcg_gen_extract2_i32(TCGv_i32 ret, TCGv_i32 al, TCGv_i32 ah, + unsigned int ofs) +{ + tcg_debug_assert(ofs <=3D 32); + if (ofs =3D=3D 0) { + tcg_gen_mov_i32(ret, al); + } else if (ofs =3D=3D 32) { + tcg_gen_mov_i32(ret, ah); + } else if (al =3D=3D ah) { + tcg_gen_rotri_i32(ret, al, ofs); + } else { + TCGv_i32 t0 =3D tcg_temp_new_i32(); + tcg_gen_shri_i32(t0, al, ofs); + tcg_gen_deposit_i32(ret, t0, ah, 32 - ofs, ofs); + tcg_temp_free_i32(t0); + } +} + void tcg_gen_movcond_i32(TCGCond cond, TCGv_i32 ret, TCGv_i32 c1, TCGv_i32 c2, TCGv_i32 v1, TCGv_i32 v2) { @@ -2297,6 +2319,28 @@ void tcg_gen_sextract_i64(TCGv_i64 ret, TCGv_i64 arg, tcg_gen_sari_i64(ret, ret, 64 - len); } =20 +/* + * Extract 64 bits from a 128-bit input, ah:al, starting from ofs. + * Unlike tcg_gen_extract_i64 above, len is fixed at 64. + */ +void tcg_gen_extract2_i64(TCGv_i64 ret, TCGv_i64 al, TCGv_i64 ah, + unsigned int ofs) +{ + tcg_debug_assert(ofs <=3D 64); + if (ofs =3D=3D 0) { + tcg_gen_mov_i64(ret, al); + } else if (ofs =3D=3D 64) { + tcg_gen_mov_i64(ret, ah); + } else if (al =3D=3D ah) { + tcg_gen_rotri_i64(ret, al, ofs); + } else { + TCGv_i64 t0 =3D tcg_temp_new_i64(); + tcg_gen_shri_i64(t0, al, ofs); + tcg_gen_deposit_i64(ret, t0, ah, 64 - ofs, ofs); + tcg_temp_free_i64(t0); + } +} + void tcg_gen_movcond_i64(TCGCond cond, TCGv_i64 ret, TCGv_i64 c1, TCGv_i64 c2, TCGv_i64 v1, TCGv_i64 v2) { --=20 2.17.1