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[97.113.179.147]) by smtp.gmail.com with ESMTPSA id j5sm7901762pfg.186.2019.04.26.10.24.23 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 26 Apr 2019 10:24:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ttC6fl6fwWNP1yc7/CG0jAts66wPZDS8qpyi15deS9k=; b=S8cewnN1aH16vqnqdoeeU3kRenXtU02RlOrVXpN2fChpnGBu7Bz+wUu205hgC4jxKE 1aB1mKoWzPaysPiYl2dw7yZtGs1dfpkBmi9ZQ1tyuK8NKUMUI+eXkN0js/OqtPIZsdMm MIIHu53fjqR5qcVx/+0UJJVdH7EthAIq1dfOmwdd+zn6bDpf4B5H2ssPY6yy52Z1NBUD tiGyY8KRKCcDS/vKPyJzcQXQlAB41cMQcDHxGR10A6X6yXh6OjFVhOeAmSgP6FrUOf4h 8ud2GKHXzWYCNfKoV6TWMMD2h2eKTisAlkzQWAPBbTmWp7Rx3rxEaDgKaYEnd+BMDSYY GxvA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ttC6fl6fwWNP1yc7/CG0jAts66wPZDS8qpyi15deS9k=; b=GKsnKdX54zZbX1oFRRZimgyHICkTEM6/uEoNVNVbl3/QE5E1aPSe7I7vWDO4divKd8 5KVKUIntOGwDpKZmY9Ov3HoCnKDS8j8XorKPm2m45Gg8Sm4jmrh9MaOrzuzMH/nLXQQN OkHXDh6lb47G8lZ/wnRvja4u62AheG9678DuzP6D6uWqSDDaGYKF844xXN8awM3Euz0/ XpJLv6ad/G+u9HmxxY7QGE23bPcMSolvYmd28saThJoiU1CWiJocb1DTQ9uSXYc2Zh7F AHy46LhvQkov3BXKM3m11irtyvLv2ayMQ1H9oUS2iC1LKMx3WC7pCfpcJgUqodxmxyeR uQ/w== X-Gm-Message-State: APjAAAXHL6F9XBym2Yu9KCYZee+UVgpxA2xHfeLZAf/EhOhbCMoySaDw 42gLGlHyy7VuDFbfbTZSahJfgowfS7E= X-Google-Smtp-Source: APXvYqyf0qQem+4VWTzykxblVHHRJehgl6VT+6WjUd3j5wB0h+ceBheRFfH6taOPHAaIy8oH4mdvpQ== X-Received: by 2002:a63:6849:: with SMTP id d70mr43407174pgc.21.1556299464851; Fri, 26 Apr 2019 10:24:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 26 Apr 2019 10:24:07 -0700 Message-Id: <20190426172421.27133-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190426172421.27133-1-richard.henderson@linaro.org> References: <20190426172421.27133-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::52b Subject: [Qemu-devel] [PULL 01/15] tcg: Implement tcg_gen_extract2_{i32, i64} X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, David Hildenbrand Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: David Hildenbrand Will be helpful for s390x. Input 128 bit and output 64 bit only, which is sufficient for now. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Signed-off-by: David Hildenbrand Message-Id: <20190225154204.26751-1-david@redhat.com> [rth: Add matching tcg_gen_extract2_i32.] Signed-off-by: Richard Henderson --- tcg/tcg-op.h | 6 ++++++ tcg/tcg-op.c | 44 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 50 insertions(+) diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h index d3e51b15af..1f1824c30a 100644 --- a/tcg/tcg-op.h +++ b/tcg/tcg-op.h @@ -308,6 +308,8 @@ void tcg_gen_extract_i32(TCGv_i32 ret, TCGv_i32 arg, unsigned int ofs, unsigned int len); void tcg_gen_sextract_i32(TCGv_i32 ret, TCGv_i32 arg, unsigned int ofs, unsigned int len); +void tcg_gen_extract2_i32(TCGv_i32 ret, TCGv_i32 al, TCGv_i32 ah, + unsigned int ofs); void tcg_gen_brcond_i32(TCGCond cond, TCGv_i32 arg1, TCGv_i32 arg2, TCGLab= el *); void tcg_gen_brcondi_i32(TCGCond cond, TCGv_i32 arg1, int32_t arg2, TCGLab= el *); void tcg_gen_setcond_i32(TCGCond cond, TCGv_i32 ret, @@ -501,6 +503,8 @@ void tcg_gen_extract_i64(TCGv_i64 ret, TCGv_i64 arg, unsigned int ofs, unsigned int len); void tcg_gen_sextract_i64(TCGv_i64 ret, TCGv_i64 arg, unsigned int ofs, unsigned int len); +void tcg_gen_extract2_i64(TCGv_i64 ret, TCGv_i64 al, TCGv_i64 ah, + unsigned int ofs); void tcg_gen_brcond_i64(TCGCond cond, TCGv_i64 arg1, TCGv_i64 arg2, TCGLab= el *); void tcg_gen_brcondi_i64(TCGCond cond, TCGv_i64 arg1, int64_t arg2, TCGLab= el *); void tcg_gen_setcond_i64(TCGCond cond, TCGv_i64 ret, @@ -1068,6 +1072,7 @@ void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr base, TCGAr= g offset, TCGType t); #define tcg_gen_deposit_z_tl tcg_gen_deposit_z_i64 #define tcg_gen_extract_tl tcg_gen_extract_i64 #define tcg_gen_sextract_tl tcg_gen_sextract_i64 +#define tcg_gen_extract2_tl tcg_gen_extract2_i64 #define tcg_const_tl tcg_const_i64 #define tcg_const_local_tl tcg_const_local_i64 #define tcg_gen_movcond_tl tcg_gen_movcond_i64 @@ -1178,6 +1183,7 @@ void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr base, TCGAr= g offset, TCGType t); #define tcg_gen_deposit_z_tl tcg_gen_deposit_z_i32 #define tcg_gen_extract_tl tcg_gen_extract_i32 #define tcg_gen_sextract_tl tcg_gen_sextract_i32 +#define tcg_gen_extract2_tl tcg_gen_extract2_i32 #define tcg_const_tl tcg_const_i32 #define tcg_const_local_tl tcg_const_local_i32 #define tcg_gen_movcond_tl tcg_gen_movcond_i32 diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 1bd7ef24af..7c56c92c8e 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -809,6 +809,28 @@ void tcg_gen_sextract_i32(TCGv_i32 ret, TCGv_i32 arg, tcg_gen_sari_i32(ret, ret, 32 - len); } =20 +/* + * Extract 32-bits from a 64-bit input, ah:al, starting from ofs. + * Unlike tcg_gen_extract_i32 above, len is fixed at 32. + */ +void tcg_gen_extract2_i32(TCGv_i32 ret, TCGv_i32 al, TCGv_i32 ah, + unsigned int ofs) +{ + tcg_debug_assert(ofs <=3D 32); + if (ofs =3D=3D 0) { + tcg_gen_mov_i32(ret, al); + } else if (ofs =3D=3D 32) { + tcg_gen_mov_i32(ret, ah); + } else if (al =3D=3D ah) { + tcg_gen_rotri_i32(ret, al, ofs); + } else { + TCGv_i32 t0 =3D tcg_temp_new_i32(); + tcg_gen_shri_i32(t0, al, ofs); + tcg_gen_deposit_i32(ret, t0, ah, 32 - ofs, ofs); + tcg_temp_free_i32(t0); + } +} + void tcg_gen_movcond_i32(TCGCond cond, TCGv_i32 ret, TCGv_i32 c1, TCGv_i32 c2, TCGv_i32 v1, TCGv_i32 v2) { @@ -2297,6 +2319,28 @@ void tcg_gen_sextract_i64(TCGv_i64 ret, TCGv_i64 arg, tcg_gen_sari_i64(ret, ret, 64 - len); } =20 +/* + * Extract 64 bits from a 128-bit input, ah:al, starting from ofs. + * Unlike tcg_gen_extract_i64 above, len is fixed at 64. + */ +void tcg_gen_extract2_i64(TCGv_i64 ret, TCGv_i64 al, TCGv_i64 ah, + unsigned int ofs) +{ + tcg_debug_assert(ofs <=3D 64); + if (ofs =3D=3D 0) { + tcg_gen_mov_i64(ret, al); + } else if (ofs =3D=3D 64) { + tcg_gen_mov_i64(ret, ah); + } else if (al =3D=3D ah) { + tcg_gen_rotri_i64(ret, al, ofs); + } else { + TCGv_i64 t0 =3D tcg_temp_new_i64(); + tcg_gen_shri_i64(t0, al, ofs); + tcg_gen_deposit_i64(ret, t0, ah, 64 - ofs, ofs); + tcg_temp_free_i64(t0); + } +} + void tcg_gen_movcond_i64(TCGCond cond, TCGv_i64 ret, TCGv_i64 c1, TCGv_i64 c2, TCGv_i64 v1, TCGv_i64 v2) { --=20 2.17.1 From nobody Sun Jun 2 07:52:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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[97.113.179.147]) by smtp.gmail.com with ESMTPSA id j5sm7901762pfg.186.2019.04.26.10.24.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 26 Apr 2019 10:24:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=KjC3dR2LZ7KhCUhnKxH1B6r5HwzGCgRo7EFbENWKPC0=; b=HsOEGT2j/5Bb+1HmIF8ZqSCHrk/QmAdQRr6CWaNcvfajqMUxeM0Om0ZEmJqt/e5B6O CMyC6FI79FWaajeR9umwQB4u9Gg8V0YEMicqZD5ZDDlLUPjwXQfhDugSGsVkdoe88W7O oJlNT9VWN7gpJv7f0Eq1xODCSv6r0E0zl8Lqg3Tac+lsL7wgfuWGPRiqO+vlLeKgH18m 4Q7uIUI1/UB8YNpK1ne9gg0zlWA05I+TFWwoihEg8CJJG/wJPbdDfokYdONSSd8N3HM+ HqeoxDyLlxlNapkwXs+IKgXQQiATyNH+sIN6lEzPZaB2G7hF2J8/Ir7lh34Y5qYlyMEG hL+g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=KjC3dR2LZ7KhCUhnKxH1B6r5HwzGCgRo7EFbENWKPC0=; b=GJKL0fJHP2YNNXQ7piGh0i8pe3Elqg6pbo+itG41yr0rP9Pcj4hCfat5IHPYypeu// V/jPPfY/XBHonYwrck2ABogeRFeM66Z6IYt6qu5KcDEIvecJHw0HbtTn7ezdPRn0k1pN t+pgM/HQirGuCOfmarKLvpBT9jAQr5S0yjWWYtSni9Up+7mxMxhcosV9H9jzErWPzEDw 1IpCM82zgUjKqhqcsCSWNHhCkRGpDTH3PPHSXAeKFDDlCMQpiaiJTwLXWZgEf1AiZrn9 ws5K+bBbhULHfxbmvTEdoHcX9noEiLyUACIgsi7E1HMJ6yEpZhzdICpQNXeDIdwGJlgE Vebg== X-Gm-Message-State: APjAAAUFGFotWaxz6c3syj+MJHIkwLFiQPAcI7DMBf4W7Ztc2+AHwYxr Mm1IbhcE3+YlYKgbMI2DJxiX6SA7PFQ= X-Google-Smtp-Source: APXvYqzGR5La8SAPkiysfc2eW9lpCJpOCnSuFwTx2376AHO9jl9tyXSee3F5fzAbakcj/lvTsC3ZkA== X-Received: by 2002:a63:5466:: with SMTP id e38mr45529970pgm.340.1556299465957; Fri, 26 Apr 2019 10:24:25 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 26 Apr 2019 10:24:08 -0700 Message-Id: <20190426172421.27133-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190426172421.27133-1-richard.henderson@linaro.org> References: <20190426172421.27133-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::441 Subject: [Qemu-devel] [PULL 02/15] tcg: Add INDEX_op_extract2_{i32,i64} X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This will let backends implement the double-word shift operation. Reviewed-by: David Hildenbrand Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.h | 2 ++ tcg/arm/tcg-target.h | 1 + tcg/i386/tcg-target.h | 2 ++ tcg/mips/tcg-target.h | 2 ++ tcg/ppc/tcg-target.h | 2 ++ tcg/riscv/tcg-target.h | 2 ++ tcg/s390/tcg-target.h | 2 ++ tcg/sparc/tcg-target.h | 2 ++ tcg/tcg-opc.h | 2 ++ tcg/tcg.h | 1 + tcg/tci/tcg-target.h | 2 ++ tcg/optimize.c | 16 ++++++++++++++++ tcg/tcg-op.c | 4 ++++ tcg/tcg.c | 4 ++++ tcg/README | 7 +++++++ 15 files changed, 51 insertions(+) diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index 2d93cf404e..6600a54a02 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -77,6 +77,7 @@ typedef enum { #define TCG_TARGET_HAS_deposit_i32 1 #define TCG_TARGET_HAS_extract_i32 1 #define TCG_TARGET_HAS_sextract_i32 1 +#define TCG_TARGET_HAS_extract2_i32 0 #define TCG_TARGET_HAS_movcond_i32 1 #define TCG_TARGET_HAS_add2_i32 1 #define TCG_TARGET_HAS_sub2_i32 1 @@ -113,6 +114,7 @@ typedef enum { #define TCG_TARGET_HAS_deposit_i64 1 #define TCG_TARGET_HAS_extract_i64 1 #define TCG_TARGET_HAS_sextract_i64 1 +#define TCG_TARGET_HAS_extract2_i64 0 #define TCG_TARGET_HAS_movcond_i64 1 #define TCG_TARGET_HAS_add2_i64 1 #define TCG_TARGET_HAS_sub2_i64 1 diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index 16172f73a3..4ee6c98958 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -116,6 +116,7 @@ extern bool use_idiv_instructions; #define TCG_TARGET_HAS_deposit_i32 use_armv7_instructions #define TCG_TARGET_HAS_extract_i32 use_armv7_instructions #define TCG_TARGET_HAS_sextract_i32 use_armv7_instructions +#define TCG_TARGET_HAS_extract2_i32 0 #define TCG_TARGET_HAS_movcond_i32 1 #define TCG_TARGET_HAS_mulu2_i32 1 #define TCG_TARGET_HAS_muls2_i32 1 diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 7995fe3eab..2c58eaa9ed 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -124,6 +124,7 @@ extern bool have_avx2; #define TCG_TARGET_HAS_deposit_i32 1 #define TCG_TARGET_HAS_extract_i32 1 #define TCG_TARGET_HAS_sextract_i32 1 +#define TCG_TARGET_HAS_extract2_i32 0 #define TCG_TARGET_HAS_movcond_i32 1 #define TCG_TARGET_HAS_add2_i32 1 #define TCG_TARGET_HAS_sub2_i32 1 @@ -162,6 +163,7 @@ extern bool have_avx2; #define TCG_TARGET_HAS_deposit_i64 1 #define TCG_TARGET_HAS_extract_i64 1 #define TCG_TARGET_HAS_sextract_i64 0 +#define TCG_TARGET_HAS_extract2_i64 0 #define TCG_TARGET_HAS_movcond_i64 1 #define TCG_TARGET_HAS_add2_i64 1 #define TCG_TARGET_HAS_sub2_i64 1 diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index 5cb8672470..c6b091d849 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -162,6 +162,7 @@ extern bool use_mips32r2_instructions; #define TCG_TARGET_HAS_deposit_i32 use_mips32r2_instructions #define TCG_TARGET_HAS_extract_i32 use_mips32r2_instructions #define TCG_TARGET_HAS_sextract_i32 0 +#define TCG_TARGET_HAS_extract2_i32 0 #define TCG_TARGET_HAS_ext8s_i32 use_mips32r2_instructions #define TCG_TARGET_HAS_ext16s_i32 use_mips32r2_instructions #define TCG_TARGET_HAS_rot_i32 use_mips32r2_instructions @@ -177,6 +178,7 @@ extern bool use_mips32r2_instructions; #define TCG_TARGET_HAS_deposit_i64 use_mips32r2_instructions #define TCG_TARGET_HAS_extract_i64 use_mips32r2_instructions #define TCG_TARGET_HAS_sextract_i64 0 +#define TCG_TARGET_HAS_extract2_i64 0 #define TCG_TARGET_HAS_ext8s_i64 use_mips32r2_instructions #define TCG_TARGET_HAS_ext16s_i64 use_mips32r2_instructions #define TCG_TARGET_HAS_rot_i64 use_mips32r2_instructions diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index 52c1bb04b1..7627fb62d3 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -77,6 +77,7 @@ extern bool have_isa_3_00; #define TCG_TARGET_HAS_deposit_i32 1 #define TCG_TARGET_HAS_extract_i32 1 #define TCG_TARGET_HAS_sextract_i32 0 +#define TCG_TARGET_HAS_extract2_i32 0 #define TCG_TARGET_HAS_movcond_i32 1 #define TCG_TARGET_HAS_mulu2_i32 0 #define TCG_TARGET_HAS_muls2_i32 0 @@ -115,6 +116,7 @@ extern bool have_isa_3_00; #define TCG_TARGET_HAS_deposit_i64 1 #define TCG_TARGET_HAS_extract_i64 1 #define TCG_TARGET_HAS_sextract_i64 0 +#define TCG_TARGET_HAS_extract2_i64 0 #define TCG_TARGET_HAS_movcond_i64 1 #define TCG_TARGET_HAS_add2_i64 1 #define TCG_TARGET_HAS_sub2_i64 1 diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index 60918cacb4..032439d806 100644 --- a/tcg/riscv/tcg-target.h +++ b/tcg/riscv/tcg-target.h @@ -93,6 +93,7 @@ typedef enum { #define TCG_TARGET_HAS_deposit_i32 0 #define TCG_TARGET_HAS_extract_i32 0 #define TCG_TARGET_HAS_sextract_i32 0 +#define TCG_TARGET_HAS_extract2_i32 0 #define TCG_TARGET_HAS_add2_i32 1 #define TCG_TARGET_HAS_sub2_i32 1 #define TCG_TARGET_HAS_mulu2_i32 0 @@ -128,6 +129,7 @@ typedef enum { #define TCG_TARGET_HAS_deposit_i64 0 #define TCG_TARGET_HAS_extract_i64 0 #define TCG_TARGET_HAS_sextract_i64 0 +#define TCG_TARGET_HAS_extract2_i64 0 #define TCG_TARGET_HAS_extrl_i64_i32 1 #define TCG_TARGET_HAS_extrh_i64_i32 1 #define TCG_TARGET_HAS_ext8s_i64 1 diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h index 853ed6e7aa..07accabbd1 100644 --- a/tcg/s390/tcg-target.h +++ b/tcg/s390/tcg-target.h @@ -85,6 +85,7 @@ extern uint64_t s390_facilities; #define TCG_TARGET_HAS_deposit_i32 (s390_facilities & FACILITY_GEN_INST= _EXT) #define TCG_TARGET_HAS_extract_i32 (s390_facilities & FACILITY_GEN_INST= _EXT) #define TCG_TARGET_HAS_sextract_i32 0 +#define TCG_TARGET_HAS_extract2_i32 0 #define TCG_TARGET_HAS_movcond_i32 1 #define TCG_TARGET_HAS_add2_i32 1 #define TCG_TARGET_HAS_sub2_i32 1 @@ -121,6 +122,7 @@ extern uint64_t s390_facilities; #define TCG_TARGET_HAS_deposit_i64 (s390_facilities & FACILITY_GEN_INST= _EXT) #define TCG_TARGET_HAS_extract_i64 (s390_facilities & FACILITY_GEN_INST= _EXT) #define TCG_TARGET_HAS_sextract_i64 0 +#define TCG_TARGET_HAS_extract2_i64 0 #define TCG_TARGET_HAS_movcond_i64 1 #define TCG_TARGET_HAS_add2_i64 1 #define TCG_TARGET_HAS_sub2_i64 1 diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h index a0ed2a3342..633841ebf2 100644 --- a/tcg/sparc/tcg-target.h +++ b/tcg/sparc/tcg-target.h @@ -116,6 +116,7 @@ extern bool use_vis3_instructions; #define TCG_TARGET_HAS_deposit_i32 0 #define TCG_TARGET_HAS_extract_i32 0 #define TCG_TARGET_HAS_sextract_i32 0 +#define TCG_TARGET_HAS_extract2_i32 0 #define TCG_TARGET_HAS_movcond_i32 1 #define TCG_TARGET_HAS_add2_i32 1 #define TCG_TARGET_HAS_sub2_i32 1 @@ -153,6 +154,7 @@ extern bool use_vis3_instructions; #define TCG_TARGET_HAS_deposit_i64 0 #define TCG_TARGET_HAS_extract_i64 0 #define TCG_TARGET_HAS_sextract_i64 0 +#define TCG_TARGET_HAS_extract2_i64 0 #define TCG_TARGET_HAS_movcond_i64 1 #define TCG_TARGET_HAS_add2_i64 1 #define TCG_TARGET_HAS_sub2_i64 1 diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h index 4e0238ad1a..1bad6e4208 100644 --- a/tcg/tcg-opc.h +++ b/tcg/tcg-opc.h @@ -79,6 +79,7 @@ DEF(rotr_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rot_i32)) DEF(deposit_i32, 1, 2, 2, IMPL(TCG_TARGET_HAS_deposit_i32)) DEF(extract_i32, 1, 1, 2, IMPL(TCG_TARGET_HAS_extract_i32)) DEF(sextract_i32, 1, 1, 2, IMPL(TCG_TARGET_HAS_sextract_i32)) +DEF(extract2_i32, 1, 2, 1, IMPL(TCG_TARGET_HAS_extract2_i32)) =20 DEF(brcond_i32, 0, 2, 2, TCG_OPF_BB_END) =20 @@ -146,6 +147,7 @@ DEF(rotr_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rot= _i64)) DEF(deposit_i64, 1, 2, 2, IMPL64 | IMPL(TCG_TARGET_HAS_deposit_i64)) DEF(extract_i64, 1, 1, 2, IMPL64 | IMPL(TCG_TARGET_HAS_extract_i64)) DEF(sextract_i64, 1, 1, 2, IMPL64 | IMPL(TCG_TARGET_HAS_sextract_i64)) +DEF(extract2_i64, 1, 2, 1, IMPL64 | IMPL(TCG_TARGET_HAS_extract2_i64)) =20 /* size changing ops */ DEF(ext_i32_i64, 1, 1, 0, IMPL64) diff --git a/tcg/tcg.h b/tcg/tcg.h index a394d78237..50de1cdda3 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -125,6 +125,7 @@ typedef uint64_t TCGRegSet; #define TCG_TARGET_HAS_deposit_i64 0 #define TCG_TARGET_HAS_extract_i64 0 #define TCG_TARGET_HAS_sextract_i64 0 +#define TCG_TARGET_HAS_extract2_i64 0 #define TCG_TARGET_HAS_movcond_i64 0 #define TCG_TARGET_HAS_add2_i64 0 #define TCG_TARGET_HAS_sub2_i64 0 diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index 086f34e69a..8b90ab71cb 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -71,6 +71,7 @@ #define TCG_TARGET_HAS_deposit_i32 1 #define TCG_TARGET_HAS_extract_i32 0 #define TCG_TARGET_HAS_sextract_i32 0 +#define TCG_TARGET_HAS_extract2_i32 0 #define TCG_TARGET_HAS_eqv_i32 0 #define TCG_TARGET_HAS_nand_i32 0 #define TCG_TARGET_HAS_nor_i32 0 @@ -97,6 +98,7 @@ #define TCG_TARGET_HAS_deposit_i64 1 #define TCG_TARGET_HAS_extract_i64 0 #define TCG_TARGET_HAS_sextract_i64 0 +#define TCG_TARGET_HAS_extract2_i64 0 #define TCG_TARGET_HAS_div_i64 0 #define TCG_TARGET_HAS_rem_i64 0 #define TCG_TARGET_HAS_ext8s_i64 1 diff --git a/tcg/optimize.c b/tcg/optimize.c index 01e80c3e46..5150c38a25 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -1202,6 +1202,22 @@ void tcg_optimize(TCGContext *s) } goto do_default; =20 + CASE_OP_32_64(extract2): + if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) { + TCGArg v1 =3D arg_info(op->args[1])->val; + TCGArg v2 =3D arg_info(op->args[2])->val; + + if (opc =3D=3D INDEX_op_extract2_i64) { + tmp =3D (v1 >> op->args[3]) | (v2 << (64 - op->args[3]= )); + } else { + tmp =3D (v1 >> op->args[3]) | (v2 << (32 - op->args[3]= )); + tmp =3D (int32_t)tmp; + } + tcg_opt_gen_movi(s, op, op->args[0], tmp); + break; + } + goto do_default; + CASE_OP_32_64(setcond): tmp =3D do_constant_folding_cond(opc, op->args[1], op->args[2], op->args[3]); diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 7c56c92c8e..deacc63e3b 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -823,6 +823,8 @@ void tcg_gen_extract2_i32(TCGv_i32 ret, TCGv_i32 al, TC= Gv_i32 ah, tcg_gen_mov_i32(ret, ah); } else if (al =3D=3D ah) { tcg_gen_rotri_i32(ret, al, ofs); + } else if (TCG_TARGET_HAS_extract2_i32) { + tcg_gen_op4i_i32(INDEX_op_extract2_i32, ret, al, ah, ofs); } else { TCGv_i32 t0 =3D tcg_temp_new_i32(); tcg_gen_shri_i32(t0, al, ofs); @@ -2333,6 +2335,8 @@ void tcg_gen_extract2_i64(TCGv_i64 ret, TCGv_i64 al, = TCGv_i64 ah, tcg_gen_mov_i64(ret, ah); } else if (al =3D=3D ah) { tcg_gen_rotri_i64(ret, al, ofs); + } else if (TCG_TARGET_HAS_extract2_i64) { + tcg_gen_op4i_i64(INDEX_op_extract2_i64, ret, al, ah, ofs); } else { TCGv_i64 t0 =3D tcg_temp_new_i64(); tcg_gen_shri_i64(t0, al, ofs); diff --git a/tcg/tcg.c b/tcg/tcg.c index 6a22c8746c..c0730f119f 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1426,6 +1426,8 @@ bool tcg_op_supported(TCGOpcode op) return TCG_TARGET_HAS_extract_i32; case INDEX_op_sextract_i32: return TCG_TARGET_HAS_sextract_i32; + case INDEX_op_extract2_i32: + return TCG_TARGET_HAS_extract2_i32; case INDEX_op_add2_i32: return TCG_TARGET_HAS_add2_i32; case INDEX_op_sub2_i32: @@ -1523,6 +1525,8 @@ bool tcg_op_supported(TCGOpcode op) return TCG_TARGET_HAS_extract_i64; case INDEX_op_sextract_i64: return TCG_TARGET_HAS_sextract_i64; + case INDEX_op_extract2_i64: + return TCG_TARGET_HAS_extract2_i64; case INDEX_op_extrl_i64_i32: return TCG_TARGET_HAS_extrl_i64_i32; case INDEX_op_extrh_i64_i32: diff --git a/tcg/README b/tcg/README index 603f4df659..c30e5418a6 100644 --- a/tcg/README +++ b/tcg/README @@ -343,6 +343,13 @@ at bit 8. This operation would be equivalent to =20 (using an arithmetic right shift). =20 +* extract2_i32/i64 dest, t1, t2, pos + +For N =3D {32,64}, extract an N-bit quantity from the concatenation +of t2:t1, beginning at pos. The tcg_gen_extract2_{i32,i64} expander +accepts 0 <=3D pos <=3D N as inputs. The backend code generator will +not see either 0 or N as inputs for these opcodes. + * extrl_i64_i32 t0, t1 =20 For 64-bit hosts only, extract the low 32-bits of input T1 and place it --=20 2.17.1 From nobody Sun Jun 2 07:52:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1556299767; cv=none; d=zoho.com; s=zohoarc; b=coCOE+SqaVgsCQaJTStzjiGcOYnQI4JFhg5gWPEKuRQg16AFhJljkdvqjvsAgKV+giIXRiUzuh8iHyb2hN43mUR+2FrrFZgl0LiHaB67AAA8z6+8gLlGJ8iUeIRiijgLgFywS6KDlUozM54x8QzqBA7o3XMpKLK/YTnwjpD8J+c= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1556299767; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=KIh7KhTzHMM8NImyp8JEXp0cQ6SpWRDrI20KK0RXxhw=; b=JAnFJK0Xi7iZzhzE2cxPzF9LhOd0MEqaUV6DSbIq5xvj/Ipg7BoK2IuXEJasYTElCG/4g3Lcd9JHdrwhlsd+b7IudFUx5weuICTf/pg6+wdC0ac4enbJ4YkfBKCJv/s9/+jLd7xMXiDIWw02bP7qSFBQ2xuJZGxV/0KJy50L7HA= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1556299767799435.02363957077876; Fri, 26 Apr 2019 10:29:27 -0700 (PDT) Received: from localhost ([127.0.0.1]:49953 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hK4f6-0003kg-Qx for importer@patchew.org; Fri, 26 Apr 2019 13:29:24 -0400 Received: from eggs.gnu.org ([209.51.188.92]:47938) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hK4aN-0008Pw-1R for qemu-devel@nongnu.org; Fri, 26 Apr 2019 13:24:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hK4aM-0006K6-0w for qemu-devel@nongnu.org; Fri, 26 Apr 2019 13:24:31 -0400 Received: from mail-pg1-x536.google.com ([2607:f8b0:4864:20::536]:33395) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hK4aL-0006H6-QN for qemu-devel@nongnu.org; Fri, 26 Apr 2019 13:24:29 -0400 Received: by mail-pg1-x536.google.com with SMTP id k19so1949076pgh.0 for ; Fri, 26 Apr 2019 10:24:29 -0700 (PDT) Received: from localhost.localdomain (97-113-179-147.tukw.qwest.net. [97.113.179.147]) by smtp.gmail.com with ESMTPSA id j5sm7901762pfg.186.2019.04.26.10.24.25 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 26 Apr 2019 10:24:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=KIh7KhTzHMM8NImyp8JEXp0cQ6SpWRDrI20KK0RXxhw=; b=RUD6SG1ZAQoiyJlACWpf6TIBHo4ZYQM5bO68uDlgzjPw0tIRxlfZo3cMdJ27zJTdkE iqF4NYY1HDFzR86HDPkr8ZJ+dgJL+gXPSHZpLLF4obU1EkwYXpbGWiYK0qktKU405NBf eUBv9g35G9dTj7jbB1KkGtpMhz9XztsedbpArL6IXdOA138N0KYK2dTAlGytU1XMBajY FMz+bH/cZWWEcc22IBnEjHF/Q5DybaeoFPC26eXiNO/Jnd210KH5ibmwh+l4JwVPhAPr /TvbXkVuw975PCcPW4gENxH0IXrzBBMW/dJ0ZZlbk6FaPVrJo9fHXw4oMTRfeNhdDTUD 2UyA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=KIh7KhTzHMM8NImyp8JEXp0cQ6SpWRDrI20KK0RXxhw=; b=CdWRtcdFBY8qKH3/+SKaFkAzSdJM2INE07gzaschLE8Ko/OZMw7bgixWtxyn9mvLcF j4MvXTPA3h8dWRTJ1jQK7j0yA2dOo7UNuam/YTEF+TjjsWNnv+CFchISEGZTGGjltrHN 6AtOwapD2bZt8s1i1eflXpmrJ03fj21tzvMG8UnTV4aa+u6pNA4hpS0T1yVAisMO65Lb /rQlwdpwv4BRSuJPwN4zyvCRw4e2Blqnun5bSQCZPqKclZh05hX8pp8pNTPudoZMjcbE TnbIflRoU/tFawR4aqxRD6qQrsnzxjBBeYeHVDHgtqUbAUF01EmDhnYE0gVgDlWw1Rhq T3fg== X-Gm-Message-State: APjAAAVwq5q9AqDhl2w8kDnfqL8TBBCH7yJHFDPtTjSrfM6bCyaT55tT hs9U3sZ4a0Ua6+A6iCJeGfHt78uZFs8= X-Google-Smtp-Source: APXvYqzM23g+2kI9oY77pApHllq/sr5kMU3BjBdee1uK2LPbjXm7KJP4mrjA3zymXmJManbvdjH8tw== X-Received: by 2002:a63:4a5f:: with SMTP id j31mr41802609pgl.369.1556299467178; Fri, 26 Apr 2019 10:24:27 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 26 Apr 2019 10:24:09 -0700 Message-Id: <20190426172421.27133-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190426172421.27133-1-richard.henderson@linaro.org> References: <20190426172421.27133-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::536 Subject: [Qemu-devel] [PULL 03/15] tcg: Use deposit and extract2 in tcg_gen_shifti_i64 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/tcg-op.c | 47 ++++++++++++++++++++++++----------------------- 1 file changed, 24 insertions(+), 23 deletions(-) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index deacc63e3b..fbc70649dd 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -1355,31 +1355,32 @@ static inline void tcg_gen_shifti_i64(TCGv_i64 ret,= TCGv_i64 arg1, tcg_gen_shli_i32(TCGV_HIGH(ret), TCGV_LOW(arg1), c); tcg_gen_movi_i32(TCGV_LOW(ret), 0); } - } else { - TCGv_i32 t0, t1; - - t0 =3D tcg_temp_new_i32(); - t1 =3D tcg_temp_new_i32(); - if (right) { - tcg_gen_shli_i32(t0, TCGV_HIGH(arg1), 32 - c); - if (arith) { - tcg_gen_sari_i32(t1, TCGV_HIGH(arg1), c); - } else { - tcg_gen_shri_i32(t1, TCGV_HIGH(arg1), c); - } - tcg_gen_shri_i32(TCGV_LOW(ret), TCGV_LOW(arg1), c); - tcg_gen_or_i32(TCGV_LOW(ret), TCGV_LOW(ret), t0); - tcg_gen_mov_i32(TCGV_HIGH(ret), t1); + } else if (right) { + if (TCG_TARGET_HAS_extract2_i32) { + tcg_gen_extract2_i32(TCGV_LOW(ret), + TCGV_LOW(arg1), TCGV_HIGH(arg1), c); } else { - tcg_gen_shri_i32(t0, TCGV_LOW(arg1), 32 - c); - /* Note: ret can be the same as arg1, so we use t1 */ - tcg_gen_shli_i32(t1, TCGV_LOW(arg1), c); - tcg_gen_shli_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), c); - tcg_gen_or_i32(TCGV_HIGH(ret), TCGV_HIGH(ret), t0); - tcg_gen_mov_i32(TCGV_LOW(ret), t1); + tcg_gen_shri_i32(TCGV_LOW(ret), TCGV_LOW(arg1), c); + tcg_gen_deposit_i32(TCGV_LOW(ret), TCGV_LOW(ret), + TCGV_HIGH(arg1), 32 - c, c); } - tcg_temp_free_i32(t0); - tcg_temp_free_i32(t1); + if (arith) { + tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), c); + } else { + tcg_gen_shri_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), c); + } + } else { + if (TCG_TARGET_HAS_extract2_i32) { + tcg_gen_extract2_i32(TCGV_HIGH(ret), + TCGV_LOW(arg1), TCGV_HIGH(arg1), 32 - c); + } else { + TCGv_i32 t0 =3D tcg_temp_new_i32(); + tcg_gen_shri_i32(t0, TCGV_LOW(arg1), 32 - c); + tcg_gen_deposit_i32(TCGV_HIGH(ret), t0, + TCGV_HIGH(arg1), c, 32 - c); + tcg_temp_free_i32(t0); + } + tcg_gen_shli_i32(TCGV_LOW(ret), TCGV_LOW(arg1), c); } } =20 --=20 2.17.1 From nobody Sun Jun 2 07:52:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[97.113.179.147]) by smtp.gmail.com with ESMTPSA id j5sm7901762pfg.186.2019.04.26.10.24.27 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 26 Apr 2019 10:24:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=NUjDwC8rJFYEblahVxs6YiCANModiBNxtQ+zHc0oNPM=; b=XCyaTyYkv+JIF3rby6W/Z1TMey13mh7VXZDoUkH2SZsBSX9LOeO5Nd35mP5Kgt4oO/ jpiAGoZmQfZBWYXpke1v2CvdFBMNpFZ0ID/UOg1pvETx27woW0jO52PbCtQBl7WFZmSg u9bdPLQA0Inu54KHZx/rYDsiBEVleqw6KdnsPLXvayDVifEvTmpTQl4KnmJPbuapBjwI fNjv5TI2L49O9CTeKyjjHpYsctfpv5y1AaB8Y/SRl/VxbGoG75mmgpUU/UAdj2dQzg7/ +zjaZlqJgJmjRlzJqzxCHDlgwIwGI1ygkEGu6BLpKl+3z8rZtFud+prq8NSfBeuPA0os VhcQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=NUjDwC8rJFYEblahVxs6YiCANModiBNxtQ+zHc0oNPM=; b=daG5bAsFKsQrqs3V1WrQgDc5yOiUrO+ezzP11Wktdzmy38siNT8sDjYhq5/5hzRFfb VDd/11AOSTOPqFmEDSjYhzjngiRUFHg/GcYcFmpCeIG7NcozeReyUwQDzvOcndamC3uV pF0ASLbL+xPIKbosRfNenRwRxspJJvJT7HmrzkT0ptlQKTTR9MehVG+hO4o+0RH30H2v 4tOpmefAnwW72vGt310W8ConD9FCpSSwRFaXTjvygQ28ruvP2L0Lh1hAoPB0NYf7vqnt Sq5txowO+rq2Nc1BvKHzSFTbVG2bb5miWYYY01a0dtg2uZcXIZjVxJzF3hHuVwRFi/nc v8dw== X-Gm-Message-State: APjAAAUcslubNSkFGWNi7BAoPoL+mvX8BdY19ywk7akhylmUN15hzVLL yA6sbnPOLijisaaXY7Lg9APzugoOID0= X-Google-Smtp-Source: APXvYqzhzLCDLvpWR98/aZ2FaT05rU2CLNU4xV8rgc8qzai8gyULHkTsGnV80TEhPEBUK9ZQVSlomQ== X-Received: by 2002:a63:e045:: with SMTP id n5mr42541292pgj.230.1556299468293; Fri, 26 Apr 2019 10:24:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 26 Apr 2019 10:24:10 -0700 Message-Id: <20190426172421.27133-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190426172421.27133-1-richard.henderson@linaro.org> References: <20190426172421.27133-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::52d Subject: [Qemu-devel] [PULL 04/15] tcg: Use extract2 in tcg_gen_deposit_{i32, i64} X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/tcg-op.c | 34 ++++++++++++++++++++++++++++++---- 1 file changed, 30 insertions(+), 4 deletions(-) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index fbc70649dd..a00d1df37e 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -611,9 +611,22 @@ void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1, = TCGv_i32 arg2, return; } =20 - mask =3D (1u << len) - 1; t1 =3D tcg_temp_new_i32(); =20 + if (TCG_TARGET_HAS_extract2_i32) { + if (ofs + len =3D=3D 32) { + tcg_gen_shli_i32(t1, arg1, len); + tcg_gen_extract2_i32(ret, t1, arg2, len); + goto done; + } + if (ofs =3D=3D 0) { + tcg_gen_extract2_i32(ret, arg1, arg2, len); + tcg_gen_rotli_i32(ret, ret, len); + goto done; + } + } + + mask =3D (1u << len) - 1; if (ofs + len < 32) { tcg_gen_andi_i32(t1, arg2, mask); tcg_gen_shli_i32(t1, t1, ofs); @@ -622,7 +635,7 @@ void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1, T= CGv_i32 arg2, } tcg_gen_andi_i32(ret, arg1, ~(mask << ofs)); tcg_gen_or_i32(ret, ret, t1); - + done: tcg_temp_free_i32(t1); } =20 @@ -2024,9 +2037,22 @@ void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1= , TCGv_i64 arg2, } } =20 - mask =3D (1ull << len) - 1; t1 =3D tcg_temp_new_i64(); =20 + if (TCG_TARGET_HAS_extract2_i64) { + if (ofs + len =3D=3D 64) { + tcg_gen_shli_i64(t1, arg1, len); + tcg_gen_extract2_i64(ret, t1, arg2, len); + goto done; + } + if (ofs =3D=3D 0) { + tcg_gen_extract2_i64(ret, arg1, arg2, len); + tcg_gen_rotli_i64(ret, ret, len); + goto done; + } + } + + mask =3D (1ull << len) - 1; if (ofs + len < 64) { tcg_gen_andi_i64(t1, arg2, mask); tcg_gen_shli_i64(t1, t1, ofs); @@ -2035,7 +2061,7 @@ void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1,= TCGv_i64 arg2, } tcg_gen_andi_i64(ret, arg1, ~(mask << ofs)); tcg_gen_or_i64(ret, ret, t1); - + done: tcg_temp_free_i64(t1); } =20 --=20 2.17.1 From nobody Sun Jun 2 07:52:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1556299952; cv=none; d=zoho.com; s=zohoarc; b=n7yrueYxmCSxbsxgIC8IePEKW0K6LE4GzS34pYFCDEaXbZ8D4+JHoCmMSThw8omEdbiqLBZPBLRMtMbgCIE4d3+RRi79Ts9YwReO1ERun5ggKuJoHzGqAe9CJ3/9LnMeCY0ffEV3Q0UtEnRLZiq6vrd2dt6KyjhWb7FlO5uQ/oU= ARC-Message-Signature: i=1; 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[97.113.179.147]) by smtp.gmail.com with ESMTPSA id j5sm7901762pfg.186.2019.04.26.10.24.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 26 Apr 2019 10:24:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=fs+VAJvIUlV2gQG99NKmKU7MN80ounXs6KwGIvA+I7I=; b=U8gt93oOkgf05Ldlc7W187XUsHmjfwaiPiHczKZ6ujc/igrQYJ/VTHvj0q5i164k46 pVvQRbYJ4ko68TYcb+f0fVnfaQ30gnX/ENcIXVdZv8Qg6oVRNMYpJsZdW6d4jkvzISTV ES53r+sSgsS6KB7yhgBx2+Ao7L7Wz/Ck/FOoktl/Lpw+RLwt2yCnG+SZKq+Uhn2+ypas wpnN7JCub/tA+W9cBBMUapIaUzfrvd1b7n8ByL4Y6xv7JlcgQhcNMtQHY9+18Je9ZiG5 z8ZMktPJ0FfRv1PcTGXjtGm2kkxHW1gJyoizGppst2RpFT7mnZZp45bhP6ErugomaQqV rUag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=fs+VAJvIUlV2gQG99NKmKU7MN80ounXs6KwGIvA+I7I=; b=XnKqqJsWaWKK1S2OqFVCmzZagYdWYRI4BCP+aG8oa0PXcroQLYYEKqcb78e/6rgUoo vdhC+YOueaE9vhnGGyeID3RblHyvjBVUJdB89oWInHVNvWW8PHUyy81/rB5ESrBJMTv+ bOXGl7s9SZ2AQEfwpTICUC3+LtqroX1ZJZFBPxY58gcpgT4n3vCsBE7oQP45iFCNANxU 4ufGqKaIVxop8qm1rn/dYASVYfhplZtlAyu0bNr1v8n2zwEPlk5AgTr2kQRE+lUYcYEk UiD6PdZeUimQVV3cbAo2jSn4gce5i7v4goky1TL9JXGTG7DkOKKlK08sfEBkrAGxFxup 0lAQ== X-Gm-Message-State: APjAAAXpWZ913T1sVepRhD6ycwMJctUIGNIZacFQuMVZtfka/cu1Pa+J J0TDj8ZQ1+lzLzWyVaTlBL6dfoYvE3w= X-Google-Smtp-Source: APXvYqwBHdFUjs1+Mz82jS0ZIiWmn9SKlP4vglpVhskcweN38adCAmDCZjwnO2TC/qsLdMJlpfPr9w== X-Received: by 2002:a63:e22:: with SMTP id d34mr39717983pgl.251.1556299469717; Fri, 26 Apr 2019 10:24:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 26 Apr 2019 10:24:11 -0700 Message-Id: <20190426172421.27133-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190426172421.27133-1-richard.henderson@linaro.org> References: <20190426172421.27133-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::533 Subject: [Qemu-devel] [PULL 05/15] tcg/i386: Support INDEX_op_extract2_{i32, i64} X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.h | 4 ++-- tcg/i386/tcg-target.inc.c | 11 +++++++++++ 2 files changed, 13 insertions(+), 2 deletions(-) diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 2c58eaa9ed..241bf19413 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -124,7 +124,7 @@ extern bool have_avx2; #define TCG_TARGET_HAS_deposit_i32 1 #define TCG_TARGET_HAS_extract_i32 1 #define TCG_TARGET_HAS_sextract_i32 1 -#define TCG_TARGET_HAS_extract2_i32 0 +#define TCG_TARGET_HAS_extract2_i32 1 #define TCG_TARGET_HAS_movcond_i32 1 #define TCG_TARGET_HAS_add2_i32 1 #define TCG_TARGET_HAS_sub2_i32 1 @@ -163,7 +163,7 @@ extern bool have_avx2; #define TCG_TARGET_HAS_deposit_i64 1 #define TCG_TARGET_HAS_extract_i64 1 #define TCG_TARGET_HAS_sextract_i64 0 -#define TCG_TARGET_HAS_extract2_i64 0 +#define TCG_TARGET_HAS_extract2_i64 1 #define TCG_TARGET_HAS_movcond_i64 1 #define TCG_TARGET_HAS_add2_i64 1 #define TCG_TARGET_HAS_sub2_i64 1 diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index e0670e5098..1fa833840e 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -452,6 +452,7 @@ static inline int tcg_target_const_match(tcg_target_lon= g val, TCGType type, #define OPC_SHUFPS (0xc6 | P_EXT) #define OPC_SHLX (0xf7 | P_EXT38 | P_DATA16) #define OPC_SHRX (0xf7 | P_EXT38 | P_SIMDF2) +#define OPC_SHRD_Ib (0xac | P_EXT) #define OPC_TESTL (0x85) #define OPC_TZCNT (0xbc | P_EXT | P_SIMDF3) #define OPC_UD2 (0x0b | P_EXT) @@ -2587,6 +2588,12 @@ static inline void tcg_out_op(TCGContext *s, TCGOpco= de opc, } break; =20 + OP_32_64(extract2): + /* Note that SHRD outputs to the r/m operand. */ + tcg_out_modrm(s, OPC_SHRD_Ib + rexw, a2, a0); + tcg_out8(s, args[3]); + break; + case INDEX_op_mb: tcg_out_mb(s, a0); break; @@ -2845,6 +2852,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) static const TCGTargetOpDef r_0 =3D { .args_ct_str =3D { "r", "0" } }; static const TCGTargetOpDef r_r_ri =3D { .args_ct_str =3D { "r", "r", = "ri" } }; static const TCGTargetOpDef r_r_re =3D { .args_ct_str =3D { "r", "r", = "re" } }; + static const TCGTargetOpDef r_0_r =3D { .args_ct_str =3D { "r", "0", "= r" } }; static const TCGTargetOpDef r_0_re =3D { .args_ct_str =3D { "r", "0", = "re" } }; static const TCGTargetOpDef r_0_ci =3D { .args_ct_str =3D { "r", "0", = "ci" } }; static const TCGTargetOpDef r_L =3D { .args_ct_str =3D { "r", "L" } }; @@ -2970,6 +2978,9 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) case INDEX_op_ctpop_i32: case INDEX_op_ctpop_i64: return &r_r; + case INDEX_op_extract2_i32: + case INDEX_op_extract2_i64: + return &r_0_r; =20 case INDEX_op_deposit_i32: case INDEX_op_deposit_i64: --=20 2.17.1 From nobody Sun Jun 2 07:52:28 2024 Delivered-To: importer@patchew.org Received-SPF: temperror (zoho.com: Error in retrieving data from DNS) client-ip=209.51.188.17; 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X-Received-From: 2607:f8b0:4864:20::429 Subject: [Qemu-devel] [PULL 06/15] tcg/arm: Support INDEX_op_extract2_i32 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.h | 2 +- tcg/arm/tcg-target.inc.c | 25 +++++++++++++++++++++++++ 2 files changed, 26 insertions(+), 1 deletion(-) diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index 4ee6c98958..17e771374d 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -116,7 +116,7 @@ extern bool use_idiv_instructions; #define TCG_TARGET_HAS_deposit_i32 use_armv7_instructions #define TCG_TARGET_HAS_extract_i32 use_armv7_instructions #define TCG_TARGET_HAS_sextract_i32 use_armv7_instructions -#define TCG_TARGET_HAS_extract2_i32 0 +#define TCG_TARGET_HAS_extract2_i32 1 #define TCG_TARGET_HAS_movcond_i32 1 #define TCG_TARGET_HAS_mulu2_i32 1 #define TCG_TARGET_HAS_muls2_i32 1 diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c index 2245a8aeb9..6873b0cf95 100644 --- a/tcg/arm/tcg-target.inc.c +++ b/tcg/arm/tcg-target.inc.c @@ -2064,6 +2064,27 @@ static inline void tcg_out_op(TCGContext *s, TCGOpco= de opc, case INDEX_op_sextract_i32: tcg_out_sextract(s, COND_AL, args[0], args[1], args[2], args[3]); break; + case INDEX_op_extract2_i32: + /* ??? These optimization vs zero should be generic. */ + /* ??? But we can't substitute 2 for 1 in the opcode stream yet. = */ + if (const_args[1]) { + if (const_args[2]) { + tcg_out_movi(s, TCG_TYPE_REG, args[0], 0); + } else { + tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, + args[2], SHIFT_IMM_LSL(32 - args[3])); + } + } else if (const_args[2]) { + tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, + args[1], SHIFT_IMM_LSR(args[3])); + } else { + /* We can do extract2 in 2 insns, vs the 3 required otherwise.= */ + tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_TMP, 0, + args[2], SHIFT_IMM_LSL(32 - args[3])); + tcg_out_dat_reg(s, COND_AL, ARITH_ORR, args[0], TCG_REG_TMP, + args[1], SHIFT_IMM_LSR(args[3])); + } + break; =20 case INDEX_op_div_i32: tcg_out_sdiv(s, COND_AL, args[0], args[1], args[2]); @@ -2108,6 +2129,8 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) =3D { .args_ct_str =3D { "s", "s", "s", "s" } }; static const TCGTargetOpDef br =3D { .args_ct_str =3D { "r", "rIN" } }; + static const TCGTargetOpDef ext2 + =3D { .args_ct_str =3D { "r", "rZ", "rZ" } }; static const TCGTargetOpDef dep =3D { .args_ct_str =3D { "r", "0", "rZ" } }; static const TCGTargetOpDef movc @@ -2174,6 +2197,8 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) return &br; case INDEX_op_deposit_i32: return &dep; + case INDEX_op_extract2_i32: + return &ext2; case INDEX_op_movcond_i32: return &movc; case INDEX_op_add2_i32: --=20 2.17.1 From nobody Sun Jun 2 07:52:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1556299784; cv=none; d=zoho.com; s=zohoarc; b=dFdXXIgA5AWkW1YkO3qMXkqw2HAtbtj03Eafk1ezqvfl/OvuotW6bnyMoZn1/bYgRE/K9mndxq9hN9zHC2WXWXMJcDGl77HlsmlzwRELEGtMbgIu/xLGS3EKJAu2c9oarruvg4hkrWbITsj9l2vWodxX0YY0AdHFcpMlHt1JkqU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1556299784; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=qG8cIyjXu/sgNDmtduLrdTs106BZZN6hG6Kr2t2NXJo=; b=RZfMR22cthGMOPky/GTbLm/gGRwZOHar22ldmbwNw4S1emxrGvjcPRATzShIpIPA8d0XsXPCUHOQC3PQIqq7F6FNdSse1s7RVpiorRKcRfYubFcvIph8A3ZJX7oMZHWmJsuvfv/aK5ZKnkxuWQyJRtgoFztCdZbW4Kzi+aTnp+4= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1556299784943725.4488541545182; Fri, 26 Apr 2019 10:29:44 -0700 (PDT) Received: from localhost ([127.0.0.1]:49958 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hK4fN-00044f-UI for importer@patchew.org; Fri, 26 Apr 2019 13:29:42 -0400 Received: from eggs.gnu.org ([209.51.188.92]:47984) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hK4aQ-0008Tq-P0 for qemu-devel@nongnu.org; Fri, 26 Apr 2019 13:24:35 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hK4aP-0006VT-MA for qemu-devel@nongnu.org; Fri, 26 Apr 2019 13:24:34 -0400 Received: from mail-pg1-x531.google.com ([2607:f8b0:4864:20::531]:37923) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hK4aP-0006SD-Fh for qemu-devel@nongnu.org; Fri, 26 Apr 2019 13:24:33 -0400 Received: by mail-pg1-x531.google.com with SMTP id j26so1936424pgl.5 for ; Fri, 26 Apr 2019 10:24:33 -0700 (PDT) Received: from localhost.localdomain (97-113-179-147.tukw.qwest.net. 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X-Received-From: 2607:f8b0:4864:20::531 Subject: [Qemu-devel] [PULL 07/15] tcg/aarch64: Support INDEX_op_extract2_{i32, i64} X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.h | 4 ++-- tcg/aarch64/tcg-target.inc.c | 11 +++++++++++ 2 files changed, 13 insertions(+), 2 deletions(-) diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index 6600a54a02..ce2bb1f90b 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -77,7 +77,7 @@ typedef enum { #define TCG_TARGET_HAS_deposit_i32 1 #define TCG_TARGET_HAS_extract_i32 1 #define TCG_TARGET_HAS_sextract_i32 1 -#define TCG_TARGET_HAS_extract2_i32 0 +#define TCG_TARGET_HAS_extract2_i32 1 #define TCG_TARGET_HAS_movcond_i32 1 #define TCG_TARGET_HAS_add2_i32 1 #define TCG_TARGET_HAS_sub2_i32 1 @@ -114,7 +114,7 @@ typedef enum { #define TCG_TARGET_HAS_deposit_i64 1 #define TCG_TARGET_HAS_extract_i64 1 #define TCG_TARGET_HAS_sextract_i64 1 -#define TCG_TARGET_HAS_extract2_i64 0 +#define TCG_TARGET_HAS_extract2_i64 1 #define TCG_TARGET_HAS_movcond_i64 1 #define TCG_TARGET_HAS_add2_i64 1 #define TCG_TARGET_HAS_sub2_i64 1 diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c index d57f9e500f..8b93598bce 100644 --- a/tcg/aarch64/tcg-target.inc.c +++ b/tcg/aarch64/tcg-target.inc.c @@ -2058,6 +2058,11 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_sbfm(s, ext, a0, a1, a2, a2 + args[3] - 1); break; =20 + case INDEX_op_extract2_i64: + case INDEX_op_extract2_i32: + tcg_out_extr(s, ext, a0, a1, a2, args[3]); + break; + case INDEX_op_add2_i32: tcg_out_addsub2(s, TCG_TYPE_I32, a0, a1, REG0(2), REG0(3), (int32_t)args[4], args[5], const_args[4], @@ -2300,6 +2305,8 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) =3D { .args_ct_str =3D { "r", "r", "rAL" } }; static const TCGTargetOpDef dep =3D { .args_ct_str =3D { "r", "0", "rZ" } }; + static const TCGTargetOpDef ext2 + =3D { .args_ct_str =3D { "r", "rZ", "rZ" } }; static const TCGTargetOpDef movc =3D { .args_ct_str =3D { "r", "r", "rA", "rZ", "rZ" } }; static const TCGTargetOpDef add2 @@ -2430,6 +2437,10 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOp= code op) case INDEX_op_deposit_i64: return &dep; =20 + case INDEX_op_extract2_i32: + case INDEX_op_extract2_i64: + return &ext2; + case INDEX_op_add2_i32: case INDEX_op_add2_i64: case INDEX_op_sub2_i32: --=20 2.17.1 From nobody Sun Jun 2 07:52:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[97.113.179.147]) by smtp.gmail.com with ESMTPSA id j5sm7901762pfg.186.2019.04.26.10.24.32 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 26 Apr 2019 10:24:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xpBWnqHFM2/Jzl+B3blBe3uumEbxe3Lpgg2RGGVZlLQ=; b=GJWNCx7Yy7Q4ylYuTU0DaY3xRIP8AARJxq0A4x22W1bwcu0I3Qin/kMzgrTeJiBuVf cbXrKhMQYa0dkxjvctTU5OKKXvbrHzEMEWw3uJofpS+5gjjVRfAo6XIEJZVnbUyQtj7F YjjWnE7vDdAEr5HauFp3efIcEcK9qYzLuv2PQlS2cw+G3fw39yiJidoxXm+hlaEfABQe +i56Cfmq+FJ+CYM5kTm2WiPp6t8u+ZdsfGCz/Aps++azJqZ9LKGDaLNYohVFrsuf9/oM tj89vLMs1AdMHq5ImM2LzY/M8PT+ttR6rBAcpkfyX1xBaRfs2L3usa8VF15X74LnxWcL 4Qiw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xpBWnqHFM2/Jzl+B3blBe3uumEbxe3Lpgg2RGGVZlLQ=; b=W6V8/MgdmVkX4mmWwC2YhRmUvrE7BvgJVbwRI+Lp/8s0HCv5TP90PjxK/PduKBwMZB SWwUA7u3d5Eb89zWDah8bG/PqBe/PYsOzkZSdaWbMMfjm9IJRvVMCUBYwVTPt1XKr3xn jeXwGRkA3qA/BhxtqaHZpT4Dwl3GKBeiM/i8V8MBn3GG02Mi+XhH2JLvkuejUfKgk8LJ hxai/rBMtc9EndQVsVMzI0k4xHxQiIozbrM1vdBVPVbPSMbWc/CWp5MbtPyXjMNrYKPI D/rxo43Dsnbo0Hr6bO8lZWFfoEd0zEdGeUW9vp2ZfFIFdQdfURSxRjDF5lCSWqunova0 zROw== X-Gm-Message-State: APjAAAVQ8WbWjhFxktUXQF+wTcwNyINJkwS/NuaPSwTlzBdiofbBBsL1 ngJBa8jOBzhNYYXYY4EsJvbHdtp1ZoM= X-Google-Smtp-Source: APXvYqyf3w4SADQerpsN0/2O+AJpvc1Tn5muXIT0Bp/0jsCkChScAcnMJWNReffaCIiGYoG4njpAKQ== X-Received: by 2002:a63:27c5:: with SMTP id n188mr21574015pgn.338.1556299473578; Fri, 26 Apr 2019 10:24:33 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 26 Apr 2019 10:24:14 -0700 Message-Id: <20190426172421.27133-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190426172421.27133-1-richard.henderson@linaro.org> References: <20190426172421.27133-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::532 Subject: [Qemu-devel] [PULL 08/15] tcg: Hoist max_insns computation to tb_gen_code X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) In order to handle TB's that translate to too much code, we need to place the control of the length of the translation in the hands of the code gen master loop. Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 4 ++-- include/exec/translator.h | 3 ++- accel/tcg/translate-all.c | 15 +++++++++++++-- accel/tcg/translator.c | 15 ++------------- target/alpha/translate.c | 4 ++-- target/arm/translate.c | 4 ++-- target/cris/translate.c | 10 +--------- target/hppa/translate.c | 5 ++--- target/i386/translate.c | 4 ++-- target/lm32/translate.c | 10 +--------- target/m68k/translate.c | 4 ++-- target/microblaze/translate.c | 10 +--------- target/mips/translate.c | 4 ++-- target/moxie/translate.c | 11 ++--------- target/nios2/translate.c | 14 ++------------ target/openrisc/translate.c | 4 ++-- target/ppc/translate.c | 4 ++-- target/riscv/translate.c | 4 ++-- target/s390x/translate.c | 4 ++-- target/sh4/translate.c | 4 ++-- target/sparc/translate.c | 4 ++-- target/tilegx/translate.c | 12 +----------- target/tricore/translate.c | 16 ++-------------- target/unicore32/translate.c | 10 +--------- target/xtensa/translate.c | 4 ++-- 25 files changed, 56 insertions(+), 127 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 97b90cb0db..58e988b3b1 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -40,8 +40,8 @@ typedef ram_addr_t tb_page_addr_t; =20 #include "qemu/log.h" =20 -void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb); -void restore_state_to_opc(CPUArchState *env, struct TranslationBlock *tb, +void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_in= sns); +void restore_state_to_opc(CPUArchState *env, TranslationBlock *tb, target_ulong *data); =20 void cpu_gen_init(void); diff --git a/include/exec/translator.h b/include/exec/translator.h index 71e7b2c347..66dfe906c4 100644 --- a/include/exec/translator.h +++ b/include/exec/translator.h @@ -123,6 +123,7 @@ typedef struct TranslatorOps { * @db: Disassembly context. * @cpu: Target vCPU. * @tb: Translation block. + * @max_insns: Maximum number of insns to translate. * * Generic translator loop. * @@ -137,7 +138,7 @@ typedef struct TranslatorOps { * - When too many instructions have been translated. */ void translator_loop(const TranslatorOps *ops, DisasContextBase *db, - CPUState *cpu, TranslationBlock *tb); + CPUState *cpu, TranslationBlock *tb, int max_insns); =20 void translator_loop_temp_check(DisasContextBase *db); =20 diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 75a6cf49f1..39532fd44c 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1674,7 +1674,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, tb_page_addr_t phys_pc, phys_page2; target_ulong virt_page2; tcg_insn_unit *gen_code_buf; - int gen_code_size, search_size; + int gen_code_size, search_size, max_insns; #ifdef CONFIG_PROFILER TCGProfile *prof =3D &tcg_ctx->prof; int64_t ti; @@ -1692,6 +1692,17 @@ TranslationBlock *tb_gen_code(CPUState *cpu, cflags &=3D ~CF_CLUSTER_MASK; cflags |=3D cpu->cluster_index << CF_CLUSTER_SHIFT; =20 + max_insns =3D cflags & CF_COUNT_MASK; + if (max_insns =3D=3D 0) { + max_insns =3D CF_COUNT_MASK; + } + if (max_insns > TCG_MAX_INSNS) { + max_insns =3D TCG_MAX_INSNS; + } + if (cpu->singlestep_enabled || singlestep) { + max_insns =3D 1; + } + buffer_overflow: tb =3D tb_alloc(pc); if (unlikely(!tb)) { @@ -1721,7 +1732,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, tcg_func_start(tcg_ctx); =20 tcg_ctx->cpu =3D ENV_GET_CPU(env); - gen_intermediate_code(cpu, tb); + gen_intermediate_code(cpu, tb, max_insns); tcg_ctx->cpu =3D NULL; =20 trace_translate_block(tb, tb->pc, tb->tc.ptr); diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c index afd0a49ea6..8d65ead708 100644 --- a/accel/tcg/translator.c +++ b/accel/tcg/translator.c @@ -32,7 +32,7 @@ void translator_loop_temp_check(DisasContextBase *db) } =20 void translator_loop(const TranslatorOps *ops, DisasContextBase *db, - CPUState *cpu, TranslationBlock *tb) + CPUState *cpu, TranslationBlock *tb, int max_insns) { int bp_insn =3D 0; =20 @@ -42,20 +42,9 @@ void translator_loop(const TranslatorOps *ops, DisasCont= extBase *db, db->pc_next =3D db->pc_first; db->is_jmp =3D DISAS_NEXT; db->num_insns =3D 0; + db->max_insns =3D max_insns; db->singlestep_enabled =3D cpu->singlestep_enabled; =20 - /* Instruction counting */ - db->max_insns =3D tb_cflags(db->tb) & CF_COUNT_MASK; - if (db->max_insns =3D=3D 0) { - db->max_insns =3D CF_COUNT_MASK; - } - if (db->max_insns > TCG_MAX_INSNS) { - db->max_insns =3D TCG_MAX_INSNS; - } - if (db->singlestep_enabled || singlestep) { - db->max_insns =3D 1; - } - ops->init_disas_context(db, cpu); tcg_debug_assert(db->is_jmp =3D=3D DISAS_NEXT); /* no early exit */ =20 diff --git a/target/alpha/translate.c b/target/alpha/translate.c index 9d8f9b3eea..2c9cccf6c1 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -3049,10 +3049,10 @@ static const TranslatorOps alpha_tr_ops =3D { .disas_log =3D alpha_tr_disas_log, }; =20 -void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb) +void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_in= sns) { DisasContext dc; - translator_loop(&alpha_tr_ops, &dc.base, cpu, tb); + translator_loop(&alpha_tr_ops, &dc.base, cpu, tb, max_insns); } =20 void restore_state_to_opc(CPUAlphaState *env, TranslationBlock *tb, diff --git a/target/arm/translate.c b/target/arm/translate.c index d9e7bb737a..4ea4018e2b 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -13756,7 +13756,7 @@ static const TranslatorOps thumb_translator_ops =3D= { }; =20 /* generate intermediate code for basic block 'tb'. */ -void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb) +void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_in= sns) { DisasContext dc; const TranslatorOps *ops =3D &arm_translator_ops; @@ -13770,7 +13770,7 @@ void gen_intermediate_code(CPUState *cpu, Translati= onBlock *tb) } #endif =20 - translator_loop(ops, &dc.base, cpu, tb); + translator_loop(ops, &dc.base, cpu, tb, max_insns); } =20 void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags) diff --git a/target/cris/translate.c b/target/cris/translate.c index 96359c0d7d..b005a5c20e 100644 --- a/target/cris/translate.c +++ b/target/cris/translate.c @@ -3081,7 +3081,7 @@ static unsigned int crisv32_decoder(CPUCRISState *env= , DisasContext *dc) */ =20 /* generate intermediate code for basic block 'tb'. */ -void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) +void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_ins= ns) { CPUCRISState *env =3D cs->env_ptr; uint32_t pc_start; @@ -3091,7 +3091,6 @@ void gen_intermediate_code(CPUState *cs, struct Trans= lationBlock *tb) uint32_t page_start; target_ulong npc; int num_insns; - int max_insns; =20 if (env->pregs[PR_VR] =3D=3D 32) { dc->decoder =3D crisv32_decoder; @@ -3137,13 +3136,6 @@ void gen_intermediate_code(CPUState *cs, struct Tran= slationBlock *tb) =20 page_start =3D pc_start & TARGET_PAGE_MASK; num_insns =3D 0; - max_insns =3D tb_cflags(tb) & CF_COUNT_MASK; - if (max_insns =3D=3D 0) { - max_insns =3D CF_COUNT_MASK; - } - if (max_insns > TCG_MAX_INSNS) { - max_insns =3D TCG_MAX_INSNS; - } =20 gen_tb_start(tb); do { diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 43b74367ea..7c03c62768 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -4312,11 +4312,10 @@ static const TranslatorOps hppa_tr_ops =3D { .disas_log =3D hppa_tr_disas_log, }; =20 -void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) - +void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_ins= ns) { DisasContext ctx; - translator_loop(&hppa_tr_ops, &ctx.base, cs, tb); + translator_loop(&hppa_tr_ops, &ctx.base, cs, tb, max_insns); } =20 void restore_state_to_opc(CPUHPPAState *env, TranslationBlock *tb, diff --git a/target/i386/translate.c b/target/i386/translate.c index b725bec37c..77d6b73e42 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -8590,11 +8590,11 @@ static const TranslatorOps i386_tr_ops =3D { }; =20 /* generate intermediate code for basic block 'tb'. */ -void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb) +void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_in= sns) { DisasContext dc; =20 - translator_loop(&i386_tr_ops, &dc.base, cpu, tb); + translator_loop(&i386_tr_ops, &dc.base, cpu, tb, max_insns); } =20 void restore_state_to_opc(CPUX86State *env, TranslationBlock *tb, diff --git a/target/lm32/translate.c b/target/lm32/translate.c index b8b5e12e63..f0e0e7058e 100644 --- a/target/lm32/translate.c +++ b/target/lm32/translate.c @@ -1050,7 +1050,7 @@ static inline void decode(DisasContext *dc, uint32_t = ir) } =20 /* generate intermediate code for basic block 'tb'. */ -void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) +void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_ins= ns) { CPULM32State *env =3D cs->env_ptr; LM32CPU *cpu =3D lm32_env_get_cpu(env); @@ -1058,7 +1058,6 @@ void gen_intermediate_code(CPUState *cs, struct Trans= lationBlock *tb) uint32_t pc_start; uint32_t page_start; int num_insns; - int max_insns; =20 pc_start =3D tb->pc; dc->features =3D cpu->features; @@ -1078,13 +1077,6 @@ void gen_intermediate_code(CPUState *cs, struct Tran= slationBlock *tb) =20 page_start =3D pc_start & TARGET_PAGE_MASK; num_insns =3D 0; - max_insns =3D tb_cflags(tb) & CF_COUNT_MASK; - if (max_insns =3D=3D 0) { - max_insns =3D CF_COUNT_MASK; - } - if (max_insns > TCG_MAX_INSNS) { - max_insns =3D TCG_MAX_INSNS; - } =20 gen_tb_start(tb); do { diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 3b2280b48b..58596278c2 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -6170,10 +6170,10 @@ static const TranslatorOps m68k_tr_ops =3D { .disas_log =3D m68k_tr_disas_log, }; =20 -void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb) +void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_in= sns) { DisasContext dc; - translator_loop(&m68k_tr_ops, &dc.base, cpu, tb); + translator_loop(&m68k_tr_ops, &dc.base, cpu, tb, max_insns); } =20 static double floatx80_to_double(CPUM68KState *env, uint16_t high, uint64_= t low) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index bc2712ddbd..885fc44b51 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1601,7 +1601,7 @@ static inline void decode(DisasContext *dc, uint32_t = ir) } =20 /* generate intermediate code for basic block 'tb'. */ -void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) +void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_ins= ns) { CPUMBState *env =3D cs->env_ptr; MicroBlazeCPU *cpu =3D mb_env_get_cpu(env); @@ -1611,7 +1611,6 @@ void gen_intermediate_code(CPUState *cs, struct Trans= lationBlock *tb) uint32_t page_start, org_flags; uint32_t npc; int num_insns; - int max_insns; =20 pc_start =3D tb->pc; dc->cpu =3D cpu; @@ -1635,13 +1634,6 @@ void gen_intermediate_code(CPUState *cs, struct Tran= slationBlock *tb) =20 page_start =3D pc_start & TARGET_PAGE_MASK; num_insns =3D 0; - max_insns =3D tb_cflags(tb) & CF_COUNT_MASK; - if (max_insns =3D=3D 0) { - max_insns =3D CF_COUNT_MASK; - } - if (max_insns > TCG_MAX_INSNS) { - max_insns =3D TCG_MAX_INSNS; - } =20 gen_tb_start(tb); do diff --git a/target/mips/translate.c b/target/mips/translate.c index 7849d53977..f96c0d01ef 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -29721,11 +29721,11 @@ static const TranslatorOps mips_tr_ops =3D { .disas_log =3D mips_tr_disas_log, }; =20 -void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) +void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_ins= ns) { DisasContext ctx; =20 - translator_loop(&mips_tr_ops, &ctx.base, cs, tb); + translator_loop(&mips_tr_ops, &ctx.base, cs, tb, max_insns); } =20 static void fpu_dump_state(CPUMIPSState *env, FILE *f, int flags) diff --git a/target/moxie/translate.c b/target/moxie/translate.c index dd055c4ca5..c668178f2c 100644 --- a/target/moxie/translate.c +++ b/target/moxie/translate.c @@ -813,13 +813,13 @@ static int decode_opc(MoxieCPU *cpu, DisasContext *ct= x) } =20 /* generate intermediate code for basic block 'tb'. */ -void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) +void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_ins= ns) { CPUMoxieState *env =3D cs->env_ptr; MoxieCPU *cpu =3D moxie_env_get_cpu(env); DisasContext ctx; target_ulong pc_start; - int num_insns, max_insns; + int num_insns; =20 pc_start =3D tb->pc; ctx.pc =3D pc_start; @@ -829,13 +829,6 @@ void gen_intermediate_code(CPUState *cs, struct Transl= ationBlock *tb) ctx.singlestep_enabled =3D 0; ctx.bstate =3D BS_NONE; num_insns =3D 0; - max_insns =3D tb_cflags(tb) & CF_COUNT_MASK; - if (max_insns =3D=3D 0) { - max_insns =3D CF_COUNT_MASK; - } - if (max_insns > TCG_MAX_INSNS) { - max_insns =3D TCG_MAX_INSNS; - } =20 gen_tb_start(tb); do { diff --git a/target/nios2/translate.c b/target/nios2/translate.c index f0bbf78a32..17d8f1877c 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -806,12 +806,11 @@ static void gen_exception(DisasContext *dc, uint32_t = excp) } =20 /* generate intermediate code for basic block 'tb'. */ -void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) +void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_ins= ns) { CPUNios2State *env =3D cs->env_ptr; DisasContext dc1, *dc =3D &dc1; int num_insns; - int max_insns; =20 /* Initialize DC */ dc->cpu_env =3D cpu_env; @@ -824,20 +823,11 @@ void gen_intermediate_code(CPUState *cs, TranslationB= lock *tb) =20 /* Set up instruction counts */ num_insns =3D 0; - if (cs->singlestep_enabled || singlestep) { - max_insns =3D 1; - } else { + if (max_insns > 1) { int page_insns =3D (TARGET_PAGE_SIZE - (tb->pc & TARGET_PAGE_MASK)= ) / 4; - max_insns =3D tb_cflags(tb) & CF_COUNT_MASK; - if (max_insns =3D=3D 0) { - max_insns =3D CF_COUNT_MASK; - } if (max_insns > page_insns) { max_insns =3D page_insns; } - if (max_insns > TCG_MAX_INSNS) { - max_insns =3D TCG_MAX_INSNS; - } } =20 gen_tb_start(tb); diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index a88502fdc1..36821948c0 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -1409,11 +1409,11 @@ static const TranslatorOps openrisc_tr_ops =3D { .disas_log =3D openrisc_tr_disas_log, }; =20 -void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) +void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_ins= ns) { DisasContext ctx; =20 - translator_loop(&openrisc_tr_ops, &ctx.base, cs, tb); + translator_loop(&openrisc_tr_ops, &ctx.base, cs, tb, max_insns); } =20 void openrisc_cpu_dump_state(CPUState *cs, FILE *f, int flags) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 93d77a2626..dee2bb6910 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -7862,11 +7862,11 @@ static const TranslatorOps ppc_tr_ops =3D { .disas_log =3D ppc_tr_disas_log, }; =20 -void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) +void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_ins= ns) { DisasContext ctx; =20 - translator_loop(&ppc_tr_ops, &ctx.base, cs, tb); + translator_loop(&ppc_tr_ops, &ctx.base, cs, tb, max_insns); } =20 void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, diff --git a/target/riscv/translate.c b/target/riscv/translate.c index dd763647ea..967eac7bc3 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -783,11 +783,11 @@ static const TranslatorOps riscv_tr_ops =3D { .disas_log =3D riscv_tr_disas_log, }; =20 -void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) +void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_ins= ns) { DisasContext ctx; =20 - translator_loop(&riscv_tr_ops, &ctx.base, cs, tb); + translator_loop(&riscv_tr_ops, &ctx.base, cs, tb, max_insns); } =20 void riscv_translate_init(void) diff --git a/target/s390x/translate.c b/target/s390x/translate.c index 0afa8f7ca5..d4951836ad 100644 --- a/target/s390x/translate.c +++ b/target/s390x/translate.c @@ -6552,11 +6552,11 @@ static const TranslatorOps s390x_tr_ops =3D { .disas_log =3D s390x_tr_disas_log, }; =20 -void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) +void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_ins= ns) { DisasContext dc; =20 - translator_loop(&s390x_tr_ops, &dc.base, cs, tb); + translator_loop(&s390x_tr_ops, &dc.base, cs, tb, max_insns); } =20 void restore_state_to_opc(CPUS390XState *env, TranslationBlock *tb, diff --git a/target/sh4/translate.c b/target/sh4/translate.c index cffc6919d0..cdf0888490 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -2383,11 +2383,11 @@ static const TranslatorOps sh4_tr_ops =3D { .disas_log =3D sh4_tr_disas_log, }; =20 -void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) +void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_ins= ns) { DisasContext ctx; =20 - translator_loop(&sh4_tr_ops, &ctx.base, cs, tb); + translator_loop(&sh4_tr_ops, &ctx.base, cs, tb, max_insns); } =20 void restore_state_to_opc(CPUSH4State *env, TranslationBlock *tb, diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 74315cdf09..091bab53af 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -5962,11 +5962,11 @@ static const TranslatorOps sparc_tr_ops =3D { .disas_log =3D sparc_tr_disas_log, }; =20 -void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) +void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_ins= ns) { DisasContext dc =3D {}; =20 - translator_loop(&sparc_tr_ops, &dc.base, cs, tb); + translator_loop(&sparc_tr_ops, &dc.base, cs, tb, max_insns); } =20 void sparc_tcg_init(void) diff --git a/target/tilegx/translate.c b/target/tilegx/translate.c index df1e4d0fef..c46a4ab151 100644 --- a/target/tilegx/translate.c +++ b/target/tilegx/translate.c @@ -2369,7 +2369,7 @@ static void translate_one_bundle(DisasContext *dc, ui= nt64_t bundle) } } =20 -void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) +void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_ins= ns) { CPUTLGState *env =3D cs->env_ptr; DisasContext ctx; @@ -2377,7 +2377,6 @@ void gen_intermediate_code(CPUState *cs, struct Trans= lationBlock *tb) uint64_t pc_start =3D tb->pc; uint64_t page_start =3D pc_start & TARGET_PAGE_MASK; int num_insns =3D 0; - int max_insns =3D tb_cflags(tb) & CF_COUNT_MASK; =20 dc->pc =3D pc_start; dc->mmuidx =3D 0; @@ -2392,15 +2391,6 @@ void gen_intermediate_code(CPUState *cs, struct Tran= slationBlock *tb) qemu_log_lock(); qemu_log("IN: %s\n", lookup_symbol(pc_start)); } - if (!max_insns) { - max_insns =3D CF_COUNT_MASK; - } - if (cs->singlestep_enabled || singlestep) { - max_insns =3D 1; - } - if (max_insns > TCG_MAX_INSNS) { - max_insns =3D TCG_MAX_INSNS; - } gen_tb_start(tb); =20 while (1) { diff --git a/target/tricore/translate.c b/target/tricore/translate.c index 352f52bb4a..8f6416144e 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -8807,24 +8807,12 @@ static void decode_opc(CPUTriCoreState *env, DisasC= ontext *ctx, int *is_branch) } } =20 -void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) +void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_ins= ns) { CPUTriCoreState *env =3D cs->env_ptr; DisasContext ctx; target_ulong pc_start; - int num_insns, max_insns; - - num_insns =3D 0; - max_insns =3D tb_cflags(tb) & CF_COUNT_MASK; - if (max_insns =3D=3D 0) { - max_insns =3D CF_COUNT_MASK; - } - if (singlestep) { - max_insns =3D 1; - } - if (max_insns > TCG_MAX_INSNS) { - max_insns =3D TCG_MAX_INSNS; - } + int num_insns =3D 0; =20 pc_start =3D tb->pc; ctx.pc =3D pc_start; diff --git a/target/unicore32/translate.c b/target/unicore32/translate.c index dfe41c9069..89b02d1c3c 100644 --- a/target/unicore32/translate.c +++ b/target/unicore32/translate.c @@ -1871,14 +1871,13 @@ static void disas_uc32_insn(CPUUniCore32State *env,= DisasContext *s) } =20 /* generate intermediate code for basic block 'tb'. */ -void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) +void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_ins= ns) { CPUUniCore32State *env =3D cs->env_ptr; DisasContext dc1, *dc =3D &dc1; target_ulong pc_start; uint32_t page_start; int num_insns; - int max_insns; =20 /* generate intermediate code */ num_temps =3D 0; @@ -1897,13 +1896,6 @@ void gen_intermediate_code(CPUState *cs, Translation= Block *tb) cpu_F1d =3D tcg_temp_new_i64(); page_start =3D pc_start & TARGET_PAGE_MASK; num_insns =3D 0; - max_insns =3D tb_cflags(tb) & CF_COUNT_MASK; - if (max_insns =3D=3D 0) { - max_insns =3D CF_COUNT_MASK; - } - if (max_insns > TCG_MAX_INSNS) { - max_insns =3D TCG_MAX_INSNS; - } =20 #ifndef CONFIG_USER_ONLY if ((env->uncached_asr & ASR_M) =3D=3D ASR_MODE_USER) { diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index 43a5e94daa..301c8e3161 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -1635,10 +1635,10 @@ static const TranslatorOps xtensa_translator_ops = =3D { .disas_log =3D xtensa_tr_disas_log, }; =20 -void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb) +void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_in= sns) { DisasContext dc =3D {}; - translator_loop(&xtensa_translator_ops, &dc.base, cpu, tb); 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[97.113.179.147]) by smtp.gmail.com with ESMTPSA id j5sm7901762pfg.186.2019.04.26.10.24.33 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 26 Apr 2019 10:24:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=3CywljlasHfL8Ycnk57vM6Ac8IPl3XHI/QQlXit0YoU=; b=MonM3534UrqIVvSEtZvvDchMqiEFFiNcO8Y5L+Zei3KnAjWH8Pazvml/voPma/mHjk T65hokEglAPGIhkt6aluCVNkuo6ZZEeiThLz3futfmKVKirRl1K2TIVg/RdaYX6cIS2N D+FXYrqKHhWNBrQ67x/wpg8ZrwwUMqa/KL16biHFcgqy2WJAPyBVGT6xXYQp41q+JHVY xpEXBCzSJt3dw3uGO+u2SdbuIYqpmU07+yBUOaIgucXcAjt45yWBGUKDbV1m+IgBwjNk RxMQ0dtFb7kU1B8j1sgziqu8DohqzIZr1YKBQwPTvLKuxoi/85v9ew1WlY/7NxgOosSM vJlA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=3CywljlasHfL8Ycnk57vM6Ac8IPl3XHI/QQlXit0YoU=; b=uVxwq4raJ8VQtPov2mrkBFo6t/JoLRrOGOrusdIvQ5BYkkJ6u/rLQxZMHF4jR21TWu s32yW5078ch+SoVh2IiLdGWZ+qCHz5R5J4k0Ph1v1lkMpDhmuWLtl1enSU16WyypMAgm 8dNDi0Wbs+pxkNusLDmMH21UJaOUQ9UIKbgXKVU1tl4NcxoPuofN5+HZYkHOG1wFGTpD 1X1bZt9EraVdG578V45rgELLYgWX56g0CDWOb5NWDXN8zOPumNdH7+dq3qfn3n3s96pH hq+2k8VSzO7SNB5Ly86EvLo/lhmWtL1V4H8Bb/SOo8LKLNiuBeoei3NatZVJBykyJfiy 8qGg== X-Gm-Message-State: APjAAAXr7K3JioqAes4ier/rWikL3k9J0Ye7wN0BVL8NEn0NbEyPNVdp mDketjA01jLj4LF2b2BwMn3FgYe4Pcs= X-Google-Smtp-Source: APXvYqyHe79xbPrb5NpT4buAHB09RHsBQ2IDeZ0/4aSeixOZSYJbTIDuO7xLUmZbqc+e+U2dY5dybw== X-Received: by 2002:a63:cc48:: with SMTP id q8mr15704362pgi.202.1556299474477; Fri, 26 Apr 2019 10:24:34 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 26 Apr 2019 10:24:15 -0700 Message-Id: <20190426172421.27133-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190426172421.27133-1-richard.henderson@linaro.org> References: <20190426172421.27133-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::544 Subject: [Qemu-devel] [PULL 09/15] tcg: Restart after TB code generation overflow X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) If a TB generates too much code, try again with fewer insns. Fixes: https://bugs.launchpad.net/bugs/1824853 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- accel/tcg/translate-all.c | 38 ++++++++++++++++++++++++++++++++------ tcg/tcg.c | 4 ++++ 2 files changed, 36 insertions(+), 6 deletions(-) diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 39532fd44c..20b59f93f4 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1722,6 +1722,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, tb->cflags =3D cflags; tb->trace_vcpu_dstate =3D *cpu->trace_dstate; tcg_ctx->tb_cflags =3D cflags; + tb_overflow: =20 #ifdef CONFIG_PROFILER /* includes aborted translations because of exceptions */ @@ -1755,14 +1756,39 @@ TranslationBlock *tb_gen_code(CPUState *cpu, ti =3D profile_getclock(); #endif =20 - /* ??? Overflow could be handled better here. In particular, we - don't need to re-do gen_intermediate_code, nor should we re-do - the tcg optimization currently hidden inside tcg_gen_code. All - that should be required is to flush the TBs, allocate a new TB, - re-initialize it per above, and re-do the actual code generation. = */ gen_code_size =3D tcg_gen_code(tcg_ctx, tb); if (unlikely(gen_code_size < 0)) { - goto buffer_overflow; + switch (gen_code_size) { + case -1: + /* + * Overflow of code_gen_buffer, or the current slice of it. + * + * TODO: We don't need to re-do gen_intermediate_code, nor + * should we re-do the tcg optimization currently hidden + * inside tcg_gen_code. All that should be required is to + * flush the TBs, allocate a new TB, re-initialize it per + * above, and re-do the actual code generation. + */ + goto buffer_overflow; + + case -2: + /* + * The code generated for the TranslationBlock is too large. + * The maximum size allowed by the unwind info is 64k. + * There may be stricter constraints from relocations + * in the tcg backend. + * + * Try again with half as many insns as we attempted this time. + * If a single insn overflows, there's a bug somewhere... + */ + max_insns =3D tb->icount; + assert(max_insns > 1); + max_insns /=3D 2; + goto tb_overflow; + + default: + g_assert_not_reached(); + } } search_size =3D encode_search(tb, (void *)gen_code_buf + gen_code_size= ); if (unlikely(search_size < 0)) { diff --git a/tcg/tcg.c b/tcg/tcg.c index c0730f119f..5d255166c0 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -3996,6 +3996,10 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) if (unlikely((void *)s->code_ptr > s->code_gen_highwater)) { return -1; } + /* Test for TB overflow, as seen by gen_insn_end_off. */ + if (unlikely(tcg_current_code_size(s) > UINT16_MAX)) { + return -2; + } } tcg_debug_assert(num_insns >=3D 0); s->gen_insn_end_off[num_insns] =3D tcg_current_code_size(s); --=20 2.17.1 From nobody Sun Jun 2 07:52:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1556299614; cv=none; d=zoho.com; s=zohoarc; b=oQnIbw+oGmH2TKIuqxVcE+TMWvyxAk2YlyPmnTCSO5rKsMYP523HPgK3cEbowuA9qyZx3R97p8HmvudeFUqL7uioCzBQH7yBtvNh/yGCnYC72nBE6Kr+rVb8akvnwGu+RhXeeraLfq9PNMktpHFaF+R8TlqJdaGZBsOAjIQuLkA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1556299614; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=kpqVFtaSGqwvohuDuKrV4p1L52nRZgnSIh7tMyl91fs=; b=fN/yDb4I45TT/LX68Wyl+mgvuokcIbFNgd6pBpNVQApHwLtlZjkxVI60jIA376Ql7WDE+x0AyaONZCfcriMG6tBJJ3HZVyo7JRtg1qHqgSq8bQn/mI4egXJBjKjZGYI2ZLJ4dxBTrdMA726yJ9OlClOdul3fQ4ZTI5FzyAHRoAk= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1556299614067726.5714896356016; Fri, 26 Apr 2019 10:26:54 -0700 (PDT) Received: from localhost ([127.0.0.1]:49935 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hK4ca-0001X6-Ts for importer@patchew.org; Fri, 26 Apr 2019 13:26:49 -0400 Received: from eggs.gnu.org ([209.51.188.92]:48019) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hK4aU-000063-Fg for qemu-devel@nongnu.org; Fri, 26 Apr 2019 13:24:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hK4aT-0006nR-70 for qemu-devel@nongnu.org; Fri, 26 Apr 2019 13:24:38 -0400 Received: from mail-pg1-x52a.google.com ([2607:f8b0:4864:20::52a]:41201) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hK4aT-0006iv-0a for qemu-devel@nongnu.org; Fri, 26 Apr 2019 13:24:37 -0400 Received: by mail-pg1-x52a.google.com with SMTP id f6so1926257pgs.8 for ; Fri, 26 Apr 2019 10:24:36 -0700 (PDT) Received: from localhost.localdomain (97-113-179-147.tukw.qwest.net. [97.113.179.147]) by smtp.gmail.com with ESMTPSA id j5sm7901762pfg.186.2019.04.26.10.24.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 26 Apr 2019 10:24:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=kpqVFtaSGqwvohuDuKrV4p1L52nRZgnSIh7tMyl91fs=; b=qWcBYc/0k38/sWxUVkByNbTVtEn4xzeSQgih+cXNC0MN0MytS/Uw/5yn3RrqPhUNDq 8d8heByOri0hnQcwY1K+rK5eJncvfMF3jQu5HK/vVk65KIrbdlKY0pd4URPyvnVrqMYv lj7gu7liX8VHWIl2yXZ2lhBvFLh0Rn061jmauCks++mZC6W7HN1epotqs+GFpjDRdTqh JMofKXPAyGKT0N1hFlUXXCHfPCjJ6oo5w5J3r75xT5z3IHgmCgpGtdjaJ30QZkrsfdJt vsdDots+LVxmH2k4sELIXV6PttlHOjXbthg4pc5Xr22725/ctIwcvqoP+Jd4usBG5giX Kphw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=kpqVFtaSGqwvohuDuKrV4p1L52nRZgnSIh7tMyl91fs=; b=kuILZUdHKKavFNb5Ukly6WjYkkBl6hiXn4zTcl5TFG44psCo6guWuBvaGTO7ejEO4c U7XtYVILjym2jwbBtOzhY+jaFxKnaKiNLTS6YydJo9m2KQ1KEMT0N8AoM00Ne+e++iWe rhcX9F7e78bu1/izk31Bz9WdBerHTJt04dP5fPiB7ClIoORg/pMxnZlfBj50qL5EM+2T p2Q1rBnLp9PvoIJ4azFfwUHdroWFn34IExFAOkqs9zO/1V9fhL0yKD4ssmI4miSyqGIh 8QxeLWORJTSNZ8oGD1FkJnMmBKf7tqzgZDpdToqu32didCs3rBDRJe2t2JPYoFqG/yac SHYw== X-Gm-Message-State: APjAAAUtSp1nH2XeU4VMlnTgo3x8SdWeB40fmQf+ILPJgmCQgLBZn7jB szF+K+mmQtcJjOvX531bFHUlVi/tW8g= X-Google-Smtp-Source: APXvYqx4FvUsZlydsQh5QPoiafubfn6X34Wk7iuPH6tdCvAmMRhvqRoVan1IMdIntgq4qQ9QTIH+Ew== X-Received: by 2002:a62:60c1:: with SMTP id u184mr3218999pfb.106.1556299475648; Fri, 26 Apr 2019 10:24:35 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 26 Apr 2019 10:24:16 -0700 Message-Id: <20190426172421.27133-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190426172421.27133-1-richard.henderson@linaro.org> References: <20190426172421.27133-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::52a Subject: [Qemu-devel] [PULL 10/15] tcg: Restart TB generation after relocation overflow X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" If the TB generates too much code, such that backend relocations overflow, try again with a smaller TB. In support of this, move relocation processing from a random place within tcg_out_op, in the handling of branch opcodes, to a new function at the end of tcg_gen_code. This is not a complete solution, as there are additional relocs generated for out-of-line ldst handling and constant pools. Signed-off-by: Richard Henderson --- tcg/tcg.h | 15 +++++++------- tcg/tcg.c | 61 ++++++++++++++++++++++++++----------------------------- 2 files changed, 36 insertions(+), 40 deletions(-) diff --git a/tcg/tcg.h b/tcg/tcg.h index 50de1cdda3..cfc57110a1 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -238,12 +238,13 @@ typedef uint64_t tcg_insn_unit; do { if (!(X)) { __builtin_unreachable(); } } while (0) #endif =20 -typedef struct TCGRelocation { - struct TCGRelocation *next; - int type; +typedef struct TCGRelocation TCGRelocation; +struct TCGRelocation { + QSIMPLEQ_ENTRY(TCGRelocation) next; tcg_insn_unit *ptr; intptr_t addend; -} TCGRelocation;=20 + int type; +}; =20 typedef struct TCGLabel TCGLabel; struct TCGLabel { @@ -254,11 +255,9 @@ struct TCGLabel { union { uintptr_t value; tcg_insn_unit *value_ptr; - TCGRelocation *first_reloc; } u; -#ifdef CONFIG_DEBUG_TCG + QSIMPLEQ_HEAD(, TCGRelocation) relocs; QSIMPLEQ_ENTRY(TCGLabel) next; -#endif }; =20 typedef struct TCGPool { @@ -691,7 +690,6 @@ struct TCGContext { #endif =20 #ifdef CONFIG_DEBUG_TCG - QSIMPLEQ_HEAD(, TCGLabel) labels; int temps_in_use; int goto_tb_issue_mask; #endif @@ -729,6 +727,7 @@ struct TCGContext { TCGTemp temps[TCG_MAX_TEMPS]; /* globals first, temps after */ =20 QTAILQ_HEAD(, TCGOp) ops, free_ops; + QSIMPLEQ_HEAD(, TCGLabel) labels; =20 /* Tells which temporary holds a given register. It does not take into account fixed registers */ diff --git a/tcg/tcg.c b/tcg/tcg.c index 5d255166c0..752c45a0ec 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -263,37 +263,17 @@ static __attribute__((unused)) inline void tcg_patch6= 4(tcg_insn_unit *p, static void tcg_out_reloc(TCGContext *s, tcg_insn_unit *code_ptr, int type, TCGLabel *l, intptr_t addend) { - TCGRelocation *r; + TCGRelocation *r =3D tcg_malloc(sizeof(TCGRelocation)); =20 - if (l->has_value) { - /* FIXME: This may break relocations on RISC targets that - modify instruction fields in place. The caller may not have=20 - written the initial value. */ - bool ok =3D patch_reloc(code_ptr, type, l->u.value, addend); - tcg_debug_assert(ok); - } else { - /* add a new relocation entry */ - r =3D tcg_malloc(sizeof(TCGRelocation)); - r->type =3D type; - r->ptr =3D code_ptr; - r->addend =3D addend; - r->next =3D l->u.first_reloc; - l->u.first_reloc =3D r; - } + r->type =3D type; + r->ptr =3D code_ptr; + r->addend =3D addend; + QSIMPLEQ_INSERT_TAIL(&l->relocs, r, next); } =20 static void tcg_out_label(TCGContext *s, TCGLabel *l, tcg_insn_unit *ptr) { - intptr_t value =3D (intptr_t)ptr; - TCGRelocation *r; - tcg_debug_assert(!l->has_value); - - for (r =3D l->u.first_reloc; r !=3D NULL; r =3D r->next) { - bool ok =3D patch_reloc(r->ptr, r->type, value, r->addend); - tcg_debug_assert(ok); - } - l->has_value =3D 1; l->u.value_ptr =3D ptr; } @@ -303,16 +283,32 @@ TCGLabel *gen_new_label(void) TCGContext *s =3D tcg_ctx; TCGLabel *l =3D tcg_malloc(sizeof(TCGLabel)); =20 - *l =3D (TCGLabel){ - .id =3D s->nb_labels++ - }; -#ifdef CONFIG_DEBUG_TCG + memset(l, 0, sizeof(TCGLabel)); + l->id =3D s->nb_labels++; + QSIMPLEQ_INIT(&l->relocs); + QSIMPLEQ_INSERT_TAIL(&s->labels, l, next); -#endif =20 return l; } =20 +static bool tcg_resolve_relocs(TCGContext *s) +{ + TCGLabel *l; + + QSIMPLEQ_FOREACH(l, &s->labels, next) { + TCGRelocation *r; + uintptr_t value =3D l->u.value; + + QSIMPLEQ_FOREACH(r, &l->relocs, next) { + if (!patch_reloc(r->ptr, r->type, value, r->addend)) { + return false; + } + } + } + return true; +} + static void set_jmp_reset_offset(TCGContext *s, int which) { size_t off =3D tcg_current_code_size(s); @@ -1096,9 +1092,7 @@ void tcg_func_start(TCGContext *s) =20 QTAILQ_INIT(&s->ops); QTAILQ_INIT(&s->free_ops); -#ifdef CONFIG_DEBUG_TCG QSIMPLEQ_INIT(&s->labels); -#endif } =20 static inline TCGTemp *tcg_temp_alloc(TCGContext *s) @@ -4015,6 +4009,9 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) return -1; } #endif + if (!tcg_resolve_relocs(s)) { + return -2; + } =20 /* flush instruction cache */ flush_icache_range((uintptr_t)s->code_buf, (uintptr_t)s->code_ptr); --=20 2.17.1 From nobody Sun Jun 2 07:52:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1556300132; cv=none; d=zoho.com; s=zohoarc; b=OAEAQ3v851yFrGEQA6jelYvhmi+W06LF1QUEOLTDZVUf2dJ7W098VPszv8xdv/uoYtvhySequUI+GjCgoygqXaITwpb5O76W3wXq8PBIVQtInkXIMgbHGDMIs03dDEpq455bAycHq8Quw0LSQ77VFm2YEJ6m40rwWKJR7G/9KxM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1556300132; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=Th3t/m0PioLpL2J3JR8QFGClCdlEYB4fbvw9qC7v3uc=; b=B6p9i6mk+lF7vr7ATGfrk0frW0cvGxWq4nj7Lshob3dJ5IvvfZyqNII5y9ge/Vtnf8Ui+A76ScTfEM9HtfHM4eTaufIBe9TfUv2XispDtqwNlBJkPwBQO3Bw8VwXPNVth/EWjJzg0ky1RIid+wNwcr07JXgAIYDujFyojy/ADUU= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1556300132873904.8816141204752; Fri, 26 Apr 2019 10:35:32 -0700 (PDT) Received: from localhost ([127.0.0.1]:50035 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hK4kz-0001Kd-RX for importer@patchew.org; Fri, 26 Apr 2019 13:35:29 -0400 Received: from eggs.gnu.org ([209.51.188.92]:48029) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hK4aV-00006v-C6 for qemu-devel@nongnu.org; Fri, 26 Apr 2019 13:24:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hK4aU-0006ry-By for qemu-devel@nongnu.org; Fri, 26 Apr 2019 13:24:39 -0400 Received: from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f]:37750) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hK4aU-0006p7-5b for qemu-devel@nongnu.org; Fri, 26 Apr 2019 13:24:38 -0400 Received: by mail-pl1-x62f.google.com with SMTP id z8so1890877pln.4 for ; Fri, 26 Apr 2019 10:24:38 -0700 (PDT) Received: from localhost.localdomain (97-113-179-147.tukw.qwest.net. [97.113.179.147]) by smtp.gmail.com with ESMTPSA id j5sm7901762pfg.186.2019.04.26.10.24.35 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 26 Apr 2019 10:24:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Th3t/m0PioLpL2J3JR8QFGClCdlEYB4fbvw9qC7v3uc=; b=bQN6xkF/6mjgQD6aoiJqtsk8mR0nzfMl75mMliR0HvOyqTyOSLkC+nS54FGwy3wrAN ec4JcnGOH0gDVgLJhdz/ZjVxjozWSn/H/MfoGlIVzqMl55sYRIgDE8wguYCbmQ+34P0J FJqx6JEr5KIEiIgQdSkGC4gZiQIX+JDeJFcchFDaKhL1eQ3og9oXXJLHRd7HdWmbnapA r9hAgjUsAsEsD2G40ia2iQLXGy9LxaK37E+H0QYD+Ih1td3bgseSvME1NVtiKEw9pnNO J5S6vc1DDkzVcdRagOD600pOzJIzNIQiM2LeeqUzAES8W4I4a90IABdfgRoaXnjGtrsq f6KA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Th3t/m0PioLpL2J3JR8QFGClCdlEYB4fbvw9qC7v3uc=; b=f/5jwPrFTVxB7vsbGuWLHsuvRVToMKoRjth+k7pi92/NN0bGUZatOjaNeq2cMu8g4R uY7a1akP24zUytO5V7x7e4qsCMOtVUT34orsekmzg2zUu5hY3preTjdQdr4VIOqZdEO6 PCMLOT9yxFflCtnx0X7W4er2iE7OebivV/stgtFYPqbwkz6r2Y1hpiRMYn9R85xYSpVC gvivTAHRxmcqUbcl22Bz7FubrgNFJcSZ4bcO0RpizN8ILvzvchOg7t4RBcn+9V7io4bv NwDpJkRPLy8EdAytvZ+RXIQ6zi6ICDxLPeUFhUCL6KiIHhQwCGc3QIvY2zfk75uXF77v xarQ== X-Gm-Message-State: APjAAAXAlxJ6adhYAslxEZbj2mW/73tunmAwsweTJASMxsd/kAaWEoke ItU3y96e1B2izcFSmzprhab8Ece/Yek= X-Google-Smtp-Source: APXvYqzjqp7aAl9jfKfz5A5GMuTEWKsj0+cNzAKHk/HO9jk9pYFfeyAiHI2RTXuW7/yOKWIokdSMGw== X-Received: by 2002:a17:902:758b:: with SMTP id j11mr10005815pll.87.1556299476903; Fri, 26 Apr 2019 10:24:36 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 26 Apr 2019 10:24:17 -0700 Message-Id: <20190426172421.27133-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190426172421.27133-1-richard.henderson@linaro.org> References: <20190426172421.27133-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::62f Subject: [Qemu-devel] [PULL 11/15] tcg: Restart TB generation after constant pool overflow X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This is part b of relocation overflow handling. Signed-off-by: Richard Henderson --- tcg/tcg-pool.inc.c | 12 +++++++----- tcg/tcg.c | 9 +++++---- 2 files changed, 12 insertions(+), 9 deletions(-) diff --git a/tcg/tcg-pool.inc.c b/tcg/tcg-pool.inc.c index 7af5513ff3..4eaa84b631 100644 --- a/tcg/tcg-pool.inc.c +++ b/tcg/tcg-pool.inc.c @@ -121,14 +121,14 @@ static inline void new_pool_l8(TCGContext *s, int rty= pe, tcg_insn_unit *label, /* To be provided by cpu/tcg-target.inc.c. */ static void tcg_out_nop_fill(tcg_insn_unit *p, int count); =20 -static bool tcg_out_pool_finalize(TCGContext *s) +static int tcg_out_pool_finalize(TCGContext *s) { TCGLabelPoolData *p =3D s->pool_labels; TCGLabelPoolData *l =3D NULL; void *a; =20 if (p =3D=3D NULL) { - return true; + return 0; } =20 /* ??? Round up to qemu_icache_linesize, but then do not round @@ -142,15 +142,17 @@ static bool tcg_out_pool_finalize(TCGContext *s) size_t size =3D sizeof(tcg_target_ulong) * p->nlong; if (!l || l->nlong !=3D p->nlong || memcmp(l->data, p->data, size)= ) { if (unlikely(a > s->code_gen_highwater)) { - return false; + return -1; } memcpy(a, p->data, size); a +=3D size; l =3D p; } - patch_reloc(p->label, p->rtype, (intptr_t)a - size, p->addend); + if (!patch_reloc(p->label, p->rtype, (intptr_t)a - size, p->addend= )) { + return -2; + } } =20 s->code_ptr =3D a; - return true; + return 0; } diff --git a/tcg/tcg.c b/tcg/tcg.c index 752c45a0ec..0394e8ab34 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1019,8 +1019,8 @@ void tcg_prologue_init(TCGContext *s) #ifdef TCG_TARGET_NEED_POOL_LABELS /* Allow the prologue to put e.g. guest_base into a pool entry. */ { - bool ok =3D tcg_out_pool_finalize(s); - tcg_debug_assert(ok); + int result =3D tcg_out_pool_finalize(s); + tcg_debug_assert(result =3D=3D 0); } #endif =20 @@ -4005,8 +4005,9 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) } #endif #ifdef TCG_TARGET_NEED_POOL_LABELS - if (!tcg_out_pool_finalize(s)) { - return -1; + i =3D tcg_out_pool_finalize(s); + if (i < 0) { + return i; } #endif if (!tcg_resolve_relocs(s)) { --=20 2.17.1 From nobody Sun Jun 2 07:52:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1556300117; cv=none; d=zoho.com; s=zohoarc; b=XxJD4aAT9FOqeLxG05NR9TyZfyR10ft7/mpq0jTfmua7hf/2pXduXq/St20+dUwrjlA+AIKhDl3e6ifGGSJcMaMMRoNjRVN7ApoLqy6DMwn4CqSyT5BvA3DiS6QpPW01P7UHO4tcWg1MOQSYRIAhycxO0Iz998pW9/YzXG7rR4k= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1556300117; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=n8SNl7SbB5n04Pd6SexcJw1I8YzVfNG3KGOvvgv8YbI=; b=oQu9pFdvr0g+7ZNZ48wWivD6AwBNB6ubaDy5bSwTH36NiXNjtF2VlH7HiYTcTdWM0hKAVarYK3t2NZN3+OM3RfNwYweUXYa2gyYZv+m5/gOPaItLq1lJqoMh1NZEInvJIOinGBx5EJPFhjAjXhBKcJikmxyf0XAGmsVvd92p8Tk= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1556300117073812.3720828692933; Fri, 26 Apr 2019 10:35:17 -0700 (PDT) Received: from localhost ([127.0.0.1]:50031 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hK4kk-00018S-M5 for importer@patchew.org; Fri, 26 Apr 2019 13:35:14 -0400 Received: from eggs.gnu.org ([209.51.188.92]:48057) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hK4aX-00009M-Nh for qemu-devel@nongnu.org; Fri, 26 Apr 2019 13:24:45 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hK4aV-000715-Nv for qemu-devel@nongnu.org; Fri, 26 Apr 2019 13:24:41 -0400 Received: from mail-pl1-x642.google.com ([2607:f8b0:4864:20::642]:38939) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hK4aV-0006ve-EO for qemu-devel@nongnu.org; Fri, 26 Apr 2019 13:24:39 -0400 Received: by mail-pl1-x642.google.com with SMTP id e92so1881900plb.6 for ; Fri, 26 Apr 2019 10:24:39 -0700 (PDT) Received: from localhost.localdomain (97-113-179-147.tukw.qwest.net. [97.113.179.147]) by smtp.gmail.com with ESMTPSA id j5sm7901762pfg.186.2019.04.26.10.24.36 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 26 Apr 2019 10:24:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=n8SNl7SbB5n04Pd6SexcJw1I8YzVfNG3KGOvvgv8YbI=; b=mPiH9nB+jG73WeOqUX/QGWYyS3857I9s9USp68njHW2DVSc1DD4l0FX/s/SdNp+j+2 6Pjo+NF5YzkS3yYo/ApbAnAGBTWBTCXvUX/nqnJXebC6n2Vsb3RNEUJjyXpQljNmJesu cVEncUxxf1zG3OKvuvpQzFRFOdqv1Fm27gh2+ZEtFJFAgoSAJzNFkjBPiJxSklSmZM7+ KEDPwk5GPu9l6J4pRJqmNw0f+eyN+pPYFHSyXx3lwaGky9gILtC6Uea7ipGLI+4wcpZ2 mGOkfriy7rFc3UMHF5cpqMec7i9SJt5hGShpm6Zr+i0wtmZzAOP4KAPNOya6AaPVMzsR FLrg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=n8SNl7SbB5n04Pd6SexcJw1I8YzVfNG3KGOvvgv8YbI=; b=YfP8FBAGtf82Yn4ar0Je8FY2zEuT7bj7aA7EpVuEFLAb9LI1625X7lXb71SEpfaOzf nmxaDGVB0YId3UMYz/gN5MVCV+4hNsI+lnKGFJ+Ho5aYIAzfxTBBz3jjjP5s9pWnYbmk elGLNIQkADM5ovKHvdGpUZrEpUXlSvMHy9GsVafMYVAb8oMt9RvnQg1n/jbDLvoRTRup eURh1w6Fci9GFtQu++Zx/63Dp8rGQ7KEqCuz8EDa5uhMhNSrJSh6W7FycOYgU54Gl8rS /Rm49+Xfd/prNt+q9rnHXzN9ajoLWLo4e1p5dxUQpy23DQRSadPC383KV3WwgIDg25mS Lr8A== X-Gm-Message-State: APjAAAWw0/H7U5MRgEnpzncKmp7xpHi8ciZPh1+DoQbeg1JhViB5MqOV ghX//UhKOzX/IrNI1Gd2JOqc8zUPhiw= X-Google-Smtp-Source: APXvYqyKBnB5C20kBNOVHjfdUDnWsj/xhM/9BTkqccYjGTKfoCl4EW51+znjWvx1vkfkHd+nq/Vc0A== X-Received: by 2002:a17:902:e285:: with SMTP id cf5mr10523914plb.77.1556299477925; Fri, 26 Apr 2019 10:24:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 26 Apr 2019 10:24:18 -0700 Message-Id: <20190426172421.27133-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190426172421.27133-1-richard.henderson@linaro.org> References: <20190426172421.27133-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::642 Subject: [Qemu-devel] [PULL 12/15] tcg: Restart TB generation after out-of-line ldst overflow X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This is part c of relocation overflow handling. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.inc.c | 16 ++++++++++------ tcg/arm/tcg-target.inc.c | 16 ++++++++++------ tcg/i386/tcg-target.inc.c | 6 ++++-- tcg/mips/tcg-target.inc.c | 6 ++++-- tcg/ppc/tcg-target.inc.c | 14 ++++++++++---- tcg/riscv/tcg-target.inc.c | 16 ++++++++++++---- tcg/s390/tcg-target.inc.c | 20 ++++++++++++-------- tcg/tcg-ldst.inc.c | 18 +++++++++--------- tcg/tcg.c | 7 ++++--- 9 files changed, 75 insertions(+), 44 deletions(-) diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c index 8b93598bce..eefa929948 100644 --- a/tcg/aarch64/tcg-target.inc.c +++ b/tcg/aarch64/tcg-target.inc.c @@ -1395,14 +1395,15 @@ static inline void tcg_out_adr(TCGContext *s, TCGRe= g rd, void *target) tcg_out_insn(s, 3406, ADR, rd, offset); } =20 -static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) +static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) { TCGMemOpIdx oi =3D lb->oi; TCGMemOp opc =3D get_memop(oi); TCGMemOp size =3D opc & MO_SIZE; =20 - bool ok =3D reloc_pc19(lb->label_ptr[0], s->code_ptr); - tcg_debug_assert(ok); + if (!reloc_pc19(lb->label_ptr[0], s->code_ptr)) { + return false; + } =20 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_X0, TCG_AREG0); tcg_out_mov(s, TARGET_LONG_BITS =3D=3D 64, TCG_REG_X1, lb->addrlo_reg); @@ -1416,16 +1417,18 @@ static void tcg_out_qemu_ld_slow_path(TCGContext *s= , TCGLabelQemuLdst *lb) } =20 tcg_out_goto(s, lb->raddr); + return true; } =20 -static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) +static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) { TCGMemOpIdx oi =3D lb->oi; TCGMemOp opc =3D get_memop(oi); TCGMemOp size =3D opc & MO_SIZE; =20 - bool ok =3D reloc_pc19(lb->label_ptr[0], s->code_ptr); - tcg_debug_assert(ok); + if (!reloc_pc19(lb->label_ptr[0], s->code_ptr)) { + return false; + } =20 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_X0, TCG_AREG0); tcg_out_mov(s, TARGET_LONG_BITS =3D=3D 64, TCG_REG_X1, lb->addrlo_reg); @@ -1434,6 +1437,7 @@ static void tcg_out_qemu_st_slow_path(TCGContext *s, = TCGLabelQemuLdst *lb) tcg_out_adr(s, TCG_REG_X4, lb->raddr); tcg_out_call(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]); tcg_out_goto(s, lb->raddr); + return true; } =20 static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi, diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c index 6873b0cf95..12a65cc9a6 100644 --- a/tcg/arm/tcg-target.inc.c +++ b/tcg/arm/tcg-target.inc.c @@ -1372,15 +1372,16 @@ static void add_qemu_ldst_label(TCGContext *s, bool= is_ld, TCGMemOpIdx oi, label->label_ptr[0] =3D label_ptr; } =20 -static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) +static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) { TCGReg argreg, datalo, datahi; TCGMemOpIdx oi =3D lb->oi; TCGMemOp opc =3D get_memop(oi); void *func; =20 - bool ok =3D reloc_pc24(lb->label_ptr[0], s->code_ptr); - tcg_debug_assert(ok); + if (!reloc_pc24(lb->label_ptr[0], s->code_ptr)) { + return false; + } =20 argreg =3D tcg_out_arg_reg32(s, TCG_REG_R0, TCG_AREG0); if (TARGET_LONG_BITS =3D=3D 64) { @@ -1432,16 +1433,18 @@ static void tcg_out_qemu_ld_slow_path(TCGContext *s= , TCGLabelQemuLdst *lb) } =20 tcg_out_goto(s, COND_AL, lb->raddr); + return true; } =20 -static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) +static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) { TCGReg argreg, datalo, datahi; TCGMemOpIdx oi =3D lb->oi; TCGMemOp opc =3D get_memop(oi); =20 - bool ok =3D reloc_pc24(lb->label_ptr[0], s->code_ptr); - tcg_debug_assert(ok); + if (!reloc_pc24(lb->label_ptr[0], s->code_ptr)) { + return false; + } =20 argreg =3D TCG_REG_R0; argreg =3D tcg_out_arg_reg32(s, argreg, TCG_AREG0); @@ -1474,6 +1477,7 @@ static void tcg_out_qemu_st_slow_path(TCGContext *s, = TCGLabelQemuLdst *lb) =20 /* Tail-call to the helper, which will return to the fast path. */ tcg_out_goto(s, COND_AL, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]); + return true; } #endif /* SOFTMMU */ =20 diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index 1fa833840e..d5ed9f1ffd 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -1730,7 +1730,7 @@ static void add_qemu_ldst_label(TCGContext *s, bool i= s_ld, bool is_64, /* * Generate code for the slow path for a load at the end of block */ -static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) +static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) { TCGMemOpIdx oi =3D l->oi; TCGMemOp opc =3D get_memop(oi); @@ -1809,12 +1809,13 @@ static void tcg_out_qemu_ld_slow_path(TCGContext *s= , TCGLabelQemuLdst *l) =20 /* Jump to the code corresponding to next IR of qemu_st */ tcg_out_jmp(s, l->raddr); + return true; } =20 /* * Generate code for the slow path for a store at the end of block */ -static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) +static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) { TCGMemOpIdx oi =3D l->oi; TCGMemOp opc =3D get_memop(oi); @@ -1877,6 +1878,7 @@ static void tcg_out_qemu_st_slow_path(TCGContext *s, = TCGLabelQemuLdst *l) /* "Tail call" to the helper, with the return address back inline. */ tcg_out_push(s, retaddr); tcg_out_jmp(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]); + return true; } #elif TCG_TARGET_REG_BITS =3D=3D 32 # define x86_guest_base_seg 0 diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c index 8a92e916dd..412cacdcb9 100644 --- a/tcg/mips/tcg-target.inc.c +++ b/tcg/mips/tcg-target.inc.c @@ -1338,7 +1338,7 @@ static void add_qemu_ldst_label(TCGContext *s, int is= _ld, TCGMemOpIdx oi, } } =20 -static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) +static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) { TCGMemOpIdx oi =3D l->oi; TCGMemOp opc =3D get_memop(oi); @@ -1385,9 +1385,10 @@ static void tcg_out_qemu_ld_slow_path(TCGContext *s,= TCGLabelQemuLdst *l) } else { tcg_out_opc_reg(s, OPC_OR, v0, TCG_REG_V0, TCG_REG_ZERO); } + return true; } =20 -static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) +static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) { TCGMemOpIdx oi =3D l->oi; TCGMemOp opc =3D get_memop(oi); @@ -1435,6 +1436,7 @@ static void tcg_out_qemu_st_slow_path(TCGContext *s, = TCGLabelQemuLdst *l) tcg_out_call_int(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)], true); /* delay slot */ tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_AREG0); + return true; } #endif =20 diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index 773690f1d9..c0923ced4f 100644 --- a/tcg/ppc/tcg-target.inc.c +++ b/tcg/ppc/tcg-target.inc.c @@ -1653,13 +1653,15 @@ static void add_qemu_ldst_label(TCGContext *s, bool= is_ld, TCGMemOpIdx oi, label->label_ptr[0] =3D lptr; } =20 -static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) +static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) { TCGMemOpIdx oi =3D lb->oi; TCGMemOp opc =3D get_memop(oi); TCGReg hi, lo, arg =3D TCG_REG_R3; =20 - **lb->label_ptr |=3D reloc_pc14_val(*lb->label_ptr, s->code_ptr); + if (!reloc_pc14(lb->label_ptr[0], s->code_ptr)) { + return false; + } =20 tcg_out_mov(s, TCG_TYPE_PTR, arg++, TCG_AREG0); =20 @@ -1695,16 +1697,19 @@ static void tcg_out_qemu_ld_slow_path(TCGContext *s= , TCGLabelQemuLdst *lb) } =20 tcg_out_b(s, 0, lb->raddr); + return true; } =20 -static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) +static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) { TCGMemOpIdx oi =3D lb->oi; TCGMemOp opc =3D get_memop(oi); TCGMemOp s_bits =3D opc & MO_SIZE; TCGReg hi, lo, arg =3D TCG_REG_R3; =20 - **lb->label_ptr |=3D reloc_pc14_val(*lb->label_ptr, s->code_ptr); + if (!reloc_pc14(lb->label_ptr[0], s->code_ptr)) { + return false; + } =20 tcg_out_mov(s, TCG_TYPE_PTR, arg++, TCG_AREG0); =20 @@ -1753,6 +1758,7 @@ static void tcg_out_qemu_st_slow_path(TCGContext *s, = TCGLabelQemuLdst *lb) tcg_out_call(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]); =20 tcg_out_b(s, 0, lb->raddr); + return true; } #endif /* SOFTMMU */ =20 diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c index b785f4acb7..2932505094 100644 --- a/tcg/riscv/tcg-target.inc.c +++ b/tcg/riscv/tcg-target.inc.c @@ -1065,7 +1065,7 @@ static void add_qemu_ldst_label(TCGContext *s, int is= _ld, TCGMemOpIdx oi, label->label_ptr[0] =3D label_ptr[0]; } =20 -static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) +static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) { TCGMemOpIdx oi =3D l->oi; TCGMemOp opc =3D get_memop(oi); @@ -1080,7 +1080,10 @@ static void tcg_out_qemu_ld_slow_path(TCGContext *s,= TCGLabelQemuLdst *l) } =20 /* resolve label address */ - patch_reloc(l->label_ptr[0], R_RISCV_BRANCH, (intptr_t) s->code_ptr, 0= ); + if (!patch_reloc(l->label_ptr[0], R_RISCV_BRANCH, + (intptr_t) s->code_ptr, 0)) { + return false; + } =20 /* call load helper */ tcg_out_mov(s, TCG_TYPE_PTR, a0, TCG_AREG0); @@ -1092,9 +1095,10 @@ static void tcg_out_qemu_ld_slow_path(TCGContext *s,= TCGLabelQemuLdst *l) tcg_out_mov(s, (opc & MO_SIZE) =3D=3D MO_64, l->datalo_reg, a0); =20 tcg_out_goto(s, l->raddr); + return true; } =20 -static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) +static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) { TCGMemOpIdx oi =3D l->oi; TCGMemOp opc =3D get_memop(oi); @@ -1111,7 +1115,10 @@ static void tcg_out_qemu_st_slow_path(TCGContext *s,= TCGLabelQemuLdst *l) } =20 /* resolve label address */ - patch_reloc(l->label_ptr[0], R_RISCV_BRANCH, (intptr_t) s->code_ptr, 0= ); + if (!patch_reloc(l->label_ptr[0], R_RISCV_BRANCH, + (intptr_t) s->code_ptr, 0)) { + return false; + } =20 /* call store helper */ tcg_out_mov(s, TCG_TYPE_PTR, a0, TCG_AREG0); @@ -1133,6 +1140,7 @@ static void tcg_out_qemu_st_slow_path(TCGContext *s, = TCGLabelQemuLdst *l) tcg_out_call(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SSIZE)]); =20 tcg_out_goto(s, l->raddr); + return true; } #endif /* CONFIG_SOFTMMU */ =20 diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c index 7db90b3bae..3d6150b10e 100644 --- a/tcg/s390/tcg-target.inc.c +++ b/tcg/s390/tcg-target.inc.c @@ -1609,16 +1609,17 @@ static void add_qemu_ldst_label(TCGContext *s, bool= is_ld, TCGMemOpIdx oi, label->label_ptr[0] =3D label_ptr; } =20 -static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) +static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) { TCGReg addr_reg =3D lb->addrlo_reg; TCGReg data_reg =3D lb->datalo_reg; TCGMemOpIdx oi =3D lb->oi; TCGMemOp opc =3D get_memop(oi); =20 - bool ok =3D patch_reloc(lb->label_ptr[0], R_390_PC16DBL, - (intptr_t)s->code_ptr, 2); - tcg_debug_assert(ok); + if (!patch_reloc(lb->label_ptr[0], R_390_PC16DBL, + (intptr_t)s->code_ptr, 2)) { + return false; + } =20 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_R2, TCG_AREG0); if (TARGET_LONG_BITS =3D=3D 64) { @@ -1630,18 +1631,20 @@ static void tcg_out_qemu_ld_slow_path(TCGContext *s= , TCGLabelQemuLdst *lb) tcg_out_mov(s, TCG_TYPE_I64, data_reg, TCG_REG_R2); =20 tgen_gotoi(s, S390_CC_ALWAYS, lb->raddr); + return true; } =20 -static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) +static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) { TCGReg addr_reg =3D lb->addrlo_reg; TCGReg data_reg =3D lb->datalo_reg; TCGMemOpIdx oi =3D lb->oi; TCGMemOp opc =3D get_memop(oi); =20 - bool ok =3D patch_reloc(lb->label_ptr[0], R_390_PC16DBL, - (intptr_t)s->code_ptr, 2); - tcg_debug_assert(ok); + if (!patch_reloc(lb->label_ptr[0], R_390_PC16DBL, + (intptr_t)s->code_ptr, 2)) { + return false; + } =20 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_R2, TCG_AREG0); if (TARGET_LONG_BITS =3D=3D 64) { @@ -1668,6 +1671,7 @@ static void tcg_out_qemu_st_slow_path(TCGContext *s, = TCGLabelQemuLdst *lb) tcg_out_call(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]); =20 tgen_gotoi(s, S390_CC_ALWAYS, lb->raddr); + return true; } #else static void tcg_prepare_user_ldst(TCGContext *s, TCGReg *addr_reg, diff --git a/tcg/tcg-ldst.inc.c b/tcg/tcg-ldst.inc.c index 47f41b921b..05f9b3ccd6 100644 --- a/tcg/tcg-ldst.inc.c +++ b/tcg/tcg-ldst.inc.c @@ -38,19 +38,19 @@ typedef struct TCGLabelQemuLdst { * Generate TB finalization at the end of block */ =20 -static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l); -static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l); +static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l); +static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l); =20 -static bool tcg_out_ldst_finalize(TCGContext *s) +static int tcg_out_ldst_finalize(TCGContext *s) { TCGLabelQemuLdst *lb; =20 /* qemu_ld/st slow paths */ QSIMPLEQ_FOREACH(lb, &s->ldst_labels, next) { - if (lb->is_ld) { - tcg_out_qemu_ld_slow_path(s, lb); - } else { - tcg_out_qemu_st_slow_path(s, lb); + if (lb->is_ld + ? !tcg_out_qemu_ld_slow_path(s, lb) + : !tcg_out_qemu_st_slow_path(s, lb)) { + return -2; } =20 /* Test for (pending) buffer overflow. The assumption is that any @@ -58,10 +58,10 @@ static bool tcg_out_ldst_finalize(TCGContext *s) the buffer completely. Thus we can test for overflow after generating code without having to check during generation. */ if (unlikely((void *)s->code_ptr > s->code_gen_highwater)) { - return false; + return -1; } } - return true; + return 0; } =20 /* diff --git a/tcg/tcg.c b/tcg/tcg.c index 0394e8ab34..f7bef51de8 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -128,7 +128,7 @@ static void tcg_out_call(TCGContext *s, tcg_insn_unit *= target); static int tcg_target_const_match(tcg_target_long val, TCGType type, const TCGArgConstraint *arg_ct); #ifdef TCG_TARGET_NEED_LDST_LABELS -static bool tcg_out_ldst_finalize(TCGContext *s); +static int tcg_out_ldst_finalize(TCGContext *s); #endif =20 #define TCG_HIGHWATER 1024 @@ -4000,8 +4000,9 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) =20 /* Generate TB finalization at the end of block */ #ifdef TCG_TARGET_NEED_LDST_LABELS - if (!tcg_out_ldst_finalize(s)) { - return -1; + i =3D tcg_out_ldst_finalize(s); + if (i < 0) { + return i; } #endif #ifdef TCG_TARGET_NEED_POOL_LABELS --=20 2.17.1 From nobody Sun Jun 2 07:52:28 2024 Delivered-To: importer@patchew.org Received-SPF: temperror (zoho.com: Error in retrieving data from DNS) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1556300277; cv=none; d=zoho.com; s=zohoarc; b=aeHBJoYjRRZ5zO33tFxOvHB5zGH84Zml6z9Dz12qkGq4hiMCFWmzy+OPohiFzbfu26RJXyAN8A3BEYXrfalQM/IrUyYHxHQxZcDDs6KOAjSxzCb/hqAHGeRDMJhrJvaxgDCbw3BtGUKqElHxygDgJOeQ0zHv0Rzc4NqI5eLnv5w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1556300277; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=57LLTjI1nQcm9nBGSTBf3sb093E20lD7cyEUFj3ghB4=; b=SDEmHEiRoblwfKsmhHcM+DRLaTnRrbnZj7CbU/6LARFCkS0Wn4wxdBpZ9XosN6c2edyG6LZrqq7eWq9S3Bn+x8Z7ePmpO7xnSfTtoZPAHnUMWG8rpvq0tUU7992Ay3LEyM9AjCWg1N9lvHQdHvfUcJrzvoNQKHKXGk9RgRsMJpQ= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1556300277408228.156936356571; Fri, 26 Apr 2019 10:37:57 -0700 (PDT) Received: from localhost ([127.0.0.1]:50089 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hK4nA-0003QH-0K for importer@patchew.org; Fri, 26 Apr 2019 13:37:44 -0400 Received: from eggs.gnu.org ([209.51.188.92]:48055) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hK4aX-00009I-Mz for qemu-devel@nongnu.org; Fri, 26 Apr 2019 13:24:45 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hK4aW-00076W-Mf for qemu-devel@nongnu.org; Fri, 26 Apr 2019 13:24:41 -0400 Received: from mail-pl1-x644.google.com ([2607:f8b0:4864:20::644]:35610) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hK4aW-00072j-Gw for qemu-devel@nongnu.org; Fri, 26 Apr 2019 13:24:40 -0400 Received: by mail-pl1-x644.google.com with SMTP id w24so1892625plp.2 for ; Fri, 26 Apr 2019 10:24:40 -0700 (PDT) Received: from localhost.localdomain (97-113-179-147.tukw.qwest.net. [97.113.179.147]) by smtp.gmail.com with ESMTPSA id j5sm7901762pfg.186.2019.04.26.10.24.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 26 Apr 2019 10:24:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=57LLTjI1nQcm9nBGSTBf3sb093E20lD7cyEUFj3ghB4=; b=BByqt0lG9dxC5Aw+SJl20Z1l6u56Mfo19JQu1ynxm2tQQ+d7qvcyfD3rUrKdNw4NFP V/iyBOrvX6uIRQuBtNJLWfkTPXuE/OLRW/PLVLTw+aUQOc60ncPZ85JxT+M0r56noJNu Zc8seyzRCQ6lt+2NzzaYoDA78fyBBx4Jxs9ANgwZNqNz9TxZ5l8gWYPA9hifVaST3hnA JpU8FzJEq7CvyautvrX62zuzAs/2U0dlUdkc2rEIezOyBpDkjzSUHkaH2KldOPVEXy4H 0UYYYmlK7jldacKJE+x4B2Diq01dBG08lFPVC3Nr1jyK0IKxiPtSdh7c2VPjVJ6zbqPo K2kQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=57LLTjI1nQcm9nBGSTBf3sb093E20lD7cyEUFj3ghB4=; b=IXqkDCYU+ka4mpYqzCnfbXw0XwcaF3iN6IPmXeipVRPYJ+VV1HZ4M/WICo+KtPo1JR mit0ILUVNT4W0bZiXxXyCEmHtEkBxqrlz9bf2+K/ABJXOqKxE4edlNDTDtMhQ2Jf09sZ V0aJSv9VjW2wQwZeShIjPT6bDvbWT4kX2GIemsuN152TE7ecr39MFEeLG6RwdApIBMQ1 Fxr0Ha00byVxEnzHQZJwmMff+HoMK9TBpqxYJtB3lti1Sn7Amlzyk8KttetEOPd5stjh 4OoDA1UaRcp699MgUg8qMDtlG+d5Gi671K9tM4D9c+Du2YYAXAwAf4BAra9/gM/n9kZo LNlA== X-Gm-Message-State: APjAAAXv6mGf2RyuH16hW9s/GWeNhkXYRubCqmoKWpavNxQ4qX0aeSVg 6td3i90OFHylCtTHxHxG60URvnjoZYM= X-Google-Smtp-Source: APXvYqxLmhUr8GQj9Sz/A8DIDAmyQbsSpMTlo1XB6tONW2XFvxcRcmeOHe3uNjZLo1GajxXQ76ozrA== X-Received: by 2002:a17:902:b407:: with SMTP id x7mr48029005plr.288.1556299479245; Fri, 26 Apr 2019 10:24:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 26 Apr 2019 10:24:19 -0700 Message-Id: <20190426172421.27133-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190426172421.27133-1-richard.henderson@linaro.org> References: <20190426172421.27133-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::644 Subject: [Qemu-devel] [PULL 13/15] tcg/ppc: Allow the constant pool to overflow at 32k X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" There is no point in coding for a 2GB offset when the max TB size is already limited to 64k. If we further restrict to 32k then we can eliminate the extra ADDIS instruction. Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.inc.c | 28 ++++++++++------------------ 1 file changed, 10 insertions(+), 18 deletions(-) diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index c0923ced4f..36b4791707 100644 --- a/tcg/ppc/tcg-target.inc.c +++ b/tcg/ppc/tcg-target.inc.c @@ -529,7 +529,6 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int ty= pe, intptr_t value, intptr_t addend) { tcg_insn_unit *target; - tcg_insn_unit old; =20 value +=3D addend; target =3D (tcg_insn_unit *)value; @@ -540,22 +539,16 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int = type, case R_PPC_REL24: return reloc_pc24(code_ptr, target); case R_PPC_ADDR16: - /* We are abusing this relocation type. This points to a pair - of insns, addis + load. If the displacement is small, we - can nop out the addis. */ - if (value =3D=3D (int16_t)value) { - code_ptr[0] =3D NOP; - old =3D deposit32(code_ptr[1], 0, 16, value); - code_ptr[1] =3D deposit32(old, 16, 5, TCG_REG_TB); - } else { - int16_t lo =3D value; - int hi =3D value - lo; - if (hi + lo !=3D value) { - return false; - } - code_ptr[0] =3D deposit32(code_ptr[0], 0, 16, hi >> 16); - code_ptr[1] =3D deposit32(code_ptr[1], 0, 16, lo); + /* + * We are (slightly) abusing this relocation type. In particular, + * assert that the low 2 bits are zero, and do not modify them. + * That way we can use this with LD et al that have opcode bits + * in the low 2 bits of the insn. + */ + if ((value & 3) || value !=3D (int16_t)value) { + return false; } + *code_ptr =3D (*code_ptr & ~0xfffc) | (value & 0xfffc); break; default: g_assert_not_reached(); @@ -701,8 +694,7 @@ static void tcg_out_movi_int(TCGContext *s, TCGType typ= e, TCGReg ret, if (!in_prologue && USE_REG_TB) { new_pool_label(s, arg, R_PPC_ADDR16, s->code_ptr, -(intptr_t)s->code_gen_ptr); - tcg_out32(s, ADDIS | TAI(ret, TCG_REG_TB, 0)); - tcg_out32(s, LD | TAI(ret, ret, 0)); + tcg_out32(s, LD | TAI(ret, TCG_REG_TB, 0)); return; } =20 --=20 2.17.1 From nobody Sun Jun 2 07:52:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1556300426; cv=none; d=zoho.com; s=zohoarc; b=jZFpisvUT0iAEC2aIPDPxVH19raYFJPuIQLs9IZ/jQlUBWAuTiXzLK0yVzoEnlam0CopOKSiFJWq79QpuS6n/9fW0ENM/6ZLlE33e3fXj2eTZMT+t4yok4onZPkEeXNAlRrP56zCO5b0Kv9wjzaLeIxHFc6nH3v1kMFM4FjkSvA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1556300426; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=XRGr1vGdXRhAkonMl1KqLt6XzNg6ocnHD4vlzm1YL7E=; b=YFwG18PVmz1sXBF4IWSjUJtBsrE0fr6Ym07+4kSKODylk6FhkD5y3lElahYu3YL4eiVhlzz3NLyHsDSAGZfw6ErM45zv2Z+ZVwZ98B2EjUUxbx9YwxdJEGTedWXvdP/1yUufGRUcP/KXOFx7ymJ+0W4w91Ugl3/cyxjO7mTrQjU= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1556300426833813.1929140616127; Fri, 26 Apr 2019 10:40:26 -0700 (PDT) Received: from localhost ([127.0.0.1]:50122 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hK4pg-0005cQ-T9 for importer@patchew.org; Fri, 26 Apr 2019 13:40:20 -0400 Received: from eggs.gnu.org ([209.51.188.92]:48075) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hK4aZ-0000AT-6c for qemu-devel@nongnu.org; Fri, 26 Apr 2019 13:24:45 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hK4aY-0007Dd-0W for qemu-devel@nongnu.org; Fri, 26 Apr 2019 13:24:43 -0400 Received: from mail-pf1-x42d.google.com ([2607:f8b0:4864:20::42d]:38580) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hK4aX-00079R-QY for qemu-devel@nongnu.org; Fri, 26 Apr 2019 13:24:41 -0400 Received: by mail-pf1-x42d.google.com with SMTP id 10so2048898pfo.5 for ; Fri, 26 Apr 2019 10:24:41 -0700 (PDT) Received: from localhost.localdomain (97-113-179-147.tukw.qwest.net. [97.113.179.147]) by smtp.gmail.com with ESMTPSA id j5sm7901762pfg.186.2019.04.26.10.24.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 26 Apr 2019 10:24:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=XRGr1vGdXRhAkonMl1KqLt6XzNg6ocnHD4vlzm1YL7E=; b=U+p2PaWsYnx2vEwrmFNjKbdHbobetC7W9bmwxh+MBgnyiCxzl7lsBjvJ2u+7dH8z4l WMINZsetqTDorWDSSHNRqlG/goLw6HRBMH3B4LpzxBTY3RnIcFJrCyvWcMw9F9Tufiq1 3WtZYEOUMG08w4G2NkNzK81S13pu7LGAlawtvmaL0K681Q2E4M0DWsl5hQDZ062qWhgG xa4LTTUO3zgnxWPuN3f0rQTj3gtiyu+yjjDDUxgeEfQF2UZ/Pn8nkv8yp3pYvGGzMqQk +AtmzcyQlsa1RONKmVRV/oPHe+j5c+NjH8bWV6uEf0oi8bUV19EBjoP+j81+oxBq1oQx 4SJA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=XRGr1vGdXRhAkonMl1KqLt6XzNg6ocnHD4vlzm1YL7E=; b=I1HpMl4fiAx4uZw2hQVsmWo7TthcQnlNQkRMg8ztArRT6EGgeY4W9FQm92O/2v6Esi 2GBTy/ZqNt7hL0X7pj2wIaphjl5fS6whvzpKV0nYAT6K6QKABM/5ajbPezoZniOJsPBT 2DrdBiHOD5iyWNwkoUkwm9PW5RmHuP9IFoE9JXw90ye4E+E2LKugoRw9kgHufYIbHXLt mPK1E4+Veg3EXWBCYevBMtWgSN4QC4tONmQgdoZeFQiQm4gnq4r9bi4WaEGQ+2hZTllC 9yHN3L/i0J1bFDtp+3MZAiF1Cwr9KtYxQiAkJNjsPIgdWcbyma34ItkEsGO6yYTqsErC iVCw== X-Gm-Message-State: APjAAAVdikFWyw6GC+AE1RuaJ5J98HT5QrLnpd4IjPbwEY3Rp6LrHIM9 tI9oKkAn6rtH1jGU/uz+/UgSqumNFJE= X-Google-Smtp-Source: APXvYqxQYBHbPVE6gWlU1L1PvABBff/fZJ9xsuVB34oX+fSuxL3V2IRYqTn5QxXlEJFcdcQ7HS190g== X-Received: by 2002:aa7:8092:: with SMTP id v18mr47460728pff.35.1556299480465; Fri, 26 Apr 2019 10:24:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 26 Apr 2019 10:24:20 -0700 Message-Id: <20190426172421.27133-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190426172421.27133-1-richard.henderson@linaro.org> References: <20190426172421.27133-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::42d Subject: [Qemu-devel] [PULL 14/15] tcg/arm: Restrict constant pool displacement to 12 bits X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This will not necessarily restrict the size of the TB, since for v7 the majority of constant pool usage is for calls from the out-of-line ldst code, which is already at the end of the TB. But this does allow us to save one insn per reference on the off-chance. Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.inc.c | 57 +++++++++++++++------------------------- 1 file changed, 21 insertions(+), 36 deletions(-) diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c index 12a65cc9a6..abf0c444b4 100644 --- a/tcg/arm/tcg-target.inc.c +++ b/tcg/arm/tcg-target.inc.c @@ -197,6 +197,24 @@ static inline bool reloc_pc24(tcg_insn_unit *code_ptr,= tcg_insn_unit *target) return false; } =20 +static inline bool reloc_pc13(tcg_insn_unit *code_ptr, tcg_insn_unit *targ= et) +{ + ptrdiff_t offset =3D tcg_ptr_byte_diff(target, code_ptr) - 8; + + if (offset >=3D -0xfff && offset <=3D 0xfff) { + tcg_insn_unit insn =3D *code_ptr; + bool u =3D (offset >=3D 0); + if (!u) { + offset =3D -offset; + } + insn =3D deposit32(insn, 23, 1, u); + insn =3D deposit32(insn, 0, 12, offset); + *code_ptr =3D insn; + return true; + } + return false; +} + static bool patch_reloc(tcg_insn_unit *code_ptr, int type, intptr_t value, intptr_t addend) { @@ -205,39 +223,10 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int = type, if (type =3D=3D R_ARM_PC24) { return reloc_pc24(code_ptr, (tcg_insn_unit *)value); } else if (type =3D=3D R_ARM_PC13) { - intptr_t diff =3D value - (uintptr_t)(code_ptr + 2); - tcg_insn_unit insn =3D *code_ptr; - bool u; - - if (diff >=3D -0xfff && diff <=3D 0xfff) { - u =3D (diff >=3D 0); - if (!u) { - diff =3D -diff; - } - } else { - int rd =3D extract32(insn, 12, 4); - int rt =3D rd =3D=3D TCG_REG_PC ? TCG_REG_TMP : rd; - - if (diff < 0x1000 || diff >=3D 0x100000) { - return false; - } - - /* add rt, pc, #high */ - *code_ptr++ =3D ((insn & 0xf0000000) | (1 << 25) | ARITH_ADD - | (TCG_REG_PC << 16) | (rt << 12) - | (20 << 7) | (diff >> 12)); - /* ldr rd, [rt, #low] */ - insn =3D deposit32(insn, 12, 4, rt); - diff &=3D 0xfff; - u =3D 1; - } - insn =3D deposit32(insn, 23, 1, u); - insn =3D deposit32(insn, 0, 12, diff); - *code_ptr =3D insn; + return reloc_pc13(code_ptr, (tcg_insn_unit *)value); } else { g_assert_not_reached(); } - return true; } =20 #define TCG_CT_CONST_ARM 0x100 @@ -605,12 +594,8 @@ static inline void tcg_out_ld8s_r(TCGContext *s, int c= ond, TCGReg rt, =20 static void tcg_out_movi_pool(TCGContext *s, int cond, int rd, uint32_t ar= g) { - /* The 12-bit range on the ldr insn is sometimes a bit too small. - In order to get around that we require two insns, one of which - will usually be a nop, but may be replaced in patch_reloc. */ new_pool_label(s, arg, R_ARM_PC13, s->code_ptr, 0); tcg_out_ld32_12(s, cond, rd, TCG_REG_PC, 0); - tcg_out_nop(s); } =20 static void tcg_out_movi32(TCGContext *s, int cond, int rd, uint32_t arg) @@ -1069,8 +1054,8 @@ static void tcg_out_call(TCGContext *s, tcg_insn_unit= *addr) tcg_out_movi32(s, COND_AL, TCG_REG_TMP, addri); tcg_out_blx(s, COND_AL, TCG_REG_TMP); } else { - /* ??? Know that movi_pool emits exactly 2 insns. */ - tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_R14, TCG_REG_PC, 4); + /* ??? Know that movi_pool emits exactly 1 insn. */ + tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_R14, TCG_REG_PC, 0); tcg_out_movi_pool(s, COND_AL, TCG_REG_PC, addri); } } --=20 2.17.1 From nobody Sun Jun 2 07:52:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1556299790; cv=none; d=zoho.com; s=zohoarc; b=fw3JKIm2cawY1Brx6bja+DRRscA+RSamRZ8OQopO5h21oRNv0736z95R3YYWJzfYmsJcMnZeGggaDRPwjZq6vuy3q+gHIQXB4aW4n6mOb/AQ26iWWvJGywJsORtAXN7DIRtEAPzDP3Hq1r83fUb8hd/Q3AhUG0tzeC8yymqxWCQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1556299790; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=s+lfsXhUEsggZv7QGs1XHx6DsIQr/qtfxf0ZchCRrog=; b=PPrvLpff9cQgQEb2yo+OZrG+sy8/AR3k5HOuzZE8KI3zUu0tJ96xs8Sx20nn7v3NvyRQ2Vo7ZKBK+jqNfRXlE323Hnm5qEpmlpVO3aaixqwmwR5AEmGoS1aGGKwwS0TZyg+V0KVnlwPL4REz1y/Fn7RDo+hW2m3kqYx0nwl9eB0= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 155629979062828.63659522130456; Fri, 26 Apr 2019 10:29:50 -0700 (PDT) Received: from localhost ([127.0.0.1]:49960 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hK4fS-00048q-Ip for importer@patchew.org; Fri, 26 Apr 2019 13:29:46 -0400 Received: from eggs.gnu.org ([209.51.188.92]:48093) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hK4aa-0000Ak-Bg for qemu-devel@nongnu.org; Fri, 26 Apr 2019 13:24:45 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hK4aZ-0007Kw-2d for qemu-devel@nongnu.org; Fri, 26 Apr 2019 13:24:44 -0400 Received: from mail-pf1-x444.google.com ([2607:f8b0:4864:20::444]:46667) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hK4aY-0007GO-S7 for qemu-devel@nongnu.org; Fri, 26 Apr 2019 13:24:43 -0400 Received: by mail-pf1-x444.google.com with SMTP id j11so2024176pff.13 for ; Fri, 26 Apr 2019 10:24:42 -0700 (PDT) Received: from localhost.localdomain (97-113-179-147.tukw.qwest.net. [97.113.179.147]) by smtp.gmail.com with ESMTPSA id j5sm7901762pfg.186.2019.04.26.10.24.40 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 26 Apr 2019 10:24:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=s+lfsXhUEsggZv7QGs1XHx6DsIQr/qtfxf0ZchCRrog=; b=L2h7WkGwnsPynm5YDKUVvrNH417QIFDzw6uhOvM9SMkqAza62HC97DPc73TO742flP SI6r88iKmIkBoG3r4UdrZAH+Rm9QK4SyGIO9kI3ADm4Jbfxkb05QYdVYHAR2Y77xZsdP wAWOv2V8VT+a4oJhxT2Ka19PG6O0H0isKjSejB52qh6ebbQn05PlidHf4GGiRlTMJgRD fbXlKv9k3zFwERwJoiU9sodO74KcEf5mYNiXokiBHgvWxnsGiXkKyo+YUCMaklljg6Rq Ia5NOqyddu/MfQq0al8Ei8CkIHP3+G3tu6GX9/IcN0ihQvjqHedfrrLZdmuyUNON7Yyu aELw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=s+lfsXhUEsggZv7QGs1XHx6DsIQr/qtfxf0ZchCRrog=; b=O8C/KJWI4EymQm+1zxcrejaEXdJS6bgKHih7ZBCYx09olmP4dbStyk60UU4EWciHRe r3cugWVldBVJs1LfmMUG5gKgxn3GeCPWhmnP+eyV7JSd5lufDIibL/jwXUAZ6FHPWS/e 2m0TjHMCRMuRC+U9mdAXWBYjmUVsNeDsRq8+7QtnWo9bwo/jjobRr7yyTQQ5SXF3uSGv HK6YH/1kbZYbEPiUxHKFVubA7OTKd2pSmTu43CdTbtYqLvZczqqB26x5a7JRFk/qgaM/ 1zhf+dsj46iVEXZbsTGxh3TaFGSyRWeYt4J1Ok6B/al9//L/p85TSFIGh3lZWxXtSOzF 4GTA== X-Gm-Message-State: APjAAAW401NyrNRHpXYUt/ri7B6FqGJ/sH1fNmfsK2B6sHlZDbxfzXGP 0Uik2Z1RigEkkmtt8vEBAlfJXKmxgf4= X-Google-Smtp-Source: APXvYqx5fXyKGlQukByXvHk3q+ubOL5D9Vsczi+FFSBJ1q+gHSEoi9Xm1Eb9PA0Oqjk8cbtmvHl99Q== X-Received: by 2002:aa7:925a:: with SMTP id 26mr2855571pfp.152.1556299481627; Fri, 26 Apr 2019 10:24:41 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 26 Apr 2019 10:24:21 -0700 Message-Id: <20190426172421.27133-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190426172421.27133-1-richard.henderson@linaro.org> References: <20190426172421.27133-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PULL 15/15] cputlb: Fix io_readx() to respect the access_type X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Shahab Vahedi , peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Shahab Vahedi This change adapts io_readx() to its input access_type. Currently io_readx() treats any memory access as a read, although it has an input argument "MMUAccessType access_type". This results in: 1) Calling the tlb_fill() only with MMU_DATA_LOAD 2) Considering only entry->addr_read as the tlb_addr Buglink: https://bugs.launchpad.net/qemu/+bug/1825359 Reviewed-by: Richard Henderson Signed-off-by: Shahab Vahedi Message-Id: <20190420072236.12347-1-shahab.vahedi@gmail.com> [rth: Remove assert; fix expression formatting.] Signed-off-by: Richard Henderson --- accel/tcg/cputlb.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 88cc8389e9..f2f618217d 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -878,10 +878,11 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBE= ntry *iotlbentry, CPUTLBEntry *entry; target_ulong tlb_addr; =20 - tlb_fill(cpu, addr, size, MMU_DATA_LOAD, mmu_idx, retaddr); + tlb_fill(cpu, addr, size, access_type, mmu_idx, retaddr); =20 entry =3D tlb_entry(env, mmu_idx, addr); - tlb_addr =3D entry->addr_read; + tlb_addr =3D (access_type =3D=3D MMU_DATA_LOAD ? + entry->addr_read : entry->addr_code); if (!(tlb_addr & ~(TARGET_PAGE_MASK | TLB_RECHECK))) { /* RAM access */ uintptr_t haddr =3D addr + entry->addend; --=20 2.17.1