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[208.66.210.181]) by smtp.gmail.com with ESMTPSA id c7sm7548700ioc.63.2019.04.26.09.27.03 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 26 Apr 2019 09:27:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oberlin-edu.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=x1D1gW1VeXrG3BnPtsTgjJU8dXr+PKiPI7BfP3fK3eY=; b=HIK6FZYZBhVvUqz7zcJgc8LWkuMw1hM1lLZ+eoxUw3c0OxYAlB6jBhBMB4PYKeavd7 VjwKwfIdKdUwmHQEbxlYqpPp8FTxI858l6+bXoP94tcrA6ma1Bm8LoQbw6wdbbl2I2nd e9D9bC8zIm8c3T6UuW+SZcuyMmfHl//GYvBjme45z86dzAdrmVB53fcKSvW8sMszY88K 5NxSwfoFNxrgwAcdgYZ2cVypsRCK7FywdB371D5DCE5kUqoN9aYVrtusmACsU2Ou/+PS ipuO4DSvzHJ6WOZ9UCK1z3Sb6Awlh8TpdyXFkvzEVqEXoZqDzJzO+uQgiW/PosOGfqa7 RbGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=x1D1gW1VeXrG3BnPtsTgjJU8dXr+PKiPI7BfP3fK3eY=; b=Iys5KtTRfUNyIbOCcFR7XgZ9Bbqz9zhHSKvL3dAfbJrfMc9xnJkQ9sPand2IJ/SA4P xma0zJlRVjbkhjzbyeBlbE2wXHEjRssIbwXaXTj11JoTxx5DH7MuS7/1hmQ7tcWt7WYc Q5o1/y8oK/L3FDqpT/c2hNpu6oInJyXt4rgwaAqM/tktdMeiHaKFzRuDQPruPgi7mT14 m9o9Ep8hjAioyaUIDIY4u091PPTF874sZT2b63ioAd6i5LEn/L7rMAp9emRzfa7rOkHI JcJU8QHsBhq/XCfcr3XI50ItTUwcwv4J1k9btus7dPmnbqE01g65KHayJ3IRf3VgWYhX +BiA== X-Gm-Message-State: APjAAAXJw45u1OiD2JgxnWil2JTtYzUpb9Bh4W7EmPn82PGl2DBtKqZo w6yzSPMkp5xkzvm5q3Nia019ciYVK+kEOA== X-Google-Smtp-Source: APXvYqzTQTk8JRvh4S3b0Mfj4DRjUrqww1w9rpA/MHbTPpRSY1UAbVLHp1pQDQkSgzpljqlOcSWStQ== X-Received: by 2002:a24:3288:: with SMTP id j130mr9427591ita.104.1556296024559; Fri, 26 Apr 2019 09:27:04 -0700 (PDT) From: Stephen Checkoway To: QEMU Developers , Thomas Huth , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Kevin Wolf , Max Reitz , "open list:Block layer core" , Markus Armbruster , Laszlo Ersek , Laurent Vivier , Paolo Bonzini Date: Fri, 26 Apr 2019 12:26:15 -0400 Message-Id: <20190426162624.55977-2-stephen.checkoway@oberlin.edu> X-Mailer: git-send-email 2.20.1 (Apple Git-117) In-Reply-To: <20190426162624.55977-1-stephen.checkoway@oberlin.edu> References: <20190426162624.55977-1-stephen.checkoway@oberlin.edu> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::12f Subject: [Qemu-devel] [PATCH v4 01/10] block/pflash_cfi02: Add test for supported commands X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stephen Checkoway Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Test the AMD command set for parallel flash chips. This test uses an ARM musicpal board with a pflash drive to test the following list of currently-supported commands. - Autoselect - CFI - Sector erase - Chip erase - Program - Unlock bypass - Reset Signed-off-by: Stephen Checkoway Acked-by: Thomas Huth --- tests/Makefile.include | 2 + tests/pflash-cfi02-test.c | 225 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 227 insertions(+) create mode 100644 tests/pflash-cfi02-test.c diff --git a/tests/Makefile.include b/tests/Makefile.include index 36fc73fef5..dbdb2c0082 100644 --- a/tests/Makefile.include +++ b/tests/Makefile.include @@ -263,6 +263,7 @@ check-qtest-arm-y +=3D tests/m25p80-test$(EXESUF) check-qtest-arm-y +=3D tests/test-arm-mptimer$(EXESUF) check-qtest-arm-y +=3D tests/boot-serial-test$(EXESUF) check-qtest-arm-y +=3D tests/hexloader-test$(EXESUF) +check-qtest-arm-$(CONFIG_PFLASH_CFI02) +=3D tests/pflash-cfi02-test$(EXESU= F) =20 check-qtest-aarch64-y =3D tests/numa-test$(EXESUF) check-qtest-aarch64-y +=3D tests/boot-serial-test$(EXESUF) @@ -773,6 +774,7 @@ tests/device-introspect-test$(EXESUF): tests/device-int= rospect-test.o tests/rtc-test$(EXESUF): tests/rtc-test.o tests/m48t59-test$(EXESUF): tests/m48t59-test.o tests/hexloader-test$(EXESUF): tests/hexloader-test.o +tests/pflash-cfi02$(EXESUF): tests/pflash-cfi02-test.o tests/endianness-test$(EXESUF): tests/endianness-test.o tests/prom-env-test$(EXESUF): tests/prom-env-test.o $(libqos-obj-y) tests/rtas-test$(EXESUF): tests/rtas-test.o $(libqos-spapr-obj-y) diff --git a/tests/pflash-cfi02-test.c b/tests/pflash-cfi02-test.c new file mode 100644 index 0000000000..40af1bb523 --- /dev/null +++ b/tests/pflash-cfi02-test.c @@ -0,0 +1,225 @@ +/* + * QTest testcase for parallel flash with AMD command set + * + * Copyright (c) 2019 Stephen Checkoway + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "libqtest.h" + +/* + * To test the pflash_cfi02 device, we run QEMU with the musicpal machine = with + * a pflash drive. This enables us to test some flash configurations, but = not + * all. In particular, we're limited to a 16-bit wide flash device. + */ + +#define MP_FLASH_SIZE_MAX (32 * 1024 * 1024) +#define BASE_ADDR (0x100000000ULL - MP_FLASH_SIZE_MAX) + +#define FLASH_WIDTH 2 +#define CFI_ADDR (FLASH_WIDTH * 0x55) +#define UNLOCK0_ADDR (FLASH_WIDTH * 0x5555) +#define UNLOCK1_ADDR (FLASH_WIDTH * 0x2AAA) + +#define CFI_CMD 0x98 +#define UNLOCK0_CMD 0xAA +#define UNLOCK1_CMD 0x55 +#define AUTOSELECT_CMD 0x90 +#define RESET_CMD 0xF0 +#define PROGRAM_CMD 0xA0 +#define SECTOR_ERASE_CMD 0x30 +#define CHIP_ERASE_CMD 0x10 +#define UNLOCK_BYPASS_CMD 0x20 +#define UNLOCK_BYPASS_RESET_CMD 0x00 + +static char image_path[] =3D "/tmp/qtest.XXXXXX"; + +static inline void flash_write(uint64_t byte_addr, uint16_t data) +{ + qtest_writew(global_qtest, BASE_ADDR + byte_addr, data); +} + +static inline uint16_t flash_read(uint64_t byte_addr) +{ + return qtest_readw(global_qtest, BASE_ADDR + byte_addr); +} + +static void unlock(void) +{ + flash_write(UNLOCK0_ADDR, UNLOCK0_CMD); + flash_write(UNLOCK1_ADDR, UNLOCK1_CMD); +} + +static void reset(void) +{ + flash_write(0, RESET_CMD); +} + +static void sector_erase(uint64_t byte_addr) +{ + unlock(); + flash_write(UNLOCK0_ADDR, 0x80); + unlock(); + flash_write(byte_addr, SECTOR_ERASE_CMD); +} + +static void wait_for_completion(uint64_t byte_addr) +{ + /* If DQ6 is toggling, step the clock and ensure the toggle stops. */ + if ((flash_read(byte_addr) & 0x40) ^ (flash_read(byte_addr) & 0x40)) { + /* Wait for erase or program to finish. */ + clock_step_next(); + /* Ensure that DQ6 has stopped toggling. */ + g_assert_cmpint(flash_read(byte_addr), =3D=3D, flash_read(byte_add= r)); + } +} + +static void bypass_program(uint64_t byte_addr, uint16_t data) +{ + flash_write(UNLOCK0_ADDR, PROGRAM_CMD); + flash_write(byte_addr, data); + /* + * Data isn't valid until DQ6 stops toggling. We don't model this as + * writes are immediate, but if this changes in the future, we can wait + * until the program is complete. + */ + wait_for_completion(byte_addr); +} + +static void program(uint64_t byte_addr, uint16_t data) +{ + unlock(); + bypass_program(byte_addr, data); +} + +static void chip_erase(void) +{ + unlock(); + flash_write(UNLOCK0_ADDR, 0x80); + unlock(); + flash_write(UNLOCK0_ADDR, SECTOR_ERASE_CMD); +} + +static void test_flash(void) +{ + global_qtest =3D qtest_initf("-M musicpal,accel=3Dqtest " + "-drive if=3Dpflash,file=3D%s,format=3Draw,= copy-on-read", + image_path); + /* Check the IDs. */ + unlock(); + flash_write(UNLOCK0_ADDR, AUTOSELECT_CMD); + g_assert_cmpint(flash_read(FLASH_WIDTH * 0x0000), =3D=3D, 0x00BF); + g_assert_cmpint(flash_read(FLASH_WIDTH * 0x0001), =3D=3D, 0x236D); + reset(); + + /* Check the erase blocks. */ + flash_write(CFI_ADDR, CFI_CMD); + g_assert_cmpint(flash_read(FLASH_WIDTH * 0x10), =3D=3D, 'Q'); + g_assert_cmpint(flash_read(FLASH_WIDTH * 0x11), =3D=3D, 'R'); + g_assert_cmpint(flash_read(FLASH_WIDTH * 0x12), =3D=3D, 'Y'); + /* Num erase regions. */ + g_assert_cmpint(flash_read(FLASH_WIDTH * 0x2C), >=3D, 1); + uint32_t nb_sectors =3D flash_read(FLASH_WIDTH * 0x2D) + + (flash_read(FLASH_WIDTH * 0x2E) << 8) + 1; + uint32_t sector_len =3D (flash_read(FLASH_WIDTH * 0x2F) << 8) + + (flash_read(FLASH_WIDTH * 0x30) << 16); + reset(); + + /* Erase and program sector. */ + for (uint32_t i =3D 0; i < nb_sectors; ++i) { + uint64_t byte_addr =3D i * sector_len; + sector_erase(byte_addr); + /* Read toggle. */ + uint16_t status0 =3D flash_read(byte_addr); + /* DQ7 is 0 during an erase. */ + g_assert_cmpint(status0 & 0x80, =3D=3D, 0); + uint16_t status1 =3D flash_read(byte_addr); + /* DQ6 toggles during an erase. */ + g_assert_cmpint(status0 & 0x40, !=3D, status1 & 0x40); + /* Wait for erase to complete. */ + clock_step_next(); + /* Ensure DQ6 has stopped toggling. */ + g_assert_cmpint(flash_read(byte_addr), =3D=3D, flash_read(byte_add= r)); + /* Now the data should be valid. */ + g_assert_cmpint(flash_read(byte_addr), =3D=3D, 0xFFFF); + + /* Program a bit pattern. */ + program(byte_addr, 0x5555); + g_assert_cmpint(flash_read(byte_addr), =3D=3D, 0x5555); + program(byte_addr, 0xAA55); + g_assert_cmpint(flash_read(byte_addr), =3D=3D, 0x0055); + } + + /* Erase the chip. */ + chip_erase(); + /* Read toggle. */ + uint16_t status0 =3D flash_read(0); + /* DQ7 is 0 during an erase. */ + g_assert_cmpint(status0 & 0x80, =3D=3D, 0); + uint16_t status1 =3D flash_read(0); + /* DQ6 toggles during an erase. */ + g_assert_cmpint(status0 & 0x40, !=3D, status1 & 0x40); + /* Wait for erase to complete. */ + clock_step_next(); + /* Ensure DQ6 has stopped toggling. */ + g_assert_cmpint(flash_read(0), =3D=3D, flash_read(0)); + /* Now the data should be valid. */ + g_assert_cmpint(flash_read(0), =3D=3D, 0xFFFF); + + /* Unlock bypass */ + unlock(); + flash_write(UNLOCK0_ADDR, UNLOCK_BYPASS_CMD); + bypass_program(0, 0x0123); + bypass_program(2, 0x4567); + bypass_program(4, 0x89AB); + /* + * Test that bypass programming, unlike normal programming can use any + * address for the PROGRAM_CMD. + */ + flash_write(6, PROGRAM_CMD); + flash_write(6, 0xCDEF); + wait_for_completion(6); + flash_write(0, UNLOCK_BYPASS_RESET_CMD); + bypass_program(8, 0x55AA); /* Should fail. */ + g_assert_cmpint(flash_read(0), =3D=3D, 0x0123); + g_assert_cmpint(flash_read(2), =3D=3D, 0x4567); + g_assert_cmpint(flash_read(4), =3D=3D, 0x89AB); + g_assert_cmpint(flash_read(6), =3D=3D, 0xCDEF); + g_assert_cmpint(flash_read(8), =3D=3D, 0xFFFF); + + qtest_quit(global_qtest); +} + +static void cleanup(void *opaque) +{ + unlink(image_path); +} + +int main(int argc, char **argv) +{ + int fd =3D mkstemp(image_path); + if (fd =3D=3D -1) { + g_printerr("Failed to create temporary file %s: %s\n", image_path, + strerror(errno)); + exit(EXIT_FAILURE); + } + if (ftruncate(fd, 8 * 1024 * 1024) < 0) { + int error_code =3D errno; + close(fd); + unlink(image_path); + g_printerr("Failed to truncate file %s to 8 MB: %s\n", image_path, + strerror(error_code)); + exit(EXIT_FAILURE); + } + close(fd); + + qtest_add_abrt_handler(cleanup, NULL); + g_test_init(&argc, &argv, NULL); + qtest_add_func("pflash-cfi02", test_flash); + int result =3D g_test_run(); + cleanup(NULL); + return result; +} --=20 2.20.1 (Apple Git-117) From nobody Mon Feb 9 11:35:11 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1556296380; cv=none; d=zoho.com; s=zohoarc; b=aOtbfR5Vp5/YhmoG+668QblRCHrwlNme0ooCzr9aRA7fyYB05yByzdQjj4SV2YAXwWLNV+BAro87091YY7W2hYWJucmYiC0nhvirtKessNV7eDGb0jMJ3woQWkcM1xUpXN+5oRgVzW/g8d3fvQGF769yigV2v8fixEOi+YxyeNg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1556296380; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; 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[208.66.210.181]) by smtp.gmail.com with ESMTPSA id c7sm7548700ioc.63.2019.04.26.09.27.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 26 Apr 2019 09:27:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oberlin-edu.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Jv0E8JtBAEhamTwvz2jAbN/sxL4NNiW4E2UIqBfaHx8=; b=wBpq5My1YhYS3rJ0tWofNmDhbicWHNc5AS/vjdNRPTRYWCKLQNAxV6bPnqvCX68XhM ayOm2dr7yPtP5s6+MGDS6VpTjSPoKg9wSWczTK30UQbIsv9SG8AtLrZLLKgJ6BZtt3q/ i1KhgoGwNamCizyTiISkFRGr6/vLyltuIvHqh7tYaOk2WrxUG7G7bVXU1E3zOGORxUKK tvAVee/SrazSyFWtM4ZnpDaCEK3zb4j1Z2yOMG6NlVAG9q1+cqy5sn/xcYHJH/YpRHiM rew3A2sWCSnUJP//AU2rPctrnL0gzSpN0kYOWjvmc4YWwq9BPycyowmYeKL00KvRJ1fx k0qw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Jv0E8JtBAEhamTwvz2jAbN/sxL4NNiW4E2UIqBfaHx8=; b=VaThOo121qRNQ7NahDAynQlfVrDqUzL3MszrdGXc2SmVTT/zVP9fWZFQ10LHutpDd4 6W0YzOnVK4pTsYh1AGKVmSvqUvNApZuLbTQZ4RYSbF2NymVn2VUdhq8YvqevF7VGl4Il tpaj+8NLBSSb00fMWFkMM7TazsRXNC6D6VbEzGKKb2g+VTt7kAFuRnhupFEi7TvXMPOF BwYb52YI2F1bP++h4V4Nzr6RuIvwl8nX8MKuf5GvAFS7js2x9Wv3AyS5MM54Z78w/RG6 6uInV6X8SwYXWrvRagGaUvPe6NrWMPHXquM95IOL8AI6V7os0+2+fTjP4xyZI0wk+QoF pN8w== X-Gm-Message-State: APjAAAXT9XdF2vOg1E7F7WB7oxYAyRCnfoT6A5tFQQA0lxo3i6M71zew LCgNq8yBfF+dW0KTqxPECnqEJQA3Fhh4nQ== X-Google-Smtp-Source: APXvYqyVmns6Y0rIN2ceyjdaf/M1qufAhLHybItqCH3h11HCk7AP+tTf5RujeFdBFK65WATr+qrgkQ== X-Received: by 2002:a24:76d5:: with SMTP id z204mr8736614itb.44.1556296025805; Fri, 26 Apr 2019 09:27:05 -0700 (PDT) From: Stephen Checkoway To: QEMU Developers , Thomas Huth , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Kevin Wolf , Max Reitz , "open list:Block layer core" , Markus Armbruster , Laszlo Ersek , Laurent Vivier , Paolo Bonzini Date: Fri, 26 Apr 2019 12:26:16 -0400 Message-Id: <20190426162624.55977-3-stephen.checkoway@oberlin.edu> X-Mailer: git-send-email 2.20.1 (Apple Git-117) In-Reply-To: <20190426162624.55977-1-stephen.checkoway@oberlin.edu> References: <20190426162624.55977-1-stephen.checkoway@oberlin.edu> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::143 Subject: [Qemu-devel] [PATCH v4 02/10] block/pflash_cfi02: Refactor, NFC intended X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stephen Checkoway Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Simplify and refactor for upcoming commits. In particular, pull out all of the code to modify the status into simple helper functions. Status handling becomes more complex once multiple chips are interleaved to produce a single device. No change in functionality is intended with this commit. Signed-off-by: Stephen Checkoway --- hw/block/pflash_cfi02.c | 221 +++++++++++++++++----------------------- 1 file changed, 95 insertions(+), 126 deletions(-) diff --git a/hw/block/pflash_cfi02.c b/hw/block/pflash_cfi02.c index f2c6201f81..4b7af71806 100644 --- a/hw/block/pflash_cfi02.c +++ b/hw/block/pflash_cfi02.c @@ -46,18 +46,19 @@ #include "hw/sysbus.h" #include "trace.h" =20 -//#define PFLASH_DEBUG -#ifdef PFLASH_DEBUG +#define PFLASH_DEBUG false #define DPRINTF(fmt, ...) \ do { \ - fprintf(stderr, "PFLASH: " fmt , ## __VA_ARGS__); \ + if (PFLASH_DEBUG) { \ + fprintf(stderr, "PFLASH: " fmt, ## __VA_ARGS__); \ + } \ } while (0) -#else -#define DPRINTF(fmt, ...) do { } while (0) -#endif =20 #define PFLASH_LAZY_ROMD_THRESHOLD 42 =20 +/* Special write cycle for CFI queries. */ +#define WCYCLE_CFI 7 + struct PFlashCFI02 { /*< private >*/ SysBusDevice parent_obj; @@ -97,6 +98,31 @@ struct PFlashCFI02 { void *storage; }; =20 +/* + * Toggle status bit DQ7. + */ +static inline void toggle_dq7(PFlashCFI02 *pfl) +{ + pfl->status ^=3D 0x80; +} + +/* + * Set status bit DQ7 to bit 7 of value. + */ +static inline void set_dq7(PFlashCFI02 *pfl, uint8_t value) +{ + pfl->status &=3D 0x7F; + pfl->status |=3D value & 0x80; +} + +/* + * Toggle status bit DQ6. + */ +static inline void toggle_dq6(PFlashCFI02 *pfl) +{ + pfl->status ^=3D 0x40; +} + /* * Set up replicated mappings of the same region. */ @@ -126,7 +152,7 @@ static void pflash_timer (void *opaque) =20 trace_pflash_timer_expired(pfl->cmd); /* Reset flash */ - pfl->status ^=3D 0x80; + toggle_dq7(pfl); if (pfl->bypass) { pfl->wcycle =3D 2; } else { @@ -136,12 +162,34 @@ static void pflash_timer (void *opaque) pfl->cmd =3D 0; } =20 -static uint32_t pflash_read(PFlashCFI02 *pfl, hwaddr offset, - int width, int be) +/* + * Read data from flash. + */ +static uint64_t pflash_data_read(PFlashCFI02 *pfl, hwaddr offset, + unsigned int width) { + uint8_t *p =3D (uint8_t *)pfl->storage + offset; + uint64_t ret =3D pfl->be ? ldn_be_p(p, width) : ldn_le_p(p, width); + /* XXX: Need a trace_pflash_data_read(offset, ret, width) */ + switch (width) { + case 1: + trace_pflash_data_read8(offset, ret); + break; + case 2: + trace_pflash_data_read16(offset, ret); + break; + case 4: + trace_pflash_data_read32(offset, ret); + break; + } + return ret; +} + +static uint64_t pflash_read(void *opaque, hwaddr offset, unsigned int widt= h) +{ + PFlashCFI02 *pfl =3D opaque; hwaddr boff; - uint32_t ret; - uint8_t *p; + uint64_t ret; =20 ret =3D -1; trace_pflash_read(offset, pfl->cmd, width, pfl->wcycle); @@ -166,39 +214,8 @@ static uint32_t pflash_read(PFlashCFI02 *pfl, hwaddr o= ffset, case 0x80: /* We accept reads during second unlock sequence... */ case 0x00: - flash_read: /* Flash area read */ - p =3D pfl->storage; - switch (width) { - case 1: - ret =3D p[offset]; - trace_pflash_data_read8(offset, ret); - break; - case 2: - if (be) { - ret =3D p[offset] << 8; - ret |=3D p[offset + 1]; - } else { - ret =3D p[offset]; - ret |=3D p[offset + 1] << 8; - } - trace_pflash_data_read16(offset, ret); - break; - case 4: - if (be) { - ret =3D p[offset] << 24; - ret |=3D p[offset + 1] << 16; - ret |=3D p[offset + 2] << 8; - ret |=3D p[offset + 3]; - } else { - ret =3D p[offset]; - ret |=3D p[offset + 1] << 8; - ret |=3D p[offset + 2] << 16; - ret |=3D p[offset + 3] << 24; - } - trace_pflash_data_read32(offset, ret); - break; - } + ret =3D pflash_data_read(pfl, offset, width); break; case 0x90: /* flash ID read */ @@ -213,23 +230,23 @@ static uint32_t pflash_read(PFlashCFI02 *pfl, hwaddr = offset, case 0x0E: case 0x0F: ret =3D boff & 0x01 ? pfl->ident3 : pfl->ident2; - if (ret =3D=3D (uint8_t)-1) { - goto flash_read; + if (ret !=3D (uint8_t)-1) { + break; } - break; + /* Fall through to data read. */ default: - goto flash_read; + ret =3D pflash_data_read(pfl, offset, width); } - DPRINTF("%s: ID " TARGET_FMT_plx " %x\n", __func__, boff, ret); + DPRINTF("%s: ID " TARGET_FMT_plx " %" PRIx64 "\n", __func__, boff,= ret); break; case 0xA0: case 0x10: case 0x30: /* Status register read */ ret =3D pfl->status; - DPRINTF("%s: status %x\n", __func__, ret); + DPRINTF("%s: status %" PRIx64 "\n", __func__, ret); /* Toggle bit 6 */ - pfl->status ^=3D 0x40; + toggle_dq6(pfl); break; case 0x98: /* CFI query mode */ @@ -245,8 +262,7 @@ static uint32_t pflash_read(PFlashCFI02 *pfl, hwaddr of= fset, } =20 /* update flash content on disk */ -static void pflash_update(PFlashCFI02 *pfl, int offset, - int size) +static void pflash_update(PFlashCFI02 *pfl, int offset, int size) { int offset_end; if (pfl->blk) { @@ -259,9 +275,10 @@ static void pflash_update(PFlashCFI02 *pfl, int offset, } } =20 -static void pflash_write(PFlashCFI02 *pfl, hwaddr offset, - uint32_t value, int width, int be) +static void pflash_write(void *opaque, hwaddr offset, uint64_t value, + unsigned int width) { + PFlashCFI02 *pfl =3D opaque; hwaddr boff; uint8_t *p; uint8_t cmd; @@ -277,7 +294,7 @@ static void pflash_write(PFlashCFI02 *pfl, hwaddr offse= t, trace_pflash_write(offset, value, width, pfl->wcycle); offset &=3D pfl->chip_len - 1; =20 - DPRINTF("%s: offset " TARGET_FMT_plx " %08x %d\n", __func__, + DPRINTF("%s: offset " TARGET_FMT_plx " %08" PRIx64 " %d\n", __func__, offset, value, width); boff =3D offset & (pfl->sector_len - 1); if (pfl->width =3D=3D 2) @@ -295,7 +312,7 @@ static void pflash_write(PFlashCFI02 *pfl, hwaddr offse= t, if (boff =3D=3D 0x55 && cmd =3D=3D 0x98) { enter_CFI_mode: /* Enter CFI query mode */ - pfl->wcycle =3D 7; + pfl->wcycle =3D WCYCLE_CFI; pfl->cmd =3D 0x98; return; } @@ -345,40 +362,22 @@ static void pflash_write(PFlashCFI02 *pfl, hwaddr off= set, goto check_unlock0; case 0xA0: trace_pflash_data_write(offset, value, width, 0); - p =3D pfl->storage; if (!pfl->ro) { - switch (width) { - case 1: - p[offset] &=3D value; - pflash_update(pfl, offset, 1); - break; - case 2: - if (be) { - p[offset] &=3D value >> 8; - p[offset + 1] &=3D value; - } else { - p[offset] &=3D value; - p[offset + 1] &=3D value >> 8; - } - pflash_update(pfl, offset, 2); - break; - case 4: - if (be) { - p[offset] &=3D value >> 24; - p[offset + 1] &=3D value >> 16; - p[offset + 2] &=3D value >> 8; - p[offset + 3] &=3D value; - } else { - p[offset] &=3D value; - p[offset + 1] &=3D value >> 8; - p[offset + 2] &=3D value >> 16; - p[offset + 3] &=3D value >> 24; - } - pflash_update(pfl, offset, 4); - break; + p =3D (uint8_t *)pfl->storage + offset; + if (pfl->be) { + uint64_t current =3D ldn_be_p(p, width); + stn_be_p(p, width, current & value); + } else { + uint64_t current =3D ldn_le_p(p, width); + stn_le_p(p, width, current & value); } + pflash_update(pfl, offset, width); } - pfl->status =3D 0x00 | ~(value & 0x80); + /* + * While programming, status bit DQ7 should hold the opposite + * value from how it was programmed. + */ + set_dq7(pfl, ~value); /* Let's pretend write is immediate */ if (pfl->bypass) goto do_bypass; @@ -426,7 +425,7 @@ static void pflash_write(PFlashCFI02 *pfl, hwaddr offse= t, memset(pfl->storage, 0xFF, pfl->chip_len); pflash_update(pfl, 0, pfl->chip_len); } - pfl->status =3D 0x00; + set_dq7(pfl, 0x00); /* Let's wait 5 seconds before chip erase is done */ timer_mod(&pfl->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + (NANOSECONDS_PER_SECOND * 5)); @@ -441,7 +440,7 @@ static void pflash_write(PFlashCFI02 *pfl, hwaddr offse= t, memset(p + offset, 0xFF, pfl->sector_len); pflash_update(pfl, offset, pfl->sector_len); } - pfl->status =3D 0x00; + set_dq7(pfl, 0x00); /* Let's wait 1/2 second before sector erase is done */ timer_mod(&pfl->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + (NANOSECONDS_PER_SECOND / 2)); @@ -467,7 +466,7 @@ static void pflash_write(PFlashCFI02 *pfl, hwaddr offse= t, goto reset_flash; } break; - case 7: /* Special value for CFI queries */ + case WCYCLE_CFI: /* Special value for CFI queries */ DPRINTF("%s: invalid write in CFI query mode\n", __func__); goto reset_flash; default: @@ -492,39 +491,9 @@ static void pflash_write(PFlashCFI02 *pfl, hwaddr offs= et, pfl->cmd =3D 0; } =20 -static uint64_t pflash_be_readfn(void *opaque, hwaddr addr, unsigned size) -{ - return pflash_read(opaque, addr, size, 1); -} - -static void pflash_be_writefn(void *opaque, hwaddr addr, - uint64_t value, unsigned size) -{ - pflash_write(opaque, addr, value, size, 1); -} - -static uint64_t pflash_le_readfn(void *opaque, hwaddr addr, unsigned size) -{ - return pflash_read(opaque, addr, size, 0); -} - -static void pflash_le_writefn(void *opaque, hwaddr addr, - uint64_t value, unsigned size) -{ - pflash_write(opaque, addr, value, size, 0); -} - -static const MemoryRegionOps pflash_cfi02_ops_be =3D { - .read =3D pflash_be_readfn, - .write =3D pflash_be_writefn, - .valid.min_access_size =3D 1, - .valid.max_access_size =3D 4, - .endianness =3D DEVICE_NATIVE_ENDIAN, -}; - -static const MemoryRegionOps pflash_cfi02_ops_le =3D { - .read =3D pflash_le_readfn, - .write =3D pflash_le_writefn, +static const MemoryRegionOps pflash_cfi02_ops =3D { + .read =3D pflash_read, + .write =3D pflash_write, .valid.min_access_size =3D 1, .valid.max_access_size =3D 4, .endianness =3D DEVICE_NATIVE_ENDIAN, @@ -552,9 +521,9 @@ static void pflash_cfi02_realize(DeviceState *dev, Erro= r **errp) =20 chip_len =3D pfl->sector_len * pfl->nb_blocs; =20 - memory_region_init_rom_device(&pfl->orig_mem, OBJECT(pfl), pfl->be ? - &pflash_cfi02_ops_be : &pflash_cfi02_ops= _le, - pfl, pfl->name, chip_len, &local_err); + memory_region_init_rom_device(&pfl->orig_mem, OBJECT(pfl), + &pflash_cfi02_ops, pfl, pfl->name, + chip_len, &local_err); if (local_err) { error_propagate(errp, local_err); return; --=20 2.20.1 (Apple Git-117) From nobody Mon Feb 9 11:35:11 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1556296265; cv=none; d=zoho.com; s=zohoarc; b=ksensbi65Kl7ZX0OQ6gIueQZA0K4ryYgsbyYaq4FmKDHpPKxjWrHfE9P14bAVghnUcEFDkCWEeeXvxnVJsChZrxvmnM8Wml5cnY1mKE4ubEPHqyegv+9wVqdczOuN7wy5cvBtkT2lULwy4xUq1N8Ml5giu6kYbsUQa2vLKCHDq8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; 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[208.66.210.181]) by smtp.gmail.com with ESMTPSA id c7sm7548700ioc.63.2019.04.26.09.27.05 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 26 Apr 2019 09:27:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oberlin-edu.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ZdFx6lN3s3QrEP9/f0SJgY/3+st2GN+DoCW00fGR9us=; b=WLldS0y0Y3nmAF3Mi/J2XlJT0ri6MjQ8KO3k+E/trtmQk71jRsQqlHJsEJVu4UON/4 sKwxqCydR5It9EUBPdN3hDeihniA83jwTvzsWdWs/WO/z87ipw9ECg1AdzGsIh9sOdJy IvC77yDWSgRQ48ARBnloItTfnL7cILDNMGIjag/cUxmtKdRLyShRqvLT6UwL5YxNAMB4 PrBXxGBGCqCMjTNlF8gQ0EkhsEi77KIPAchdrLrIEgOQvVgTOe/G1A7amfefwh4Y5R3e ZXGLPmZf8y3P+NNM5FTIpZQPlZG0PgJe2ksPeQYlwmBqmCdUgU37QhqvM3eiOUSS4nTi G3vg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZdFx6lN3s3QrEP9/f0SJgY/3+st2GN+DoCW00fGR9us=; b=GpXuZRKMpcSFhBfOtqmFmAfUAXKvQFmEbC81GHsxZOQiQYLQPphN8UhFauHVotQTdD DRTQNbxyfSZ53K35oML8GcGh+7xBmisowXrjh0z+QiyWGetBdq7WYAknhXKlkYEGhDRd NbeiRUDzv1glHPSVrs0VWidY123MMEvf9VdCkeNC969O1fVaU1/ycFqRj1Xn9arqyaYe Rny0hzHFOZpLMa5zGeAGq4kN/A2LmTXQCOA2U8ZCpCEb3H/ke9uAVkgO/GVlydwGiwbk XwXnH2J4KcyfSY6u6QtqjBsyFo1rFpELE7v1TL58nzfYJW3wN0KSKp18ou/K0nJiFV15 9sMw== X-Gm-Message-State: APjAAAWoezapj9dp2ab+j8yBsoWhNNjDNONF44NLQFWVIVRFujnC8KLq kVPr2ichJ7fZlz93BaO8SpTIUGJzOJX2cQ== X-Google-Smtp-Source: APXvYqxb6WcTx1S/5kEippPHsj+E61trCwyo0GD4RHVzUwDmPjhzWCDhrm/gXBnjXwE67YvKdqhe+Q== X-Received: by 2002:a24:9a03:: with SMTP id l3mr8930838ite.3.1556296027015; Fri, 26 Apr 2019 09:27:07 -0700 (PDT) From: Stephen Checkoway To: QEMU Developers , Thomas Huth , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Kevin Wolf , Max Reitz , "open list:Block layer core" , Markus Armbruster , Laszlo Ersek , Laurent Vivier , Paolo Bonzini Date: Fri, 26 Apr 2019 12:26:17 -0400 Message-Id: <20190426162624.55977-4-stephen.checkoway@oberlin.edu> X-Mailer: git-send-email 2.20.1 (Apple Git-117) In-Reply-To: <20190426162624.55977-1-stephen.checkoway@oberlin.edu> References: <20190426162624.55977-1-stephen.checkoway@oberlin.edu> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::143 Subject: [Qemu-devel] [PATCH v4 03/10] block/pflash_cfi02: Fix command address comparison X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stephen Checkoway Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Most AMD commands only examine 11 bits of the address. This masks the addresses used in the comparison to 11 bits. The exceptions are word or sector addresses which use offset directly rather than the shifted offset, boff. Signed-off-by: Stephen Checkoway Acked-by: Thomas Huth --- hw/block/pflash_cfi02.c | 8 +++++++- tests/pflash-cfi02-test.c | 12 ++++++++++-- 2 files changed, 17 insertions(+), 3 deletions(-) diff --git a/hw/block/pflash_cfi02.c b/hw/block/pflash_cfi02.c index 4b7af71806..e4bff0c8f8 100644 --- a/hw/block/pflash_cfi02.c +++ b/hw/block/pflash_cfi02.c @@ -296,11 +296,13 @@ static void pflash_write(void *opaque, hwaddr offset,= uint64_t value, =20 DPRINTF("%s: offset " TARGET_FMT_plx " %08" PRIx64 " %d\n", __func__, offset, value, width); - boff =3D offset & (pfl->sector_len - 1); + boff =3D offset; if (pfl->width =3D=3D 2) boff =3D boff >> 1; else if (pfl->width =3D=3D 4) boff =3D boff >> 2; + /* Only the least-significant 11 bits are used in most cases. */ + boff &=3D 0x7FF; switch (pfl->wcycle) { case 0: /* Set the device in I/O access mode if required */ @@ -519,6 +521,10 @@ static void pflash_cfi02_realize(DeviceState *dev, Err= or **errp) return; } =20 + /* Only 11 bits are used in the comparison. */ + pfl->unlock_addr0 &=3D 0x7FF; + pfl->unlock_addr1 &=3D 0x7FF; + chip_len =3D pfl->sector_len * pfl->nb_blocs; =20 memory_region_init_rom_device(&pfl->orig_mem, OBJECT(pfl), diff --git a/tests/pflash-cfi02-test.c b/tests/pflash-cfi02-test.c index 40af1bb523..ea5f8b2648 100644 --- a/tests/pflash-cfi02-test.c +++ b/tests/pflash-cfi02-test.c @@ -21,8 +21,8 @@ =20 #define FLASH_WIDTH 2 #define CFI_ADDR (FLASH_WIDTH * 0x55) -#define UNLOCK0_ADDR (FLASH_WIDTH * 0x5555) -#define UNLOCK1_ADDR (FLASH_WIDTH * 0x2AAA) +#define UNLOCK0_ADDR (FLASH_WIDTH * 0x555) +#define UNLOCK1_ADDR (FLASH_WIDTH * 0x2AA) =20 #define CFI_CMD 0x98 #define UNLOCK0_CMD 0xAA @@ -190,6 +190,14 @@ static void test_flash(void) g_assert_cmpint(flash_read(6), =3D=3D, 0xCDEF); g_assert_cmpint(flash_read(8), =3D=3D, 0xFFFF); =20 + /* Test ignored high order bits of address. */ + flash_write(FLASH_WIDTH * 0x5555, UNLOCK0_CMD); + flash_write(FLASH_WIDTH * 0x2AAA, UNLOCK1_CMD); + flash_write(FLASH_WIDTH * 0x5555, AUTOSELECT_CMD); + g_assert_cmpint(flash_read(FLASH_WIDTH * 0x0000), =3D=3D, 0x00BF); + g_assert_cmpint(flash_read(FLASH_WIDTH * 0x0001), =3D=3D, 0x236D); + reset(); + qtest_quit(global_qtest); } =20 --=20 2.20.1 (Apple Git-117) From nobody Mon Feb 9 11:35:11 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1556296582; cv=none; d=zoho.com; s=zohoarc; b=NM3zfjhXZ5QMUzrkN+yI8rrUQ8u/VgUX3C3OPrg9oz8b2yaWfREra3sWntsVlA7rvabj0skLfFTbT9D9oWK9FXvopu+HKlTZqYHoNxsQkcvBpkvN6StzZgGOkKm+NJn3oWJfRn6Hv2uJgR58PPP9jJ37jR1kdnQbfiarF3DXFgE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1556296582; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=HUxd5d4SsnIof3sx04gSLg+giupKdlcNcg7iY4bhlWI=; b=ncizpSKw4kEfxgoyuKd5HERATMXPIVADXtgcuVDZbkmiNa+A8d313GVtxcop/A8ly0Pzzi9VXKxp7vb4QevZoW/4n4QxTk0UDaWwYO5q9xN6i22E0G7fSxeXsEIzsbz9inVpWq9IWNsms2UqDO1T/K4gAsA8XDBRNFLo7JppJVw= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1556296582014380.51659266095874; Fri, 26 Apr 2019 09:36:22 -0700 (PDT) Received: from localhost ([127.0.0.1]:49436 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hK3pe-0002vy-OQ for importer@patchew.org; Fri, 26 Apr 2019 12:36:14 -0400 Received: from eggs.gnu.org ([209.51.188.92]:33961) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hK3h2-0004BO-3o for qemu-devel@nongnu.org; Fri, 26 Apr 2019 12:27:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hK3gu-0000xW-La for qemu-devel@nongnu.org; Fri, 26 Apr 2019 12:27:18 -0400 Received: from mail-io1-xd41.google.com ([2607:f8b0:4864:20::d41]:46952) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hK3gs-0000vU-N8 for qemu-devel@nongnu.org; Fri, 26 Apr 2019 12:27:12 -0400 Received: by mail-io1-xd41.google.com with SMTP id p23so3377563iol.13 for ; Fri, 26 Apr 2019 09:27:09 -0700 (PDT) Received: from worksec.oberlin.net (ip-210-181.oberlin.net. [208.66.210.181]) by smtp.gmail.com with ESMTPSA id c7sm7548700ioc.63.2019.04.26.09.27.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 26 Apr 2019 09:27:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oberlin-edu.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=HUxd5d4SsnIof3sx04gSLg+giupKdlcNcg7iY4bhlWI=; b=QtYsTdILayJWZPuc63mtHgGLLPS7kR5R5IFEaKFs1j4jrgcaQajSee9EhKp0wncoTI x7n0vj5/W+syxby2Hcd/4qTl6/S95bqMLfBN0bDG2AXpYxKQ3X4VHW3Uct+VXzoq3GgK k62gKihJGH3xqZqzDCRAhNM3N9wuirJq1wCbbpRXEEpIt5dP7M9f634PdQz8Mm2j57n2 0GDhKGyhPUwA630Vl25LdmlNAlCti3JjmrBWdRAZ1t6PeMDdFx1c3fAZAiWLZziP58/1 O88zfhpFnvaYO3RzKIB2AsMn58hpWeYvtxJdwLs60VR3fYhhSLdsZO9rKKLYQ6KgQzAQ /EuQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=HUxd5d4SsnIof3sx04gSLg+giupKdlcNcg7iY4bhlWI=; b=htqYToBvrVSB9fRUK32rMC67EGSNYtnxym8gYTDvMranu8j0IGhAQnupDiiPRfnnrP U3AwpDJHsia1LLkOHr0wJ2dd6LXLFnYgTvmgM0h7hf3dy+BYy6JLqdwEDEGGS+XI6NOK vf6yTig35/ZF0qwHrdtJF6UeYYe/M4ZxIBr+RY4cfZRf2k/n2ZCYt1TCPBpU40GyJ6PL QFQiqJiJFKw3FSHUzojT8qGVG6AKC7YvkIq0T2tM0czVUVLXjEroU5jKaJcYVTjopZGK HWNWJtBIlJ7fWFRpwjrgQ70dNBaKcHJ/U2SUM5cKzHwT/3lrj/Qa2xecGbRtTF+a+g6H 8swg== X-Gm-Message-State: APjAAAXdielmckzWUBaqRL5iPvK2YvxtJlL0a0JjmHNePfzkSZ34qjy8 nx/hVr9MhSdi1gHcRNjR0JnFwpwohRlUkA== X-Google-Smtp-Source: APXvYqzfafiTIiwO8SfjSGI2VnabksK7O70gYVqRq0kJ5TI+jtKCJdw5CjXCu2W6PrDXRvmoIEWkuw== X-Received: by 2002:a5e:d514:: with SMTP id e20mr7273908iom.8.1556296028392; Fri, 26 Apr 2019 09:27:08 -0700 (PDT) From: Stephen Checkoway To: QEMU Developers , Thomas Huth , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Kevin Wolf , Max Reitz , "open list:Block layer core" , Markus Armbruster , Laszlo Ersek , Laurent Vivier , Paolo Bonzini Date: Fri, 26 Apr 2019 12:26:18 -0400 Message-Id: <20190426162624.55977-5-stephen.checkoway@oberlin.edu> X-Mailer: git-send-email 2.20.1 (Apple Git-117) In-Reply-To: <20190426162624.55977-1-stephen.checkoway@oberlin.edu> References: <20190426162624.55977-1-stephen.checkoway@oberlin.edu> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::d41 Subject: [Qemu-devel] [PATCH v4 04/10] block/pflash_cfi02: Implement intereleaved flash devices X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stephen Checkoway Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" It's common for multiple narrow flash chips to be hooked up in parallel to support wider buses. For example, four 8-bit wide flash chips (x8) may be combined in parallel to produce a 32-bit wide device. Similarly, two 16-bit wide chips (x16) may be combined. This commit introduces `device-width` and `max-device-width` properties, similar to pflash_cfi01, with the following meanings: - `width`: The width of the logical, qemu device (same as before); - `device-width`: The width of an individual flash chip, defaulting to `width`; and - `max-device-width`: The maximum width of an individual flash chip, defaulting to `device-width`. Nothing needs to change to support reading such interleaved devices but commands (e.g., erase and programming) must be sent to all devices at the same time or else the various chips will be in different states. For example, a 4-byte wide logical device can be composed of four x8/x16 devices in x8 mode. That is, each device supports both x8 or x16 and they're being used in the byte, rather than word, mode. This configuration would have `width=3D4`, `device-width=3D1`, and `max-device-width=3D2`. In addition to commands being sent to all devices, guest firmware expects the status and CFI queries to be replicated for each device. (The one exception to the response replication is that each device gets to report its own status bit DQ7 while programming because its value depends on the value being programmed which will usually differ for each device.) Testing is limited to 16-bit wide devices due to the current inability to override the properties set by `pflash_cfi02_register`, but multiple configurations are tested. Stop using global_qtest. Instead, package the qtest variable inside the FlashConfig structure. Signed-off-by: Stephen Checkoway Acked-by: Thomas Huth --- hw/block/pflash_cfi02.c | 270 +++++++++++++++------ tests/pflash-cfi02-test.c | 476 ++++++++++++++++++++++++++++++-------- 2 files changed, 576 insertions(+), 170 deletions(-) diff --git a/hw/block/pflash_cfi02.c b/hw/block/pflash_cfi02.c index e4bff0c8f8..101628b4ec 100644 --- a/hw/block/pflash_cfi02.c +++ b/hw/block/pflash_cfi02.c @@ -28,7 +28,6 @@ * - unlock bypass command * - CFI queries * - * It does not support flash interleaving. * It does not implement boot blocs with reduced size * It does not implement software data protection as found in many real ch= ips * It does not implement erase suspend/resume commands @@ -67,15 +66,19 @@ struct PFlashCFI02 { BlockBackend *blk; uint32_t sector_len; uint32_t nb_blocs; - uint32_t chip_len; + uint64_t total_len; + uint64_t interleave_multiplier; uint8_t mappings; - uint8_t width; + uint8_t bank_width; /* Width of the QEMU device in bytes. */ + uint8_t device_width; /* Width of individual pflash chip. */ + uint8_t max_device_width; /* Maximum width of individual pflash chip. = */ uint8_t be; + int device_shift; /* Amount to shift an offset to get a device address= . */ int wcycle; /* if 0, the flash is read normally */ int bypass; int ro; uint8_t cmd; - uint8_t status; + uint64_t status; /* FIXME: implement array device properties */ uint16_t ident0; uint16_t ident1; @@ -103,16 +106,17 @@ struct PFlashCFI02 { */ static inline void toggle_dq7(PFlashCFI02 *pfl) { - pfl->status ^=3D 0x80; + pfl->status ^=3D pfl->interleave_multiplier * 0x80; } =20 /* * Set status bit DQ7 to bit 7 of value. */ -static inline void set_dq7(PFlashCFI02 *pfl, uint8_t value) +static inline void set_dq7(PFlashCFI02 *pfl, uint64_t value) { - pfl->status &=3D 0x7F; - pfl->status |=3D value & 0x80; + uint64_t mask =3D pfl->interleave_multiplier * 0x80; + pfl->status &=3D ~mask; + pfl->status |=3D value & mask; } =20 /* @@ -120,7 +124,7 @@ static inline void set_dq7(PFlashCFI02 *pfl, uint8_t va= lue) */ static inline void toggle_dq6(PFlashCFI02 *pfl) { - pfl->status ^=3D 0x40; + pfl->status ^=3D pfl->interleave_multiplier * 0x40; } =20 /* @@ -188,7 +192,6 @@ static uint64_t pflash_data_read(PFlashCFI02 *pfl, hwad= dr offset, static uint64_t pflash_read(void *opaque, hwaddr offset, unsigned int widt= h) { PFlashCFI02 *pfl =3D opaque; - hwaddr boff; uint64_t ret; =20 ret =3D -1; @@ -198,12 +201,10 @@ static uint64_t pflash_read(void *opaque, hwaddr offs= et, unsigned int width) ++pfl->read_counter > PFLASH_LAZY_ROMD_THRESHOLD) { pflash_register_memory(pfl, 1); } - offset &=3D pfl->chip_len - 1; - boff =3D offset & 0xFF; - if (pfl->width =3D=3D 2) - boff =3D boff >> 1; - else if (pfl->width =3D=3D 4) - boff =3D boff >> 2; + /* Mask by the total length of the chip to account for alias mappings.= */ + offset &=3D pfl->total_len - 1; + hwaddr device_addr =3D offset >> pfl->device_shift; + switch (pfl->cmd) { default: /* This should never happen : reset state & treat it as a read*/ @@ -215,29 +216,32 @@ static uint64_t pflash_read(void *opaque, hwaddr offs= et, unsigned int width) /* We accept reads during second unlock sequence... */ case 0x00: /* Flash area read */ - ret =3D pflash_data_read(pfl, offset, width); - break; + return pflash_data_read(pfl, offset, width); case 0x90: /* flash ID read */ - switch (boff) { + switch (device_addr & 0xFF) { case 0x00: + ret =3D pfl->ident0; + break; case 0x01: - ret =3D boff & 0x01 ? pfl->ident1 : pfl->ident0; + ret =3D pfl->ident1; break; case 0x02: ret =3D 0x00; /* Pretend all sectors are unprotected */ break; case 0x0E: case 0x0F: - ret =3D boff & 0x01 ? pfl->ident3 : pfl->ident2; + ret =3D device_addr & 0x01 ? pfl->ident3 : pfl->ident2; if (ret !=3D (uint8_t)-1) { break; } /* Fall through to data read. */ default: - ret =3D pflash_data_read(pfl, offset, width); + return pflash_data_read(pfl, offset, width); } - DPRINTF("%s: ID " TARGET_FMT_plx " %" PRIx64 "\n", __func__, boff,= ret); + ret *=3D pfl->interleave_multiplier; + DPRINTF("%s: ID " TARGET_FMT_plx " %" PRIx64 "\n", + __func__, device_addr & 0xFF, ret); break; case 0xA0: case 0x10: @@ -250,8 +254,8 @@ static uint64_t pflash_read(void *opaque, hwaddr offset= , unsigned int width) break; case 0x98: /* CFI query mode */ - if (boff < sizeof(pfl->cfi_table)) { - ret =3D pfl->cfi_table[boff]; + if (device_addr < sizeof(pfl->cfi_table)) { + ret =3D pfl->interleave_multiplier * pfl->cfi_table[device_add= r]; } else { ret =3D 0; } @@ -279,30 +283,36 @@ static void pflash_write(void *opaque, hwaddr offset,= uint64_t value, unsigned int width) { PFlashCFI02 *pfl =3D opaque; - hwaddr boff; uint8_t *p; uint8_t cmd; =20 cmd =3D value; - if (pfl->cmd !=3D 0xA0 && cmd =3D=3D 0xF0) { -#if 0 - DPRINTF("%s: flash reset asked (%02x %02x)\n", - __func__, pfl->cmd, cmd); -#endif - goto reset_flash; + if (pfl->cmd !=3D 0xA0) { + if (value !=3D pfl->interleave_multiplier * cmd) { + DPRINTF("%s: cmd 0x%02x not sent to all devices: expected=3D" + "0x%0*" PRIx64 " actual=3D0x%0*" PRIx64 "\n", + __func__, cmd, + pfl->bank_width * 2, pfl->interleave_multiplier * cmd, + pfl->bank_width * 2, value); + } + + if (cmd =3D=3D 0xF0) { + goto reset_flash; + } } + trace_pflash_write(offset, value, width, pfl->wcycle); - offset &=3D pfl->chip_len - 1; - - DPRINTF("%s: offset " TARGET_FMT_plx " %08" PRIx64 " %d\n", __func__, - offset, value, width); - boff =3D offset; - if (pfl->width =3D=3D 2) - boff =3D boff >> 1; - else if (pfl->width =3D=3D 4) - boff =3D boff >> 2; - /* Only the least-significant 11 bits are used in most cases. */ - boff &=3D 0x7FF; + + /* Mask by the total length of the chip to account for alias mappings.= */ + offset &=3D pfl->total_len - 1; + + DPRINTF("%s: offset " TARGET_FMT_plx " 0x%0*" PRIx64 "\n", + __func__, offset, width * 2, value); + + hwaddr device_addr =3D (offset >> pfl->device_shift); + /* Address bits A11 and greater are don't cares for most commands. */ + unsigned int masked_addr =3D device_addr & 0x7FF; + switch (pfl->wcycle) { case 0: /* Set the device in I/O access mode if required */ @@ -311,16 +321,16 @@ static void pflash_write(void *opaque, hwaddr offset,= uint64_t value, pfl->read_counter =3D 0; /* We're in read mode */ check_unlock0: - if (boff =3D=3D 0x55 && cmd =3D=3D 0x98) { + if (masked_addr =3D=3D 0x55 && cmd =3D=3D 0x98) { enter_CFI_mode: /* Enter CFI query mode */ pfl->wcycle =3D WCYCLE_CFI; pfl->cmd =3D 0x98; return; } - if (boff !=3D pfl->unlock_addr0 || cmd !=3D 0xAA) { - DPRINTF("%s: unlock0 failed " TARGET_FMT_plx " %02x %04x\n", - __func__, boff, cmd, pfl->unlock_addr0); + if (masked_addr !=3D pfl->unlock_addr0 || cmd !=3D 0xAA) { + DPRINTF("%s: unlock0 failed %04x %02x %04x\n", + __func__, masked_addr, cmd, pfl->unlock_addr0); goto reset_flash; } DPRINTF("%s: unlock sequence started\n", __func__); @@ -328,18 +338,18 @@ static void pflash_write(void *opaque, hwaddr offset,= uint64_t value, case 1: /* We started an unlock sequence */ check_unlock1: - if (boff !=3D pfl->unlock_addr1 || cmd !=3D 0x55) { - DPRINTF("%s: unlock1 failed " TARGET_FMT_plx " %02x\n", __func= __, - boff, cmd); + if (masked_addr !=3D pfl->unlock_addr1 || cmd !=3D 0x55) { + DPRINTF("%s: unlock1 failed %03x %02x\n", __func__, + masked_addr, cmd); goto reset_flash; } DPRINTF("%s: unlock sequence done\n", __func__); break; case 2: /* We finished an unlock sequence */ - if (!pfl->bypass && boff !=3D pfl->unlock_addr0) { - DPRINTF("%s: command failed " TARGET_FMT_plx " %02x\n", __func= __, - boff, cmd); + if (!pfl->bypass && masked_addr !=3D pfl->unlock_addr0) { + DPRINTF("%s: command failed %03x %02x\n", __func__, + masked_addr, cmd); goto reset_flash; } switch (cmd) { @@ -390,8 +400,9 @@ static void pflash_write(void *opaque, hwaddr offset, u= int64_t value, goto reset_flash; } /* We can enter CFI query mode from autoselect mode */ - if (boff =3D=3D 0x55 && cmd =3D=3D 0x98) + if (masked_addr =3D=3D 0x55 && cmd =3D=3D 0x98) { goto enter_CFI_mode; + } /* No break here */ default: DPRINTF("%s: invalid write for command %02x\n", @@ -416,7 +427,7 @@ static void pflash_write(void *opaque, hwaddr offset, u= int64_t value, case 5: switch (cmd) { case 0x10: - if (boff !=3D pfl->unlock_addr0) { + if (masked_addr !=3D pfl->unlock_addr0) { DPRINTF("%s: chip erase: invalid address " TARGET_FMT_plx = "\n", __func__, offset); goto reset_flash; @@ -424,8 +435,8 @@ static void pflash_write(void *opaque, hwaddr offset, u= int64_t value, /* Chip erase */ DPRINTF("%s: start chip erase\n", __func__); if (!pfl->ro) { - memset(pfl->storage, 0xFF, pfl->chip_len); - pflash_update(pfl, 0, pfl->chip_len); + memset(pfl->storage, 0xFF, pfl->total_len); + pflash_update(pfl, 0, pfl->total_len); } set_dq7(pfl, 0x00); /* Let's wait 5 seconds before chip erase is done */ @@ -521,22 +532,132 @@ static void pflash_cfi02_realize(DeviceState *dev, E= rror **errp) return; } =20 + if (pfl->bank_width =3D=3D 0) { + error_setg(errp, "attribute \"width\" not specified or zero."); + return; + } + + /* + * device-width defaults to width and max-device-width defaults to + * device-width. Check that the device-width and max-device-width + * configurations are supported. + */ + if (pfl->device_width =3D=3D 0) { + pfl->device_width =3D pfl->bank_width; + } + if (pfl->max_device_width =3D=3D 0) { + pfl->max_device_width =3D pfl->device_width; + } + if (pfl->bank_width % pfl->device_width !=3D 0) { + error_setg(errp, + "attribute \"width\" (%u) not a multiple of attribute " + "\"device-width\" (%u).", + pfl->bank_width, pfl->device_width); + return; + } + + /* + * Writing commands to the flash device and reading CFI responses or + * status values requires transforming a QEMU device offset into a + * flash device address given in terms of the device's maximum width. = We + * can do this by shifting a QEMU device offset right a constant numbe= r of + * bits depending on the bank_width, device_width, and max_device_widt= h. + * + * num_devices =3D bank_width / device_width is the number of interlea= ved + * flash devices. To compute a device byte address, we need to divide + * offset by num_devices (equivalently shift right by log2(num_devices= )). + * To turn a device byte address into a device word address, we need to + * divide by max_device_width (equivalently shift right by + * log2(max_device_width)). + * + * In tabular form. + * =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + * bank_width device_width max_device_width num_devices shift + * ------------------------------------------------------------------ + * 1 1 1 1 0 + * 1 1 2 1 1 + * 2 1 1 2 1 + * 2 1 2 2 2 + * 2 2 2 1 1 + * 4 1 1 4 2 + * 4 1 2 4 3 + * 4 1 4 4 4 + * 4 2 2 2 2 + * 4 2 4 2 3 + * 4 4 4 1 2 + * =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + */ + pfl->device_shift =3D ctz32(pfl->bank_width) - ctz32(pfl->device_width= ) + + ctz32(pfl->max_device_width); + pfl->interleave_multiplier =3D 0; + for (unsigned int shift =3D 0; shift < pfl->bank_width; + shift +=3D pfl->device_width) { + pfl->interleave_multiplier |=3D 1 << (shift * 8); + } + + uint16_t device_interface_code; + if (pfl->max_device_width =3D=3D 1 && pfl->device_width =3D=3D 1) { + device_interface_code =3D 0; /* x8 only. */ + } else if (pfl->max_device_width =3D=3D 2 && + (pfl->device_width =3D=3D 1 || pfl->device_width =3D=3D 2))= { + /* XXX: Some devices only support x16, this code doesn't model the= m. */ + device_interface_code =3D 2; /* Supports x8 or x16. */ + } else if (pfl->max_device_width =3D=3D 4 && pfl->device_width =3D=3D = 1) { + /* + * XXX: this is x32-only. The standards I've seen don't specify a = value + * for x8/x32 but do mention them. + */ + device_interface_code =3D 3; /* x32 only. */ + } else if (pfl->max_device_width =3D=3D 4 && + (pfl->device_width =3D=3D 2 || pfl->device_width =3D=3D 4))= { + device_interface_code =3D 4; /* Supports x16 or x32. */ + } else { + error_setg(errp, + "unsupported configuration: \"device-width\"=3D%u " + "\"max-device-width\"=3D%u.", + pfl->device_width, pfl->max_device_width); + return; + } + + pfl->total_len =3D pfl->sector_len * pfl->nb_blocs; + + /* + * If the flash is not a power of 2, then the code for handling multip= le + * mappings will not work correctly. + */ + if (!is_power_of_2(pfl->total_len)) { + error_setg(errp, "total pflash length (%" PRIx64 ") not a power of= 2.", + pfl->total_len); + return; + } + + int num_devices =3D pfl->bank_width / pfl->device_width; + uint64_t sector_len_per_device =3D pfl->sector_len / num_devices; + uint64_t device_len =3D sector_len_per_device * pfl->nb_blocs; + + if (sector_len_per_device & 0xff || sector_len_per_device >=3D (1 << 2= 4)) { + error_setg(errp, + "unsupported configuration: sector length per device = =3D " + "%" PRIx64 ".", + sector_len_per_device); + return; + } + + memory_region_init_rom_device(&pfl->orig_mem, OBJECT(pfl), + &pflash_cfi02_ops, pfl, pfl->name, + pfl->total_len, &local_err); /* Only 11 bits are used in the comparison. */ pfl->unlock_addr0 &=3D 0x7FF; pfl->unlock_addr1 &=3D 0x7FF; =20 chip_len =3D pfl->sector_len * pfl->nb_blocs; =20 - memory_region_init_rom_device(&pfl->orig_mem, OBJECT(pfl), - &pflash_cfi02_ops, pfl, pfl->name, - chip_len, &local_err); if (local_err) { error_propagate(errp, local_err); return; } =20 pfl->storage =3D memory_region_get_ram_ptr(&pfl->orig_mem); - pfl->chip_len =3D chip_len; =20 if (pfl->blk) { uint64_t perm; @@ -566,6 +687,7 @@ static void pflash_cfi02_realize(DeviceState *dev, Erro= r **errp) pfl->wcycle =3D 0; pfl->cmd =3D 0; pfl->status =3D 0; + /* Hardcoded CFI table (mostly from SG29 Spansion flash) */ /* Standard "QRY" string */ pfl->cfi_table[0x10] =3D 'Q'; @@ -591,8 +713,8 @@ static void pflash_cfi02_realize(DeviceState *dev, Erro= r **errp) pfl->cfi_table[0x1D] =3D 0x00; /* Vpp max (no Vpp pin) */ pfl->cfi_table[0x1E] =3D 0x00; - /* Reserved */ - pfl->cfi_table[0x1F] =3D 0x07; + /* Timeout per single byte/word write (16 us) */ + pfl->cfi_table[0x1F] =3D 0x04; /* Timeout for min size buffer write (NA) */ pfl->cfi_table[0x20] =3D 0x00; /* Typical timeout for block erase (512 ms) */ @@ -608,13 +730,13 @@ static void pflash_cfi02_realize(DeviceState *dev, Er= ror **errp) /* Max timeout for chip erase */ pfl->cfi_table[0x26] =3D 0x0D; /* Device size */ - pfl->cfi_table[0x27] =3D ctz32(chip_len); - /* Flash device interface (8 & 16 bits) */ - pfl->cfi_table[0x28] =3D 0x02; - pfl->cfi_table[0x29] =3D 0x00; + pfl->cfi_table[0x27] =3D ctz32(device_len); + /* Flash device interface */ + pfl->cfi_table[0x28] =3D device_interface_code; + pfl->cfi_table[0x29] =3D device_interface_code >> 8; /* Max number of bytes in multi-bytes write */ /* XXX: disable buffered write as it's not supported */ - // pfl->cfi_table[0x2A] =3D 0x05; + /* pfl->cfi_table[0x2A] =3D 0x05; */ pfl->cfi_table[0x2A] =3D 0x00; pfl->cfi_table[0x2B] =3D 0x00; /* Number of erase block regions (uniform) */ @@ -622,8 +744,8 @@ static void pflash_cfi02_realize(DeviceState *dev, Erro= r **errp) /* Erase block region 1 */ pfl->cfi_table[0x2D] =3D pfl->nb_blocs - 1; pfl->cfi_table[0x2E] =3D (pfl->nb_blocs - 1) >> 8; - pfl->cfi_table[0x2F] =3D pfl->sector_len >> 8; - pfl->cfi_table[0x30] =3D pfl->sector_len >> 16; + pfl->cfi_table[0x2F] =3D sector_len_per_device >> 8; + pfl->cfi_table[0x30] =3D sector_len_per_device >> 16; =20 /* Extended */ pfl->cfi_table[0x31] =3D 'P'; @@ -648,7 +770,9 @@ static Property pflash_cfi02_properties[] =3D { DEFINE_PROP_DRIVE("drive", PFlashCFI02, blk), DEFINE_PROP_UINT32("num-blocks", PFlashCFI02, nb_blocs, 0), DEFINE_PROP_UINT32("sector-length", PFlashCFI02, sector_len, 0), - DEFINE_PROP_UINT8("width", PFlashCFI02, width, 0), + DEFINE_PROP_UINT8("width", PFlashCFI02, bank_width, 0), + DEFINE_PROP_UINT8("device-width", PFlashCFI02, device_width, 0), + DEFINE_PROP_UINT8("max-device-width", PFlashCFI02, max_device_width, 0= ), DEFINE_PROP_UINT8("mappings", PFlashCFI02, mappings, 0), DEFINE_PROP_UINT8("big-endian", PFlashCFI02, be, 0), DEFINE_PROP_UINT16("id0", PFlashCFI02, ident0, 0), @@ -696,7 +820,7 @@ PFlashCFI02 *pflash_cfi02_register(hwaddr base, hwaddr size, BlockBackend *blk, uint32_t sector_len, - int nb_mappings, int width, + int nb_mappings, int bank_width, uint16_t id0, uint16_t id1, uint16_t id2, uint16_t id3, uint16_t unlock_addr0, @@ -711,7 +835,7 @@ PFlashCFI02 *pflash_cfi02_register(hwaddr base, assert(size % sector_len =3D=3D 0); qdev_prop_set_uint32(dev, "num-blocks", size / sector_len); qdev_prop_set_uint32(dev, "sector-length", sector_len); - qdev_prop_set_uint8(dev, "width", width); + qdev_prop_set_uint8(dev, "width", bank_width); qdev_prop_set_uint8(dev, "mappings", nb_mappings); qdev_prop_set_uint8(dev, "big-endian", !!be); qdev_prop_set_uint16(dev, "id0", id0); diff --git a/tests/pflash-cfi02-test.c b/tests/pflash-cfi02-test.c index ea5f8b2648..a1be26da73 100644 --- a/tests/pflash-cfi02-test.c +++ b/tests/pflash-cfi02-test.c @@ -17,12 +17,18 @@ */ =20 #define MP_FLASH_SIZE_MAX (32 * 1024 * 1024) +#define FLASH_SIZE (8 * 1024 * 1024) #define BASE_ADDR (0x100000000ULL - MP_FLASH_SIZE_MAX) =20 -#define FLASH_WIDTH 2 -#define CFI_ADDR (FLASH_WIDTH * 0x55) -#define UNLOCK0_ADDR (FLASH_WIDTH * 0x555) -#define UNLOCK1_ADDR (FLASH_WIDTH * 0x2AA) +/* Use a newtype to keep flash addresses separate from byte addresses. */ +typedef struct { + uint64_t addr; +} faddr; +#define FLASH_ADDR(x) ((faddr) { .addr =3D (x) }) + +#define CFI_ADDR FLASH_ADDR(0x55) +#define UNLOCK0_ADDR FLASH_ADDR(0x555) +#define UNLOCK1_ADDR FLASH_ADDR(0x2AA) =20 #define CFI_CMD 0x98 #define UNLOCK0_CMD 0xAA @@ -35,170 +41,381 @@ #define UNLOCK_BYPASS_CMD 0x20 #define UNLOCK_BYPASS_RESET_CMD 0x00 =20 +typedef struct { + int bank_width; + int device_width; + int max_device_width; + + QTestState *qtest; +} FlashConfig; + static char image_path[] =3D "/tmp/qtest.XXXXXX"; =20 -static inline void flash_write(uint64_t byte_addr, uint16_t data) +/* + * The pflash implementation allows some parameters to be unspecified. We = want + * to test those configurations but we also need to know the real values in + * our testing code. So after we launch qemu, we'll need a new FlashConfig + * with the correct values filled in. + */ +static FlashConfig expand_config_defaults(const FlashConfig *c) { - qtest_writew(global_qtest, BASE_ADDR + byte_addr, data); + FlashConfig ret =3D *c; + + if (ret.device_width =3D=3D 0) { + ret.device_width =3D ret.bank_width; + } + if (ret.max_device_width =3D=3D 0) { + ret.max_device_width =3D ret.device_width; + } + return ret; +} + +/* + * Return a bit mask suitable for extracting the least significant + * status/query response from an interleaved response. + */ +static inline uint64_t device_mask(const FlashConfig *c) +{ + if (c->device_width =3D=3D 8) { + return (uint64_t)-1; + } + return (1ULL << (c->device_width * 8)) - 1ULL; +} + +/* + * Return a bit mask exactly as long as the bank_width. + */ +static inline uint64_t bank_mask(const FlashConfig *c) +{ + if (c->bank_width =3D=3D 8) { + return (uint64_t)-1; + } + return (1ULL << (c->bank_width * 8)) - 1ULL; +} + +static inline void flash_write(const FlashConfig *c, uint64_t byte_addr, + uint64_t data) +{ + /* Sanity check our tests. */ + assert((data & ~bank_mask(c)) =3D=3D 0); + uint64_t addr =3D BASE_ADDR + byte_addr; + switch (c->bank_width) { + case 1: + qtest_writeb(c->qtest, addr, data); + break; + case 2: + qtest_writew(c->qtest, addr, data); + break; + case 4: + qtest_writel(c->qtest, addr, data); + break; + case 8: + qtest_writeq(c->qtest, addr, data); + break; + default: + abort(); + } +} + +static inline uint64_t flash_read(const FlashConfig *c, uint64_t byte_addr) +{ + uint64_t addr =3D BASE_ADDR + byte_addr; + switch (c->bank_width) { + case 1: + return qtest_readb(c->qtest, addr); + case 2: + return qtest_readw(c->qtest, addr); + case 4: + return qtest_readl(c->qtest, addr); + case 8: + return qtest_readq(c->qtest, addr); + default: + abort(); + } +} + +/* + * Convert a flash address expressed in the maximum width of the device as= a + * byte address. + */ +static inline uint64_t as_byte_addr(const FlashConfig *c, faddr flash_addr) +{ + /* + * Command addresses are always given as addresses in the maximum + * supported bus size for the flash chip. So an x8/x16 chip in x8 mode + * uses addresses 0xAAA and 0x555 to unlock because the least signific= ant + * bit is ignored. (0x555 rather than 0x554 is traditional.) + * + * Interleaving flash chips use the least significant bits of a byte + * address to refer to data from the individual chips. Two interleaved= x8 + * devices would use command addresses 0xAAA and 0x554. Two interleaved + * x16 devices would use 0x1554 and 0xAA8. + * + * More exotic configurations are possible. Two interleaved x8/x16 dev= ices + * in x8 mode would also use 0x1554 and 0xAA8. + * + * In general we need to multiply an address by the number of devices, + * which is bank_width / device_width, and multiply that by the maximum + * device width. + */ + int num_devices =3D c->bank_width / c->device_width; + return flash_addr.addr * (num_devices * c->max_device_width); +} + +/* + * Return the command value or expected status replicated across all devic= es. + */ +static inline uint64_t replicate(const FlashConfig *c, uint64_t data) +{ + /* Sanity check our tests. */ + assert((data & ~device_mask(c)) =3D=3D 0); + for (int i =3D c->device_width; i < c->bank_width; i +=3D c->device_wi= dth) { + data |=3D data << (c->device_width * 8); + } + return data; +} + +static inline void flash_cmd(const FlashConfig *c, faddr cmd_addr, + uint8_t cmd) +{ + flash_write(c, as_byte_addr(c, cmd_addr), replicate(c, cmd)); +} + +static inline uint64_t flash_query(const FlashConfig *c, faddr query_addr) +{ + return flash_read(c, as_byte_addr(c, query_addr)); } =20 -static inline uint16_t flash_read(uint64_t byte_addr) +static inline uint64_t flash_query_1(const FlashConfig *c, faddr query_add= r) { - return qtest_readw(global_qtest, BASE_ADDR + byte_addr); + return flash_query(c, query_addr) & device_mask(c); } =20 -static void unlock(void) +static void unlock(const FlashConfig *c) { - flash_write(UNLOCK0_ADDR, UNLOCK0_CMD); - flash_write(UNLOCK1_ADDR, UNLOCK1_CMD); + flash_cmd(c, UNLOCK0_ADDR, UNLOCK0_CMD); + flash_cmd(c, UNLOCK1_ADDR, UNLOCK1_CMD); } =20 -static void reset(void) +static void reset(const FlashConfig *c) { - flash_write(0, RESET_CMD); + flash_cmd(c, FLASH_ADDR(0), RESET_CMD); } =20 -static void sector_erase(uint64_t byte_addr) +static void sector_erase(const FlashConfig *c, uint64_t byte_addr) { - unlock(); - flash_write(UNLOCK0_ADDR, 0x80); - unlock(); - flash_write(byte_addr, SECTOR_ERASE_CMD); + unlock(c); + flash_cmd(c, UNLOCK0_ADDR, 0x80); + unlock(c); + flash_write(c, byte_addr, replicate(c, SECTOR_ERASE_CMD)); } =20 -static void wait_for_completion(uint64_t byte_addr) +static void wait_for_completion(const FlashConfig *c, uint64_t byte_addr) { /* If DQ6 is toggling, step the clock and ensure the toggle stops. */ - if ((flash_read(byte_addr) & 0x40) ^ (flash_read(byte_addr) & 0x40)) { + const uint64_t dq6 =3D replicate(c, 0x40); + if ((flash_read(c, byte_addr) & dq6) ^ (flash_read(c, byte_addr) & dq6= )) { /* Wait for erase or program to finish. */ - clock_step_next(); + qtest_clock_step_next(c->qtest); /* Ensure that DQ6 has stopped toggling. */ - g_assert_cmpint(flash_read(byte_addr), =3D=3D, flash_read(byte_add= r)); + g_assert_cmpint(flash_read(c, byte_addr), =3D=3D, flash_read(c, by= te_addr)); } } =20 -static void bypass_program(uint64_t byte_addr, uint16_t data) +static void bypass_program(const FlashConfig *c, uint64_t byte_addr, + uint16_t data) { - flash_write(UNLOCK0_ADDR, PROGRAM_CMD); - flash_write(byte_addr, data); + flash_cmd(c, UNLOCK0_ADDR, PROGRAM_CMD); + flash_write(c, byte_addr, data); /* * Data isn't valid until DQ6 stops toggling. We don't model this as * writes are immediate, but if this changes in the future, we can wait * until the program is complete. */ - wait_for_completion(byte_addr); + wait_for_completion(c, byte_addr); } =20 -static void program(uint64_t byte_addr, uint16_t data) +static void program(const FlashConfig *c, uint64_t byte_addr, uint16_t dat= a) { - unlock(); - bypass_program(byte_addr, data); + unlock(c); + bypass_program(c, byte_addr, data); } =20 -static void chip_erase(void) +static void chip_erase(const FlashConfig *c) { - unlock(); - flash_write(UNLOCK0_ADDR, 0x80); - unlock(); - flash_write(UNLOCK0_ADDR, SECTOR_ERASE_CMD); + unlock(c); + flash_cmd(c, UNLOCK0_ADDR, 0x80); + unlock(c); + flash_cmd(c, UNLOCK0_ADDR, CHIP_ERASE_CMD); } =20 -static void test_flash(void) +/* + * Check that the device interface code dic is appropriate for the given + * width. + * + * Device interface codes are specified in JEP173. + */ +static bool device_supports_width(uint16_t dic, int width) { - global_qtest =3D qtest_initf("-M musicpal,accel=3Dqtest " - "-drive if=3Dpflash,file=3D%s,format=3Draw,= copy-on-read", - image_path); + switch (width) { + case 1: + /* + * x8-only, x8/x16, or x32 + * XXX: Currently we use dic =3D 3 for an x8/x32 device even though + * that's only for x32. If there's a more appropriate value, both = this + * test and pflash-cfi02.c should be modified. + */ + return dic =3D=3D 0 || dic =3D=3D 2 || dic =3D=3D 3; + case 2: + /* x16-only, x8/x16, or x16/x32. */ + return dic =3D=3D 1 || dic =3D=3D 2 || dic =3D=3D 4; + case 4: + /* x32-only or x16/x32. */ + return dic =3D=3D 3 || dic =3D=3D 4; + } + g_test_incomplete("Device width test not supported"); + return true; +} + +static void test_flash(const void *opaque) +{ + const FlashConfig *config =3D opaque; + QTestState *qtest; + qtest =3D qtest_initf("-M musicpal,accel=3Dqtest" + " -drive if=3Dpflash,file=3D%s,format=3Draw,copy-o= n-read" + " -global driver=3Dcfi.pflash02," + "property=3Ddevice-width,value=3D%d" + " -global driver=3Dcfi.pflash02," + "property=3Dmax-device-width,value=3D%d", + image_path, + config->device_width, + config->max_device_width); + FlashConfig explicit_config =3D expand_config_defaults(config); + explicit_config.qtest =3D qtest; + const FlashConfig *c =3D &explicit_config; + /* Check the IDs. */ - unlock(); - flash_write(UNLOCK0_ADDR, AUTOSELECT_CMD); - g_assert_cmpint(flash_read(FLASH_WIDTH * 0x0000), =3D=3D, 0x00BF); - g_assert_cmpint(flash_read(FLASH_WIDTH * 0x0001), =3D=3D, 0x236D); - reset(); + unlock(c); + flash_cmd(c, UNLOCK0_ADDR, AUTOSELECT_CMD); + g_assert_cmpint(flash_query(c, FLASH_ADDR(0)), =3D=3D, replicate(c, 0x= BF)); + if (c->device_width >=3D 2) { + /* + * XXX: The ID returned by the musicpal flash chip is 16 bits which + * wouldn't happen with an 8-bit device. It would probably be best= to + * prohibit addresses larger than the device width in pflash_cfi02= .c, + * but then we couldn't test smaller device widths at all. + */ + g_assert_cmpint(flash_query(c, FLASH_ADDR(1)), =3D=3D, + replicate(c, 0x236D)); + } + reset(c); =20 /* Check the erase blocks. */ - flash_write(CFI_ADDR, CFI_CMD); - g_assert_cmpint(flash_read(FLASH_WIDTH * 0x10), =3D=3D, 'Q'); - g_assert_cmpint(flash_read(FLASH_WIDTH * 0x11), =3D=3D, 'R'); - g_assert_cmpint(flash_read(FLASH_WIDTH * 0x12), =3D=3D, 'Y'); + flash_cmd(c, CFI_ADDR, CFI_CMD); + g_assert_cmpint(flash_query(c, FLASH_ADDR(0x10)), =3D=3D, replicate(c,= 'Q')); + g_assert_cmpint(flash_query(c, FLASH_ADDR(0x11)), =3D=3D, replicate(c,= 'R')); + g_assert_cmpint(flash_query(c, FLASH_ADDR(0x12)), =3D=3D, replicate(c,= 'Y')); + /* Num erase regions. */ - g_assert_cmpint(flash_read(FLASH_WIDTH * 0x2C), >=3D, 1); - uint32_t nb_sectors =3D flash_read(FLASH_WIDTH * 0x2D) + - (flash_read(FLASH_WIDTH * 0x2E) << 8) + 1; - uint32_t sector_len =3D (flash_read(FLASH_WIDTH * 0x2F) << 8) + - (flash_read(FLASH_WIDTH * 0x30) << 16); - reset(); + g_assert_cmpint(flash_query_1(c, FLASH_ADDR(0x2C)), >=3D, 1); =20 + /* Check device length. */ + uint32_t device_len =3D 1 << flash_query_1(c, FLASH_ADDR(0x27)); + g_assert_cmpint(device_len * (c->bank_width / c->device_width), =3D=3D, + FLASH_SIZE); + + /* Check nb_sectors * sector_len is device_len. */ + uint32_t nb_sectors =3D flash_query_1(c, FLASH_ADDR(0x2D)) + + (flash_query_1(c, FLASH_ADDR(0x2E)) << 8) + 1; + uint32_t sector_len =3D (flash_query_1(c, FLASH_ADDR(0x2F)) << 8) + + (flash_query_1(c, FLASH_ADDR(0x30)) << 16); + g_assert_cmpint(nb_sectors * sector_len, =3D=3D, device_len); + + /* Check the device interface code supports the width and max width. */ + uint16_t device_interface_code =3D flash_query_1(c, FLASH_ADDR(0x28)) + + (flash_query_1(c, FLASH_ADDR(0x29)) <= < 8); + g_assert_true(device_supports_width(device_interface_code, + c->device_width)); + g_assert_true(device_supports_width(device_interface_code, + c->max_device_width)); + reset(c); + + const uint64_t dq7 =3D replicate(c, 0x80); + const uint64_t dq6 =3D replicate(c, 0x40); /* Erase and program sector. */ for (uint32_t i =3D 0; i < nb_sectors; ++i) { uint64_t byte_addr =3D i * sector_len; - sector_erase(byte_addr); + sector_erase(c, byte_addr); /* Read toggle. */ - uint16_t status0 =3D flash_read(byte_addr); + uint64_t status0 =3D flash_read(c, byte_addr); /* DQ7 is 0 during an erase. */ - g_assert_cmpint(status0 & 0x80, =3D=3D, 0); - uint16_t status1 =3D flash_read(byte_addr); + g_assert_cmpint(status0 & dq7, =3D=3D, 0); + uint64_t status1 =3D flash_read(c, byte_addr); /* DQ6 toggles during an erase. */ - g_assert_cmpint(status0 & 0x40, !=3D, status1 & 0x40); + g_assert_cmpint(status0 & dq6, =3D=3D, ~status1 & dq6); /* Wait for erase to complete. */ - clock_step_next(); + qtest_clock_step_next(c->qtest); /* Ensure DQ6 has stopped toggling. */ - g_assert_cmpint(flash_read(byte_addr), =3D=3D, flash_read(byte_add= r)); + g_assert_cmpint(flash_read(c, byte_addr), =3D=3D, flash_read(c, by= te_addr)); /* Now the data should be valid. */ - g_assert_cmpint(flash_read(byte_addr), =3D=3D, 0xFFFF); + g_assert_cmpint(flash_read(c, byte_addr), =3D=3D, bank_mask(c)); =20 /* Program a bit pattern. */ - program(byte_addr, 0x5555); - g_assert_cmpint(flash_read(byte_addr), =3D=3D, 0x5555); - program(byte_addr, 0xAA55); - g_assert_cmpint(flash_read(byte_addr), =3D=3D, 0x0055); + program(c, byte_addr, 0x55); + g_assert_cmpint(flash_read(c, byte_addr) & 0xFF, =3D=3D, 0x55); + program(c, byte_addr, 0xA5); + g_assert_cmpint(flash_read(c, byte_addr) & 0xFF, =3D=3D, 0x05); } =20 /* Erase the chip. */ - chip_erase(); + chip_erase(c); /* Read toggle. */ - uint16_t status0 =3D flash_read(0); + uint64_t status0 =3D flash_read(c, 0); /* DQ7 is 0 during an erase. */ - g_assert_cmpint(status0 & 0x80, =3D=3D, 0); - uint16_t status1 =3D flash_read(0); + g_assert_cmpint(status0 & dq7, =3D=3D, 0); + uint64_t status1 =3D flash_read(c, 0); /* DQ6 toggles during an erase. */ - g_assert_cmpint(status0 & 0x40, !=3D, status1 & 0x40); + g_assert_cmpint(status0 & dq6, =3D=3D, ~status1 & dq6); /* Wait for erase to complete. */ - clock_step_next(); + qtest_clock_step_next(c->qtest); /* Ensure DQ6 has stopped toggling. */ - g_assert_cmpint(flash_read(0), =3D=3D, flash_read(0)); + g_assert_cmpint(flash_read(c, 0), =3D=3D, flash_read(c, 0)); /* Now the data should be valid. */ - g_assert_cmpint(flash_read(0), =3D=3D, 0xFFFF); + + for (uint32_t i =3D 0; i < nb_sectors; ++i) { + uint64_t byte_addr =3D i * sector_len; + g_assert_cmpint(flash_read(c, byte_addr), =3D=3D, bank_mask(c)); + } =20 /* Unlock bypass */ - unlock(); - flash_write(UNLOCK0_ADDR, UNLOCK_BYPASS_CMD); - bypass_program(0, 0x0123); - bypass_program(2, 0x4567); - bypass_program(4, 0x89AB); + unlock(c); + flash_cmd(c, UNLOCK0_ADDR, UNLOCK_BYPASS_CMD); + bypass_program(c, 0 * c->bank_width, 0x01); + bypass_program(c, 1 * c->bank_width, 0x23); + bypass_program(c, 2 * c->bank_width, 0x45); /* * Test that bypass programming, unlike normal programming can use any * address for the PROGRAM_CMD. */ - flash_write(6, PROGRAM_CMD); - flash_write(6, 0xCDEF); - wait_for_completion(6); - flash_write(0, UNLOCK_BYPASS_RESET_CMD); - bypass_program(8, 0x55AA); /* Should fail. */ - g_assert_cmpint(flash_read(0), =3D=3D, 0x0123); - g_assert_cmpint(flash_read(2), =3D=3D, 0x4567); - g_assert_cmpint(flash_read(4), =3D=3D, 0x89AB); - g_assert_cmpint(flash_read(6), =3D=3D, 0xCDEF); - g_assert_cmpint(flash_read(8), =3D=3D, 0xFFFF); + flash_cmd(c, FLASH_ADDR(3 * c->bank_width), PROGRAM_CMD); + flash_write(c, 3 * c->bank_width, 0x67); + wait_for_completion(c, 3 * c->bank_width); + flash_cmd(c, FLASH_ADDR(0), UNLOCK_BYPASS_RESET_CMD); + bypass_program(c, 4 * c->bank_width, 0x89); /* Should fail. */ + g_assert_cmpint(flash_read(c, 0 * c->bank_width), =3D=3D, 0x01); + g_assert_cmpint(flash_read(c, 1 * c->bank_width), =3D=3D, 0x23); + g_assert_cmpint(flash_read(c, 2 * c->bank_width), =3D=3D, 0x45); + g_assert_cmpint(flash_read(c, 3 * c->bank_width), =3D=3D, 0x67); + g_assert_cmpint(flash_read(c, 4 * c->bank_width), =3D=3D, bank_mask(c)= ); =20 /* Test ignored high order bits of address. */ - flash_write(FLASH_WIDTH * 0x5555, UNLOCK0_CMD); - flash_write(FLASH_WIDTH * 0x2AAA, UNLOCK1_CMD); - flash_write(FLASH_WIDTH * 0x5555, AUTOSELECT_CMD); - g_assert_cmpint(flash_read(FLASH_WIDTH * 0x0000), =3D=3D, 0x00BF); - g_assert_cmpint(flash_read(FLASH_WIDTH * 0x0001), =3D=3D, 0x236D); - reset(); + flash_cmd(c, FLASH_ADDR(0x5555), UNLOCK0_CMD); + flash_cmd(c, FLASH_ADDR(0x2AAA), UNLOCK1_CMD); + flash_cmd(c, FLASH_ADDR(0x5555), AUTOSELECT_CMD); + g_assert_cmpint(flash_query(c, FLASH_ADDR(0)), =3D=3D, replicate(c, 0x= BF)); + reset(c); =20 - qtest_quit(global_qtest); + qtest_quit(qtest); } =20 static void cleanup(void *opaque) @@ -206,6 +423,61 @@ static void cleanup(void *opaque) unlink(image_path); } =20 +/* + * XXX: Tests are limited to bank_width =3D 2 for now because that's what + * hw/arm/musicpal.c has. + */ +static const FlashConfig configuration[] =3D { + /* One x16 device. */ + { + .bank_width =3D 2, + .device_width =3D 2, + .max_device_width =3D 2, + }, + /* Implicitly one x16 device. */ + { + .bank_width =3D 2, + .device_width =3D 0, + .max_device_width =3D 0, + }, + /* Implicitly one x16 device. */ + { + .bank_width =3D 2, + .device_width =3D 2, + .max_device_width =3D 0, + }, + /* Interleave two x8 devices. */ + { + .bank_width =3D 2, + .device_width =3D 1, + .max_device_width =3D 1, + }, + /* Interleave two implicit x8 devices. */ + { + .bank_width =3D 2, + .device_width =3D 1, + .max_device_width =3D 0, + }, + /* Interleave two x8/x16 devices in x8 mode. */ + { + .bank_width =3D 2, + .device_width =3D 1, + .max_device_width =3D 2, + }, + /* One x16/x32 device in x16 mode. */ + { + .bank_width =3D 2, + .device_width =3D 2, + .max_device_width =3D 4, + }, + /* Two x8/x32 devices in x8 mode; I am not sure if such devices exist.= */ + { + .bank_width =3D 2, + .device_width =3D 1, + .max_device_width =3D 4, + }, +}; + int main(int argc, char **argv) { int fd =3D mkstemp(image_path); @@ -214,7 +486,7 @@ int main(int argc, char **argv) strerror(errno)); exit(EXIT_FAILURE); } - if (ftruncate(fd, 8 * 1024 * 1024) < 0) { + if (ftruncate(fd, FLASH_SIZE) < 0) { int error_code =3D errno; close(fd); unlink(image_path); @@ -226,7 +498,17 @@ int main(int argc, char **argv) =20 qtest_add_abrt_handler(cleanup, NULL); g_test_init(&argc, &argv, NULL); - qtest_add_func("pflash-cfi02", test_flash); + + size_t nb_configurations =3D sizeof configuration / sizeof configurati= on[0]; + for (size_t i =3D 0; i < nb_configurations; ++i) { + const FlashConfig *config =3D &configuration[i]; + char *path =3D g_strdup_printf("pflash-cfi02/%d-%d-%d", + config->bank_width, + config->device_width, + config->max_device_width); + qtest_add_data_func(path, config, test_flash); + g_free(path); + } int result =3D g_test_run(); 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[208.66.210.181]) by smtp.gmail.com with ESMTPSA id c7sm7548700ioc.63.2019.04.26.09.27.08 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 26 Apr 2019 09:27:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oberlin-edu.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=jlDK6aFL3Em4ov4fxxKNW11QOoWrQCpftLnncWbSkrg=; b=bJYS6XgTtUIa6KBpphvjEGqi4Vk66+o0UGgRd1EbRXJYoo+e+tCIMAxFs+g0368hFS K4yZMKJGSMBwnBcJS0XVM96nmQ11tU/dAXMAHuapkWMwlUf69zaSH09HFbhLRVt1frTo F2InqZhANxwx1QlqnQE94heTCdPdCcyfpQpQbZ6WdmUSEQmMyio7egH0jFs7zOV2VF9s kxKfvU3yV+t0s/DOvV9lTYo8FRPyKrJXsnxf6SbWLsSUFhigX+ryq6GKztgDxqIp0y7/ 6GH0CoulkWlZzYE5EAjBI7hyvR/oRxAsl+WlLVrfKtbWx4L3jHdpjiB6WZSJPyvh3HSm TVTA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jlDK6aFL3Em4ov4fxxKNW11QOoWrQCpftLnncWbSkrg=; b=a4QVFvmAQB1stz8woQ9cTQGUz07xo081I9GRlNKCaKDf5v/nmCYhgJ2n76fCbs+seV e/HwmhwLxuGDci6Ju2cQHnv9x0qQpjXxYW5k/P21r8J1L82HO8BoDKZbICLgdswKvjFe Kbj4oXBR5bHODs2mqLwvkPyKbIYjadD2DuttGg9kMy6nXc2paYsIHd0bbrFb+se4Gq0U 7+3JD/uTjtxoNqYWzNB4P5Li2jqkV88jsWlBJzM3FV0gFDWWwLAX9nT2utuDLo34dIaG lgCoY2OG0LYj+MsEIKKKYH1WY/qlZz9YNv10U72qhj47YX51bjHA8qoNphuVihS7PQqf Fqiw== X-Gm-Message-State: APjAAAVRikX6aweOW+DM6f3D7uUk15/B9y0zjE0BImmP/YTq5Lp7kGQT nU596+CXzyYBKjBk/l+h2XaRssi9SG1blg== X-Google-Smtp-Source: APXvYqxq7U3E9NO8QT58aSvgaIBDHygijU6JaUcd2+sAd4Zz80U0VLH9ErC4klXTXa44Ob1XYhdddg== X-Received: by 2002:a05:660c:209:: with SMTP id y9mr9562987itj.31.1556296029683; Fri, 26 Apr 2019 09:27:09 -0700 (PDT) From: Stephen Checkoway To: QEMU Developers , Thomas Huth , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Kevin Wolf , Max Reitz , "open list:Block layer core" , Markus Armbruster , Laszlo Ersek , Laurent Vivier , Paolo Bonzini Date: Fri, 26 Apr 2019 12:26:19 -0400 Message-Id: <20190426162624.55977-6-stephen.checkoway@oberlin.edu> X-Mailer: git-send-email 2.20.1 (Apple Git-117) In-Reply-To: <20190426162624.55977-1-stephen.checkoway@oberlin.edu> References: <20190426162624.55977-1-stephen.checkoway@oberlin.edu> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::141 Subject: [Qemu-devel] [PATCH v4 05/10] block/pflash_cfi02: Implement nonuniform sector sizes X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stephen Checkoway Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Some flash chips support sectors of different sizes. For example, the AMD AM29LV160DT has 31 64 kB sectors, one 32 kB sector, two 8 kB sectors, and a 16 kB sector, in that order. The AM29LV160DB has those in the reverse order. The `num-blocks` and `sector-length` properties work exactly as they did before: a flash device with uniform sector lengths. To get non-uniform sector lengths for up to four regions, the following properties may be set - region 0. `num-blocks0` and `sector-length0`; - region 1. `num-blocks1` and `sector-length1`; - region 2. `num-blocks2` and `sector-length2`; and - region 3. `num-blocks3` and `sector-length3`. If the uniform and nonuniform properties are set, then both must specify a flash device with the same total size. It would be better to disallow both being set, or make `num-blocks0` and `sector-length0` alias `num-blocks` and `sector-length`, but that would make testing currently impossible. Signed-off-by: Stephen Checkoway Acked-by: Thomas Huth --- hw/block/pflash_cfi02.c | 177 +++++++++++++++++++++++++----------- tests/pflash-cfi02-test.c | 185 ++++++++++++++++++++++++++++---------- 2 files changed, 265 insertions(+), 97 deletions(-) diff --git a/hw/block/pflash_cfi02.c b/hw/block/pflash_cfi02.c index 101628b4ec..c4efbe8cdf 100644 --- a/hw/block/pflash_cfi02.c +++ b/hw/block/pflash_cfi02.c @@ -28,7 +28,6 @@ * - unlock bypass command * - CFI queries * - * It does not implement boot blocs with reduced size * It does not implement software data protection as found in many real ch= ips * It does not implement erase suspend/resume commands * It does not implement multiple sectors erase @@ -55,6 +54,13 @@ do { = \ =20 #define PFLASH_LAZY_ROMD_THRESHOLD 42 =20 +/* + * The size of the cfi_table indirectly depends on this and the start of t= he + * PRI table directly depends on it. 4 is the maximum size (and also what + * seems common) without changing the PRT table address. + */ +#define PFLASH_MAX_ERASE_REGIONS 4 + /* Special write cycle for CFI queries. */ #define WCYCLE_CFI 7 =20 @@ -64,8 +70,10 @@ struct PFlashCFI02 { /*< public >*/ =20 BlockBackend *blk; - uint32_t sector_len; - uint32_t nb_blocs; + uint32_t uniform_nb_blocs; + uint32_t uniform_sector_len; + uint32_t nb_blocs[PFLASH_MAX_ERASE_REGIONS]; + uint32_t sector_len[PFLASH_MAX_ERASE_REGIONS]; uint64_t total_len; uint64_t interleave_multiplier; uint8_t mappings; @@ -86,7 +94,7 @@ struct PFlashCFI02 { uint16_t ident3; uint16_t unlock_addr0; uint16_t unlock_addr1; - uint8_t cfi_table[0x52]; + uint8_t cfi_table[0x4D]; QEMUTimer timer; /* The device replicates the flash memory across its memory space. Em= ulate * that by having a container (.mem) filled with an array of aliases @@ -189,6 +197,25 @@ static uint64_t pflash_data_read(PFlashCFI02 *pfl, hwa= ddr offset, return ret; } =20 +/* + * offset should be a byte offset of the QEMU device and _not_ a device + * offset. + */ +static uint32_t pflash_sector_len(PFlashCFI02 *pfl, hwaddr offset) +{ + assert(offset < pfl->total_len); + int nb_regions =3D pfl->cfi_table[0x2C]; + hwaddr addr =3D 0; + for (int i =3D 0; i < nb_regions; ++i) { + uint64_t region_size =3D (uint64_t)pfl->nb_blocs[i] * pfl->sector_= len[i]; + if (addr <=3D offset && offset < addr + region_size) { + return pfl->sector_len[i]; + } + addr +=3D region_size; + } + abort(); +} + static uint64_t pflash_read(void *opaque, hwaddr offset, unsigned int widt= h) { PFlashCFI02 *pfl =3D opaque; @@ -285,6 +312,7 @@ static void pflash_write(void *opaque, hwaddr offset, u= int64_t value, PFlashCFI02 *pfl =3D opaque; uint8_t *p; uint8_t cmd; + uint32_t sector_len; =20 cmd =3D value; if (pfl->cmd !=3D 0xA0) { @@ -446,12 +474,14 @@ static void pflash_write(void *opaque, hwaddr offset,= uint64_t value, case 0x30: /* Sector erase */ p =3D pfl->storage; - offset &=3D ~(pfl->sector_len - 1); - DPRINTF("%s: start sector erase at " TARGET_FMT_plx "\n", __fu= nc__, - offset); + sector_len =3D pflash_sector_len(pfl, offset); + offset &=3D ~(sector_len - 1); + DPRINTF("%s: start sector erase at %0*" PRIx64 "-%0*" PRIx64 "= \n", + __func__, pfl->bank_width * 2, offset, + pfl->bank_width * 2, offset + sector_len - 1); if (!pfl->ro) { - memset(p + offset, 0xFF, pfl->sector_len); - pflash_update(pfl, offset, pfl->sector_len); + memset(p + offset, 0xFF, sector_len); + pflash_update(pfl, offset, sector_len); } set_dq7(pfl, 0x00); /* Let's wait 1/2 second before sector erase is done */ @@ -515,15 +545,14 @@ static const MemoryRegionOps pflash_cfi02_ops =3D { static void pflash_cfi02_realize(DeviceState *dev, Error **errp) { PFlashCFI02 *pfl =3D PFLASH_CFI02(dev); - uint32_t chip_len; int ret; Error *local_err =3D NULL; =20 - if (pfl->sector_len =3D=3D 0) { + if (pfl->uniform_sector_len =3D=3D 0 && pfl->sector_len[0] =3D=3D 0) { error_setg(errp, "attribute \"sector-length\" not specified or zer= o."); return; } - if (pfl->nb_blocs =3D=3D 0) { + if (pfl->uniform_nb_blocs =3D=3D 0 && pfl->nb_blocs[0] =3D=3D 0) { error_setg(errp, "attribute \"num-blocks\" not specified or zero."= ); return; } @@ -619,7 +648,53 @@ static void pflash_cfi02_realize(DeviceState *dev, Err= or **errp) return; } =20 - pfl->total_len =3D pfl->sector_len * pfl->nb_blocs; + int num_devices =3D pfl->bank_width / pfl->device_width; + int nb_regions; + pfl->total_len =3D 0; + for (nb_regions =3D 0; nb_regions < PFLASH_MAX_ERASE_REGIONS; ++nb_reg= ions) { + if (pfl->nb_blocs[nb_regions] =3D=3D 0) { + break; + } + uint64_t sector_len_per_device =3D pfl->sector_len[nb_regions] / + num_devices; + + /* + * The size of each flash sector must be a power of 2 and it must = be + * aligned at the same power of 2. + */ + if (sector_len_per_device & 0xff || + sector_len_per_device >=3D (1 << 24) || + !is_power_of_2(sector_len_per_device)) + { + error_setg(errp, "unsupported configuration: " + "sector length[%d] per device =3D %" PRIx64 ".", + nb_regions, sector_len_per_device); + return; + } + if ((pfl->total_len / num_devices) & (sector_len_per_device - 1)) { + error_setg(errp, "unsupported configuration: " + "flash region %d not correctly aligned.", + nb_regions); + return; + } + + pfl->total_len +=3D (uint64_t)pfl->sector_len[nb_regions] * + pfl->nb_blocs[nb_regions]; + } + + uint64_t uniform_len =3D (uint64_t)pfl->uniform_nb_blocs * + pfl->uniform_sector_len; + if (nb_regions =3D=3D 0) { + nb_regions =3D 1; + pfl->nb_blocs[0] =3D pfl->uniform_nb_blocs; + pfl->sector_len[0] =3D pfl->uniform_sector_len; + pfl->total_len =3D uniform_len; + } else if (uniform_len !=3D 0 && uniform_len !=3D pfl->total_len) { + error_setg(errp, "\"num-blocks\"*\"sector-length\" " + "different from \"num-blocks0\"*\'sector-length0\" + ..= . + " + "\"num-blocks3\"*\"sector-length3\""); + return; + } =20 /* * If the flash is not a power of 2, then the code for handling multip= le @@ -631,18 +706,6 @@ static void pflash_cfi02_realize(DeviceState *dev, Err= or **errp) return; } =20 - int num_devices =3D pfl->bank_width / pfl->device_width; - uint64_t sector_len_per_device =3D pfl->sector_len / num_devices; - uint64_t device_len =3D sector_len_per_device * pfl->nb_blocs; - - if (sector_len_per_device & 0xff || sector_len_per_device >=3D (1 << 2= 4)) { - error_setg(errp, - "unsupported configuration: sector length per device = =3D " - "%" PRIx64 ".", - sector_len_per_device); - return; - } - memory_region_init_rom_device(&pfl->orig_mem, OBJECT(pfl), &pflash_cfi02_ops, pfl, pfl->name, pfl->total_len, &local_err); @@ -650,8 +713,6 @@ static void pflash_cfi02_realize(DeviceState *dev, Erro= r **errp) pfl->unlock_addr0 &=3D 0x7FF; pfl->unlock_addr1 &=3D 0x7FF; =20 - chip_len =3D pfl->sector_len * pfl->nb_blocs; - if (local_err) { error_propagate(errp, local_err); return; @@ -672,8 +733,8 @@ static void pflash_cfi02_realize(DeviceState *dev, Erro= r **errp) } =20 if (pfl->blk) { - if (!blk_check_size_and_read_all(pfl->blk, pfl->storage, chip_len, - errp)) { + if (!blk_check_size_and_read_all(pfl->blk, pfl->storage, + pfl->total_len, errp)) { vmstate_unregister_ram(&pfl->orig_mem, DEVICE(pfl)); return; } @@ -697,7 +758,7 @@ static void pflash_cfi02_realize(DeviceState *dev, Erro= r **errp) pfl->cfi_table[0x13] =3D 0x02; pfl->cfi_table[0x14] =3D 0x00; /* Primary extended table address */ - pfl->cfi_table[0x15] =3D 0x31; + pfl->cfi_table[0x15] =3D 0x40; pfl->cfi_table[0x16] =3D 0x00; /* Alternate command set (none) */ pfl->cfi_table[0x17] =3D 0x00; @@ -730,7 +791,7 @@ static void pflash_cfi02_realize(DeviceState *dev, Erro= r **errp) /* Max timeout for chip erase */ pfl->cfi_table[0x26] =3D 0x0D; /* Device size */ - pfl->cfi_table[0x27] =3D ctz32(device_len); + pfl->cfi_table[0x27] =3D ctz32(pfl->total_len / num_devices); /* Flash device interface */ pfl->cfi_table[0x28] =3D device_interface_code; pfl->cfi_table[0x29] =3D device_interface_code >> 8; @@ -739,37 +800,49 @@ static void pflash_cfi02_realize(DeviceState *dev, Er= ror **errp) /* pfl->cfi_table[0x2A] =3D 0x05; */ pfl->cfi_table[0x2A] =3D 0x00; pfl->cfi_table[0x2B] =3D 0x00; - /* Number of erase block regions (uniform) */ - pfl->cfi_table[0x2C] =3D 0x01; - /* Erase block region 1 */ - pfl->cfi_table[0x2D] =3D pfl->nb_blocs - 1; - pfl->cfi_table[0x2E] =3D (pfl->nb_blocs - 1) >> 8; - pfl->cfi_table[0x2F] =3D sector_len_per_device >> 8; - pfl->cfi_table[0x30] =3D sector_len_per_device >> 16; + /* Number of erase block regions */ + pfl->cfi_table[0x2C] =3D nb_regions; + /* Erase block regions */ + for (int i =3D 0; i < nb_regions; ++i) { + uint32_t sector_len_per_device =3D pfl->sector_len[i] / num_device= s; + pfl->cfi_table[0x2D + 4 * i] =3D pfl->nb_blocs[i] - 1; + pfl->cfi_table[0x2E + 4 * i] =3D (pfl->nb_blocs[i] - 1) >> 8; + pfl->cfi_table[0x2F + 4 * i] =3D sector_len_per_device >> 8; + pfl->cfi_table[0x30 + 4 * i] =3D sector_len_per_device >> 16; + } =20 /* Extended */ - pfl->cfi_table[0x31] =3D 'P'; - pfl->cfi_table[0x32] =3D 'R'; - pfl->cfi_table[0x33] =3D 'I'; + pfl->cfi_table[0x40] =3D 'P'; + pfl->cfi_table[0x41] =3D 'R'; + pfl->cfi_table[0x42] =3D 'I'; =20 - pfl->cfi_table[0x34] =3D '1'; - pfl->cfi_table[0x35] =3D '0'; + pfl->cfi_table[0x43] =3D '1'; /* version 1.0 */ + pfl->cfi_table[0x44] =3D '0'; =20 - pfl->cfi_table[0x36] =3D 0x00; - pfl->cfi_table[0x37] =3D 0x00; - pfl->cfi_table[0x38] =3D 0x00; - pfl->cfi_table[0x39] =3D 0x00; + pfl->cfi_table[0x45] =3D 0x00; /* Address sensitive unlock required. */ + pfl->cfi_table[0x46] =3D 0x00; /* Erase suspend not supported. */ + pfl->cfi_table[0x47] =3D 0x00; /* Sector protect not supported. */ + pfl->cfi_table[0x48] =3D 0x00; /* Temporary sector unprotect not suppo= rted. */ =20 - pfl->cfi_table[0x3a] =3D 0x00; + pfl->cfi_table[0x49] =3D 0x00; /* Sector protect/unprotect scheme. */ =20 - pfl->cfi_table[0x3b] =3D 0x00; - pfl->cfi_table[0x3c] =3D 0x00; + pfl->cfi_table[0x4a] =3D 0x00; /* Simultaneous operation not supported= . */ + pfl->cfi_table[0x4b] =3D 0x00; /* Burst mode not supported. */ + pfl->cfi_table[0x4c] =3D 0x00; /* Page mode not supported. */ } =20 static Property pflash_cfi02_properties[] =3D { DEFINE_PROP_DRIVE("drive", PFlashCFI02, blk), - DEFINE_PROP_UINT32("num-blocks", PFlashCFI02, nb_blocs, 0), - DEFINE_PROP_UINT32("sector-length", PFlashCFI02, sector_len, 0), + DEFINE_PROP_UINT32("num-blocks", PFlashCFI02, uniform_nb_blocs, 0), + DEFINE_PROP_UINT32("sector-length", PFlashCFI02, uniform_sector_len, 0= ), + DEFINE_PROP_UINT32("num-blocks0", PFlashCFI02, nb_blocs[0], 0), + DEFINE_PROP_UINT32("sector-length0", PFlashCFI02, sector_len[0], 0), + DEFINE_PROP_UINT32("num-blocks1", PFlashCFI02, nb_blocs[1], 0), + DEFINE_PROP_UINT32("sector-length1", PFlashCFI02, sector_len[1], 0), + DEFINE_PROP_UINT32("num-blocks2", PFlashCFI02, nb_blocs[2], 0), + DEFINE_PROP_UINT32("sector-length2", PFlashCFI02, sector_len[2], 0), + DEFINE_PROP_UINT32("num-blocks3", PFlashCFI02, nb_blocs[3], 0), + DEFINE_PROP_UINT32("sector-length3", PFlashCFI02, sector_len[3], 0), DEFINE_PROP_UINT8("width", PFlashCFI02, bank_width, 0), DEFINE_PROP_UINT8("device-width", PFlashCFI02, device_width, 0), DEFINE_PROP_UINT8("max-device-width", PFlashCFI02, max_device_width, 0= ), diff --git a/tests/pflash-cfi02-test.c b/tests/pflash-cfi02-test.c index a1be26da73..703f084c5d 100644 --- a/tests/pflash-cfi02-test.c +++ b/tests/pflash-cfi02-test.c @@ -17,9 +17,11 @@ */ =20 #define MP_FLASH_SIZE_MAX (32 * 1024 * 1024) -#define FLASH_SIZE (8 * 1024 * 1024) #define BASE_ADDR (0x100000000ULL - MP_FLASH_SIZE_MAX) =20 +#define UNIFORM_FLASH_SIZE (8 * 1024 * 1024) +#define UNIFORM_FLASH_SECTOR_SIZE (64 * 1024) + /* Use a newtype to keep flash addresses separate from byte addresses. */ typedef struct { uint64_t addr; @@ -42,10 +44,15 @@ typedef struct { #define UNLOCK_BYPASS_RESET_CMD 0x00 =20 typedef struct { + /* Interleave configuration. */ int bank_width; int device_width; int max_device_width; =20 + /* Nonuniform block size. */ + int nb_blocs[4]; + int sector_len[4]; + QTestState *qtest; } FlashConfig; =20 @@ -61,12 +68,22 @@ static FlashConfig expand_config_defaults(const FlashCo= nfig *c) { FlashConfig ret =3D *c; =20 + if (ret.bank_width =3D=3D 0) { + ret.bank_width =3D 2; + } if (ret.device_width =3D=3D 0) { ret.device_width =3D ret.bank_width; } if (ret.max_device_width =3D=3D 0) { ret.max_device_width =3D ret.device_width; } + if (ret.nb_blocs[0] =3D=3D 0 && ret.sector_len[0] =3D=3D 0) { + ret.sector_len[0] =3D UNIFORM_FLASH_SECTOR_SIZE; + ret.nb_blocs[0] =3D UNIFORM_FLASH_SIZE / UNIFORM_FLASH_SECTOR_SIZE; + } + + /* XXX: Limitations of test harness. */ + assert(ret.bank_width =3D=3D 2); return ret; } =20 @@ -158,8 +175,8 @@ static inline uint64_t as_byte_addr(const FlashConfig *= c, faddr flash_addr) * which is bank_width / device_width, and multiply that by the maximum * device width. */ - int num_devices =3D c->bank_width / c->device_width; - return flash_addr.addr * (num_devices * c->max_device_width); + int nb_devices =3D c->bank_width / c->device_width; + return flash_addr.addr * (nb_devices * c->max_device_width); } =20 /* @@ -277,22 +294,52 @@ static bool device_supports_width(uint16_t dic, int w= idth) return true; } =20 -static void test_flash(const void *opaque) +/* + * Test flash commands with a variety of device geometry. + */ +static void test_geometry(const void *opaque) { const FlashConfig *config =3D opaque; QTestState *qtest; qtest =3D qtest_initf("-M musicpal,accel=3Dqtest" " -drive if=3Dpflash,file=3D%s,format=3Draw,copy-o= n-read" + /* Interleave properties. */ " -global driver=3Dcfi.pflash02," "property=3Ddevice-width,value=3D%d" " -global driver=3Dcfi.pflash02," - "property=3Dmax-device-width,value=3D%d", + "property=3Dmax-device-width,value=3D%d" + /* Device geometry properties. */ + " -global driver=3Dcfi.pflash02," + "property=3Dnum-blocks0,value=3D%d" + " -global driver=3Dcfi.pflash02," + "property=3Dsector-length0,value=3D%d" + " -global driver=3Dcfi.pflash02," + "property=3Dnum-blocks1,value=3D%d" + " -global driver=3Dcfi.pflash02," + "property=3Dsector-length1,value=3D%d" + " -global driver=3Dcfi.pflash02," + "property=3Dnum-blocks2,value=3D%d" + " -global driver=3Dcfi.pflash02," + "property=3Dsector-length2,value=3D%d" + " -global driver=3Dcfi.pflash02," + "property=3Dnum-blocks3,value=3D%d" + " -global driver=3Dcfi.pflash02," + "property=3Dsector-length3,value=3D%d", image_path, config->device_width, - config->max_device_width); + config->max_device_width, + config->nb_blocs[0], + config->sector_len[0], + config->nb_blocs[1], + config->sector_len[1], + config->nb_blocs[2], + config->sector_len[2], + config->nb_blocs[3], + config->sector_len[3]); FlashConfig explicit_config =3D expand_config_defaults(config); explicit_config.qtest =3D qtest; const FlashConfig *c =3D &explicit_config; + int nb_devices =3D c->bank_width / c->device_width; =20 /* Check the IDs. */ unlock(c); @@ -317,19 +364,14 @@ static void test_flash(const void *opaque) g_assert_cmpint(flash_query(c, FLASH_ADDR(0x12)), =3D=3D, replicate(c,= 'Y')); =20 /* Num erase regions. */ - g_assert_cmpint(flash_query_1(c, FLASH_ADDR(0x2C)), >=3D, 1); + int nb_erase_regions =3D flash_query_1(c, FLASH_ADDR(0x2C)); + g_assert_cmpint(nb_erase_regions, =3D=3D, + !!c->nb_blocs[0] + !!c->nb_blocs[1] + !!c->nb_blocs[2]= + + !!c->nb_blocs[3]); =20 /* Check device length. */ uint32_t device_len =3D 1 << flash_query_1(c, FLASH_ADDR(0x27)); - g_assert_cmpint(device_len * (c->bank_width / c->device_width), =3D=3D, - FLASH_SIZE); - - /* Check nb_sectors * sector_len is device_len. */ - uint32_t nb_sectors =3D flash_query_1(c, FLASH_ADDR(0x2D)) + - (flash_query_1(c, FLASH_ADDR(0x2E)) << 8) + 1; - uint32_t sector_len =3D (flash_query_1(c, FLASH_ADDR(0x2F)) << 8) + - (flash_query_1(c, FLASH_ADDR(0x30)) << 16); - g_assert_cmpint(nb_sectors * sector_len, =3D=3D, device_len); + g_assert_cmpint(device_len * nb_devices, =3D=3D, UNIFORM_FLASH_SIZE); =20 /* Check the device interface code supports the width and max width. */ uint16_t device_interface_code =3D flash_query_1(c, FLASH_ADDR(0x28)) + @@ -339,32 +381,47 @@ static void test_flash(const void *opaque) g_assert_true(device_supports_width(device_interface_code, c->max_device_width)); reset(c); - const uint64_t dq7 =3D replicate(c, 0x80); const uint64_t dq6 =3D replicate(c, 0x40); - /* Erase and program sector. */ - for (uint32_t i =3D 0; i < nb_sectors; ++i) { - uint64_t byte_addr =3D i * sector_len; - sector_erase(c, byte_addr); - /* Read toggle. */ - uint64_t status0 =3D flash_read(c, byte_addr); - /* DQ7 is 0 during an erase. */ - g_assert_cmpint(status0 & dq7, =3D=3D, 0); - uint64_t status1 =3D flash_read(c, byte_addr); - /* DQ6 toggles during an erase. */ - g_assert_cmpint(status0 & dq6, =3D=3D, ~status1 & dq6); - /* Wait for erase to complete. */ - qtest_clock_step_next(c->qtest); - /* Ensure DQ6 has stopped toggling. */ - g_assert_cmpint(flash_read(c, byte_addr), =3D=3D, flash_read(c, by= te_addr)); - /* Now the data should be valid. */ - g_assert_cmpint(flash_read(c, byte_addr), =3D=3D, bank_mask(c)); =20 - /* Program a bit pattern. */ - program(c, byte_addr, 0x55); - g_assert_cmpint(flash_read(c, byte_addr) & 0xFF, =3D=3D, 0x55); - program(c, byte_addr, 0xA5); - g_assert_cmpint(flash_read(c, byte_addr) & 0xFF, =3D=3D, 0x05); + uint64_t byte_addr =3D 0; + for (int region =3D 0; region < nb_erase_regions; ++region) { + uint64_t base =3D 0x2D + 4 * region; + flash_cmd(c, CFI_ADDR, CFI_CMD); + uint32_t nb_sectors =3D flash_query_1(c, FLASH_ADDR(base + 0)) + + (flash_query_1(c, FLASH_ADDR(base + 1)) << 8= ) + 1; + uint32_t sector_len =3D (flash_query_1(c, FLASH_ADDR(base + 2)) <<= 8) + + (flash_query_1(c, FLASH_ADDR(base + 3)) << 1= 6); + sector_len *=3D nb_devices; + g_assert_cmpint(nb_sectors, =3D=3D, c->nb_blocs[region]); + g_assert_cmpint(sector_len, =3D=3D, c->sector_len[region]); + reset(c); + + /* Erase and program sector. */ + for (uint32_t i =3D 0; i < nb_sectors; ++i) { + sector_erase(c, byte_addr); + /* Read toggle. */ + uint64_t status0 =3D flash_read(c, byte_addr); + /* DQ7 is 0 during an erase. */ + g_assert_cmpint(status0 & dq7, =3D=3D, 0); + uint64_t status1 =3D flash_read(c, byte_addr); + /* DQ6 toggles during an erase. */ + g_assert_cmpint(status0 & dq6, =3D=3D, ~status1 & dq6); + /* Wait for erase to complete. */ + qtest_clock_step_next(c->qtest); + /* Ensure DQ6 has stopped toggling. */ + g_assert_cmpint(flash_read(c, byte_addr), =3D=3D, + flash_read(c, byte_addr)); + /* Now the data should be valid. */ + g_assert_cmpint(flash_read(c, byte_addr), =3D=3D, bank_mask(c)= ); + + /* Program a bit pattern. */ + program(c, byte_addr, 0x55); + g_assert_cmpint(flash_read(c, byte_addr) & 0xFF, =3D=3D, 0x55); + program(c, byte_addr, 0xA5); + g_assert_cmpint(flash_read(c, byte_addr) & 0xFF, =3D=3D, 0x05); + byte_addr +=3D sector_len; + } } =20 /* Erase the chip. */ @@ -382,9 +439,11 @@ static void test_flash(const void *opaque) g_assert_cmpint(flash_read(c, 0), =3D=3D, flash_read(c, 0)); /* Now the data should be valid. */ =20 - for (uint32_t i =3D 0; i < nb_sectors; ++i) { - uint64_t byte_addr =3D i * sector_len; - g_assert_cmpint(flash_read(c, byte_addr), =3D=3D, bank_mask(c)); + for (int region =3D 0; region < nb_erase_regions; ++region) { + for (uint32_t i =3D 0; i < c->nb_blocs[region]; ++i) { + uint64_t byte_addr =3D i * c->sector_len[region]; + g_assert_cmpint(flash_read(c, byte_addr), =3D=3D, bank_mask(c)= ); + } } =20 /* Unlock bypass */ @@ -476,6 +535,32 @@ static const FlashConfig configuration[] =3D { .device_width =3D 1, .max_device_width =3D 4, }, + /* Nonuniform sectors (top boot). */ + { + .bank_width =3D 2, + .nb_blocs =3D { 127, 1, 2, 1 }, + .sector_len =3D { 0x10000, 0x08000, 0x02000, 0x04000 }, + }, + /* Nonuniform sectors (top boot) with two x8 devices. */ + { + .bank_width =3D 2, + .device_width =3D 1, + .nb_blocs =3D { 127, 1, 2, 1 }, + .sector_len =3D { 0x10000, 0x08000, 0x02000, 0x04000 }, + }, + /* Nonuniform sectors (bottom boot). */ + { + .bank_width =3D 2, + .nb_blocs =3D { 1, 2, 1, 127 }, + .sector_len =3D { 0x04000, 0x02000, 0x08000, 0x10000 }, + }, + /* Nonuniform sectors (bottom boot) with two x8 devices. */ + { + .bank_width =3D 2, + .device_width =3D 1, + .nb_blocs =3D { 1, 2, 1, 127 }, + .sector_len =3D { 0x04000, 0x02000, 0x08000, 0x10000 }, + }, }; =20 int main(int argc, char **argv) @@ -486,7 +571,7 @@ int main(int argc, char **argv) strerror(errno)); exit(EXIT_FAILURE); } - if (ftruncate(fd, FLASH_SIZE) < 0) { + if (ftruncate(fd, UNIFORM_FLASH_SIZE) < 0) { int error_code =3D errno; close(fd); unlink(image_path); @@ -502,11 +587,21 @@ int main(int argc, char **argv) size_t nb_configurations =3D sizeof configuration / sizeof configurati= on[0]; for (size_t i =3D 0; i < nb_configurations; ++i) { const FlashConfig *config =3D &configuration[i]; - char *path =3D g_strdup_printf("pflash-cfi02/%d-%d-%d", + char *path =3D g_strdup_printf("pflash-cfi02" + "/geometry/%dx%x-%dx%x-%dx%x-%dx%x" + "/%d-%d-%d", + config->nb_blocs[0], + config->sector_len[0], + config->nb_blocs[1], + config->sector_len[1], + config->nb_blocs[2], + config->sector_len[2], + config->nb_blocs[3], + config->sector_len[3], config->bank_width, config->device_width, config->max_device_width); - qtest_add_data_func(path, config, test_flash); + qtest_add_data_func(path, config, test_geometry); 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[208.66.210.181]) by smtp.gmail.com with ESMTPSA id c7sm7548700ioc.63.2019.04.26.09.27.09 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 26 Apr 2019 09:27:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oberlin-edu.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=sXNPBantsfkNJHGqd1x2CHXS2MLrXNyNJGuBb1+37Bk=; b=O0ZhkdO4kCR2gd5cmgcvpZWeCily9JauPO2Z6f+ztll9NtIYMVMItpzcKviq2bu07X mgLRr7070+3mF5+o0cLdbMXzGY6O1NlMb9heXBfmr1hl8fvJEnGgZ0VDdveGA63SncK6 j63F0fe5eDUC6LNeiNuNJKKjffXrHJCcPAVrCC4BiQmriPmIb7mJDKfWZ7f9ZAzwsFp/ BXN/bZjXeoh41JZs1cyZHvwgLdAMKGSTiyeOiUjiWcV8S+D4sQgZZEXAtSztLcGsrnZn 2EyvFDX7QwKNOgfMNKPcrHnq0tzBW8wSc9O6IY0vXxCpQB6+DI+P01jJE3hLeIQWuiD5 42SA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=sXNPBantsfkNJHGqd1x2CHXS2MLrXNyNJGuBb1+37Bk=; b=nJydJ+6b5Je/NfQN26zYB7z7HZjSvXQ85oPlsirZ0rPKxL6QELNb/mW71FnVy0lq+R YnpStbGUha5jFzr8fhcVfo6kyLg/B0ZhIJwTEO81l7nGyJZyRLVaRlXJ07EXgQ4xZ/+v Os894EdFwmSC1z3zpEh8KIym2oXuF36y0DPMsIkZaQNSB++LFF2eZENNYd3wTTA+VCAy WfGuHrmMZWkGRq9wj/n5cJl6Q5HI5BT7ihEZHs9ErO//zCIfJEhONl/VUJ5xThl2rh0w iVnUVbT0PlDqxTtzbOTZ1qWxhtYqJ9Tqqk0pes1W2wR7AdQZ1pF3eXOCnpXOMWvwJXbm 4H+A== X-Gm-Message-State: APjAAAWFqUUJyEBzkkiBRImuCJVJMyvvBnbWV+UAVx7xrg6pivdSlKi7 4Pj7Q5mHdVP4oyiH4VEQEGi2l6DIPL2/MQ== X-Google-Smtp-Source: APXvYqzOppszHgJITBZKjAUkTmZLUfyGu8SFFL0e1xrhZHjZ5OyASkjpZpW1J6k859dIYnxa4TkIYA== X-Received: by 2002:a5d:9b02:: with SMTP id y2mr2047560ion.238.1556296030890; Fri, 26 Apr 2019 09:27:10 -0700 (PDT) From: Stephen Checkoway To: QEMU Developers , Thomas Huth , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Kevin Wolf , Max Reitz , "open list:Block layer core" , Markus Armbruster , Laszlo Ersek , Laurent Vivier , Paolo Bonzini Date: Fri, 26 Apr 2019 12:26:20 -0400 Message-Id: <20190426162624.55977-7-stephen.checkoway@oberlin.edu> X-Mailer: git-send-email 2.20.1 (Apple Git-117) In-Reply-To: <20190426162624.55977-1-stephen.checkoway@oberlin.edu> References: <20190426162624.55977-1-stephen.checkoway@oberlin.edu> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::d30 Subject: [Qemu-devel] [PATCH v4 06/10] block/pflash_cfi02: Fix CFI in autoselect mode X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stephen Checkoway Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" After a flash device enters CFI mode from autoselect mode, the reset command returns the device to autoselect mode. An additional reset command is necessary to return to read array mode. Signed-off-by: Stephen Checkoway Acked-by: Thomas Huth --- hw/block/pflash_cfi02.c | 21 +++++++++++++++++---- tests/pflash-cfi02-test.c | 39 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 56 insertions(+), 4 deletions(-) diff --git a/hw/block/pflash_cfi02.c b/hw/block/pflash_cfi02.c index c4efbe8cdf..be10036886 100644 --- a/hw/block/pflash_cfi02.c +++ b/hw/block/pflash_cfi02.c @@ -61,8 +61,9 @@ do { = \ */ #define PFLASH_MAX_ERASE_REGIONS 4 =20 -/* Special write cycle for CFI queries. */ +/* Special write cycles for CFI queries. */ #define WCYCLE_CFI 7 +#define WCYCLE_AUTOSELECT_CFI 8 =20 struct PFlashCFI02 { /*< private >*/ @@ -325,6 +326,12 @@ static void pflash_write(void *opaque, hwaddr offset, = uint64_t value, } =20 if (cmd =3D=3D 0xF0) { + if (pfl->wcycle =3D=3D WCYCLE_AUTOSELECT_CFI) { + /* Return to autoselect mode. */ + pfl->wcycle =3D 3; + pfl->cmd =3D 0x90; + return; + } goto reset_flash; } } @@ -350,7 +357,6 @@ static void pflash_write(void *opaque, hwaddr offset, u= int64_t value, /* We're in read mode */ check_unlock0: if (masked_addr =3D=3D 0x55 && cmd =3D=3D 0x98) { - enter_CFI_mode: /* Enter CFI query mode */ pfl->wcycle =3D WCYCLE_CFI; pfl->cmd =3D 0x98; @@ -427,9 +433,15 @@ static void pflash_write(void *opaque, hwaddr offset, = uint64_t value, /* Unlock bypass reset */ goto reset_flash; } - /* We can enter CFI query mode from autoselect mode */ + /* + * We can enter CFI query mode from autoselect mode, but we mu= st + * return to autoselect mode after a reset. + */ if (masked_addr =3D=3D 0x55 && cmd =3D=3D 0x98) { - goto enter_CFI_mode; + /* Enter autoselect CFI query mode */ + pfl->wcycle =3D WCYCLE_AUTOSELECT_CFI; + pfl->cmd =3D 0x98; + return; } /* No break here */ default: @@ -510,6 +522,7 @@ static void pflash_write(void *opaque, hwaddr offset, u= int64_t value, } break; case WCYCLE_CFI: /* Special value for CFI queries */ + case WCYCLE_AUTOSELECT_CFI: DPRINTF("%s: invalid write in CFI query mode\n", __func__); goto reset_flash; default: diff --git a/tests/pflash-cfi02-test.c b/tests/pflash-cfi02-test.c index 703f084c5d..c2798bbb36 100644 --- a/tests/pflash-cfi02-test.c +++ b/tests/pflash-cfi02-test.c @@ -477,6 +477,42 @@ static void test_geometry(const void *opaque) qtest_quit(qtest); } =20 +/* + * Test that + * 1. enter autoselect mode; + * 2. enter CFI mode; and then + * 3. exit CFI mode + * leaves the flash device in autoselect mode. + */ +static void test_cfi_in_autoselect(const void *opaque) +{ + const FlashConfig *config =3D opaque; + QTestState *qtest; + qtest =3D qtest_initf("-M musicpal,accel=3Dqtest" + " -drive if=3Dpflash,file=3D%s,format=3Draw,copy-o= n-read", + image_path); + FlashConfig explicit_config =3D expand_config_defaults(config); + explicit_config.qtest =3D qtest; + const FlashConfig *c =3D &explicit_config; + + /* 1. Enter autoselect. */ + unlock(c); + flash_cmd(c, UNLOCK0_ADDR, AUTOSELECT_CMD); + g_assert_cmpint(flash_query(c, FLASH_ADDR(0)), =3D=3D, replicate(c, 0x= BF)); + + /* 2. Enter CFI. */ + flash_cmd(c, CFI_ADDR, CFI_CMD); + g_assert_cmpint(flash_query(c, FLASH_ADDR(0x10)), =3D=3D, replicate(c,= 'Q')); + g_assert_cmpint(flash_query(c, FLASH_ADDR(0x11)), =3D=3D, replicate(c,= 'R')); + g_assert_cmpint(flash_query(c, FLASH_ADDR(0x12)), =3D=3D, replicate(c,= 'Y')); + + /* 3. Exit CFI. */ + reset(c); + g_assert_cmpint(flash_query(c, FLASH_ADDR(0)), =3D=3D, replicate(c, 0x= BF)); + + qtest_quit(qtest); +} + static void cleanup(void *opaque) { unlink(image_path); @@ -604,6 +640,9 @@ int main(int argc, char **argv) qtest_add_data_func(path, config, test_geometry); g_free(path); } + + qtest_add_data_func("pflash-cfi02/cfi-in-autoselect", &configuration[0= ], + test_cfi_in_autoselect); int result =3D g_test_run(); cleanup(NULL); return result; --=20 2.20.1 (Apple Git-117) From nobody Mon Feb 9 11:35:11 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1556296181; cv=none; d=zoho.com; s=zohoarc; b=N8oqUJ5aoe9y15czm0jtSH4RbeOr9yHitA4f7uUNXaefm/wI021XJHQv2KBMz7lkp7AqiwRJ+W0KIZJzaYW/QUwpB+hyYqPUtwVxhhmsG8Kb4eY/h3lht7SfwQj5KD/zmhRQPts3Rw5aiZV86TKoC2iK/LtFvq5mWNPAVNesm5w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1556296181; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=lnIQMa985gJdik6sa+sHszvNo6LvfSu/P2J8+RNmRRI=; b=eY3s3vGZLC3wLvGvUd0Jg08R9h4U9FMsogJUeMs3UMmt8tp0LiNB4zeMEIwnzjiWgEUajt6fx6LVd/wdjyc1TZgPrwQpeJAKsZ3tc9kC1DOKfEfKsvjhXHzvU4LToKwO5lyv20Fk0xXabfdyXcIVzdkIkYlwda2FleuCIe5Aops= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1556296180995365.401393610362; Fri, 26 Apr 2019 09:29:40 -0700 (PDT) Received: from localhost ([127.0.0.1]:49298 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hK3jF-0005dC-QT for importer@patchew.org; Fri, 26 Apr 2019 12:29:37 -0400 Received: from eggs.gnu.org ([209.51.188.92]:33990) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hK3h4-0004Dk-09 for qemu-devel@nongnu.org; Fri, 26 Apr 2019 12:27:22 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hK3h0-000105-9O for qemu-devel@nongnu.org; Fri, 26 Apr 2019 12:27:20 -0400 Received: from mail-it1-x142.google.com ([2607:f8b0:4864:20::142]:54755) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hK3gy-0000xU-AC for qemu-devel@nongnu.org; Fri, 26 Apr 2019 12:27:16 -0400 Received: by mail-it1-x142.google.com with SMTP id a190so6785122ite.4 for ; Fri, 26 Apr 2019 09:27:12 -0700 (PDT) Received: from worksec.oberlin.net (ip-210-181.oberlin.net. [208.66.210.181]) by smtp.gmail.com with ESMTPSA id c7sm7548700ioc.63.2019.04.26.09.27.11 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 26 Apr 2019 09:27:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oberlin-edu.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=lnIQMa985gJdik6sa+sHszvNo6LvfSu/P2J8+RNmRRI=; b=Nlfdf4SoJDlgU9ZiXcWSjZ/8czDC66M4qABzfPAW0PWIGD6P5VUh8JaMvGz6SHl3DZ ko+GOWzLQMfYU/UOS8ZhHmIr4nHQbh1MsaJU6pjfpAA/enyyLnB6YnymXvIzrpnee4rg zndHHtua5uXVWIzFp6sqQIAjyY1A1pASgP/oR0YeQl6NoaCcAPIa+z76QQ6SoB+Iv7y3 gJaph/HC9j2upmmnle/jbbs3XX7Kp9TPATOguF4jyfLG4ehi+xr/jPOcv4JKy+KWSolI 3eVhKrQuTNOYDKzEhMX4bzgzOzf4RCLth++V4Rsrze0bypa6C3CXYnnAOt44AAqHYlte 6y0A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lnIQMa985gJdik6sa+sHszvNo6LvfSu/P2J8+RNmRRI=; b=pfJJyYqtaCDhPtILitNHAwuK97clZBbDT3LrfHyP8kfkyNB7rSXjZPmL3UEkVTWk3Y vz3rIusoLBOqQESqGPOWI2K8Ugsf99JvSonkfmasrevppXboO6ToanziuUqT1GFckI7k +w4/iveuGO8Qnm3n/g/dQu0pneGhjzQgxafZZHH0k+zyJUTWO5BCBN/UEmOcaVChuIxA m5sr3XGkW2+ePlESTIMoKqhs3HKBgcGyBiBzhNEDe+Z2eOGoFT46jJKK6urQLQ35qbbQ M3XXflAhuyJi1MV2G0cJsw3IDbMlbOT7htrPhPxCfyOAnKKJWMJcOi0PMlwE5T20nmlN WNvw== X-Gm-Message-State: APjAAAW+iMe2UCt5XD4tZ59pbskGqPuHNmxwV6fhxXw40LSWXlcrJpoy SvulLtIGFC6JGHKwbDcPqN5lmQi3HSA5QQ== X-Google-Smtp-Source: APXvYqxqaI0mY7AlRXbj8xyN+OUvIkgFbcifUaMGSHkCek8FxKWLgeJOcB0SClS2E8c3jbEy73aNQw== X-Received: by 2002:a24:25cf:: with SMTP id g198mr8920622itg.141.1556296032294; Fri, 26 Apr 2019 09:27:12 -0700 (PDT) From: Stephen Checkoway To: QEMU Developers , Thomas Huth , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Kevin Wolf , Max Reitz , "open list:Block layer core" , Markus Armbruster , Laszlo Ersek , Laurent Vivier , Paolo Bonzini Date: Fri, 26 Apr 2019 12:26:21 -0400 Message-Id: <20190426162624.55977-8-stephen.checkoway@oberlin.edu> X-Mailer: git-send-email 2.20.1 (Apple Git-117) In-Reply-To: <20190426162624.55977-1-stephen.checkoway@oberlin.edu> References: <20190426162624.55977-1-stephen.checkoway@oberlin.edu> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::142 Subject: [Qemu-devel] [PATCH v4 07/10] block/pflash_cfi02: Fix reset command not ignored during erase X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stephen Checkoway Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" When the flash device is performing a chip erase, all commands are ignored. When it is performing a sector erase, only the erase suspend command is valid, which is currently not supported. In particular, the reset command should not cause the device to reset to read array mode while programming is on going. Signed-off-by: Stephen Checkoway --- hw/block/pflash_cfi02.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/block/pflash_cfi02.c b/hw/block/pflash_cfi02.c index be10036886..cb1160eb35 100644 --- a/hw/block/pflash_cfi02.c +++ b/hw/block/pflash_cfi02.c @@ -325,7 +325,8 @@ static void pflash_write(void *opaque, hwaddr offset, u= int64_t value, pfl->bank_width * 2, value); } =20 - if (cmd =3D=3D 0xF0) { + /* Reset does nothing during chip erase and sector erase. */ + if (cmd =3D=3D 0xF0 && pfl->cmd !=3D 0x10 && pfl->cmd !=3D 0x30) { if (pfl->wcycle =3D=3D WCYCLE_AUTOSELECT_CFI) { /* Return to autoselect mode. */ pfl->wcycle =3D 3; --=20 2.20.1 (Apple Git-117) From nobody Mon Feb 9 11:35:11 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1556296568; cv=none; d=zoho.com; s=zohoarc; b=bWFA9VvejFf9T+ImtipsO4yKjus2Aw+YhZjt0iphF1AOWOfnR5INubwnaJUB+d5+YD33+DAnsVNxwgJIQwgsqxYmnUe1t/TXZ4Dmx8RU0RYtXxCJFJgSjXlLkQZn4zSqKaTb2ZfV49wi8lHO98f8sX2MHtP7vwNRSHd60COw5N4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1556296568; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=8SFi3qB3aJ0FGRNSlQB9vIIAiPOLAkGzq+Kg6xm/nFM=; b=PNU/Oc31SwDxVBl0atyv5byu7rL+vEzdMWVIST9PhZvX5hIdZWGhfN6rAwUHpb9tUVjZ+mavTYlC5xaW5iIzAN2NbnUWR4+SIghZ6c+QERnW/OHvYwBfwH6mj2Psbu+d/KZk5M7dcQP1lYA/rQ44S8x/PL4d7MBpyGWKWnADMwc= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1556296568439622.9318536493081; Fri, 26 Apr 2019 09:36:08 -0700 (PDT) Received: from localhost ([127.0.0.1]:49434 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hK3pX-0002tj-Av for importer@patchew.org; Fri, 26 Apr 2019 12:36:07 -0400 Received: from eggs.gnu.org ([209.51.188.92]:34061) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hK3h6-0004GK-4A for qemu-devel@nongnu.org; Fri, 26 Apr 2019 12:27:26 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hK3h4-00012t-30 for qemu-devel@nongnu.org; Fri, 26 Apr 2019 12:27:24 -0400 Received: from mail-it1-x143.google.com ([2607:f8b0:4864:20::143]:51213) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hK3h0-0000y9-7j for qemu-devel@nongnu.org; Fri, 26 Apr 2019 12:27:20 -0400 Received: by mail-it1-x143.google.com with SMTP id s3so6812553itk.1 for ; Fri, 26 Apr 2019 09:27:14 -0700 (PDT) Received: from worksec.oberlin.net (ip-210-181.oberlin.net. [208.66.210.181]) by smtp.gmail.com with ESMTPSA id c7sm7548700ioc.63.2019.04.26.09.27.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 26 Apr 2019 09:27:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oberlin-edu.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8SFi3qB3aJ0FGRNSlQB9vIIAiPOLAkGzq+Kg6xm/nFM=; b=slv/DIrkkstlNEdAEPXoCrnZLpuLl6eROkmjkr7qXV3n3DyVxjubfnyeAP4tHRE0KV 2fETb8KQt7K/8JozMA3QDteHcTMJ7E3o/ETSNgaTgROmO/+7d/0GywE3OgKADvOP+St4 nHXQfPC4gfT8nzGFBrNJ0u3QSo78EO9sQpdaMF8I3lGSZxDD5B4mKzfs243Bx8gUqC+p clYuRZztpPklSlLrjXf55/nigxXvNuCHdLUOm8jlbEK9/YtVfHUUTWR1uRcq19xJEGEd gihUaPiij2+v/g59vnwARXTM2GpEE+egeTy+UFuEHbUsDleVu7yqptPjklaj5SM/VXp6 pqKQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8SFi3qB3aJ0FGRNSlQB9vIIAiPOLAkGzq+Kg6xm/nFM=; b=r934WfUZZUoCYEYK2PBonVJHutY69gXAqfsZgW1W91WQCv/HfymZrE93zcLNX+iq5w h3QjhFRE++bhIz5q1ZtYHj6xSMnO59sy+8vLd3PpJS/PFF6eD/GSoFXqtjTBtbCH1esX xA5DUrDC6douSHJ9bxd5lk8RYVg17EZ7XBPdeiKXkOLplLkcWxostpaoBLIVk11O3Tjb So2//qKCYkRhC7IQrS8306eVFuYC1SinAUJhpr1qf65oBKuamcagUidBMIRBHZr8ABEz QmyD8FDxCaivjv29GTm73mU3MB4oUK2GSVnBcaLYdNQ4NGGbmAL/bRuOLH74HvgjiPHu DVLQ== X-Gm-Message-State: APjAAAU0iL5A6qLJmD7BvSiUovGhpOjV8pNlepIaJOs9c66p3/wZ5w+l mVsPJmNyTuEc380V8evkaLuT+jnjMVu70w== X-Google-Smtp-Source: APXvYqyYuxgkEkjktVqvbekPhIxZSaK+hWYu+bmegf+75LXuv2evRCw0ACfIEqEYLkIzqiWbGqK1hQ== X-Received: by 2002:a24:c2c1:: with SMTP id i184mr9265147itg.82.1556296033532; Fri, 26 Apr 2019 09:27:13 -0700 (PDT) From: Stephen Checkoway To: QEMU Developers , Thomas Huth , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Kevin Wolf , Max Reitz , "open list:Block layer core" , Markus Armbruster , Laszlo Ersek , Laurent Vivier , Paolo Bonzini Date: Fri, 26 Apr 2019 12:26:22 -0400 Message-Id: <20190426162624.55977-9-stephen.checkoway@oberlin.edu> X-Mailer: git-send-email 2.20.1 (Apple Git-117) In-Reply-To: <20190426162624.55977-1-stephen.checkoway@oberlin.edu> References: <20190426162624.55977-1-stephen.checkoway@oberlin.edu> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::143 Subject: [Qemu-devel] [PATCH v4 08/10] block/pflash_cfi02: Implement multi-sector erase X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stephen Checkoway Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" After two unlock cycles and a sector erase command, the AMD flash chips start a 50 us erase time out. Any additional sector erase commands add a sector to be erased and restart the 50 us timeout. During the timeout, status bit DQ3 is cleared. After the time out, DQ3 is asserted during erasure. Signed-off-by: Stephen Checkoway Acked-by: Thomas Huth --- hw/block/pflash_cfi02.c | 94 +++++++++++++++++++++++++++++++-------- tests/pflash-cfi02-test.c | 59 ++++++++++++++++++++++-- 2 files changed, 131 insertions(+), 22 deletions(-) diff --git a/hw/block/pflash_cfi02.c b/hw/block/pflash_cfi02.c index cb1160eb35..21ceb0823b 100644 --- a/hw/block/pflash_cfi02.c +++ b/hw/block/pflash_cfi02.c @@ -30,7 +30,6 @@ * * It does not implement software data protection as found in many real ch= ips * It does not implement erase suspend/resume commands - * It does not implement multiple sectors erase */ =20 #include "qemu/osdep.h" @@ -106,6 +105,7 @@ struct PFlashCFI02 { MemoryRegion orig_mem; int rom_mode; int read_counter; /* used for lazy switch-back to rom mode */ + int sectors_to_erase; char *name; void *storage; }; @@ -136,6 +136,22 @@ static inline void toggle_dq6(PFlashCFI02 *pfl) pfl->status ^=3D pfl->interleave_multiplier * 0x40; } =20 +/* + * Turn on DQ3. + */ +static inline void assert_dq3(PFlashCFI02 *pfl) +{ + pfl->status |=3D pfl->interleave_multiplier * 0x08; +} + +/* + * Turn off DQ3. + */ +static inline void reset_dq3(PFlashCFI02 *pfl) +{ + pfl->status &=3D ~(pfl->interleave_multiplier * 0x08); +} + /* * Set up replicated mappings of the same region. */ @@ -159,11 +175,37 @@ static void pflash_register_memory(PFlashCFI02 *pfl, = int rom_mode) pfl->rom_mode =3D rom_mode; } =20 -static void pflash_timer (void *opaque) +static void pflash_timer(void *opaque) { PFlashCFI02 *pfl =3D opaque; =20 trace_pflash_timer_expired(pfl->cmd); + if (pfl->cmd =3D=3D 0x30) { + /* + * Sector erase. If DQ3 is 0 when the timer expires, then the 50 + * us erase timeout has expired so we need to start the timer for = the + * sector erase algorithm. Otherwise, the erase completed and we s= hould + * go back to read array mode. + */ + if ((pfl->status & 0x08) =3D=3D 0) { + assert_dq3(pfl); + /* + * CFI address 0x21 is "Typical timeout per individual block e= rase + * 2^N ms" + */ + uint64_t timeout =3D ((1ULL << pfl->cfi_table[0x21]) * + pfl->sectors_to_erase) * 1000000; + timer_mod(&pfl->timer, + qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + timeout); + DPRINTF("%s: erase timeout fired; erasing %d sectors\n", + __func__, pfl->sectors_to_erase); + return; + } + DPRINTF("%s: sector erase complete\n", __func__); + pfl->sectors_to_erase =3D 0; + reset_dq3(pfl); + } + /* Reset flash */ toggle_dq7(pfl); if (pfl->bypass) { @@ -307,13 +349,30 @@ static void pflash_update(PFlashCFI02 *pfl, int offse= t, int size) } } =20 +static void pflash_sector_erase(PFlashCFI02 *pfl, hwaddr offset) +{ + uint64_t sector_len =3D pflash_sector_len(pfl, offset); + offset &=3D ~(sector_len - 1); + DPRINTF("%s: start sector erase at %0*" PRIx64 "-%0*" PRIx64 "\n", + __func__, pfl->bank_width * 2, offset, + pfl->bank_width * 2, offset + sector_len - 1); + if (!pfl->ro) { + uint8_t *p =3D pfl->storage; + memset(p + offset, 0xFF, sector_len); + pflash_update(pfl, offset, sector_len); + } + set_dq7(pfl, 0x00); + ++pfl->sectors_to_erase; + /* Set (or reset) the 50 us timer for additional erase commands. */ + timer_mod(&pfl->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 50000); +} + static void pflash_write(void *opaque, hwaddr offset, uint64_t value, unsigned int width) { PFlashCFI02 *pfl =3D opaque; uint8_t *p; uint8_t cmd; - uint32_t sector_len; =20 cmd =3D value; if (pfl->cmd !=3D 0xA0) { @@ -486,20 +545,7 @@ static void pflash_write(void *opaque, hwaddr offset, = uint64_t value, break; case 0x30: /* Sector erase */ - p =3D pfl->storage; - sector_len =3D pflash_sector_len(pfl, offset); - offset &=3D ~(sector_len - 1); - DPRINTF("%s: start sector erase at %0*" PRIx64 "-%0*" PRIx64 "= \n", - __func__, pfl->bank_width * 2, offset, - pfl->bank_width * 2, offset + sector_len - 1); - if (!pfl->ro) { - memset(p + offset, 0xFF, sector_len); - pflash_update(pfl, offset, sector_len); - } - set_dq7(pfl, 0x00); - /* Let's wait 1/2 second before sector erase is done */ - timer_mod(&pfl->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + - (NANOSECONDS_PER_SECOND / 2)); + pflash_sector_erase(pfl, offset); break; default: DPRINTF("%s: invalid command %02x (wc 5)\n", __func__, cmd); @@ -513,7 +559,19 @@ static void pflash_write(void *opaque, hwaddr offset, = uint64_t value, /* Ignore writes during chip erase */ return; case 0x30: - /* Ignore writes during sector erase */ + /* + * If DQ3 is 0, additional sector erase commands can be + * written and anything else (other than an erase suspend) res= ets + * the device. + */ + if ((pfl->status & 0x08) =3D=3D 0) { + if (cmd =3D=3D 0x30) { + pflash_sector_erase(pfl, offset); + } else { + goto reset_flash; + } + } + /* Ignore writes during the actual erase. */ return; default: /* Should never happen */ diff --git a/tests/pflash-cfi02-test.c b/tests/pflash-cfi02-test.c index c2798bbb36..0384593792 100644 --- a/tests/pflash-cfi02-test.c +++ b/tests/pflash-cfi02-test.c @@ -35,6 +35,7 @@ typedef struct { #define CFI_CMD 0x98 #define UNLOCK0_CMD 0xAA #define UNLOCK1_CMD 0x55 +#define SECOND_UNLOCK_CMD 0x80 #define AUTOSELECT_CMD 0x90 #define RESET_CMD 0xF0 #define PROGRAM_CMD 0xA0 @@ -222,7 +223,7 @@ static void reset(const FlashConfig *c) static void sector_erase(const FlashConfig *c, uint64_t byte_addr) { unlock(c); - flash_cmd(c, UNLOCK0_ADDR, 0x80); + flash_cmd(c, UNLOCK0_ADDR, SECOND_UNLOCK_CMD); unlock(c); flash_write(c, byte_addr, replicate(c, SECTOR_ERASE_CMD)); } @@ -261,7 +262,7 @@ static void program(const FlashConfig *c, uint64_t byte= _addr, uint16_t data) static void chip_erase(const FlashConfig *c) { unlock(c); - flash_cmd(c, UNLOCK0_ADDR, 0x80); + flash_cmd(c, UNLOCK0_ADDR, SECOND_UNLOCK_CMD); unlock(c); flash_cmd(c, UNLOCK0_ADDR, CHIP_ERASE_CMD); } @@ -383,6 +384,7 @@ static void test_geometry(const void *opaque) reset(c); const uint64_t dq7 =3D replicate(c, 0x80); const uint64_t dq6 =3D replicate(c, 0x40); + const uint64_t dq3 =3D replicate(c, 0x08); =20 uint64_t byte_addr =3D 0; for (int region =3D 0; region < nb_erase_regions; ++region) { @@ -400,18 +402,29 @@ static void test_geometry(const void *opaque) /* Erase and program sector. */ for (uint32_t i =3D 0; i < nb_sectors; ++i) { sector_erase(c, byte_addr); - /* Read toggle. */ + + /* Check that DQ3 is 0. */ + g_assert_cmpint(flash_read(c, byte_addr) & dq3, =3D=3D, 0); + qtest_clock_step_next(c->qtest); /* Step over the 50 us timeou= t. */ + + /* Check that DQ3 is 1. */ uint64_t status0 =3D flash_read(c, byte_addr); + g_assert_cmpint(status0 & dq3, =3D=3D, dq3); + /* DQ7 is 0 during an erase. */ g_assert_cmpint(status0 & dq7, =3D=3D, 0); uint64_t status1 =3D flash_read(c, byte_addr); + /* DQ6 toggles during an erase. */ g_assert_cmpint(status0 & dq6, =3D=3D, ~status1 & dq6); + /* Wait for erase to complete. */ - qtest_clock_step_next(c->qtest); + wait_for_completion(c, byte_addr); + /* Ensure DQ6 has stopped toggling. */ g_assert_cmpint(flash_read(c, byte_addr), =3D=3D, flash_read(c, byte_addr)); + /* Now the data should be valid. */ g_assert_cmpint(flash_read(c, byte_addr), =3D=3D, bank_mask(c)= ); =20 @@ -474,6 +487,44 @@ static void test_geometry(const void *opaque) g_assert_cmpint(flash_query(c, FLASH_ADDR(0)), =3D=3D, replicate(c, 0x= BF)); reset(c); =20 + /* + * Program a word on each sector, erase one or two sectors per region,= and + * verify that all of those, and only those, are erased. + */ + byte_addr =3D 0; + for (int region =3D 0; region < nb_erase_regions; ++region) { + for (int i =3D 0; i < config->nb_blocs[region]; ++i) { + program(c, byte_addr, 0); + byte_addr +=3D config->sector_len[region]; + } + } + unlock(c); + flash_cmd(c, UNLOCK0_ADDR, SECOND_UNLOCK_CMD); + unlock(c); + byte_addr =3D 0; + const uint64_t erase_cmd =3D replicate(c, SECTOR_ERASE_CMD); + for (int region =3D 0; region < nb_erase_regions; ++region) { + flash_write(c, byte_addr, erase_cmd); + if (c->nb_blocs[region] > 1) { + flash_write(c, byte_addr + c->sector_len[region], erase_cmd); + } + byte_addr +=3D c->sector_len[region] * c->nb_blocs[region]; + } + + qtest_clock_step_next(c->qtest); /* Step over the 50 us timeout. */ + wait_for_completion(c, 0); + byte_addr =3D 0; + for (int region =3D 0; region < nb_erase_regions; ++region) { + for (int i =3D 0; i < config->nb_blocs[region]; ++i) { + if (i < 2) { + g_assert_cmpint(flash_read(c, byte_addr), =3D=3D, bank_mas= k(c)); + } else { + g_assert_cmpint(flash_read(c, byte_addr), =3D=3D, 0); + } + byte_addr +=3D config->sector_len[region]; + } + } + qtest_quit(qtest); } =20 --=20 2.20.1 (Apple Git-117) From nobody Mon Feb 9 11:35:11 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1556296742; cv=none; d=zoho.com; s=zohoarc; b=KoGnIB84ZqCCkDqrLm0euK68AxEUNs1Xv2SaPjP5gwLuuxwfinX8SxnWlATVT9EfA1Rd0ntBmjaliGOBjTxFJa3FSelQafHxcERRqOgB1ct9iwywcIcfZpzaCAUwdx3RcnHKqe9vGti93quxjBOtoH45dFTOP1eBEy8x10HXCSg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1556296742; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; 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[208.66.210.181]) by smtp.gmail.com with ESMTPSA id c7sm7548700ioc.63.2019.04.26.09.27.13 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 26 Apr 2019 09:27:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oberlin-edu.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=dx8hoKvL8B1bCipDJo9GnMrAGumkWeneXZIyMDuY6mk=; b=xhWSCjB18RKo4jwYZvJqUdsB8WGIhHQhTx+rWMDEp26hzYMSA9m4mBN4uHqsILKjEl hgXmv0wE7egy/U6I8WOSmOFt2gWajVrIZFihMVO8IwmcxsD6JaTQ8rFB5RSQP1mXnYsh pPTPHgKKyhDX2crAEjKpm4kMS5buwdqu1ewfLjEvxLH/2vIMB9LJTS+PX9CL0bf15DGr zxswmtASkXMvMhEcMb1Od6ILtkfdSfp2+7SaOoRv0m5mn65rmu/VbTbZ0155W0D4iO3s i/z7/MtqM8KUIh1cfpcgGxyUwEQdu+JK+iCR0+xUL5SUfUlhI19ViZ8LOzB0fJBlv7w7 GyTQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=dx8hoKvL8B1bCipDJo9GnMrAGumkWeneXZIyMDuY6mk=; b=fFryf+SSZql0oFnq9yhhOlOnxSJNwUxKhbOE2FPGD3kihPs5w/vBCHfrnB1OE5pj/W oxloqFqHG0gXIar+zLViAm3wlI7f6jZLzfBIjs9z5edRzGRE8pATl89UD/+Fg/d7qhQ4 SR71Ao+wbRnCcsdkhG833IJXlDQ86WewXWcyewZADX4hzb3YwhC4Snt0fhgRCu5Q/69z QJ8RAoepTEZXmx+gxtsWdFOIKUfYN/5J3O/FcfZ2GTPl3qBy4OWPNh+zEWBYuBE6lD8Y 6aOSxZ6nQWL7tnfmYSJjClbMVNKFlBAg0xvne9ndpd7BubN2eDUt9/lF3Swu6HPVpCTc pVfA== X-Gm-Message-State: APjAAAVFtmV0pHAJyTPPVPdNvykVo+QYJrCIir+8DDpiWSGxHdlNDIZH e7rsViXPyJ+nuUKUiAJfr7Blo+qWpoqizQ== X-Google-Smtp-Source: APXvYqxo7/h0pFFzhiLvIh9/xuZqMXCrCh+8XHx5Ju0OrnMXsktTDWbZvECx0WoOLotMT7Q+oswPkw== X-Received: by 2002:a24:df02:: with SMTP id r2mr9978017itg.104.1556296034782; Fri, 26 Apr 2019 09:27:14 -0700 (PDT) From: Stephen Checkoway To: QEMU Developers , Thomas Huth , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Kevin Wolf , Max Reitz , "open list:Block layer core" , Markus Armbruster , Laszlo Ersek , Laurent Vivier , Paolo Bonzini Date: Fri, 26 Apr 2019 12:26:23 -0400 Message-Id: <20190426162624.55977-10-stephen.checkoway@oberlin.edu> X-Mailer: git-send-email 2.20.1 (Apple Git-117) In-Reply-To: <20190426162624.55977-1-stephen.checkoway@oberlin.edu> References: <20190426162624.55977-1-stephen.checkoway@oberlin.edu> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::142 Subject: [Qemu-devel] [PATCH v4 09/10] block/pflash_cfi02: Implement erase suspend/resume X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stephen Checkoway Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" During a sector erase (but not a chip erase), the embeded erase program can be suspended. Once suspended, the sectors not selected for erasure may be read and programmed. Autoselect mode is allowed during erase suspend mode. Presumably, CFI queries are similarly allowed so this commit allows them as well. Since guest firmware can use status bits DQ7, DQ6, DQ3, and DQ2 to determine the current state of sector erasure, these bits are properly implemented. Signed-off-by: Stephen Checkoway Acked-by: Thomas Huth --- hw/block/pflash_cfi02.c | 153 ++++++++++++++++++++++++++++++++++---- tests/pflash-cfi02-test.c | 112 ++++++++++++++++++++++++++++ 2 files changed, 251 insertions(+), 14 deletions(-) diff --git a/hw/block/pflash_cfi02.c b/hw/block/pflash_cfi02.c index 21ceb0823b..d9087cafff 100644 --- a/hw/block/pflash_cfi02.c +++ b/hw/block/pflash_cfi02.c @@ -29,7 +29,6 @@ * - CFI queries * * It does not implement software data protection as found in many real ch= ips - * It does not implement erase suspend/resume commands */ =20 #include "qemu/osdep.h" @@ -37,6 +36,7 @@ #include "hw/block/block.h" #include "hw/block/flash.h" #include "qapi/error.h" +#include "qemu/bitmap.h" #include "qemu/timer.h" #include "sysemu/block-backend.h" #include "qemu/host-utils.h" @@ -72,6 +72,7 @@ struct PFlashCFI02 { BlockBackend *blk; uint32_t uniform_nb_blocs; uint32_t uniform_sector_len; + uint32_t total_sectors; uint32_t nb_blocs[PFLASH_MAX_ERASE_REGIONS]; uint32_t sector_len[PFLASH_MAX_ERASE_REGIONS]; uint64_t total_len; @@ -106,6 +107,8 @@ struct PFlashCFI02 { int rom_mode; int read_counter; /* used for lazy switch-back to rom mode */ int sectors_to_erase; + uint64_t erase_time_remaining; + unsigned long *sector_erase_map; char *name; void *storage; }; @@ -152,6 +155,14 @@ static inline void reset_dq3(PFlashCFI02 *pfl) pfl->status &=3D ~(pfl->interleave_multiplier * 0x08); } =20 +/* + * Toggle status bit DQ2. + */ +static inline void toggle_dq2(PFlashCFI02 *pfl) +{ + pfl->status ^=3D pfl->interleave_multiplier * 0x04; +} + /* * Set up replicated mappings of the same region. */ @@ -175,6 +186,29 @@ static void pflash_register_memory(PFlashCFI02 *pfl, i= nt rom_mode) pfl->rom_mode =3D rom_mode; } =20 +/* + * Returns the time it takes to erase the number of sectors scheduled for + * erasure based on CFI address 0x21 which is "Typical timeout per individ= ual + * block erase 2^N ms." + */ +static uint64_t pflash_erase_time(PFlashCFI02 *pfl) +{ + /* + * If there are no sectors to erase (which can happen if all of the se= ctors + * to be erased are protected), then erase takes 100 us. Protected sec= tors + * aren't supported so this should never happen. + */ + return ((1ULL << pfl->cfi_table[0x21]) * pfl->sectors_to_erase) * SCAL= E_US; +} + +/* + * Returns true if the device is currently in erase suspend mode. + */ +static inline bool pflash_erase_suspend_mode(PFlashCFI02 *pfl) +{ + return pfl->erase_time_remaining > 0; +} + static void pflash_timer(void *opaque) { PFlashCFI02 *pfl =3D opaque; @@ -189,12 +223,7 @@ static void pflash_timer(void *opaque) */ if ((pfl->status & 0x08) =3D=3D 0) { assert_dq3(pfl); - /* - * CFI address 0x21 is "Typical timeout per individual block e= rase - * 2^N ms" - */ - uint64_t timeout =3D ((1ULL << pfl->cfi_table[0x21]) * - pfl->sectors_to_erase) * 1000000; + uint64_t timeout =3D pflash_erase_time(pfl); timer_mod(&pfl->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + timeout); DPRINTF("%s: erase timeout fired; erasing %d sectors\n", @@ -202,6 +231,7 @@ static void pflash_timer(void *opaque) return; } DPRINTF("%s: sector erase complete\n", __func__); + bitmap_zero(pfl->sector_erase_map, pfl->total_sectors); pfl->sectors_to_erase =3D 0; reset_dq3(pfl); } @@ -240,25 +270,45 @@ static uint64_t pflash_data_read(PFlashCFI02 *pfl, hw= addr offset, return ret; } =20 +typedef struct { + uint32_t len; + uint32_t num; +} SectorInfo; + /* * offset should be a byte offset of the QEMU device and _not_ a device * offset. */ -static uint32_t pflash_sector_len(PFlashCFI02 *pfl, hwaddr offset) +static SectorInfo pflash_sector_info(PFlashCFI02 *pfl, hwaddr offset) { assert(offset < pfl->total_len); int nb_regions =3D pfl->cfi_table[0x2C]; hwaddr addr =3D 0; + uint32_t sector_num =3D 0; for (int i =3D 0; i < nb_regions; ++i) { uint64_t region_size =3D (uint64_t)pfl->nb_blocs[i] * pfl->sector_= len[i]; if (addr <=3D offset && offset < addr + region_size) { - return pfl->sector_len[i]; + return (SectorInfo) { + .len =3D pfl->sector_len[i], + .num =3D sector_num + (offset - addr) / pfl->sector_len[i], + }; } + sector_num +=3D pfl->nb_blocs[i]; addr +=3D region_size; } abort(); } =20 +/* + * Returns true if the offset refers to a flash sector that is currently b= eing + * erased. + */ +static bool pflash_sector_is_erasing(PFlashCFI02 *pfl, hwaddr offset) +{ + long sector_num =3D pflash_sector_info(pfl, offset).num; + return test_bit(sector_num, pfl->sector_erase_map); +} + static uint64_t pflash_read(void *opaque, hwaddr offset, unsigned int widt= h) { PFlashCFI02 *pfl =3D opaque; @@ -285,6 +335,15 @@ static uint64_t pflash_read(void *opaque, hwaddr offse= t, unsigned int width) case 0x80: /* We accept reads during second unlock sequence... */ case 0x00: + if (pflash_erase_suspend_mode(pfl) && + pflash_sector_is_erasing(pfl, offset)) { + /* Toggle bit 2, but not 6. */ + toggle_dq2(pfl); + /* Status register read */ + ret =3D pfl->status; + DPRINTF("%s: status %" PRIx64 "\n", __func__, ret); + break; + } /* Flash area read */ return pflash_data_read(pfl, offset, width); case 0x90: @@ -313,14 +372,16 @@ static uint64_t pflash_read(void *opaque, hwaddr offs= et, unsigned int width) DPRINTF("%s: ID " TARGET_FMT_plx " %" PRIx64 "\n", __func__, device_addr & 0xFF, ret); break; - case 0xA0: case 0x10: case 0x30: + /* Toggle bit 2 during erase, but not program. */ + toggle_dq2(pfl); + case 0xA0: + /* Toggle bit 6 */ + toggle_dq6(pfl); /* Status register read */ ret =3D pfl->status; DPRINTF("%s: status %" PRIx64 "\n", __func__, ret); - /* Toggle bit 6 */ - toggle_dq6(pfl); break; case 0x98: /* CFI query mode */ @@ -351,7 +412,8 @@ static void pflash_update(PFlashCFI02 *pfl, int offset,= int size) =20 static void pflash_sector_erase(PFlashCFI02 *pfl, hwaddr offset) { - uint64_t sector_len =3D pflash_sector_len(pfl, offset); + SectorInfo sector_info =3D pflash_sector_info(pfl, offset); + uint64_t sector_len =3D sector_info.len; offset &=3D ~(sector_len - 1); DPRINTF("%s: start sector erase at %0*" PRIx64 "-%0*" PRIx64 "\n", __func__, pfl->bank_width * 2, offset, @@ -363,6 +425,7 @@ static void pflash_sector_erase(PFlashCFI02 *pfl, hwadd= r offset) } set_dq7(pfl, 0x00); ++pfl->sectors_to_erase; + set_bit(sector_info.num, pfl->sector_erase_map); /* Set (or reset) the 50 us timer for additional erase commands. */ timer_mod(&pfl->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 50000); } @@ -422,6 +485,25 @@ static void pflash_write(void *opaque, hwaddr offset, = uint64_t value, pfl->cmd =3D 0x98; return; } + /* Handle erase resume in erase suspend mode, otherwise reset. */ + if (cmd =3D=3D 0x30) { + if (pflash_erase_suspend_mode(pfl)) { + /* Resume the erase. */ + timer_mod(&pfl->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUA= L) + + pfl->erase_time_remaining); + pfl->erase_time_remaining =3D 0; + pfl->wcycle =3D 6; + pfl->cmd =3D 0x30; + set_dq7(pfl, 0x00); + assert_dq3(pfl); + return; + } + goto reset_flash; + } + /* Ignore erase suspend. */ + if (cmd =3D=3D 0xB0) { + return; + } if (masked_addr !=3D pfl->unlock_addr0 || cmd !=3D 0xAA) { DPRINTF("%s: unlock0 failed %04x %02x %04x\n", __func__, masked_addr, cmd, pfl->unlock_addr0); @@ -467,6 +549,14 @@ static void pflash_write(void *opaque, hwaddr offset, = uint64_t value, /* We need another unlock sequence */ goto check_unlock0; case 0xA0: + if (pflash_erase_suspend_mode(pfl) && + pflash_sector_is_erasing(pfl, offset)) { + /* Ignore writes to erasing sectors. */ + if (pfl->bypass) { + goto do_bypass; + } + goto reset_flash; + } trace_pflash_data_write(offset, value, width, 0); if (!pfl->ro) { p =3D (uint8_t *)pfl->storage + offset; @@ -525,6 +615,10 @@ static void pflash_write(void *opaque, hwaddr offset, = uint64_t value, } break; case 5: + if (pflash_erase_suspend_mode(pfl)) { + /* Erasing is not supported in erase suspend mode. */ + goto reset_flash; + } switch (cmd) { case 0x10: if (masked_addr !=3D pfl->unlock_addr0) { @@ -559,6 +653,30 @@ static void pflash_write(void *opaque, hwaddr offset, = uint64_t value, /* Ignore writes during chip erase */ return; case 0x30: + if (cmd =3D=3D 0xB0) { + /* + * If erase suspend happens during the erase timeout (so D= Q3 is + * 0), then the device suspends erasing immediately. Set t= he + * remaining time to be the total time to erase. Otherwise, + * there is a maximum amount of time it can take to enter + * suspend mode. Let's ignore that and suspend immediately= and + * set the remaining time to the actual time remaining on = the + * timer. + */ + if ((pfl->status & 0x08) =3D=3D 0) { + pfl->erase_time_remaining =3D pflash_erase_time(pfl); + } else { + int64_t delta =3D timer_expire_time_ns(&pfl->timer) - + qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + /* Make sure we have a positive time remaining. */ + pfl->erase_time_remaining =3D delta <=3D 0 ? 1 : delta; + } + reset_dq3(pfl); + timer_del(&pfl->timer); + pfl->wcycle =3D 0; + pfl->cmd =3D 0; + return; + } /* * If DQ3 is 0, additional sector erase commands can be * written and anything else (other than an erase suspend) res= ets @@ -723,10 +841,12 @@ static void pflash_cfi02_realize(DeviceState *dev, Er= ror **errp) int num_devices =3D pfl->bank_width / pfl->device_width; int nb_regions; pfl->total_len =3D 0; + pfl->total_sectors =3D 0; for (nb_regions =3D 0; nb_regions < PFLASH_MAX_ERASE_REGIONS; ++nb_reg= ions) { if (pfl->nb_blocs[nb_regions] =3D=3D 0) { break; } + pfl->total_sectors +=3D pfl->nb_blocs[nb_regions]; uint64_t sector_len_per_device =3D pfl->sector_len[nb_regions] / num_devices; =20 @@ -761,6 +881,7 @@ static void pflash_cfi02_realize(DeviceState *dev, Erro= r **errp) pfl->nb_blocs[0] =3D pfl->uniform_nb_blocs; pfl->sector_len[0] =3D pfl->uniform_sector_len; pfl->total_len =3D uniform_len; + pfl->total_sectors =3D pfl->uniform_nb_blocs; } else if (uniform_len !=3D 0 && uniform_len !=3D pfl->total_len) { error_setg(errp, "\"num-blocks\"*\"sector-length\" " "different from \"num-blocks0\"*\'sector-length0\" + ..= . + " @@ -785,6 +906,9 @@ static void pflash_cfi02_realize(DeviceState *dev, Erro= r **errp) pfl->unlock_addr0 &=3D 0x7FF; pfl->unlock_addr1 &=3D 0x7FF; =20 + /* Allocate memory for a bitmap for sectors being erased. */ + pfl->sector_erase_map =3D bitmap_new(pfl->total_sectors); + if (local_err) { error_propagate(errp, local_err); return; @@ -892,7 +1016,7 @@ static void pflash_cfi02_realize(DeviceState *dev, Err= or **errp) pfl->cfi_table[0x44] =3D '0'; =20 pfl->cfi_table[0x45] =3D 0x00; /* Address sensitive unlock required. */ - pfl->cfi_table[0x46] =3D 0x00; /* Erase suspend not supported. */ + pfl->cfi_table[0x46] =3D 0x02; /* Erase suspend to read/write. */ pfl->cfi_table[0x47] =3D 0x00; /* Sector protect not supported. */ pfl->cfi_table[0x48] =3D 0x00; /* Temporary sector unprotect not suppo= rted. */ =20 @@ -934,6 +1058,7 @@ static void pflash_cfi02_unrealize(DeviceState *dev, E= rror **errp) { PFlashCFI02 *pfl =3D PFLASH_CFI02(dev); timer_del(&pfl->timer); + g_free(pfl->sector_erase_map); } =20 static void pflash_cfi02_class_init(ObjectClass *klass, void *data) diff --git a/tests/pflash-cfi02-test.c b/tests/pflash-cfi02-test.c index 0384593792..7de8e297f8 100644 --- a/tests/pflash-cfi02-test.c +++ b/tests/pflash-cfi02-test.c @@ -43,6 +43,8 @@ typedef struct { #define CHIP_ERASE_CMD 0x10 #define UNLOCK_BYPASS_CMD 0x20 #define UNLOCK_BYPASS_RESET_CMD 0x00 +#define ERASE_SUSPEND_CMD 0xB0 +#define ERASE_RESUME_CMD SECTOR_ERASE_CMD =20 typedef struct { /* Interleave configuration. */ @@ -267,6 +269,16 @@ static void chip_erase(const FlashConfig *c) flash_cmd(c, UNLOCK0_ADDR, CHIP_ERASE_CMD); } =20 +static void erase_suspend(const FlashConfig *c) +{ + flash_cmd(c, FLASH_ADDR(0), ERASE_SUSPEND_CMD); +} + +static void erase_resume(const FlashConfig *c) +{ + flash_cmd(c, FLASH_ADDR(0), ERASE_RESUME_CMD); +} + /* * Check that the device interface code dic is appropriate for the given * width. @@ -381,10 +393,21 @@ static void test_geometry(const void *opaque) c->device_width)); g_assert_true(device_supports_width(device_interface_code, c->max_device_width)); + + /* Check that erase suspend to read/write is supported. */ + uint16_t pri =3D flash_query_1(c, FLASH_ADDR(0x15)) + + (flash_query_1(c, FLASH_ADDR(0x16)) << 8); + g_assert_cmpint(pri, >=3D, 0x2D + 4 * nb_erase_regions); + g_assert_cmpint(flash_query(c, FLASH_ADDR(pri + 0)), =3D=3D, replicate= (c, 'P')); + g_assert_cmpint(flash_query(c, FLASH_ADDR(pri + 1)), =3D=3D, replicate= (c, 'R')); + g_assert_cmpint(flash_query(c, FLASH_ADDR(pri + 2)), =3D=3D, replicate= (c, 'I')); + g_assert_cmpint(flash_query_1(c, FLASH_ADDR(pri + 6)), =3D=3D, 2); /* = R/W */ reset(c); + const uint64_t dq7 =3D replicate(c, 0x80); const uint64_t dq6 =3D replicate(c, 0x40); const uint64_t dq3 =3D replicate(c, 0x08); + const uint64_t dq2 =3D replicate(c, 0x04); =20 uint64_t byte_addr =3D 0; for (int region =3D 0; region < nb_erase_regions; ++region) { @@ -525,6 +548,95 @@ static void test_geometry(const void *opaque) } } =20 + /* Test erase suspend/resume during erase timeout. */ + sector_erase(c, 0); + /* + * Check that DQ 3 is 0 and DQ6 and DQ2 are toggling in the sector bei= ng + * erased as well as in a sector not being erased. + */ + byte_addr =3D c->sector_len[0]; + status0 =3D flash_read(c, 0); + status1 =3D flash_read(c, 0); + g_assert_cmpint(status0 & dq3, =3D=3D, 0); + g_assert_cmpint(status0 & dq6, =3D=3D, ~status1 & dq6); + g_assert_cmpint(status0 & dq2, =3D=3D, ~status1 & dq2); + status0 =3D flash_read(c, byte_addr); + status1 =3D flash_read(c, byte_addr); + g_assert_cmpint(status0 & dq3, =3D=3D, 0); + g_assert_cmpint(status0 & dq6, =3D=3D, ~status1 & dq6); + g_assert_cmpint(status0 & dq2, =3D=3D, ~status1 & dq2); + + /* + * Check that after suspending, DQ6 does not toggle but DQ2 does toggl= e in + * an erase suspended sector but that neither toggle (we should be + * getting data) in a sector not being erased. + */ + erase_suspend(c); + status0 =3D flash_read(c, 0); + status1 =3D flash_read(c, 0); + g_assert_cmpint(status0 & dq6, =3D=3D, status1 & dq6); + g_assert_cmpint(status0 & dq2, =3D=3D, ~status1 & dq2); + g_assert_cmpint(flash_read(c, byte_addr), =3D=3D, flash_read(c, byte_a= ddr)); + + /* Check that after resuming, DQ3 is 1 and DQ6 and DQ2 toggle. */ + erase_resume(c); + status0 =3D flash_read(c, 0); + status1 =3D flash_read(c, 0); + g_assert_cmpint(status0 & dq3, =3D=3D, dq3); + g_assert_cmpint(status0 & dq6, =3D=3D, ~status1 & dq6); + g_assert_cmpint(status0 & dq2, =3D=3D, ~status1 & dq2); + status0 =3D flash_read(c, byte_addr); + status1 =3D flash_read(c, byte_addr); + g_assert_cmpint(status0 & dq3, =3D=3D, dq3); + g_assert_cmpint(status0 & dq6, =3D=3D, ~status1 & dq6); + g_assert_cmpint(status0 & dq2, =3D=3D, ~status1 & dq2); + wait_for_completion(c, 0); + + /* Repeat this process but this time suspend after the timeout. */ + sector_erase(c, 0); + qtest_clock_step_next(c->qtest); + /* + * Check that DQ 3 is 1 and DQ6 and DQ2 are toggling in the sector bei= ng + * erased as well as in a sector not being erased. + */ + byte_addr =3D c->sector_len[0]; + status0 =3D flash_read(c, 0); + status1 =3D flash_read(c, 0); + g_assert_cmpint(status0 & dq3, =3D=3D, dq3); + g_assert_cmpint(status0 & dq6, =3D=3D, ~status1 & dq6); + g_assert_cmpint(status0 & dq2, =3D=3D, ~status1 & dq2); + status0 =3D flash_read(c, byte_addr); + status1 =3D flash_read(c, byte_addr); + g_assert_cmpint(status0 & dq3, =3D=3D, dq3); + g_assert_cmpint(status0 & dq6, =3D=3D, ~status1 & dq6); + g_assert_cmpint(status0 & dq2, =3D=3D, ~status1 & dq2); + + /* + * Check that after suspending, DQ6 does not toggle but DQ2 does toggl= e in + * an erase suspended sector but that neither toggle (we should be + * getting data) in a sector not being erased. + */ + erase_suspend(c); + status0 =3D flash_read(c, 0); + status1 =3D flash_read(c, 0); + g_assert_cmpint(status0 & dq6, =3D=3D, status1 & dq6); + g_assert_cmpint(status0 & dq2, =3D=3D, ~status1 & dq2); + g_assert_cmpint(flash_read(c, byte_addr), =3D=3D, flash_read(c, byte_a= ddr)); + + /* Check that after resuming, DQ3 is 1 and DQ6 and DQ2 toggle. */ + erase_resume(c); + status0 =3D flash_read(c, 0); + status1 =3D flash_read(c, 0); + g_assert_cmpint(status0 & dq3, =3D=3D, dq3); + g_assert_cmpint(status0 & dq6, =3D=3D, ~status1 & dq6); + g_assert_cmpint(status0 & dq2, =3D=3D, ~status1 & dq2); + status0 =3D flash_read(c, byte_addr); + status1 =3D flash_read(c, byte_addr); + g_assert_cmpint(status0 & dq3, =3D=3D, dq3); + g_assert_cmpint(status0 & dq6, =3D=3D, ~status1 & dq6); + g_assert_cmpint(status0 & dq2, =3D=3D, ~status1 & dq2); + wait_for_completion(c, 0); + qtest_quit(qtest); } =20 --=20 2.20.1 (Apple Git-117) From nobody Mon Feb 9 11:35:11 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[208.66.210.181]) by smtp.gmail.com with ESMTPSA id c7sm7548700ioc.63.2019.04.26.09.27.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 26 Apr 2019 09:27:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oberlin-edu.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/jtNWxB61SZw8gmWc4QLGq2l28K8nb8bWXBa9rEihZY=; b=bitbOCJbc0qOeUGjyEFrVHTixRuriDk5SRjebwSIBNIbbGmZJfUNNpMiyyPUFzqSE5 AlE1+Boi4Qy4a5rUy1KBWQgUkuQJXKe/SHUZZ/oq8RaINH1ksLTfX9HBpnpXfRNTHIP3 Vx2NvFrPvkdunsBIB3hvhuU1+vpEvGtmtn0ADGxIX5hnghaZRZk3iPknoGzy5thYFEdG Fvy4/b0KT3HWSHliL0rV35kAQIGMO/IP3rC7Y6QUIFc6Kq/4/Y/YXyOPitZaQZeXn4Rf bl3boXKuN7Q2Bb8xPsHTYURZtxccfhqTrRMyce34cfdiX0rNEh+oKW28uyDcRIl+Qjyh 0l7Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/jtNWxB61SZw8gmWc4QLGq2l28K8nb8bWXBa9rEihZY=; b=Ma3SK0RNtREmM8POw1i2YBLinJS1mYPvaxza58JV96+fPJ89NDcXAuQzU55zMlGgk5 HOaRpioa7bSiGHWbPMH8ZaKN8ps1rlUpFFSHd0n6yOYB7FNq+bG4cl7sENEaF3BQpDf0 mu3KHvw2rYBeoNCN/glICUUvO/e4s436RFkdZqdkK2LMHKJ/4LT4ML7zVMFXQE2oXN+C mj9/+Dfr7v51pr+Agg7JZe7C1sRNbsOeQ62Z6G0q7Z7xeJ1qfH/vW5+iQ88AizmOXQk6 6me4EfzMRR8SpUPzCuttJvux4uoIFJJJHB6OhjqQFHlH7zcvHdzTkAdo7XUd14fMYTmv fduA== X-Gm-Message-State: APjAAAXcZ2or2v8vGqqTggRHiEQ52w6/PfQT4cU37nOokXqZRL9Qam0K KX2G/yzgX7+eXz53pR/0nkKBWe9LHln0ww== X-Google-Smtp-Source: APXvYqzC+u18lrPykPMI4QhLTCi5Ewn8XSh2Pd0OAsTylGFQvooVTvxfmDt8O6flGWJp23r5TUgxCQ== X-Received: by 2002:a02:880a:: with SMTP id r10mr9099579jai.67.1556296035933; Fri, 26 Apr 2019 09:27:15 -0700 (PDT) From: Stephen Checkoway To: QEMU Developers , Thomas Huth , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Kevin Wolf , Max Reitz , "open list:Block layer core" , Markus Armbruster , Laszlo Ersek , Laurent Vivier , Paolo Bonzini Date: Fri, 26 Apr 2019 12:26:24 -0400 Message-Id: <20190426162624.55977-11-stephen.checkoway@oberlin.edu> X-Mailer: git-send-email 2.20.1 (Apple Git-117) In-Reply-To: <20190426162624.55977-1-stephen.checkoway@oberlin.edu> References: <20190426162624.55977-1-stephen.checkoway@oberlin.edu> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::143 Subject: [Qemu-devel] [PATCH v4 10/10] block/pflash_cfi02: Use the chip erase time specified in the CFI table X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stephen Checkoway Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" When erasing the chip, use the typical time specified in the CFI table rather than arbitrarily selecting 5 seconds. Since the currently unconfigurable value set in the table is 12, this means a chip erase takes 4096 ms so this isn't a big change in behavior. Signed-off-by: Stephen Checkoway Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 --- hw/block/pflash_cfi02.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/block/pflash_cfi02.c b/hw/block/pflash_cfi02.c index d9087cafff..76c8af4365 100644 --- a/hw/block/pflash_cfi02.c +++ b/hw/block/pflash_cfi02.c @@ -633,9 +633,9 @@ static void pflash_write(void *opaque, hwaddr offset, u= int64_t value, pflash_update(pfl, 0, pfl->total_len); } set_dq7(pfl, 0x00); - /* Let's wait 5 seconds before chip erase is done */ + /* Wait the time specified at CFI address 0x22. */ timer_mod(&pfl->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + - (NANOSECONDS_PER_SECOND * 5)); + (1ULL << pfl->cfi_table[0x22]) * SCALE_MS); break; case 0x30: /* Sector erase */ --=20 2.20.1 (Apple Git-117)