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[97.113.179.147]) by smtp.gmail.com with ESMTPSA id c25sm24366591pfo.69.2019.04.23.08.38.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 23 Apr 2019 08:38:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/g6HfJ2gjjF5BRknAhZhLqn8QoGjqCxyswuw+nR205c=; b=Vc2Qyv97RjQl7ZRx8/ZRsWmM5EDZ50u70Q9TFNIrHweu893rTAC99i4f7fPYOMEAiM qkC0SjHS8zcyttmDcAD9t1h74ZVFcMN/NGAfpdFmZWQkYXRzuZZ5bESZzR8EDDlycpaM eTxSdqJyV7UNFTh8awGDygmE+MnS4DAGm/BYYsVCXXIlHLbpJ7ztPNWthPXWhwszUI+6 1QY0TNe3+Om35JSJQzep5GXqnSH+U8aSRyG2x+cbWXFQtR6cV9zicyrNqjpTxaKuowio 2g2NedXHx24vPIWInvUMvPNDkxR+GiDgNiCmFycPawDK2Bqz6dRj0n3Gy2wrhY3mCr3o FVAw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/g6HfJ2gjjF5BRknAhZhLqn8QoGjqCxyswuw+nR205c=; b=HnCP3xe5/eTYS6qJXA0kTTaaHSoUDOW1KH6peyLG3RnK2IVIrO0X3Bl2AO31jXDjzD 0M9yiKHNFDO3xI92uB7DdvaxEKPMtH/xoj4bQ67f9Mu4ZScgV3Oe1UgLVhIJkp3UJKz+ Ido3bW3KAACQdu7iT3Gl9xE3r2HcaASJblkDzNxv5wnGbifIEmzA3Aa/VXxtNT1pApLF B2lnq+0DVo6L2Q46rY9owIaIA0b+6LJ/4aMQn4eGGkmBagtpCXVYh+Tp5/n4iVgw9j+P 6Nv3i8NWAR6lKTCyoTSFYDSyFHl88WsClerzy8sKAih+ll3Lk7EStFge2dSs538xi2so RJGw== X-Gm-Message-State: APjAAAUA+1jusbdSKNFyaRopJ3Vhz+RZS9tF1yMHLT9BBBW89+sJgO6b hO66TBkI+PDjoXlDHYVD4NQHfVIkKQw= X-Google-Smtp-Source: APXvYqwBEmWY4uhFdfgmcOvLZzZ8zq8ZVfpHFIEfu6n7etLs3f9Wb9OH//LGoJYt4wTUMRcxEm+jZg== X-Received: by 2002:a65:6108:: with SMTP id z8mr25217771pgu.106.1556033937746; Tue, 23 Apr 2019 08:38:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 23 Apr 2019 08:38:47 -0700 Message-Id: <20190423153853.19790-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190423153853.19790-1-richard.henderson@linaro.org> References: <20190423153853.19790-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::441 Subject: [Qemu-devel] [PATCH v2 1/7] tcg: Hoist max_insns computation to tb_gen_code X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) In order to handle TB's that translate to too much code, we need to place the control of the length of the translation in the hands of the code gen master loop. Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 4 ++-- include/exec/translator.h | 3 ++- accel/tcg/translate-all.c | 15 +++++++++++++-- accel/tcg/translator.c | 15 ++------------- target/alpha/translate.c | 4 ++-- target/arm/translate.c | 4 ++-- target/cris/translate.c | 10 +--------- target/hppa/translate.c | 5 ++--- target/i386/translate.c | 4 ++-- target/lm32/translate.c | 10 +--------- target/m68k/translate.c | 4 ++-- target/microblaze/translate.c | 10 +--------- target/mips/translate.c | 4 ++-- target/moxie/translate.c | 11 ++--------- target/nios2/translate.c | 14 ++------------ target/openrisc/translate.c | 4 ++-- target/ppc/translate.c | 4 ++-- target/riscv/translate.c | 4 ++-- target/s390x/translate.c | 4 ++-- target/sh4/translate.c | 4 ++-- target/sparc/translate.c | 4 ++-- target/tilegx/translate.c | 12 +----------- target/tricore/translate.c | 16 ++-------------- target/unicore32/translate.c | 10 +--------- target/xtensa/translate.c | 4 ++-- 25 files changed, 56 insertions(+), 127 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 97b90cb0db..58e988b3b1 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -40,8 +40,8 @@ typedef ram_addr_t tb_page_addr_t; =20 #include "qemu/log.h" =20 -void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb); -void restore_state_to_opc(CPUArchState *env, struct TranslationBlock *tb, +void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_in= sns); +void restore_state_to_opc(CPUArchState *env, TranslationBlock *tb, target_ulong *data); =20 void cpu_gen_init(void); diff --git a/include/exec/translator.h b/include/exec/translator.h index 71e7b2c347..66dfe906c4 100644 --- a/include/exec/translator.h +++ b/include/exec/translator.h @@ -123,6 +123,7 @@ typedef struct TranslatorOps { * @db: Disassembly context. * @cpu: Target vCPU. * @tb: Translation block. + * @max_insns: Maximum number of insns to translate. * * Generic translator loop. * @@ -137,7 +138,7 @@ typedef struct TranslatorOps { * - When too many instructions have been translated. */ void translator_loop(const TranslatorOps *ops, DisasContextBase *db, - CPUState *cpu, TranslationBlock *tb); + CPUState *cpu, TranslationBlock *tb, int max_insns); =20 void translator_loop_temp_check(DisasContextBase *db); =20 diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 8f593b926f..fcdfe6c0ec 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1673,7 +1673,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, tb_page_addr_t phys_pc, phys_page2; target_ulong virt_page2; tcg_insn_unit *gen_code_buf; - int gen_code_size, search_size; + int gen_code_size, search_size, max_insns; #ifdef CONFIG_PROFILER TCGProfile *prof =3D &tcg_ctx->prof; int64_t ti; @@ -1691,6 +1691,17 @@ TranslationBlock *tb_gen_code(CPUState *cpu, cflags &=3D ~CF_CLUSTER_MASK; cflags |=3D cpu->cluster_index << CF_CLUSTER_SHIFT; =20 + max_insns =3D cflags & CF_COUNT_MASK; + if (max_insns =3D=3D 0) { + max_insns =3D CF_COUNT_MASK; + } + if (max_insns > TCG_MAX_INSNS) { + max_insns =3D TCG_MAX_INSNS; + } + if (cpu->singlestep_enabled || singlestep) { + max_insns =3D 1; + } + buffer_overflow: tb =3D tb_alloc(pc); if (unlikely(!tb)) { @@ -1720,7 +1731,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, tcg_func_start(tcg_ctx); =20 tcg_ctx->cpu =3D ENV_GET_CPU(env); - gen_intermediate_code(cpu, tb); + gen_intermediate_code(cpu, tb, max_insns); tcg_ctx->cpu =3D NULL; =20 trace_translate_block(tb, tb->pc, tb->tc.ptr); diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c index afd0a49ea6..8d65ead708 100644 --- a/accel/tcg/translator.c +++ b/accel/tcg/translator.c @@ -32,7 +32,7 @@ void translator_loop_temp_check(DisasContextBase *db) } =20 void translator_loop(const TranslatorOps *ops, DisasContextBase *db, - CPUState *cpu, TranslationBlock *tb) + CPUState *cpu, TranslationBlock *tb, int max_insns) { int bp_insn =3D 0; =20 @@ -42,20 +42,9 @@ void translator_loop(const TranslatorOps *ops, DisasCont= extBase *db, db->pc_next =3D db->pc_first; db->is_jmp =3D DISAS_NEXT; db->num_insns =3D 0; + db->max_insns =3D max_insns; db->singlestep_enabled =3D cpu->singlestep_enabled; =20 - /* Instruction counting */ - db->max_insns =3D tb_cflags(db->tb) & CF_COUNT_MASK; - if (db->max_insns =3D=3D 0) { - db->max_insns =3D CF_COUNT_MASK; - } - if (db->max_insns > TCG_MAX_INSNS) { - db->max_insns =3D TCG_MAX_INSNS; - } - if (db->singlestep_enabled || singlestep) { - db->max_insns =3D 1; - } - ops->init_disas_context(db, cpu); tcg_debug_assert(db->is_jmp =3D=3D DISAS_NEXT); /* no early exit */ =20 diff --git a/target/alpha/translate.c b/target/alpha/translate.c index 9d8f9b3eea..2c9cccf6c1 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -3049,10 +3049,10 @@ static const TranslatorOps alpha_tr_ops =3D { .disas_log =3D alpha_tr_disas_log, }; =20 -void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb) +void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_in= sns) { DisasContext dc; - translator_loop(&alpha_tr_ops, &dc.base, cpu, tb); + translator_loop(&alpha_tr_ops, &dc.base, cpu, tb, max_insns); } =20 void restore_state_to_opc(CPUAlphaState *env, TranslationBlock *tb, diff --git a/target/arm/translate.c b/target/arm/translate.c index d408e4d7ef..b6b65ca360 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -13755,7 +13755,7 @@ static const TranslatorOps thumb_translator_ops =3D= { }; =20 /* generate intermediate code for basic block 'tb'. */ -void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb) +void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_in= sns) { DisasContext dc; const TranslatorOps *ops =3D &arm_translator_ops; @@ -13769,7 +13769,7 @@ void gen_intermediate_code(CPUState *cpu, Translati= onBlock *tb) } #endif =20 - translator_loop(ops, &dc.base, cpu, tb); + translator_loop(ops, &dc.base, cpu, tb, max_insns); } =20 void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprint= f, diff --git a/target/cris/translate.c b/target/cris/translate.c index 11b2c11174..777810452d 100644 --- a/target/cris/translate.c +++ b/target/cris/translate.c @@ -3080,7 +3080,7 @@ static unsigned int crisv32_decoder(CPUCRISState *env= , DisasContext *dc) */ =20 /* generate intermediate code for basic block 'tb'. */ -void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) +void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_ins= ns) { CPUCRISState *env =3D cs->env_ptr; uint32_t pc_start; @@ -3090,7 +3090,6 @@ void gen_intermediate_code(CPUState *cs, struct Trans= lationBlock *tb) uint32_t page_start; target_ulong npc; int num_insns; - int max_insns; =20 if (env->pregs[PR_VR] =3D=3D 32) { dc->decoder =3D crisv32_decoder; @@ -3136,13 +3135,6 @@ void gen_intermediate_code(CPUState *cs, struct Tran= slationBlock *tb) =20 page_start =3D pc_start & TARGET_PAGE_MASK; num_insns =3D 0; - max_insns =3D tb_cflags(tb) & CF_COUNT_MASK; - if (max_insns =3D=3D 0) { - max_insns =3D CF_COUNT_MASK; - } - if (max_insns > TCG_MAX_INSNS) { - max_insns =3D TCG_MAX_INSNS; - } =20 gen_tb_start(tb); do { diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 43b74367ea..7c03c62768 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -4312,11 +4312,10 @@ static const TranslatorOps hppa_tr_ops =3D { .disas_log =3D hppa_tr_disas_log, }; =20 -void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) - +void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_ins= ns) { DisasContext ctx; - translator_loop(&hppa_tr_ops, &ctx.base, cs, tb); + translator_loop(&hppa_tr_ops, &ctx.base, cs, tb, max_insns); } =20 void restore_state_to_opc(CPUHPPAState *env, TranslationBlock *tb, diff --git a/target/i386/translate.c b/target/i386/translate.c index b725bec37c..77d6b73e42 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -8590,11 +8590,11 @@ static const TranslatorOps i386_tr_ops =3D { }; =20 /* generate intermediate code for basic block 'tb'. */ -void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb) +void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_in= sns) { DisasContext dc; =20 - translator_loop(&i386_tr_ops, &dc.base, cpu, tb); + translator_loop(&i386_tr_ops, &dc.base, cpu, tb, max_insns); } =20 void restore_state_to_opc(CPUX86State *env, TranslationBlock *tb, diff --git a/target/lm32/translate.c b/target/lm32/translate.c index b32feb7564..ac5169c4e7 100644 --- a/target/lm32/translate.c +++ b/target/lm32/translate.c @@ -1049,7 +1049,7 @@ static inline void decode(DisasContext *dc, uint32_t = ir) } =20 /* generate intermediate code for basic block 'tb'. */ -void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) +void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_ins= ns) { CPULM32State *env =3D cs->env_ptr; LM32CPU *cpu =3D lm32_env_get_cpu(env); @@ -1057,7 +1057,6 @@ void gen_intermediate_code(CPUState *cs, struct Trans= lationBlock *tb) uint32_t pc_start; uint32_t page_start; int num_insns; - int max_insns; =20 pc_start =3D tb->pc; dc->features =3D cpu->features; @@ -1077,13 +1076,6 @@ void gen_intermediate_code(CPUState *cs, struct Tran= slationBlock *tb) =20 page_start =3D pc_start & TARGET_PAGE_MASK; num_insns =3D 0; - max_insns =3D tb_cflags(tb) & CF_COUNT_MASK; - if (max_insns =3D=3D 0) { - max_insns =3D CF_COUNT_MASK; - } - if (max_insns > TCG_MAX_INSNS) { - max_insns =3D TCG_MAX_INSNS; - } =20 gen_tb_start(tb); do { diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 6217a683f1..838ff64875 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -6169,10 +6169,10 @@ static const TranslatorOps m68k_tr_ops =3D { .disas_log =3D m68k_tr_disas_log, }; =20 -void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb) +void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_in= sns) { DisasContext dc; - translator_loop(&m68k_tr_ops, &dc.base, cpu, tb); + translator_loop(&m68k_tr_ops, &dc.base, cpu, tb, max_insns); } =20 static double floatx80_to_double(CPUM68KState *env, uint16_t high, uint64_= t low) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 78ca265b04..efdea5b635 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1600,7 +1600,7 @@ static inline void decode(DisasContext *dc, uint32_t = ir) } =20 /* generate intermediate code for basic block 'tb'. */ -void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) +void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_ins= ns) { CPUMBState *env =3D cs->env_ptr; MicroBlazeCPU *cpu =3D mb_env_get_cpu(env); @@ -1610,7 +1610,6 @@ void gen_intermediate_code(CPUState *cs, struct Trans= lationBlock *tb) uint32_t page_start, org_flags; uint32_t npc; int num_insns; - int max_insns; =20 pc_start =3D tb->pc; dc->cpu =3D cpu; @@ -1634,13 +1633,6 @@ void gen_intermediate_code(CPUState *cs, struct Tran= slationBlock *tb) =20 page_start =3D pc_start & TARGET_PAGE_MASK; num_insns =3D 0; - max_insns =3D tb_cflags(tb) & CF_COUNT_MASK; - if (max_insns =3D=3D 0) { - max_insns =3D CF_COUNT_MASK; - } - if (max_insns > TCG_MAX_INSNS) { - max_insns =3D TCG_MAX_INSNS; - } =20 gen_tb_start(tb); do diff --git a/target/mips/translate.c b/target/mips/translate.c index 364bd6dc4f..ee630e1c5d 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -29720,11 +29720,11 @@ static const TranslatorOps mips_tr_ops =3D { .disas_log =3D mips_tr_disas_log, }; =20 -void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) +void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_ins= ns) { DisasContext ctx; =20 - translator_loop(&mips_tr_ops, &ctx.base, cs, tb); + translator_loop(&mips_tr_ops, &ctx.base, cs, tb, max_insns); } =20 static void fpu_dump_state(CPUMIPSState *env, FILE *f, fprintf_function fp= u_fprintf, diff --git a/target/moxie/translate.c b/target/moxie/translate.c index 68ca223e22..d6eebf527f 100644 --- a/target/moxie/translate.c +++ b/target/moxie/translate.c @@ -813,13 +813,13 @@ static int decode_opc(MoxieCPU *cpu, DisasContext *ct= x) } =20 /* generate intermediate code for basic block 'tb'. */ -void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) +void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_ins= ns) { CPUMoxieState *env =3D cs->env_ptr; MoxieCPU *cpu =3D moxie_env_get_cpu(env); DisasContext ctx; target_ulong pc_start; - int num_insns, max_insns; + int num_insns; =20 pc_start =3D tb->pc; ctx.pc =3D pc_start; @@ -829,13 +829,6 @@ void gen_intermediate_code(CPUState *cs, struct Transl= ationBlock *tb) ctx.singlestep_enabled =3D 0; ctx.bstate =3D BS_NONE; num_insns =3D 0; - max_insns =3D tb_cflags(tb) & CF_COUNT_MASK; - if (max_insns =3D=3D 0) { - max_insns =3D CF_COUNT_MASK; - } - if (max_insns > TCG_MAX_INSNS) { - max_insns =3D TCG_MAX_INSNS; - } =20 gen_tb_start(tb); do { diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 7fa03ed05a..a402e572df 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -805,12 +805,11 @@ static void gen_exception(DisasContext *dc, uint32_t = excp) } =20 /* generate intermediate code for basic block 'tb'. */ -void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) +void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_ins= ns) { CPUNios2State *env =3D cs->env_ptr; DisasContext dc1, *dc =3D &dc1; int num_insns; - int max_insns; =20 /* Initialize DC */ dc->cpu_env =3D cpu_env; @@ -823,20 +822,11 @@ void gen_intermediate_code(CPUState *cs, TranslationB= lock *tb) =20 /* Set up instruction counts */ num_insns =3D 0; - if (cs->singlestep_enabled || singlestep) { - max_insns =3D 1; - } else { + if (max_insns > 1) { int page_insns =3D (TARGET_PAGE_SIZE - (tb->pc & TARGET_PAGE_MASK)= ) / 4; - max_insns =3D tb_cflags(tb) & CF_COUNT_MASK; - if (max_insns =3D=3D 0) { - max_insns =3D CF_COUNT_MASK; - } if (max_insns > page_insns) { max_insns =3D page_insns; } - if (max_insns > TCG_MAX_INSNS) { - max_insns =3D TCG_MAX_INSNS; - } } =20 gen_tb_start(tb); diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 89680f882d..92a2b99f9a 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -1408,11 +1408,11 @@ static const TranslatorOps openrisc_tr_ops =3D { .disas_log =3D openrisc_tr_disas_log, }; =20 -void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) +void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_ins= ns) { DisasContext ctx; =20 - translator_loop(&openrisc_tr_ops, &ctx.base, cs, tb); + translator_loop(&openrisc_tr_ops, &ctx.base, cs, tb, max_insns); } =20 void openrisc_cpu_dump_state(CPUState *cs, FILE *f, diff --git a/target/ppc/translate.c b/target/ppc/translate.c index badc1ae1a3..d625687910 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -7864,11 +7864,11 @@ static const TranslatorOps ppc_tr_ops =3D { .disas_log =3D ppc_tr_disas_log, }; =20 -void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) +void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_ins= ns) { DisasContext ctx; =20 - translator_loop(&ppc_tr_ops, &ctx.base, cs, tb); + translator_loop(&ppc_tr_ops, &ctx.base, cs, tb, max_insns); } =20 void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, diff --git a/target/riscv/translate.c b/target/riscv/translate.c index dd763647ea..967eac7bc3 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -783,11 +783,11 @@ static const TranslatorOps riscv_tr_ops =3D { .disas_log =3D riscv_tr_disas_log, }; =20 -void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) +void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_ins= ns) { DisasContext ctx; =20 - translator_loop(&riscv_tr_ops, &ctx.base, cs, tb); + translator_loop(&riscv_tr_ops, &ctx.base, cs, tb, max_insns); } =20 void riscv_translate_init(void) diff --git a/target/s390x/translate.c b/target/s390x/translate.c index 0afa8f7ca5..d4951836ad 100644 --- a/target/s390x/translate.c +++ b/target/s390x/translate.c @@ -6552,11 +6552,11 @@ static const TranslatorOps s390x_tr_ops =3D { .disas_log =3D s390x_tr_disas_log, }; =20 -void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) +void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_ins= ns) { DisasContext dc; =20 - translator_loop(&s390x_tr_ops, &dc.base, cs, tb); + translator_loop(&s390x_tr_ops, &dc.base, cs, tb, max_insns); } =20 void restore_state_to_opc(CPUS390XState *env, TranslationBlock *tb, diff --git a/target/sh4/translate.c b/target/sh4/translate.c index ab254b0e8d..34d3438250 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -2382,11 +2382,11 @@ static const TranslatorOps sh4_tr_ops =3D { .disas_log =3D sh4_tr_disas_log, }; =20 -void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) +void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_ins= ns) { DisasContext ctx; =20 - translator_loop(&sh4_tr_ops, &ctx.base, cs, tb); + translator_loop(&sh4_tr_ops, &ctx.base, cs, tb, max_insns); } =20 void restore_state_to_opc(CPUSH4State *env, TranslationBlock *tb, diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 74315cdf09..091bab53af 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -5962,11 +5962,11 @@ static const TranslatorOps sparc_tr_ops =3D { .disas_log =3D sparc_tr_disas_log, }; =20 -void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) +void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_ins= ns) { DisasContext dc =3D {}; =20 - translator_loop(&sparc_tr_ops, &dc.base, cs, tb); + translator_loop(&sparc_tr_ops, &dc.base, cs, tb, max_insns); } =20 void sparc_tcg_init(void) diff --git a/target/tilegx/translate.c b/target/tilegx/translate.c index df1e4d0fef..c46a4ab151 100644 --- a/target/tilegx/translate.c +++ b/target/tilegx/translate.c @@ -2369,7 +2369,7 @@ static void translate_one_bundle(DisasContext *dc, ui= nt64_t bundle) } } =20 -void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) +void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_ins= ns) { CPUTLGState *env =3D cs->env_ptr; DisasContext ctx; @@ -2377,7 +2377,6 @@ void gen_intermediate_code(CPUState *cs, struct Trans= lationBlock *tb) uint64_t pc_start =3D tb->pc; uint64_t page_start =3D pc_start & TARGET_PAGE_MASK; int num_insns =3D 0; - int max_insns =3D tb_cflags(tb) & CF_COUNT_MASK; =20 dc->pc =3D pc_start; dc->mmuidx =3D 0; @@ -2392,15 +2391,6 @@ void gen_intermediate_code(CPUState *cs, struct Tran= slationBlock *tb) qemu_log_lock(); qemu_log("IN: %s\n", lookup_symbol(pc_start)); } - if (!max_insns) { - max_insns =3D CF_COUNT_MASK; - } - if (cs->singlestep_enabled || singlestep) { - max_insns =3D 1; - } - if (max_insns > TCG_MAX_INSNS) { - max_insns =3D TCG_MAX_INSNS; - } gen_tb_start(tb); =20 while (1) { diff --git a/target/tricore/translate.c b/target/tricore/translate.c index b12c391be5..30d3ff77f5 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -8807,24 +8807,12 @@ static void decode_opc(CPUTriCoreState *env, DisasC= ontext *ctx, int *is_branch) } } =20 -void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) +void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_ins= ns) { CPUTriCoreState *env =3D cs->env_ptr; DisasContext ctx; target_ulong pc_start; - int num_insns, max_insns; - - num_insns =3D 0; - max_insns =3D tb_cflags(tb) & CF_COUNT_MASK; - if (max_insns =3D=3D 0) { - max_insns =3D CF_COUNT_MASK; - } - if (singlestep) { - max_insns =3D 1; - } - if (max_insns > TCG_MAX_INSNS) { - max_insns =3D TCG_MAX_INSNS; - } + int num_insns =3D 0; =20 pc_start =3D tb->pc; ctx.pc =3D pc_start; diff --git a/target/unicore32/translate.c b/target/unicore32/translate.c index 002569ff3b..8547164e47 100644 --- a/target/unicore32/translate.c +++ b/target/unicore32/translate.c @@ -1870,14 +1870,13 @@ static void disas_uc32_insn(CPUUniCore32State *env,= DisasContext *s) } =20 /* generate intermediate code for basic block 'tb'. */ -void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) +void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_ins= ns) { CPUUniCore32State *env =3D cs->env_ptr; DisasContext dc1, *dc =3D &dc1; target_ulong pc_start; uint32_t page_start; int num_insns; - int max_insns; =20 /* generate intermediate code */ num_temps =3D 0; @@ -1896,13 +1895,6 @@ void gen_intermediate_code(CPUState *cs, Translation= Block *tb) cpu_F1d =3D tcg_temp_new_i64(); page_start =3D pc_start & TARGET_PAGE_MASK; num_insns =3D 0; - max_insns =3D tb_cflags(tb) & CF_COUNT_MASK; - if (max_insns =3D=3D 0) { - max_insns =3D CF_COUNT_MASK; - } - if (max_insns > TCG_MAX_INSNS) { - max_insns =3D TCG_MAX_INSNS; - } =20 #ifndef CONFIG_USER_ONLY if ((env->uncached_asr & ASR_M) =3D=3D ASR_MODE_USER) { diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index 65561d2c49..435955dab0 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -1634,10 +1634,10 @@ static const TranslatorOps xtensa_translator_ops = =3D { .disas_log =3D xtensa_tr_disas_log, }; =20 -void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb) +void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_in= sns) { DisasContext dc =3D {}; - translator_loop(&xtensa_translator_ops, &dc.base, cpu, tb); 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X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH v2 2/7] tcg: Restart after TB code generation overflow X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) If a TB generates too much code, try again with fewer insns. Fixes: https://bugs.launchpad.net/bugs/1824853 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- accel/tcg/translate-all.c | 38 ++++++++++++++++++++++++++++++++------ tcg/tcg.c | 4 ++++ 2 files changed, 36 insertions(+), 6 deletions(-) diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index fcdfe6c0ec..65b8370cbe 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1721,6 +1721,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, tb->cflags =3D cflags; tb->trace_vcpu_dstate =3D *cpu->trace_dstate; tcg_ctx->tb_cflags =3D cflags; + tb_overflow: =20 #ifdef CONFIG_PROFILER /* includes aborted translations because of exceptions */ @@ -1754,14 +1755,39 @@ TranslationBlock *tb_gen_code(CPUState *cpu, ti =3D profile_getclock(); #endif =20 - /* ??? Overflow could be handled better here. In particular, we - don't need to re-do gen_intermediate_code, nor should we re-do - the tcg optimization currently hidden inside tcg_gen_code. All - that should be required is to flush the TBs, allocate a new TB, - re-initialize it per above, and re-do the actual code generation. = */ gen_code_size =3D tcg_gen_code(tcg_ctx, tb); if (unlikely(gen_code_size < 0)) { - goto buffer_overflow; + switch (gen_code_size) { + case -1: + /* + * Overflow of code_gen_buffer, or the current slice of it. + * + * TODO: We don't need to re-do gen_intermediate_code, nor + * should we re-do the tcg optimization currently hidden + * inside tcg_gen_code. All that should be required is to + * flush the TBs, allocate a new TB, re-initialize it per + * above, and re-do the actual code generation. + */ + goto buffer_overflow; + + case -2: + /* + * The code generated for the TranslationBlock is too large. + * The maximum size allowed by the unwind info is 64k. + * There may be stricter constraints from relocations + * in the tcg backend. + * + * Try again with half as many insns as we attempted this time. + * If a single insn overflows, there's a bug somewhere... + */ + max_insns =3D tb->icount; + assert(max_insns > 1); + max_insns /=3D 2; + goto tb_overflow; + + default: + g_assert_not_reached(); + } } search_size =3D encode_search(tb, (void *)gen_code_buf + gen_code_size= ); if (unlikely(search_size < 0)) { diff --git a/tcg/tcg.c b/tcg/tcg.c index 9b2bf7f439..aa0e94521b 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -3991,6 +3991,10 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) if (unlikely((void *)s->code_ptr > s->code_gen_highwater)) { return -1; } + /* Test for TB overflow, as seen by gen_insn_end_off. */ + if (unlikely(tcg_current_code_size(s) > UINT16_MAX)) { + return -2; + } } tcg_debug_assert(num_insns >=3D 0); s->gen_insn_end_off[num_insns] =3D tcg_current_code_size(s); --=20 2.17.1 From nobody Sun May 5 12:52:30 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1556034210; cv=none; d=zoho.com; s=zohoarc; b=hjYLL9DdIsCr/n0gkl6dFthgAs5qa4dnuAjCHzxm+azbytdi5AEATokKbWi9hHyfb24hyAEDJ1rRSP1On/D3GOrE/O36nBR8Usez7O0Cxpjs5N762rq2cOhrWiwAwtWtB3SsvXdY5M3ltMlNzR+qZpvcsCiAZ/frj4ocfOCoutg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1556034210; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=xZfsJsQ1qLJS0hBY66Swluu5gyuxQl80LmSEU3qiQnM=; b=WoYZ+hqtkYRLepN4xEUINfwI1sSiLLyPTx8O6YE6y9eg0nL3q0zrLyR7L3wUm5sLXvZNn8L1S7Zw7jzH86EdAbRopIJsp6VTkrunDkDRgD9stTs97KIVQydfOvZRHnWgq767B3IMGrJD2vXfENjWm3q4jMdW8NHWah+69SSIzZE= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1556034210412494.20972714148525; Tue, 23 Apr 2019 08:43:30 -0700 (PDT) Received: from localhost ([127.0.0.1]:55586 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hIxZv-0004e9-D2 for importer@patchew.org; Tue, 23 Apr 2019 11:43:27 -0400 Received: from eggs.gnu.org ([209.51.188.92]:35500) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hIxVe-00018m-PK for qemu-devel@nongnu.org; Tue, 23 Apr 2019 11:39:04 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hIxVd-0006wp-Hm for qemu-devel@nongnu.org; Tue, 23 Apr 2019 11:39:02 -0400 Received: from mail-pf1-x444.google.com ([2607:f8b0:4864:20::444]:36111) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hIxVd-0006wR-BX for qemu-devel@nongnu.org; Tue, 23 Apr 2019 11:39:01 -0400 Received: by mail-pf1-x444.google.com with SMTP id z5so7691981pfn.3 for ; Tue, 23 Apr 2019 08:39:01 -0700 (PDT) Received: from localhost.localdomain (97-113-179-147.tukw.qwest.net. [97.113.179.147]) by smtp.gmail.com with ESMTPSA id c25sm24366591pfo.69.2019.04.23.08.38.58 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 23 Apr 2019 08:38:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=xZfsJsQ1qLJS0hBY66Swluu5gyuxQl80LmSEU3qiQnM=; b=J/A1OJ91F4e+iRgxhDnnQyvKsMY+/Ywbqg3LQdq53eUOkdlsG6b+CU0MUgrlVz1p+h pQ25zTuY5Fc1nsWXlf6EDHQvekPwyW/pzdq0V6C8xpZA/N8h6I16ltdfvEZ8FwcJyakS p/I8i4Wqf31ZvIqU4bJ1CPAsxQXaGfnpbSgpeSUFRKlhTyHB1o+YSeROF/LrxEZMIryg hrnpQPW/E0+XwT0TPpRUvOAVB0UZtep0sW3kokbXk32hSNEH9RMJoQEzevuim9OvLWXw F5Yh/Gfc8DnKwC52r0Voi1xcepZmVDEkh74OaXjNoqydTeVtZvqKnO/ZceFhE3+1CO0E 4feg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=xZfsJsQ1qLJS0hBY66Swluu5gyuxQl80LmSEU3qiQnM=; b=ky/R/Um8YhgwcWkPmrHSdZbaFEJ000HiRfnF1H5FNO7BMj8834/LU6Eke7QwG7f9TC lvzj+DS43uYLqlIKuPjbP7uPIkpmi46SIe7gOzaIynuxF9Obfmhvo0yUrRsq6r3yIB9P ZB2BQliXKjl0RVa273cU/ac3BV8PEcoX7XP5Bx8Oe94G1tYHyXHZYEGCLId8JcqhHjnv UJfrrBcwh0e6Jrfy4C2MZi0YzrSl2VOEbA5fiR7OJE77oIJzrNHxqk+/PfUpS6CgX2rR 39CFa1MHyC63xuT2i6V5jbUKnnhG+dgFs2zqWeLd8ZXCLHzTGOLEkUewUWld0RkCFCvL 7rQw== X-Gm-Message-State: APjAAAWJBaS4Pe3dNd5crac4YtQx0+JpAvJDviIXXFUtkAOg1uGIyhus xAr90gMkKsB2JKwV6+JorwlcZn4pIEc= X-Google-Smtp-Source: APXvYqwy+xXi5GbRfFpccVLJNziA85nvDxbXVKLdt843fi6xp8rj65Rx1bvvq53fUF0tsCPXMNMo8A== X-Received: by 2002:a63:224b:: with SMTP id t11mr8564219pgm.161.1556033940024; Tue, 23 Apr 2019 08:39:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 23 Apr 2019 08:38:49 -0700 Message-Id: <20190423153853.19790-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190423153853.19790-1-richard.henderson@linaro.org> References: <20190423153853.19790-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH v2 3/7] tcg: Restart TB generation after relocation overflow X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" If the TB generates too much code, such that backend relocations overflow, try again with a smaller TB. In support of this, move relocation processing from a random place within tcg_out_op, in the handling of branch opcodes, to a new function at the end of tcg_gen_code. This is not a complete solution, as there are additional relocs generated for out-of-line ldst handling and constant pools. Signed-off-by: Richard Henderson --- tcg/tcg.h | 15 +++++++------- tcg/tcg.c | 61 ++++++++++++++++++++++++++----------------------------- 2 files changed, 36 insertions(+), 40 deletions(-) diff --git a/tcg/tcg.h b/tcg/tcg.h index 32b7cf3489..d2f86174a3 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -237,12 +237,13 @@ typedef uint64_t tcg_insn_unit; do { if (!(X)) { __builtin_unreachable(); } } while (0) #endif =20 -typedef struct TCGRelocation { - struct TCGRelocation *next; - int type; +typedef struct TCGRelocation TCGRelocation; +struct TCGRelocation { + QSIMPLEQ_ENTRY(TCGRelocation) next; tcg_insn_unit *ptr; intptr_t addend; -} TCGRelocation;=20 + int type; +};=20 =20 typedef struct TCGLabel TCGLabel; struct TCGLabel { @@ -253,11 +254,9 @@ struct TCGLabel { union { uintptr_t value; tcg_insn_unit *value_ptr; - TCGRelocation *first_reloc; } u; -#ifdef CONFIG_DEBUG_TCG + QSIMPLEQ_HEAD(, TCGRelocation) relocs; QSIMPLEQ_ENTRY(TCGLabel) next; -#endif }; =20 typedef struct TCGPool { @@ -690,7 +689,6 @@ struct TCGContext { #endif =20 #ifdef CONFIG_DEBUG_TCG - QSIMPLEQ_HEAD(, TCGLabel) labels; int temps_in_use; int goto_tb_issue_mask; #endif @@ -728,6 +726,7 @@ struct TCGContext { TCGTemp temps[TCG_MAX_TEMPS]; /* globals first, temps after */ =20 QTAILQ_HEAD(, TCGOp) ops, free_ops; + QSIMPLEQ_HEAD(, TCGLabel) labels; =20 /* Tells which temporary holds a given register. It does not take into account fixed registers */ diff --git a/tcg/tcg.c b/tcg/tcg.c index aa0e94521b..ab11235c42 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -262,37 +262,17 @@ static __attribute__((unused)) inline void tcg_patch6= 4(tcg_insn_unit *p, static void tcg_out_reloc(TCGContext *s, tcg_insn_unit *code_ptr, int type, TCGLabel *l, intptr_t addend) { - TCGRelocation *r; + TCGRelocation *r =3D tcg_malloc(sizeof(TCGRelocation)); =20 - if (l->has_value) { - /* FIXME: This may break relocations on RISC targets that - modify instruction fields in place. The caller may not have=20 - written the initial value. */ - bool ok =3D patch_reloc(code_ptr, type, l->u.value, addend); - tcg_debug_assert(ok); - } else { - /* add a new relocation entry */ - r =3D tcg_malloc(sizeof(TCGRelocation)); - r->type =3D type; - r->ptr =3D code_ptr; - r->addend =3D addend; - r->next =3D l->u.first_reloc; - l->u.first_reloc =3D r; - } + r->type =3D type; + r->ptr =3D code_ptr; + r->addend =3D addend; + QSIMPLEQ_INSERT_TAIL(&l->relocs, r, next); } =20 static void tcg_out_label(TCGContext *s, TCGLabel *l, tcg_insn_unit *ptr) { - intptr_t value =3D (intptr_t)ptr; - TCGRelocation *r; - tcg_debug_assert(!l->has_value); - - for (r =3D l->u.first_reloc; r !=3D NULL; r =3D r->next) { - bool ok =3D patch_reloc(r->ptr, r->type, value, r->addend); - tcg_debug_assert(ok); - } - l->has_value =3D 1; l->u.value_ptr =3D ptr; } @@ -302,16 +282,32 @@ TCGLabel *gen_new_label(void) TCGContext *s =3D tcg_ctx; TCGLabel *l =3D tcg_malloc(sizeof(TCGLabel)); =20 - *l =3D (TCGLabel){ - .id =3D s->nb_labels++ - }; -#ifdef CONFIG_DEBUG_TCG + memset(l, 0, sizeof(TCGLabel)); + l->id =3D s->nb_labels++; + QSIMPLEQ_INIT(&l->relocs); + QSIMPLEQ_INSERT_TAIL(&s->labels, l, next); -#endif =20 return l; } =20 +static bool tcg_resolve_relocs(TCGContext *s) +{ + TCGLabel *l; + + QSIMPLEQ_FOREACH(l, &s->labels, next) { + TCGRelocation *r; + uintptr_t value =3D l->u.value; + + QSIMPLEQ_FOREACH(r, &l->relocs, next) { + if (!patch_reloc(r->ptr, r->type, value, r->addend)) { + return false; + } + } + } + return true; +} + static void set_jmp_reset_offset(TCGContext *s, int which) { size_t off =3D tcg_current_code_size(s); @@ -1095,9 +1091,7 @@ void tcg_func_start(TCGContext *s) =20 QTAILQ_INIT(&s->ops); QTAILQ_INIT(&s->free_ops); -#ifdef CONFIG_DEBUG_TCG QSIMPLEQ_INIT(&s->labels); -#endif } =20 static inline TCGTemp *tcg_temp_alloc(TCGContext *s) @@ -4010,6 +4004,9 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) return -1; } #endif + if (!tcg_resolve_relocs(s)) { + return -2; + } =20 /* flush instruction cache */ flush_icache_range((uintptr_t)s->code_buf, (uintptr_t)s->code_ptr); --=20 2.17.1 From nobody Sun May 5 12:52:30 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1556034218; cv=none; d=zoho.com; s=zohoarc; b=ikyjTqtwhZnagG69PMInZ6mCKof6tPKOmhCmE/cdJhS/m6AHTaBgu0xGoW58LoFgCfp5uxBNDvjuL7HGT+78Xkpr3eQ1wnDpaO7+1i5YLxYAmO737b7qNySGVQNnI3adiTLOk8KCSKU3u+gBENJL56riaHjuKDH+Ntv3fG5MyaY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1556034218; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=SJOqjegP+m673OZYoqgV5dWxHoBCuzthxG6rISUB5Lg=; b=VSwslLwp5ejCP6S6HoZbRIcIq5U6ehXv1tm2iHy9Bvk8TNgcukAp4wEFNZniOjL9FsHSeIf5/wLvWKnwr5FdLt+TGP9IjLUX1+JAyIZGeJ28tiLtNV3lNNzaWDhW9bOApvjvfxtEFFYtobXWXvFpL18bBueYzuVW1c52/TI2i+U= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1556034218334906.950378791317; Tue, 23 Apr 2019 08:43:38 -0700 (PDT) Received: from localhost ([127.0.0.1]:55591 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hIxa1-0004hb-BJ for importer@patchew.org; Tue, 23 Apr 2019 11:43:33 -0400 Received: from eggs.gnu.org ([209.51.188.92]:35513) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hIxVf-00019T-Se for qemu-devel@nongnu.org; Tue, 23 Apr 2019 11:39:04 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hIxVe-0006xb-Sj for qemu-devel@nongnu.org; Tue, 23 Apr 2019 11:39:03 -0400 Received: from mail-pg1-x542.google.com ([2607:f8b0:4864:20::542]:35419) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hIxVe-0006x7-Mg for qemu-devel@nongnu.org; Tue, 23 Apr 2019 11:39:02 -0400 Received: by mail-pg1-x542.google.com with SMTP id g8so7813247pgf.2 for ; Tue, 23 Apr 2019 08:39:02 -0700 (PDT) Received: from localhost.localdomain (97-113-179-147.tukw.qwest.net. [97.113.179.147]) by smtp.gmail.com with ESMTPSA id c25sm24366591pfo.69.2019.04.23.08.39.00 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 23 Apr 2019 08:39:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=SJOqjegP+m673OZYoqgV5dWxHoBCuzthxG6rISUB5Lg=; b=RPpjm/wD0KiSqAmeZRidiNQ2unSolGymuPUL2cu5ZhSf3IC2frP4SRK/K28ZUEpaDk cUXpM9e6nyjpgmn8CI2GNV4Uvm3fY8xSUJ/HcA/8kvxYJy4+0oh/p9qtNHwlbXW2EZX/ VmOEIwSXFsIn0sn0okF+unf2CihX0Boq/u/nRF2BUUDAzRvt1OmGVmXZOG41PdtdvOZL 9GH0X66Jmmy2RLF7tCdsC1G/aJojJIVapiBX3yl1FalfcaufBzatfU6eLlqnhVvCL2Go zdy4qwjol4trb433/cZuO9TVXQ8aWVxViLjBQS77lZZMgohjbaqvlNqe3j1yKfb3dQzB yc0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=SJOqjegP+m673OZYoqgV5dWxHoBCuzthxG6rISUB5Lg=; b=p/ZwD6DKjexsZwK5KOnjybGwjDZDVD2+Vp/n9e+/1nkultEem+8d9oiG9zmQORFjtN B6lg5I4nwnCjtZ34YBnm+7weO1V6/RYSqOkGxr9T3I0n1eO3LJV3pN3TvbCeL5envAOc SiKqKCsFC1dHHH38/rkxsWKZRxc008qYXtxfTEi06UHrOy4bhFJn110sK7NafaHcjkQ1 MJP7cHEuuV6XycuG2t5a5JyzJUxV7VEn1JlkI0QX5vjaxvRKQBKUC95WQIoVgBj100qw NbnHYWgQcOzV83+lJTad9ANWkm1LSGG/3JaAkS1mtH3CDulmKpN+IOxCk3Gn2CJTGtrl bojA== X-Gm-Message-State: APjAAAVsoZ/oA7Bv1G1vzd0Ez++A2THQ96FUDB3v3SMTXg0wns7NynX9 u+5znj+9EetvCbps186dZyGBI0+WTR8= X-Google-Smtp-Source: APXvYqyx3aguO2hpm+z8MwU+kPJt9rLXyHz9RrbVqZVHP088cNSWv9vOLqoDC9FtIZcO9h8dcG6pFQ== X-Received: by 2002:a63:5a4b:: with SMTP id k11mr25055482pgm.119.1556033941333; Tue, 23 Apr 2019 08:39:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 23 Apr 2019 08:38:50 -0700 Message-Id: <20190423153853.19790-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190423153853.19790-1-richard.henderson@linaro.org> References: <20190423153853.19790-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::542 Subject: [Qemu-devel] [PATCH v2 4/7] tcg: Restart TB generation after constant pool overflow X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This is part b of relocation overflow handling. Signed-off-by: Richard Henderson --- tcg/tcg-pool.inc.c | 12 +++++++----- tcg/tcg.c | 9 +++++---- 2 files changed, 12 insertions(+), 9 deletions(-) diff --git a/tcg/tcg-pool.inc.c b/tcg/tcg-pool.inc.c index 7af5513ff3..4eaa84b631 100644 --- a/tcg/tcg-pool.inc.c +++ b/tcg/tcg-pool.inc.c @@ -121,14 +121,14 @@ static inline void new_pool_l8(TCGContext *s, int rty= pe, tcg_insn_unit *label, /* To be provided by cpu/tcg-target.inc.c. */ static void tcg_out_nop_fill(tcg_insn_unit *p, int count); =20 -static bool tcg_out_pool_finalize(TCGContext *s) +static int tcg_out_pool_finalize(TCGContext *s) { TCGLabelPoolData *p =3D s->pool_labels; TCGLabelPoolData *l =3D NULL; void *a; =20 if (p =3D=3D NULL) { - return true; + return 0; } =20 /* ??? Round up to qemu_icache_linesize, but then do not round @@ -142,15 +142,17 @@ static bool tcg_out_pool_finalize(TCGContext *s) size_t size =3D sizeof(tcg_target_ulong) * p->nlong; if (!l || l->nlong !=3D p->nlong || memcmp(l->data, p->data, size)= ) { if (unlikely(a > s->code_gen_highwater)) { - return false; + return -1; } memcpy(a, p->data, size); a +=3D size; l =3D p; } - patch_reloc(p->label, p->rtype, (intptr_t)a - size, p->addend); + if (!patch_reloc(p->label, p->rtype, (intptr_t)a - size, p->addend= )) { + return -2; + } } =20 s->code_ptr =3D a; - return true; + return 0; } diff --git a/tcg/tcg.c b/tcg/tcg.c index ab11235c42..50eb933efe 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1018,8 +1018,8 @@ void tcg_prologue_init(TCGContext *s) #ifdef TCG_TARGET_NEED_POOL_LABELS /* Allow the prologue to put e.g. guest_base into a pool entry. */ { - bool ok =3D tcg_out_pool_finalize(s); - tcg_debug_assert(ok); + int result =3D tcg_out_pool_finalize(s); + tcg_debug_assert(result =3D=3D 0); } #endif =20 @@ -4000,8 +4000,9 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) } #endif #ifdef TCG_TARGET_NEED_POOL_LABELS - if (!tcg_out_pool_finalize(s)) { - return -1; + i =3D tcg_out_pool_finalize(s); + if (i < 0) { + return i; } #endif if (!tcg_resolve_relocs(s)) { --=20 2.17.1 From nobody Sun May 5 12:52:30 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1556034081; cv=none; d=zoho.com; s=zohoarc; b=TszzlB72NprhZJGEU9tUzBkcvFUNW9WABdez4LqEHDCUHa3FnibreURXW21u+yWRmCnrwjvGet4ldKH3moFF3h6xUNAwGZVSZkZeQujg7T3pF5Lha3okzKV8yosbGQqugBnsUBR0BbF2vqWuezh0e9dF3ocYVUHh+HhpF0LYoyg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1556034081; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=Dr1xxtYX0/E9eW9xk4t7llMkf5skxlCLSQfUtFunfiQ=; b=HoKDnLDhq8qrIWrr6invB6yAOQCGU+iQm6J2Uz/DvX+Gm/ZoLkaGvYFWmENPRyjcf2o6cdYForkJikYYxajmOgTpkD0FTdpRVXLvobgcEWbebU/+A+y2GCkK8EboleLFZHSAx7O6Y5Vr2f0d6Tt2NDVz1TYQUwG+R1YH8B4v5C0= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1556034081560456.88240403842633; Tue, 23 Apr 2019 08:41:21 -0700 (PDT) Received: from localhost ([127.0.0.1]:55567 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hIxXp-0002Qb-Ai for importer@patchew.org; Tue, 23 Apr 2019 11:41:17 -0400 Received: from eggs.gnu.org ([209.51.188.92]:35565) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hIxVi-0001Be-EQ for qemu-devel@nongnu.org; Tue, 23 Apr 2019 11:39:12 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hIxVg-0006yo-84 for qemu-devel@nongnu.org; Tue, 23 Apr 2019 11:39:06 -0400 Received: from mail-pf1-x443.google.com ([2607:f8b0:4864:20::443]:33300) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hIxVf-0006xp-VX for qemu-devel@nongnu.org; Tue, 23 Apr 2019 11:39:04 -0400 Received: by mail-pf1-x443.google.com with SMTP id h5so7693282pfo.0 for ; Tue, 23 Apr 2019 08:39:03 -0700 (PDT) Received: from localhost.localdomain (97-113-179-147.tukw.qwest.net. [97.113.179.147]) by smtp.gmail.com with ESMTPSA id c25sm24366591pfo.69.2019.04.23.08.39.01 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 23 Apr 2019 08:39:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Dr1xxtYX0/E9eW9xk4t7llMkf5skxlCLSQfUtFunfiQ=; b=Jo0iVO4R+hTI+orPsVXhjqBZdcIqWlX2FSIFQCDjtQ2ClEHDo+LOBMznC0nmU5FCID MVHDpnWEPcLEa6u2nFKbwYtilyTVZ2prcv0Vzbjxl2j2sCDaIfsXI+wWZxmTvFzB7ojI dRCM0EWm4wKEDdFD62ydvFBVjEUWQoH1lX8h6CW8KjUXF+cvqD+Jh983z74T/voll8ol +OnZ8n/dC6Lgzn/MUebcJiLRuOG1SY6Sl0ySQP2Q2TnUoRg5v5mKjxHusCY0pB4i7GVn 87z+Z/Rpbl/dQZ+f8GnpYo9QF7XzSv7/q2CxbXYDjOav9N5/Mz6IHp/YyrVFMRJSs48L ajmw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Dr1xxtYX0/E9eW9xk4t7llMkf5skxlCLSQfUtFunfiQ=; b=MQxk+NFgRk6FHrRhBpmDti8IsvuX/suXFiEB4g9xc5FLR2f5D4yUlXRXDHoWMzUh7Z YQ8VOBfjWmrnrXO+5zFV3CsC9l3d/spEeigZ7NLgW+xmNW7V/br3ry/ZHYeeGjWMwrM1 Xq7X/Cw3ZmlHVjWEk6FVU3jlmG4oKpscJWQzMsz4JvqUYu4FudjIt8GThwEle0T5G8Kc 7yscxAAgSXrhY9GFncsS+dFCDJHGQOPN4AqsTf+8dX6KxjpPEi76rjgsJAKbIRqb8ExG q9DdrZmohHFmr5gDsKBKyytLLV5zQ8IHiail+MCgWfO8XtcANlJT9STO0pp2zyDthLEW Qj9Q== X-Gm-Message-State: APjAAAXSP6kNEOkhcw3nRTJb0WsgTZcLnIIU7qB2ofLcibjh8ztWDJuL fEYxgacHTynwivORf/FrXCps+q67nGg= X-Google-Smtp-Source: APXvYqw0fmx07Gq2mAeI89HhOrUX97V5YUC7iJ1Pxeh3FGzmlns+a6ayU0wdG42CtmOMjAM0AoaA2Q== X-Received: by 2002:a65:4481:: with SMTP id l1mr25075520pgq.66.1556033942498; Tue, 23 Apr 2019 08:39:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 23 Apr 2019 08:38:51 -0700 Message-Id: <20190423153853.19790-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190423153853.19790-1-richard.henderson@linaro.org> References: <20190423153853.19790-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::443 Subject: [Qemu-devel] [PATCH v2 5/7] tcg: Restart TB generation after out-of-line ldst overflow X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This is part c of relocation overflow handling. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.inc.c | 16 ++++++++++------ tcg/arm/tcg-target.inc.c | 16 ++++++++++------ tcg/i386/tcg-target.inc.c | 6 ++++-- tcg/mips/tcg-target.inc.c | 6 ++++-- tcg/ppc/tcg-target.inc.c | 14 ++++++++++---- tcg/riscv/tcg-target.inc.c | 16 ++++++++++++---- tcg/s390/tcg-target.inc.c | 20 ++++++++++++-------- tcg/tcg-ldst.inc.c | 18 +++++++++--------- tcg/tcg.c | 7 ++++--- 9 files changed, 75 insertions(+), 44 deletions(-) diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c index d57f9e500f..16713b0281 100644 --- a/tcg/aarch64/tcg-target.inc.c +++ b/tcg/aarch64/tcg-target.inc.c @@ -1395,14 +1395,15 @@ static inline void tcg_out_adr(TCGContext *s, TCGRe= g rd, void *target) tcg_out_insn(s, 3406, ADR, rd, offset); } =20 -static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) +static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) { TCGMemOpIdx oi =3D lb->oi; TCGMemOp opc =3D get_memop(oi); TCGMemOp size =3D opc & MO_SIZE; =20 - bool ok =3D reloc_pc19(lb->label_ptr[0], s->code_ptr); - tcg_debug_assert(ok); + if (!reloc_pc19(lb->label_ptr[0], s->code_ptr)) { + return false; + } =20 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_X0, TCG_AREG0); tcg_out_mov(s, TARGET_LONG_BITS =3D=3D 64, TCG_REG_X1, lb->addrlo_reg); @@ -1416,16 +1417,18 @@ static void tcg_out_qemu_ld_slow_path(TCGContext *s= , TCGLabelQemuLdst *lb) } =20 tcg_out_goto(s, lb->raddr); + return true; } =20 -static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) +static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) { TCGMemOpIdx oi =3D lb->oi; TCGMemOp opc =3D get_memop(oi); TCGMemOp size =3D opc & MO_SIZE; =20 - bool ok =3D reloc_pc19(lb->label_ptr[0], s->code_ptr); - tcg_debug_assert(ok); + if (!reloc_pc19(lb->label_ptr[0], s->code_ptr)) { + return false; + } =20 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_X0, TCG_AREG0); tcg_out_mov(s, TARGET_LONG_BITS =3D=3D 64, TCG_REG_X1, lb->addrlo_reg); @@ -1434,6 +1437,7 @@ static void tcg_out_qemu_st_slow_path(TCGContext *s, = TCGLabelQemuLdst *lb) tcg_out_adr(s, TCG_REG_X4, lb->raddr); tcg_out_call(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]); tcg_out_goto(s, lb->raddr); + return true; } =20 static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi, diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c index 2245a8aeb9..0514b0ac25 100644 --- a/tcg/arm/tcg-target.inc.c +++ b/tcg/arm/tcg-target.inc.c @@ -1372,15 +1372,16 @@ static void add_qemu_ldst_label(TCGContext *s, bool= is_ld, TCGMemOpIdx oi, label->label_ptr[0] =3D label_ptr; } =20 -static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) +static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) { TCGReg argreg, datalo, datahi; TCGMemOpIdx oi =3D lb->oi; TCGMemOp opc =3D get_memop(oi); void *func; =20 - bool ok =3D reloc_pc24(lb->label_ptr[0], s->code_ptr); - tcg_debug_assert(ok); + if (!reloc_pc24(lb->label_ptr[0], s->code_ptr)) { + return false; + } =20 argreg =3D tcg_out_arg_reg32(s, TCG_REG_R0, TCG_AREG0); if (TARGET_LONG_BITS =3D=3D 64) { @@ -1432,16 +1433,18 @@ static void tcg_out_qemu_ld_slow_path(TCGContext *s= , TCGLabelQemuLdst *lb) } =20 tcg_out_goto(s, COND_AL, lb->raddr); + return true; } =20 -static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) +static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) { TCGReg argreg, datalo, datahi; TCGMemOpIdx oi =3D lb->oi; TCGMemOp opc =3D get_memop(oi); =20 - bool ok =3D reloc_pc24(lb->label_ptr[0], s->code_ptr); - tcg_debug_assert(ok); + if (!reloc_pc24(lb->label_ptr[0], s->code_ptr)) { + return false; + } =20 argreg =3D TCG_REG_R0; argreg =3D tcg_out_arg_reg32(s, argreg, TCG_AREG0); @@ -1474,6 +1477,7 @@ static void tcg_out_qemu_st_slow_path(TCGContext *s, = TCGLabelQemuLdst *lb) =20 /* Tail-call to the helper, which will return to the fast path. */ tcg_out_goto(s, COND_AL, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]); + return true; } #endif /* SOFTMMU */ =20 diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index e0670e5098..01ca7837fc 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -1729,7 +1729,7 @@ static void add_qemu_ldst_label(TCGContext *s, bool i= s_ld, bool is_64, /* * Generate code for the slow path for a load at the end of block */ -static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) +static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) { TCGMemOpIdx oi =3D l->oi; TCGMemOp opc =3D get_memop(oi); @@ -1808,12 +1808,13 @@ static void tcg_out_qemu_ld_slow_path(TCGContext *s= , TCGLabelQemuLdst *l) =20 /* Jump to the code corresponding to next IR of qemu_st */ tcg_out_jmp(s, l->raddr); + return true; } =20 /* * Generate code for the slow path for a store at the end of block */ -static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) +static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) { TCGMemOpIdx oi =3D l->oi; TCGMemOp opc =3D get_memop(oi); @@ -1876,6 +1877,7 @@ static void tcg_out_qemu_st_slow_path(TCGContext *s, = TCGLabelQemuLdst *l) /* "Tail call" to the helper, with the return address back inline. */ tcg_out_push(s, retaddr); tcg_out_jmp(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]); + return true; } #elif TCG_TARGET_REG_BITS =3D=3D 32 # define x86_guest_base_seg 0 diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c index 8a92e916dd..412cacdcb9 100644 --- a/tcg/mips/tcg-target.inc.c +++ b/tcg/mips/tcg-target.inc.c @@ -1338,7 +1338,7 @@ static void add_qemu_ldst_label(TCGContext *s, int is= _ld, TCGMemOpIdx oi, } } =20 -static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) +static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) { TCGMemOpIdx oi =3D l->oi; TCGMemOp opc =3D get_memop(oi); @@ -1385,9 +1385,10 @@ static void tcg_out_qemu_ld_slow_path(TCGContext *s,= TCGLabelQemuLdst *l) } else { tcg_out_opc_reg(s, OPC_OR, v0, TCG_REG_V0, TCG_REG_ZERO); } + return true; } =20 -static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) +static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) { TCGMemOpIdx oi =3D l->oi; TCGMemOp opc =3D get_memop(oi); @@ -1435,6 +1436,7 @@ static void tcg_out_qemu_st_slow_path(TCGContext *s, = TCGLabelQemuLdst *l) tcg_out_call_int(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)], true); /* delay slot */ tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_AREG0); + return true; } #endif =20 diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index 773690f1d9..c0923ced4f 100644 --- a/tcg/ppc/tcg-target.inc.c +++ b/tcg/ppc/tcg-target.inc.c @@ -1653,13 +1653,15 @@ static void add_qemu_ldst_label(TCGContext *s, bool= is_ld, TCGMemOpIdx oi, label->label_ptr[0] =3D lptr; } =20 -static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) +static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) { TCGMemOpIdx oi =3D lb->oi; TCGMemOp opc =3D get_memop(oi); TCGReg hi, lo, arg =3D TCG_REG_R3; =20 - **lb->label_ptr |=3D reloc_pc14_val(*lb->label_ptr, s->code_ptr); + if (!reloc_pc14(lb->label_ptr[0], s->code_ptr)) { + return false; + } =20 tcg_out_mov(s, TCG_TYPE_PTR, arg++, TCG_AREG0); =20 @@ -1695,16 +1697,19 @@ static void tcg_out_qemu_ld_slow_path(TCGContext *s= , TCGLabelQemuLdst *lb) } =20 tcg_out_b(s, 0, lb->raddr); + return true; } =20 -static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) +static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) { TCGMemOpIdx oi =3D lb->oi; TCGMemOp opc =3D get_memop(oi); TCGMemOp s_bits =3D opc & MO_SIZE; TCGReg hi, lo, arg =3D TCG_REG_R3; =20 - **lb->label_ptr |=3D reloc_pc14_val(*lb->label_ptr, s->code_ptr); + if (!reloc_pc14(lb->label_ptr[0], s->code_ptr)) { + return false; + } =20 tcg_out_mov(s, TCG_TYPE_PTR, arg++, TCG_AREG0); =20 @@ -1753,6 +1758,7 @@ static void tcg_out_qemu_st_slow_path(TCGContext *s, = TCGLabelQemuLdst *lb) tcg_out_call(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]); =20 tcg_out_b(s, 0, lb->raddr); + return true; } #endif /* SOFTMMU */ =20 diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c index b785f4acb7..2932505094 100644 --- a/tcg/riscv/tcg-target.inc.c +++ b/tcg/riscv/tcg-target.inc.c @@ -1065,7 +1065,7 @@ static void add_qemu_ldst_label(TCGContext *s, int is= _ld, TCGMemOpIdx oi, label->label_ptr[0] =3D label_ptr[0]; } =20 -static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) +static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) { TCGMemOpIdx oi =3D l->oi; TCGMemOp opc =3D get_memop(oi); @@ -1080,7 +1080,10 @@ static void tcg_out_qemu_ld_slow_path(TCGContext *s,= TCGLabelQemuLdst *l) } =20 /* resolve label address */ - patch_reloc(l->label_ptr[0], R_RISCV_BRANCH, (intptr_t) s->code_ptr, 0= ); + if (!patch_reloc(l->label_ptr[0], R_RISCV_BRANCH, + (intptr_t) s->code_ptr, 0)) { + return false; + } =20 /* call load helper */ tcg_out_mov(s, TCG_TYPE_PTR, a0, TCG_AREG0); @@ -1092,9 +1095,10 @@ static void tcg_out_qemu_ld_slow_path(TCGContext *s,= TCGLabelQemuLdst *l) tcg_out_mov(s, (opc & MO_SIZE) =3D=3D MO_64, l->datalo_reg, a0); =20 tcg_out_goto(s, l->raddr); + return true; } =20 -static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) +static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) { TCGMemOpIdx oi =3D l->oi; TCGMemOp opc =3D get_memop(oi); @@ -1111,7 +1115,10 @@ static void tcg_out_qemu_st_slow_path(TCGContext *s,= TCGLabelQemuLdst *l) } =20 /* resolve label address */ - patch_reloc(l->label_ptr[0], R_RISCV_BRANCH, (intptr_t) s->code_ptr, 0= ); + if (!patch_reloc(l->label_ptr[0], R_RISCV_BRANCH, + (intptr_t) s->code_ptr, 0)) { + return false; + } =20 /* call store helper */ tcg_out_mov(s, TCG_TYPE_PTR, a0, TCG_AREG0); @@ -1133,6 +1140,7 @@ static void tcg_out_qemu_st_slow_path(TCGContext *s, = TCGLabelQemuLdst *l) tcg_out_call(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SSIZE)]); =20 tcg_out_goto(s, l->raddr); + return true; } #endif /* CONFIG_SOFTMMU */ =20 diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c index 7db90b3bae..3d6150b10e 100644 --- a/tcg/s390/tcg-target.inc.c +++ b/tcg/s390/tcg-target.inc.c @@ -1609,16 +1609,17 @@ static void add_qemu_ldst_label(TCGContext *s, bool= is_ld, TCGMemOpIdx oi, label->label_ptr[0] =3D label_ptr; } =20 -static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) +static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) { TCGReg addr_reg =3D lb->addrlo_reg; TCGReg data_reg =3D lb->datalo_reg; TCGMemOpIdx oi =3D lb->oi; TCGMemOp opc =3D get_memop(oi); =20 - bool ok =3D patch_reloc(lb->label_ptr[0], R_390_PC16DBL, - (intptr_t)s->code_ptr, 2); - tcg_debug_assert(ok); + if (!patch_reloc(lb->label_ptr[0], R_390_PC16DBL, + (intptr_t)s->code_ptr, 2)) { + return false; + } =20 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_R2, TCG_AREG0); if (TARGET_LONG_BITS =3D=3D 64) { @@ -1630,18 +1631,20 @@ static void tcg_out_qemu_ld_slow_path(TCGContext *s= , TCGLabelQemuLdst *lb) tcg_out_mov(s, TCG_TYPE_I64, data_reg, TCG_REG_R2); =20 tgen_gotoi(s, S390_CC_ALWAYS, lb->raddr); + return true; } =20 -static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) +static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) { TCGReg addr_reg =3D lb->addrlo_reg; TCGReg data_reg =3D lb->datalo_reg; TCGMemOpIdx oi =3D lb->oi; TCGMemOp opc =3D get_memop(oi); =20 - bool ok =3D patch_reloc(lb->label_ptr[0], R_390_PC16DBL, - (intptr_t)s->code_ptr, 2); - tcg_debug_assert(ok); + if (!patch_reloc(lb->label_ptr[0], R_390_PC16DBL, + (intptr_t)s->code_ptr, 2)) { + return false; + } =20 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_R2, TCG_AREG0); if (TARGET_LONG_BITS =3D=3D 64) { @@ -1668,6 +1671,7 @@ static void tcg_out_qemu_st_slow_path(TCGContext *s, = TCGLabelQemuLdst *lb) tcg_out_call(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]); =20 tgen_gotoi(s, S390_CC_ALWAYS, lb->raddr); + return true; } #else static void tcg_prepare_user_ldst(TCGContext *s, TCGReg *addr_reg, diff --git a/tcg/tcg-ldst.inc.c b/tcg/tcg-ldst.inc.c index 47f41b921b..05f9b3ccd6 100644 --- a/tcg/tcg-ldst.inc.c +++ b/tcg/tcg-ldst.inc.c @@ -38,19 +38,19 @@ typedef struct TCGLabelQemuLdst { * Generate TB finalization at the end of block */ =20 -static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l); -static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l); +static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l); +static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l); =20 -static bool tcg_out_ldst_finalize(TCGContext *s) +static int tcg_out_ldst_finalize(TCGContext *s) { TCGLabelQemuLdst *lb; =20 /* qemu_ld/st slow paths */ QSIMPLEQ_FOREACH(lb, &s->ldst_labels, next) { - if (lb->is_ld) { - tcg_out_qemu_ld_slow_path(s, lb); - } else { - tcg_out_qemu_st_slow_path(s, lb); + if (lb->is_ld + ? !tcg_out_qemu_ld_slow_path(s, lb) + : !tcg_out_qemu_st_slow_path(s, lb)) { + return -2; } =20 /* Test for (pending) buffer overflow. The assumption is that any @@ -58,10 +58,10 @@ static bool tcg_out_ldst_finalize(TCGContext *s) the buffer completely. Thus we can test for overflow after generating code without having to check during generation. */ if (unlikely((void *)s->code_ptr > s->code_gen_highwater)) { - return false; + return -1; } } - return true; + return 0; } =20 /* diff --git a/tcg/tcg.c b/tcg/tcg.c index 50eb933efe..f54ba97b16 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -127,7 +127,7 @@ static void tcg_out_call(TCGContext *s, tcg_insn_unit *= target); static int tcg_target_const_match(tcg_target_long val, TCGType type, const TCGArgConstraint *arg_ct); #ifdef TCG_TARGET_NEED_LDST_LABELS -static bool tcg_out_ldst_finalize(TCGContext *s); +static int tcg_out_ldst_finalize(TCGContext *s); #endif =20 #define TCG_HIGHWATER 1024 @@ -3995,8 +3995,9 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) =20 /* Generate TB finalization at the end of block */ #ifdef TCG_TARGET_NEED_LDST_LABELS - if (!tcg_out_ldst_finalize(s)) { - return -1; + i =3D tcg_out_ldst_finalize(s); + if (i < 0) { + return i; } #endif #ifdef TCG_TARGET_NEED_POOL_LABELS --=20 2.17.1 From nobody Sun May 5 12:52:30 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1556034081; cv=none; d=zoho.com; s=zohoarc; b=E2gbmBl+qtrtJtjCLGSe6p7q5DIPErReMTgWBINUVMP5jDM8YEqb7wDm+VF8KJZXjHejK5hWstnGWQOiJBvaNcTuISxwL4O13Yuz7HI4tuzEp+aSRUH0M565yXsZFW8oDjOrLbPZZ7jqVNGJi9yjo9AUGWCGi9rV/cunKo3vVMY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1556034081; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=57LLTjI1nQcm9nBGSTBf3sb093E20lD7cyEUFj3ghB4=; b=UaZy4JKuQus6+GWvO4OcJs9/BvmYe+FBGZO1wJBVzABAECH8HzNVrzmWjFGFDDNQJZaJaBMO99wFmMDHuPnbH2o3tnLUl1lEASBWnIjFuFUoSmgRtnCG2nlx+uYz4iFoWlV3pxQnILlt9vCytpktDAGeN1kmLuPxIOmKPfmhElc= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1556034081472731.3171048710037; Tue, 23 Apr 2019 08:41:21 -0700 (PDT) Received: from localhost ([127.0.0.1]:55565 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hIxXg-0002Nm-4U for importer@patchew.org; Tue, 23 Apr 2019 11:41:08 -0400 Received: from eggs.gnu.org ([209.51.188.92]:35561) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hIxVi-0001BV-9X for qemu-devel@nongnu.org; Tue, 23 Apr 2019 11:39:07 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hIxVh-0006zj-9P for qemu-devel@nongnu.org; Tue, 23 Apr 2019 11:39:06 -0400 Received: from mail-pf1-x444.google.com ([2607:f8b0:4864:20::444]:38149) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hIxVh-0006z8-2q for qemu-devel@nongnu.org; Tue, 23 Apr 2019 11:39:05 -0400 Received: by mail-pf1-x444.google.com with SMTP id 10so7684970pfo.5 for ; Tue, 23 Apr 2019 08:39:05 -0700 (PDT) Received: from localhost.localdomain (97-113-179-147.tukw.qwest.net. [97.113.179.147]) by smtp.gmail.com with ESMTPSA id c25sm24366591pfo.69.2019.04.23.08.39.02 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 23 Apr 2019 08:39:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=57LLTjI1nQcm9nBGSTBf3sb093E20lD7cyEUFj3ghB4=; b=qNuvcvhNnhZbx/yd/VUCDX//HI1BfjWUrDj+M8bOpioUZDA2dP4FCuMIXWb1iqxM7E GOcPJ5Q5fwbChkuX2/cNpOz5jiH9+eX/rO4D8ScTiq6fvT3CHu5L1Af3Rns6s9j5BqB1 Sk1ThWAiXdtl5leI85xLIch9DmbWPrCf4IoH9KQz+NnvGup6TmbOBesQnOen+gepWpKJ scH4Q/PYbkYZdb1ux8brs0g55QZCHxTY5MylEGwa4ZuOUMoCdoXUxEs4SxuIzb08mGAo wohYa3gQjP9H7xQj0LVp7V2lIBiU3nMsIK7cGwsWC75TaYt26LapEYEulSijB7i/iEfC IaUg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=57LLTjI1nQcm9nBGSTBf3sb093E20lD7cyEUFj3ghB4=; b=mRq/WDcS02Qfbuw+xcrwuYNQu5Rb6vS9ZbuoHlAhDYnMqZJg9P0FTZvjIoEGlMS7qD CaY78cN0kQrpcs13ZO3Dpf0HjtIBzFwTZfzkLZqwP1D/WFT3Xinkn9THmotH433xYDHy qd1wU+JeH3G7BQ4JyK+qGdYCRT0uOqT4//49N8BvGU6BJPt8TYK6lhFaiPaXD7an5Cxp q8q+sVZsIEYavu1SwC4lxOyYHC5ThHj53NWPdRlsWOLE+nK7t27muBSPEWW/EDflO0s6 WCgimJeYW7EXgjU37OzHqjSNedRIRiHqJQ/zUceGOKsB9nd+0wWX3AwhXumztfhqqF9A i48A== X-Gm-Message-State: APjAAAUtkSN8F6AHAv0Lf4sj//HY8CtWvUhPphSpP1CDF7unRvh+k83a M3qPQpAaSaIxEGD0t6ayvGCgysjy9Pk= X-Google-Smtp-Source: APXvYqw4adtsohSSdcizms8bvo2IsuIXBOSeO+RGpGkRcTFOiAYGmZAK7dh2Rl4E34+/xq4voFRTWg== X-Received: by 2002:a63:e048:: with SMTP id n8mr25323272pgj.41.1556033943708; Tue, 23 Apr 2019 08:39:03 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 23 Apr 2019 08:38:52 -0700 Message-Id: <20190423153853.19790-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190423153853.19790-1-richard.henderson@linaro.org> References: <20190423153853.19790-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH v2 6/7] tcg/ppc: Allow the constant pool to overflow at 32k X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" There is no point in coding for a 2GB offset when the max TB size is already limited to 64k. If we further restrict to 32k then we can eliminate the extra ADDIS instruction. Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.inc.c | 28 ++++++++++------------------ 1 file changed, 10 insertions(+), 18 deletions(-) diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index c0923ced4f..36b4791707 100644 --- a/tcg/ppc/tcg-target.inc.c +++ b/tcg/ppc/tcg-target.inc.c @@ -529,7 +529,6 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int ty= pe, intptr_t value, intptr_t addend) { tcg_insn_unit *target; - tcg_insn_unit old; =20 value +=3D addend; target =3D (tcg_insn_unit *)value; @@ -540,22 +539,16 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int = type, case R_PPC_REL24: return reloc_pc24(code_ptr, target); case R_PPC_ADDR16: - /* We are abusing this relocation type. This points to a pair - of insns, addis + load. If the displacement is small, we - can nop out the addis. */ - if (value =3D=3D (int16_t)value) { - code_ptr[0] =3D NOP; - old =3D deposit32(code_ptr[1], 0, 16, value); - code_ptr[1] =3D deposit32(old, 16, 5, TCG_REG_TB); - } else { - int16_t lo =3D value; - int hi =3D value - lo; - if (hi + lo !=3D value) { - return false; - } - code_ptr[0] =3D deposit32(code_ptr[0], 0, 16, hi >> 16); - code_ptr[1] =3D deposit32(code_ptr[1], 0, 16, lo); + /* + * We are (slightly) abusing this relocation type. In particular, + * assert that the low 2 bits are zero, and do not modify them. + * That way we can use this with LD et al that have opcode bits + * in the low 2 bits of the insn. + */ + if ((value & 3) || value !=3D (int16_t)value) { + return false; } + *code_ptr =3D (*code_ptr & ~0xfffc) | (value & 0xfffc); break; default: g_assert_not_reached(); @@ -701,8 +694,7 @@ static void tcg_out_movi_int(TCGContext *s, TCGType typ= e, TCGReg ret, if (!in_prologue && USE_REG_TB) { new_pool_label(s, arg, R_PPC_ADDR16, s->code_ptr, -(intptr_t)s->code_gen_ptr); - tcg_out32(s, ADDIS | TAI(ret, TCG_REG_TB, 0)); - tcg_out32(s, LD | TAI(ret, ret, 0)); + tcg_out32(s, LD | TAI(ret, TCG_REG_TB, 0)); return; } =20 --=20 2.17.1 From nobody Sun May 5 12:52:30 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1556034333; cv=none; d=zoho.com; s=zohoarc; b=OkzfbN5oG2b8xcQ89X3YIKCijay5Aefn1w3Sj0TrSyIk4emAeTNhv9WmGi2e1HgVh/gi3mzA5sUonZhXdzo+AG2gchMEFVwwW0U0geSZ4gLXi8rlI+nI6OuoIqv7u6nLHbhWWbZ+2m9IGCo9v7wdBroxSXrvzsI3uPOCJoSvOGo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1556034333; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=etFJ/jJqxo/gX9AJnnw5VNXWmGywWB8mmeO93OmpSSU=; b=ULW4ZHAt5/gxrYz9ehyuIV/P78DKJPicG69haRZmg9l/l2+7Dg+Vgj1GCoFY8MGJlWl5q44yyhR+S8V35lG2OCdLgvT4fL+0uFFGfpaoRVK6qhRJoCSmN3AsGYZxI+Td0vRgKvAzIqT+gP3Ug0rM5BzwLiQQR4kBxkzseOj7fH8= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1556034333479501.2520960398342; Tue, 23 Apr 2019 08:45:33 -0700 (PDT) Received: from localhost ([127.0.0.1]:55628 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hIxbu-0006CU-Gw for importer@patchew.org; Tue, 23 Apr 2019 11:45:30 -0400 Received: from eggs.gnu.org ([209.51.188.92]:35588) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hIxVk-0001D4-3X for qemu-devel@nongnu.org; Tue, 23 Apr 2019 11:39:12 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hIxVi-00071F-Rn for qemu-devel@nongnu.org; Tue, 23 Apr 2019 11:39:08 -0400 Received: from mail-pg1-x541.google.com ([2607:f8b0:4864:20::541]:45117) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hIxVi-00070M-LA for qemu-devel@nongnu.org; Tue, 23 Apr 2019 11:39:06 -0400 Received: by mail-pg1-x541.google.com with SMTP id y3so7786198pgk.12 for ; Tue, 23 Apr 2019 08:39:06 -0700 (PDT) Received: from localhost.localdomain (97-113-179-147.tukw.qwest.net. [97.113.179.147]) by smtp.gmail.com with ESMTPSA id c25sm24366591pfo.69.2019.04.23.08.39.03 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 23 Apr 2019 08:39:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=etFJ/jJqxo/gX9AJnnw5VNXWmGywWB8mmeO93OmpSSU=; b=jzgbkHifc0abmPHiZtAeTm0bryfoAm5kvYT9Xolo5gyj//anWu2C4KsJNQ+7/2GqC3 0yxKduAVuxgBgqG2Hqa0hUjf9dXNyqbo9xyl+TkR/5JoEErIyJKxHjPLNNMdyhCbvAWB 5it/q0YkaOdyN3W+inI+cta48J0A7VyCBpwY51HvfNilamCfCLxxIyMf1zbk2I20bf7r 2UZmSdyPIEx1IEqK84gXxJoZ+OLBx1PkODd3rX6ekFKgq5qDkmwStd2DSbfWCP8Yr515 Oywszf182Dio3MYL8LkJ7uChvTxZdN0R61TSoJZOBRvnoSIyn+sRHuwQprFUQNqJ9FlO W0Nw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=etFJ/jJqxo/gX9AJnnw5VNXWmGywWB8mmeO93OmpSSU=; b=I2kp3eKxEw72pZW2qNr78XvGEV2HYQJJMKPkjdnLg0pruU7WeKq6b0uXNqv3CfsiUV m3KHYrV7hrsv//RMW6ILgpkqndGCts4rxIWkz0XKSGYttaWn+5ITemaOpPfiEvjyz5kF E+4Udv85IuezR5td1bJKHMgEQHDdrEXSJyhkayZfNRBv3SCH7T528slwkMci9Z799vMP AGgBrWeabq/B2KLy/8ktDl+o5O60fu312JH82lfA9yJOeXd/kUg4lONiYNYA7OYyUT+X jOMEf2paQBQEYFpmL9vtan7Y0lCiR836W43OovQ1BYJ2ADI3dQXy1BqeioGo4uxulUiO ApOw== X-Gm-Message-State: APjAAAU0or1R0DR0asQ+oRFWUQEZWRRDPFomWzP52cPhamXAHC45J/9x RUpMEfik8cOpWEhVvaHxxrlVnQzYFwI= X-Google-Smtp-Source: APXvYqwmhZ/mifNyiO5vzOGyhy5H+UEd+42htPFUp8TLCozTMxdl45DRdhGpVo8CgGbWbIPoNGbO6g== X-Received: by 2002:a65:638f:: with SMTP id h15mr25225228pgv.147.1556033945214; Tue, 23 Apr 2019 08:39:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 23 Apr 2019 08:38:53 -0700 Message-Id: <20190423153853.19790-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190423153853.19790-1-richard.henderson@linaro.org> References: <20190423153853.19790-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH v2 7/7] tcg/arm: Restrict constant pool displacement to 12 bits X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Richard Henderson This will not necessarily restrict the size of the TB, since for v7 the majority of constant pool usage is for calls from the out-of-line ldst code, which is already at the end of the TB. But this does allow us to save one insn per reference on the off-chance. Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.inc.c | 57 +++++++++++++++------------------------- 1 file changed, 21 insertions(+), 36 deletions(-) diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c index 0514b0ac25..5515728295 100644 --- a/tcg/arm/tcg-target.inc.c +++ b/tcg/arm/tcg-target.inc.c @@ -197,6 +197,24 @@ static inline bool reloc_pc24(tcg_insn_unit *code_ptr,= tcg_insn_unit *target) return false; } =20 +static inline bool reloc_pc13(tcg_insn_unit *code_ptr, tcg_insn_unit *targ= et) +{ + ptrdiff_t offset =3D tcg_ptr_byte_diff(target, code_ptr) - 8; + + if (offset >=3D -0xfff && offset <=3D 0xfff) { + tcg_insn_unit insn =3D *code_ptr; + bool u =3D (offset >=3D 0); + if (!u) { + offset =3D -offset; + } + insn =3D deposit32(insn, 23, 1, u); + insn =3D deposit32(insn, 0, 12, offset); + *code_ptr =3D insn; + return true; + } + return false; +} + static bool patch_reloc(tcg_insn_unit *code_ptr, int type, intptr_t value, intptr_t addend) { @@ -205,39 +223,10 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int = type, if (type =3D=3D R_ARM_PC24) { return reloc_pc24(code_ptr, (tcg_insn_unit *)value); } else if (type =3D=3D R_ARM_PC13) { - intptr_t diff =3D value - (uintptr_t)(code_ptr + 2); - tcg_insn_unit insn =3D *code_ptr; - bool u; - - if (diff >=3D -0xfff && diff <=3D 0xfff) { - u =3D (diff >=3D 0); - if (!u) { - diff =3D -diff; - } - } else { - int rd =3D extract32(insn, 12, 4); - int rt =3D rd =3D=3D TCG_REG_PC ? TCG_REG_TMP : rd; - - if (diff < 0x1000 || diff >=3D 0x100000) { - return false; - } - - /* add rt, pc, #high */ - *code_ptr++ =3D ((insn & 0xf0000000) | (1 << 25) | ARITH_ADD - | (TCG_REG_PC << 16) | (rt << 12) - | (20 << 7) | (diff >> 12)); - /* ldr rd, [rt, #low] */ - insn =3D deposit32(insn, 12, 4, rt); - diff &=3D 0xfff; - u =3D 1; - } - insn =3D deposit32(insn, 23, 1, u); - insn =3D deposit32(insn, 0, 12, diff); - *code_ptr =3D insn; + return reloc_pc13(code_ptr, (tcg_insn_unit *)value); } else { g_assert_not_reached(); } - return true; } =20 #define TCG_CT_CONST_ARM 0x100 @@ -605,12 +594,8 @@ static inline void tcg_out_ld8s_r(TCGContext *s, int c= ond, TCGReg rt, =20 static void tcg_out_movi_pool(TCGContext *s, int cond, int rd, uint32_t ar= g) { - /* The 12-bit range on the ldr insn is sometimes a bit too small. - In order to get around that we require two insns, one of which - will usually be a nop, but may be replaced in patch_reloc. */ new_pool_label(s, arg, R_ARM_PC13, s->code_ptr, 0); tcg_out_ld32_12(s, cond, rd, TCG_REG_PC, 0); - tcg_out_nop(s); } =20 static void tcg_out_movi32(TCGContext *s, int cond, int rd, uint32_t arg) @@ -1069,8 +1054,8 @@ static void tcg_out_call(TCGContext *s, tcg_insn_unit= *addr) tcg_out_movi32(s, COND_AL, TCG_REG_TMP, addri); tcg_out_blx(s, COND_AL, TCG_REG_TMP); } else { - /* ??? Know that movi_pool emits exactly 2 insns. */ - tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_R14, TCG_REG_PC, 4); + /* ??? Know that movi_pool emits exactly 1 insn. */ + tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_R14, TCG_REG_PC, 0); tcg_out_movi_pool(s, COND_AL, TCG_REG_PC, addri); } } --=20 2.17.1