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[132.162.70.93]) by smtp.gmail.com with ESMTPSA id t67sm2487587ita.35.2019.04.19.08.40.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 19 Apr 2019 08:40:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oberlin-edu.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=7zqS2468sT/HtISYB7AAYD8azC667R2g/p5gFYHkaPE=; b=RA/J0VnLQievAa8YV5gFDgDFEDG+GF0UvMGCw8OO/4W3MWuGI548yNG3L3vGmkcFPA KrytLgINElecr0gGSKWpRcLJSPc7FifO/2dtgOzodIutrF08lSU7T8SiZrH3zR9+6ZJW GA1nr3yeIvp2GhCe8HeREdNN7Odg+9OcymbTVeR/yIs1A57RplG0Wbx96dbRVis/1xez PzyVUg7QAxz3e5kAJkBlUfZpti2pJ0je5ffif5d1u9rfzUnNODITxfsyv2C3rwFfeD92 PJ0CJ+y438y6jFx1uPWt7BYMIGzpw3SXDvfmEsy0P/TBK6H81/yPM/eBeCyUeLhbt/32 CHMw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=7zqS2468sT/HtISYB7AAYD8azC667R2g/p5gFYHkaPE=; b=i54pDCO5MGMWs/ru6OjfGTlSoTsXGgahPQ0DZTCj8mk0D71RpnSpeyrGpywL1gcPqP PQHJGCrba5erU3563ODcPUZUcbV2Bw2wtDfnziBcYwgIdN9ZtjIIPJoFFdKvoZ/vMO3r dYUXMVblxlHdAAaJEdM2zXPExBFa8wPFE2lNizn+SoTv/1oFP1rOtei8TsQ62Gi9D79F QDaSbcmMKWg59NHJz7ZzkeRuaKvxT+3TTs1HWg+wl3iq6aLmMgKBS1kwJxHLdjTIlkoU NxNuU2VATDkqLoJXSs0o4EZAZ/d/bH+UzNvuX6zFvCxzuhEQmukrV/2dDd37Rs/Fa5FG 0x7g== X-Gm-Message-State: APjAAAXwDhhjExzjkbVXmeazFr7VZ7llxs8P2KmKvd1A5Ash/J5yZzbA x7DkE8WPRLMoZtwyMEIFB4l8jw== X-Google-Smtp-Source: APXvYqxfEOYKQz7U56VO37UbsLPATlQlt8gjVfj0UOhpvmZwXNDRzSpWY0yOoVAQfhwy/8lo+oExeg== X-Received: by 2002:a24:ee83:: with SMTP id b125mr3801829iti.43.1555688452779; Fri, 19 Apr 2019 08:40:52 -0700 (PDT) From: Stephen Checkoway To: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paolo Bonzini , QEMU Developers , Artyom Tarasenko , Laurent Vivier , qemu-trivial@nongnu.org, =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Mark Cave-Ayland Date: Fri, 19 Apr 2019 11:40:41 -0400 Message-Id: <20190419154041.77802-1-stephen.checkoway@oberlin.edu> X-Mailer: git-send-email 2.20.1 (Apple Git-117) MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::143 Subject: [Qemu-devel] [PATCH v3] hw/char/escc: Lower irq when transmit buffer is filled X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stephen Checkoway Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) The SCC/ESCC will briefly stop asserting an interrupt when the transmit FIFO is filled. This code doesn't model the transmit FIFO/shift register so the pending transmit interrupt is never deasserted which means that an edge-triggered interrupt controller will never see the low-to-high transition it needs to raise another interrupt. The practical consequence of this is that guest firmware with an interrupt service routine for the ESCC that does not send all of the data it has immediately will stop sending data if the following sequence of events occurs: 1. Disable processor interrupts 2. Write a character to the ESCC 3. Add additional characters to a buffer which is drained by the ISR 4. Enable processor interrupts In this case, the first character will be sent, the interrupt will fire and the ISR will output the second character. Since the pending transmit interrupt remains asserted, no additional interrupts will ever fire. This behavior was triggered by firmware for an embedded system with a Z85C30 which necessitated this patch. This patch fixes that situation by explicitly lowering the IRQ when a character is written to the buffer and no other interrupts are currently pending. Signed-off-by: Stephen Checkoway Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- I added a sentence about the Z85C30 necessitating this to the commit messag= e. hw/char/escc.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/hw/char/escc.c b/hw/char/escc.c index 628f5f81f7..c5b05a63f1 100644 --- a/hw/char/escc.c +++ b/hw/char/escc.c @@ -509,6 +509,13 @@ static void escc_mem_write(void *opaque, hwaddr addr, break; case SERIAL_DATA: trace_escc_mem_writeb_data(CHN_C(s), val); + /* + * Lower the irq when data is written to the Tx buffer and no other + * interrupts are currently pending. The irq will be raised again = once + * the Tx buffer becomes empty below. + */ + s->txint =3D 0; + escc_update_irq(s); s->tx =3D val; if (s->wregs[W_TXCTRL2] & TXCTRL2_TXEN) { // tx enabled if (qemu_chr_fe_backend_connected(&s->chr)) { --=20 2.20.1 (Apple Git-117)