From nobody Mon Nov 10 11:19:24 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1555441266; cv=none; d=zoho.com; s=zohoarc; b=Hk39HwSmBoksHQNQ548jLD1l75KIGOl9BErev1RhscagnOhUqoSm/kjgEv4Xd47+HnmCahGBrRP7AZ1JJfRvkhCgmVaDgYIf0b9zK8B7YOpeZd67TcwWwiqXt5pq1vAbZ6Bo1R37VYmhPdkeicTurpR8t1BFM9TShLrzUJ2ZiUY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1555441266; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=A/Af4y1yJCSt+jtmFD6z5ctlF1gjQ48CTKDgJ8DX58Q=; b=KHemjAWCJARrjqVXVSzFammFl2toofkiPOjpYAsA4r/YHomzHEEg2pm0xycqX991K2i9RtEBz6KuA5wpwa5hd+sXBhSqlJCQEDxjMxNDXF80H98Aq2Pm76OT5sOIw1lT+Rg7eIsVc0pGsbedVT8mOSRSccCjo2dDYlEcGtD99QM= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1555441266862526.1573548875209; Tue, 16 Apr 2019 12:01:06 -0700 (PDT) Received: from localhost ([127.0.0.1]:41143 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hGTKA-0002WR-H6 for importer@patchew.org; Tue, 16 Apr 2019 15:00:54 -0400 Received: from eggs.gnu.org ([209.51.188.92]:54601) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hGTD9-0004nP-BR for qemu-devel@nongnu.org; Tue, 16 Apr 2019 14:53:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hGTD7-0004oh-4I for qemu-devel@nongnu.org; Tue, 16 Apr 2019 14:53:38 -0400 Received: from mx1.redhat.com ([209.132.183.28]:34754) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hGTD6-0004mD-Mg; Tue, 16 Apr 2019 14:53:37 -0400 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 80B40307D90F; Tue, 16 Apr 2019 18:53:35 +0000 (UTC) Received: from t460s.redhat.com (ovpn-116-105.ams2.redhat.com [10.36.116.105]) by smtp.corp.redhat.com (Postfix) with ESMTP id 078F05D707; Tue, 16 Apr 2019 18:53:33 +0000 (UTC) From: David Hildenbrand To: qemu-devel@nongnu.org Date: Tue, 16 Apr 2019 20:52:32 +0200 Message-Id: <20190416185301.25344-13-david@redhat.com> In-Reply-To: <20190416185301.25344-1-david@redhat.com> References: <20190416185301.25344-1-david@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.48]); Tue, 16 Apr 2019 18:53:35 +0000 (UTC) Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH v2 12/41] s390x/tcg: Implement VECTOR COUNT LEADING ZEROS X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , David Hildenbrand , Cornelia Huck , Richard Henderson , qemu-s390x@nongnu.org, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" For 8/16, use the 32 bit variant and properly subtract the added leading zero bits. Reviewed-by: Richard Henderson Signed-off-by: David Hildenbrand --- target/s390x/helper.h | 2 ++ target/s390x/insn-data.def | 2 ++ target/s390x/translate_vx.inc.c | 31 +++++++++++++++++++++++++++++++ target/s390x/vec_int_helper.c | 14 ++++++++++++++ 4 files changed, 49 insertions(+) diff --git a/target/s390x/helper.h b/target/s390x/helper.h index 21921397fe..670677427c 100644 --- a/target/s390x/helper.h +++ b/target/s390x/helper.h @@ -150,6 +150,8 @@ DEF_HELPER_FLAGS_4(gvec_vavg8, TCG_CALL_NO_RWG, void, p= tr, cptr, cptr, i32) DEF_HELPER_FLAGS_4(gvec_vavg16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i3= 2) DEF_HELPER_FLAGS_4(gvec_vavgl8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i3= 2) DEF_HELPER_FLAGS_4(gvec_vavgl16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i= 32) +DEF_HELPER_FLAGS_3(gvec_vclz8, TCG_CALL_NO_RWG, void, ptr, cptr, i32) +DEF_HELPER_FLAGS_3(gvec_vclz16, TCG_CALL_NO_RWG, void, ptr, cptr, i32) =20 #ifndef CONFIG_USER_ONLY DEF_HELPER_3(servc, i32, env, i64, i64) diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def index 1d159cb201..be3c07aafb 100644 --- a/target/s390x/insn-data.def +++ b/target/s390x/insn-data.def @@ -1084,6 +1084,8 @@ E(0xe7fb, VCH, VRR_b, V, 0, 0, 0, 0, vc, 0, TCG_COND_GT, IF_VEC) /* VECTOR COMPARE HIGH LOGICAL */ E(0xe7f9, VCHL, VRR_b, V, 0, 0, 0, 0, vc, 0, TCG_COND_GTU, IF_VEC) +/* VECTOR COUNT LEADING ZEROS */ + F(0xe753, VCLZ, VRR_a, V, 0, 0, 0, 0, vclz, 0, IF_VEC) =20 #ifndef CONFIG_USER_ONLY /* COMPARE AND SWAP AND PURGE */ diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.in= c.c index 3e4e28c742..5f17dbec3f 100644 --- a/target/s390x/translate_vx.inc.c +++ b/target/s390x/translate_vx.inc.c @@ -182,6 +182,9 @@ static void get_vec_element_ptr_i64(TCGv_ptr ptr, uint8= _t reg, TCGv_i64 enr, tcg_temp_free_i64(tmp); } =20 +#define gen_gvec_2(v1, v2, gen) \ + tcg_gen_gvec_2(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \ + 16, 16, gen) #define gen_gvec_3(v1, v2, v3, gen) \ tcg_gen_gvec_3(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \ vec_full_reg_offset(v3), 16, 16, gen) @@ -1413,3 +1416,31 @@ static DisasJumpType op_vc(DisasContext *s, DisasOps= *o) } return DISAS_NEXT; } + +static void gen_clz_i32(TCGv_i32 d, TCGv_i32 a) +{ + tcg_gen_clzi_i32(d, a, 32); +} + +static void gen_clz_i64(TCGv_i64 d, TCGv_i64 a) +{ + tcg_gen_clzi_i64(d, a, 64); +} + +static DisasJumpType op_vclz(DisasContext *s, DisasOps *o) +{ + const uint8_t es =3D get_field(s->fields, m3); + static const GVecGen2 g[4] =3D { + { .fno =3D gen_helper_gvec_vclz8, }, + { .fno =3D gen_helper_gvec_vclz16, }, + { .fni4 =3D gen_clz_i32, }, + { .fni8 =3D gen_clz_i64, }, + }; + + if (es > ES_64) { + gen_program_exception(s, PGM_SPECIFICATION); + return DISAS_NORETURN; + } + gen_gvec_2(get_field(s->fields, v1), get_field(s->fields, v2), &g[es]); + return DISAS_NEXT; +} diff --git a/target/s390x/vec_int_helper.c b/target/s390x/vec_int_helper.c index 8f97d3f466..016512547c 100644 --- a/target/s390x/vec_int_helper.c +++ b/target/s390x/vec_int_helper.c @@ -46,3 +46,17 @@ void HELPER(gvec_vavgl##BITS)(void *v1, const void *v2, = const void *v3, \ } DEF_VAVGL(8) DEF_VAVGL(16) + +#define DEF_VCLZ(BITS) = \ +void HELPER(gvec_vclz##BITS)(void *v1, const void *v2, uint32_t desc) = \ +{ = \ + int i; = \ + = \ + for (i =3D 0; i < (128 / BITS); i++) { = \ + const uint##BITS##_t a =3D s390_vec_read_element##BITS(v2, i); = \ + = \ + s390_vec_write_element##BITS(v1, i, clz32(a) - 32 + BITS); = \ + } = \ +} +DEF_VCLZ(8) +DEF_VCLZ(16) --=20 2.20.1