From nobody Mon Nov 10 11:17:35 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1555441425; cv=none; d=zoho.com; s=zohoarc; b=FLgf7upcwrff71EiWYDBqIH9j2SOhjmuxZ8+SfSy4ZDXbRJTJuy+eD8hnnxlUVQeo4z9b6dg99H20GY8Bo6NfFHg0hxEhEcdj4Ga60RMbcuH/hX9vC877XaSWHhxHU/mRFVO0vSM4ADQK55UZvzQ9Kcuw8BMw4xDnzO5Uqs1+A4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1555441425; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=911xwCwZxYiWISOmz7oLUYWP/jt9cHLeihZ6tOm0OyE=; b=N93c8qhZA8h0Q0TypvJGGhyEVImcQ/etW3SAxtEJUZIY34Nx/S8HVkE6fydCXnqsMDTeEBBUfEYOO1huA9FrJnOS2GcNFkkOkKPy0u6uLCbe6iAV0BurdxKGVjafUXREj2WfM5XFsTsKzPysktSBvl0yu6pF+NKRLGBUYMhwC8c= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1555441425099858.5690393129272; Tue, 16 Apr 2019 12:03:45 -0700 (PDT) Received: from localhost ([127.0.0.1]:41187 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hGTMq-0004iv-4T for importer@patchew.org; Tue, 16 Apr 2019 15:03:40 -0400 Received: from eggs.gnu.org ([209.51.188.92]:54507) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hGTD5-0004j9-A4 for qemu-devel@nongnu.org; Tue, 16 Apr 2019 14:53:36 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hGTD3-0004hR-1x for qemu-devel@nongnu.org; Tue, 16 Apr 2019 14:53:34 -0400 Received: from mx1.redhat.com ([209.132.183.28]:37606) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hGTD2-0004cF-Hf; Tue, 16 Apr 2019 14:53:32 -0400 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 229A88830F; Tue, 16 Apr 2019 18:53:30 +0000 (UTC) Received: from t460s.redhat.com (ovpn-116-105.ams2.redhat.com [10.36.116.105]) by smtp.corp.redhat.com (Postfix) with ESMTP id CA39B5D707; Tue, 16 Apr 2019 18:53:27 +0000 (UTC) From: David Hildenbrand To: qemu-devel@nongnu.org Date: Tue, 16 Apr 2019 20:52:29 +0200 Message-Id: <20190416185301.25344-10-david@redhat.com> In-Reply-To: <20190416185301.25344-1-david@redhat.com> References: <20190416185301.25344-1-david@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.28]); Tue, 16 Apr 2019 18:53:30 +0000 (UTC) Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH v2 09/41] s390x/tcg: Implement VECTOR CHECKSUM X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , David Hildenbrand , Cornelia Huck , Richard Henderson , qemu-s390x@nongnu.org, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Time to introduce read_vec_element_i32 and write_vec_element_i32. Take proper care of properly adding the carry. We can perform both additions including the carry via tcg_gen_add2_i32(). Reviewed-by: Richard Henderson Signed-off-by: David Hildenbrand --- target/s390x/insn-data.def | 2 + target/s390x/translate_vx.inc.c | 65 +++++++++++++++++++++++++++++++++ 2 files changed, 67 insertions(+) diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def index 9889dc0b01..64459465c5 100644 --- a/target/s390x/insn-data.def +++ b/target/s390x/insn-data.def @@ -1072,6 +1072,8 @@ F(0xe7f2, VAVG, VRR_c, V, 0, 0, 0, 0, vavg, 0, IF_VEC) /* VECTOR AVERAGE LOGICAL */ F(0xe7f0, VAVGL, VRR_c, V, 0, 0, 0, 0, vavgl, 0, IF_VEC) +/* VECTOR CHECKSUM */ + F(0xe766, VCKSM, VRR_c, V, 0, 0, 0, 0, vcksm, 0, IF_VEC) =20 #ifndef CONFIG_USER_ONLY /* COMPARE AND SWAP AND PURGE */ diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.in= c.c index 7e8418e585..0f90f981b6 100644 --- a/target/s390x/translate_vx.inc.c +++ b/target/s390x/translate_vx.inc.c @@ -90,6 +90,33 @@ static void read_vec_element_i64(TCGv_i64 dst, uint8_t r= eg, uint8_t enr, } } =20 +static void read_vec_element_i32(TCGv_i32 dst, uint8_t reg, uint8_t enr, + TCGMemOp memop) +{ + const int offs =3D vec_reg_offset(reg, enr, memop & MO_SIZE); + + switch (memop) { + case ES_8: + tcg_gen_ld8u_i32(dst, cpu_env, offs); + break; + case ES_16: + tcg_gen_ld16u_i32(dst, cpu_env, offs); + break; + case ES_8 | MO_SIGN: + tcg_gen_ld8s_i32(dst, cpu_env, offs); + break; + case ES_16 | MO_SIGN: + tcg_gen_ld16s_i32(dst, cpu_env, offs); + break; + case ES_32: + case ES_32 | MO_SIGN: + tcg_gen_ld_i32(dst, cpu_env, offs); + break; + default: + g_assert_not_reached(); + } +} + static void write_vec_element_i64(TCGv_i64 src, int reg, uint8_t enr, TCGMemOp memop) { @@ -113,6 +140,25 @@ static void write_vec_element_i64(TCGv_i64 src, int re= g, uint8_t enr, } } =20 +static void write_vec_element_i32(TCGv_i32 src, int reg, uint8_t enr, + TCGMemOp memop) +{ + const int offs =3D vec_reg_offset(reg, enr, memop & MO_SIZE); + + switch (memop) { + case ES_8: + tcg_gen_st8_i32(src, cpu_env, offs); + break; + case ES_16: + tcg_gen_st16_i32(src, cpu_env, offs); + break; + case ES_32: + tcg_gen_st_i32(src, cpu_env, offs); + break; + default: + g_assert_not_reached(); + } +} =20 static void get_vec_element_ptr_i64(TCGv_ptr ptr, uint8_t reg, TCGv_i64 en= r, uint8_t es) @@ -1300,3 +1346,22 @@ static DisasJumpType op_vavgl(DisasContext *s, Disas= Ops *o) get_field(s->fields, v3), &g[es]); return DISAS_NEXT; } + +static DisasJumpType op_vcksm(DisasContext *s, DisasOps *o) +{ + TCGv_i32 tmp =3D tcg_temp_new_i32(); + TCGv_i32 sum =3D tcg_temp_new_i32(); + int i; + + read_vec_element_i32(sum, get_field(s->fields, v3), 1, ES_32); + for (i =3D 0; i < 4; i++) { + read_vec_element_i32(tmp, get_field(s->fields, v2), i, ES_32); + tcg_gen_add2_i32(tmp, sum, sum, sum, tmp, tmp); + } + zero_vec(get_field(s->fields, v1)); + write_vec_element_i32(sum, get_field(s->fields, v1), 1, ES_32); + + tcg_temp_free_i32(tmp); + tcg_temp_free_i32(sum); + return DISAS_NEXT; +} --=20 2.20.1