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X-Received-From: 2a00:1450:4864:20::442 Subject: [Qemu-devel] [PATCH 08/26] target/arm: Handle SFPA and FPCA bits in reads and writes of CONTROL X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The M-profile CONTROL register has two bits -- SFPA and FPCA -- which relate to floating-point support, and should be RES0 otherwise. Handle them correctly in the MSR/MRS register access code. Neither is banked between security states, so they are stored in v7m.control[M_REG_S] regardless of current security state. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper.c | 57 ++++++++++++++++++++++++++++++++++++++------- 1 file changed, 49 insertions(+), 8 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index b4f1609a1c6..297eb38fef0 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -12032,7 +12032,14 @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_= t reg) return xpsr_read(env) & mask; break; case 20: /* CONTROL */ - return env->v7m.control[env->v7m.secure]; + { + uint32_t value =3D env->v7m.control[env->v7m.secure]; + if (!env->v7m.secure) { + /* SFPA is RAZ/WI from NS; FPCA is stored in the M_REG_S bank = */ + value |=3D env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK; + } + return value; + } case 0x94: /* CONTROL_NS */ /* We have to handle this here because unprivileged Secure code * can read the NS CONTROL register. @@ -12040,7 +12047,8 @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t= reg) if (!env->v7m.secure) { return 0; } - return env->v7m.control[M_REG_NS]; + return env->v7m.control[M_REG_NS] | + (env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK); } =20 if (el =3D=3D 0) { @@ -12146,9 +12154,13 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t ma= skreg, uint32_t val) */ uint32_t mask =3D extract32(maskreg, 8, 4); uint32_t reg =3D extract32(maskreg, 0, 8); + int cur_el =3D arm_current_el(env); =20 - if (arm_current_el(env) =3D=3D 0 && reg > 7) { - /* only xPSR sub-fields may be written by unprivileged */ + if (cur_el =3D=3D 0 && reg > 7 && reg !=3D 20) { + /* + * only xPSR sub-fields and CONTROL.SFPA may be written by + * unprivileged code + */ return; } =20 @@ -12207,6 +12219,15 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t ma= skreg, uint32_t val) env->v7m.control[M_REG_NS] &=3D ~R_V7M_CONTROL_NPRIV_MASK; env->v7m.control[M_REG_NS] |=3D val & R_V7M_CONTROL_NPRIV_= MASK; } + /* + * SFPA is RAZ/WI from NS. FPCA is RO if NSACR.CP10 =3D=3D 0, + * RES0 if the FPU is not present, and is stored in the S bank + */ + if (arm_feature(env, ARM_FEATURE_VFP) && + extract32(env->v7m.nsacr, 10, 1)) { + env->v7m.control[M_REG_S] &=3D ~R_V7M_CONTROL_FPCA_MASK; + env->v7m.control[M_REG_S] |=3D val & R_V7M_CONTROL_FPCA_MA= SK; + } return; case 0x98: /* SP_NS */ { @@ -12309,21 +12330,41 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t m= askreg, uint32_t val) env->v7m.faultmask[env->v7m.secure] =3D val & 1; break; case 20: /* CONTROL */ - /* Writing to the SPSEL bit only has an effect if we are in + /* + * Writing to the SPSEL bit only has an effect if we are in * thread mode; other bits can be updated by any privileged code. * write_v7m_control_spsel() deals with updating the SPSEL bit in * env->v7m.control, so we only need update the others. * For v7M, we must just ignore explicit writes to SPSEL in handler * mode; for v8M the write is permitted but will have no effect. + * All these bits are writes-ignored from non-privileged code, + * except for SFPA. */ - if (arm_feature(env, ARM_FEATURE_V8) || - !arm_v7m_is_handler_mode(env)) { + if (cur_el > 0 && (arm_feature(env, ARM_FEATURE_V8) || + !arm_v7m_is_handler_mode(env))) { write_v7m_control_spsel(env, (val & R_V7M_CONTROL_SPSEL_MASK) = !=3D 0); } - if (arm_feature(env, ARM_FEATURE_M_MAIN)) { + if (cur_el > 0 && arm_feature(env, ARM_FEATURE_M_MAIN)) { env->v7m.control[env->v7m.secure] &=3D ~R_V7M_CONTROL_NPRIV_MA= SK; env->v7m.control[env->v7m.secure] |=3D val & R_V7M_CONTROL_NPR= IV_MASK; } + if (arm_feature(env, ARM_FEATURE_VFP)) { + /* + * SFPA is RAZ/WI from NS or if no FPU. + * FPCA is RO if NSACR.CP10 =3D=3D 0, RES0 if the FPU is not p= resent. + * Both are stored in the S bank. + */ + if (env->v7m.secure) { + env->v7m.control[M_REG_S] &=3D ~R_V7M_CONTROL_SFPA_MASK; + env->v7m.control[M_REG_S] |=3D val & R_V7M_CONTROL_SFPA_MA= SK; + } + if (cur_el > 0 && + (env->v7m.secure || !arm_feature(env, ARM_FEATURE_M_SECURI= TY) || + extract32(env->v7m.nsacr, 10, 1))) { + env->v7m.control[M_REG_S] &=3D ~R_V7M_CONTROL_FPCA_MASK; + env->v7m.control[M_REG_S] |=3D val & R_V7M_CONTROL_FPCA_MA= SK; + } + } break; default: bad_reg: --=20 2.20.1