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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id v184sm39476572wma.6.2019.04.16.05.58.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 16 Apr 2019 05:58:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=tbRH/Ezbfxbs3Pgygk5ZQu6eKyrO+ofFIElvSltfNOo=; b=A9vP0bpklygXGRW0rxA0JfeHZRuzpet/z9aiLVI13QTur7CangcXFT15WZhWyGz4rD vcshJX0Yb6E6KhAPvL+/Sylnc0izQHA21p8aWkNDjephbziESyRc5Y/wUCi/OprmbyZ/ kdcfm55GuNrIPMLEqMoPTzNpmsowRD5O4Ra5Xi8+11DyxiGcAl5t4lHcLVLJfT/JFJ5+ 2q/6+5IxTb7163KpS0l3U17skby3qtc7JBxfKcjtiFbBh0bAWvjqmyiD4kRjt+nH5Wo6 YbJKse8K5Bf7YYph8nNNlnc+ovkCFS9bbUJsO/JV4eVTutCDj3I1cIBFFvazHbmezZ6I R1sA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=tbRH/Ezbfxbs3Pgygk5ZQu6eKyrO+ofFIElvSltfNOo=; b=bkp8VbZEV8d5mpUp32TiSBTp/SBu10EUBIWmAayyOEp3Z+7k7vv5FrJ2JEtGr9lwy+ P3T5E9UmKtX6sdaaxpIfqygGEia8qegVuWTUIrnaS1yht3PpPTjF5lUJkP7+3BWUiHBq GBZ9W0+A/vy2mNezqS41ODVkyC/M63oWZZcgiZGduwJoi6QNyf9rsVUeP3TRjrHayOEk pDUX3SYuy+IgY1l+IMonWyN0ai8n/41WZbEr3D1cNvhC4V9Wef6rBcXe1krBg5Mj3QXk PZXRE/pt+GrxXV/jOUEPjZqmoJFWATQKq6glGgZjouPG/qJh0Trt4ZcjpRZhqKikOjgi dMJg== X-Gm-Message-State: APjAAAVNz1CDUk1ie4iqFE/JNMIQUbNjh3seWtcgR4Pd6+94IsMVyIhU lj/MmA6bhQL7wPzux/9WP0OfwtDYBZc= X-Google-Smtp-Source: APXvYqxSkPDEd2caSBKIaLh1p9TG26HbNa+sKD0jXmnYtpijNzsNIimzvnMqVhgMYo4OZTzDmDPUTg== X-Received: by 2002:adf:efc1:: with SMTP id i1mr51646257wrp.199.1555419502123; Tue, 16 Apr 2019 05:58:22 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 16 Apr 2019 13:57:34 +0100 Message-Id: <20190416125744.27770-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190416125744.27770-1-peter.maydell@linaro.org> References: <20190416125744.27770-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 Subject: [Qemu-devel] [PATCH 16/26] target/arm: Move NS TBFLAG from bit 19 to bit 6 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Move the NS TBFLAG down from bit 19 to bit 6, which has not been used since commit c1e3781090b9d36c60 in 2015, when we started passing the entire MMU index in the TB flags rather than just a 'privilege level' bit. This rearrangement is not strictly necessary, but means that we can put M-profile-only bits next to each other rather than scattered across the flag word. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu.h | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 0e0cb6b2271..c436f628987 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3139,6 +3139,12 @@ FIELD(TBFLAG_ANY, BE_DATA, 23, 1) FIELD(TBFLAG_A32, THUMB, 0, 1) FIELD(TBFLAG_A32, VECLEN, 1, 3) FIELD(TBFLAG_A32, VECSTRIDE, 4, 2) +/* + * Indicates whether cp register reads and writes by guest code should acc= ess + * the secure or nonsecure bank of banked registers; note that this is not + * the same thing as the current security state of the processor! + */ +FIELD(TBFLAG_A32, NS, 6, 1) FIELD(TBFLAG_A32, VFPEN, 7, 1) FIELD(TBFLAG_A32, CONDEXEC, 8, 8) FIELD(TBFLAG_A32, SCTLR_B, 16, 1) @@ -3146,11 +3152,6 @@ FIELD(TBFLAG_A32, SCTLR_B, 16, 1) * checks on the other bits at runtime */ FIELD(TBFLAG_A32, XSCALE_CPAR, 17, 2) -/* Indicates whether cp register reads and writes by guest code should acc= ess - * the secure or nonsecure bank of banked registers; note that this is not - * the same thing as the current security state of the processor! - */ -FIELD(TBFLAG_A32, NS, 19, 1) /* For M profile only, Handler (ie not Thread) mode */ FIELD(TBFLAG_A32, HANDLER, 21, 1) /* For M profile only, whether we should generate stack-limit checks */ --=20 2.20.1