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[2.103.80.5]) by smtp.gmail.com with ESMTPSA id g13sm7398293wmh.11.2019.04.12.18.13.49 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 12 Apr 2019 18:13:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=FeXe8RFIVGBeVpBLaXWlnd5FFTp3tZwvMuAxPZUccqw=; b=I06EI0piQdj2rjxRt9bF7uvs/UAshtxhBmtT7b6Y6DIVJC3hfc2EaVk/M1bss7AcTY xSfLpQ8ObfQkx4591tZA6QUjFshwlJxRvb51aYF0AzOVq03AOxsXXCMQ7wmT1vtuv8af RSKJXHthFInt9h9KIVB7NVZ24BnT5kaXJvfcSm88fwRmLSDur+jzForK2WOyqNT2qBsX kG0bK280GbxVZPn7PfALfy+/bOEPHQ35UMqw5iQ66pxnSliaDh7xrDwOjoZmRfghtC0c 7J259gQQyL7d7orxR/Za+etoWhZ62pcTwv545ukx8K5ZjuB+ryf401UBP56VDZ8/oSWE cRWw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=FeXe8RFIVGBeVpBLaXWlnd5FFTp3tZwvMuAxPZUccqw=; b=VKfl4Ta3Ct28uwtNE+Pl+V7hFj2A/agkZ4wBIUpa3JXG+bJmy5y7tFH9Q6cUESCGPQ d2YDGVXWBoTmF98YNXzLsSChe59MWPdWpcVm1EsJ58CbDilhqem65MA8+UNMCzjd1St+ OcabzQ99ikSCuUJ3EAgjWwSvgd3gvcMjMO6EBb6zub4UI3/9w1IhOdS9Ofcgs+YGB05D BH/JZFFrh07mgGlKAhJYC43zD5s3/Fx332WiuxUJWIVkE5sDmBpWlO2NgZYcqcK9gG4g 0aILhr3giHkvt52qxW9l8pEjN6z7+ueamT67x2v+plegb/OxE/dHIivH0Kv5mmEnQPqr BzFQ== X-Gm-Message-State: APjAAAVb8EpP/gKArLW23dvgOKu9aBXtzxo3kmN5YVWfOiBKzX2HHx9z cgjzmJBVipPLrH75y1756CPhnm/876GE X-Google-Smtp-Source: APXvYqz54MWqjpzvXzEwnC1HbdkyhNwAdeJlR/vZJDPBdZ3oGCefYAKODgEMLUXb/M/9FJNVX9ERdQ== X-Received: by 2002:a1c:d7:: with SMTP id 206mr12605541wma.69.1555118030683; Fri, 12 Apr 2019 18:13:50 -0700 (PDT) From: Jules Irenge To: qemu-devel@nongnu.org Date: Sat, 13 Apr 2019 02:13:00 +0100 Message-Id: <20190413011302.6610-2-jbi.octave@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190413011302.6610-1-jbi.octave@gmail.com> References: <20190413011302.6610-1-jbi.octave@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::342 Subject: [Qemu-devel] [PATCH v4 1/3] target/mips: add or remove space to fix checkpatch errors X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: arikalo@wavecomp.com, Jules Irenge , aurelien@aurel32.net, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Add or remove space to fix errors issued by checkpatch.pl tool "ERROR: spaces required around that..." "ERROR: space required after that..." "ERROR: space required before the open parenthesis" "ERROR: space required after that..." "ERROR: space prohibited between function name and open parenthesis" "ERROR: code indent should never use tabs" within "target/mips/cpu.h" file. Signed-off-by: Jules Irenge --- target/mips/cpu.h | 162 +++++++++++++++++++++++----------------------- 1 file changed, 81 insertions(+), 81 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index a10eeb0de3..4bfa24bda0 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -22,10 +22,10 @@ typedef struct CPUMIPSTLBContext CPUMIPSTLBContext; =20 typedef union wr_t wr_t; union wr_t { - int8_t b[MSA_WRLEN/8]; - int16_t h[MSA_WRLEN/16]; - int32_t w[MSA_WRLEN/32]; - int64_t d[MSA_WRLEN/64]; + int8_t b[MSA_WRLEN / 8]; + int16_t h[MSA_WRLEN / 16]; + int32_t w[MSA_WRLEN / 32]; + int64_t d[MSA_WRLEN / 64]; }; =20 typedef union fpr_t fpr_t; @@ -71,16 +71,16 @@ struct CPUMIPSFPUContext { #define FCR31_FS 24 #define FCR31_ABS2008 19 #define FCR31_NAN2008 18 -#define SET_FP_COND(num,env) do { ((env).fcr31) |=3D ((num) ? (1 << ((= num) + 24)) : (1 << 23)); } while(0) -#define CLEAR_FP_COND(num,env) do { ((env).fcr31) &=3D ~((num) ? (1 << (= (num) + 24)) : (1 << 23)); } while(0) +#define SET_FP_COND(num, env) do { ((env).fcr31) |=3D ((num) ? (1 << (= (num) + 24)) : (1 << 23)); } while (0) +#define CLEAR_FP_COND(num, env) do { ((env).fcr31) &=3D ~((num) ? (1 << = ((num) + 24)) : (1 << 23)); } while (0) #define GET_FP_COND(env) ((((env).fcr31 >> 24) & 0xfe) | (((env).f= cr31 >> 23) & 0x1)) #define GET_FP_CAUSE(reg) (((reg) >> 12) & 0x3f) #define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f) #define GET_FP_FLAGS(reg) (((reg) >> 2) & 0x1f) -#define SET_FP_CAUSE(reg,v) do { (reg) =3D ((reg) & ~(0x3f << 12)) | = ((v & 0x3f) << 12); } while(0) -#define SET_FP_ENABLE(reg,v) do { (reg) =3D ((reg) & ~(0x1f << 7)) | = ((v & 0x1f) << 7); } while(0) -#define SET_FP_FLAGS(reg,v) do { (reg) =3D ((reg) & ~(0x1f << 2)) | = ((v & 0x1f) << 2); } while(0) -#define UPDATE_FP_FLAGS(reg,v) do { (reg) |=3D ((v & 0x1f) << 2); } whil= e(0) +#define SET_FP_CAUSE(reg, v) do { (reg) =3D ((reg) & ~(0x3f << 12)) |= ((v & 0x3f) << 12); } while (0) +#define SET_FP_ENABLE(reg, v) do { (reg) =3D ((reg) & ~(0x1f << 7)) |= ((v & 0x1f) << 7); } while (0) +#define SET_FP_FLAGS(reg, v) do { (reg) =3D ((reg) & ~(0x1f << 2)) |= ((v & 0x1f) << 2); } while (0) +#define UPDATE_FP_FLAGS(reg, v) do { (reg) |=3D ((v & 0x1f) << 2); } whi= le (0) #define FP_INEXACT 1 #define FP_UNDERFLOW 2 #define FP_OVERFLOW 4 @@ -95,25 +95,25 @@ struct CPUMIPSFPUContext { typedef struct CPUMIPSMVPContext CPUMIPSMVPContext; struct CPUMIPSMVPContext { int32_t CP0_MVPControl; -#define CP0MVPCo_CPA 3 -#define CP0MVPCo_STLB 2 -#define CP0MVPCo_VPC 1 -#define CP0MVPCo_EVP 0 +#define CP0MVPCo_CPA 3 +#define CP0MVPCo_STLB 2 +#define CP0MVPCo_VPC 1 +#define CP0MVPCo_EVP 0 int32_t CP0_MVPConf0; -#define CP0MVPC0_M 31 -#define CP0MVPC0_TLBS 29 -#define CP0MVPC0_GS 28 -#define CP0MVPC0_PCP 27 -#define CP0MVPC0_PTLBE 16 -#define CP0MVPC0_TCA 15 -#define CP0MVPC0_PVPE 10 -#define CP0MVPC0_PTC 0 +#define CP0MVPC0_M 31 +#define CP0MVPC0_TLBS 29 +#define CP0MVPC0_GS 28 +#define CP0MVPC0_PCP 27 +#define CP0MVPC0_PTLBE 16 +#define CP0MVPC0_TCA 15 +#define CP0MVPC0_PVPE 10 +#define CP0MVPC0_PTC 0 int32_t CP0_MVPConf1; -#define CP0MVPC1_CIM 31 -#define CP0MVPC1_CIF 30 -#define CP0MVPC1_PCX 20 -#define CP0MVPC1_PCP2 10 -#define CP0MVPC1_PCP1 0 +#define CP0MVPC1_CIM 31 +#define CP0MVPC1_CIF 30 +#define CP0MVPC1_PCX 20 +#define CP0MVPC1_PCP2 10 +#define CP0MVPC1_PCP1 0 }; =20 typedef struct mips_def_t mips_def_t; @@ -481,44 +481,44 @@ struct CPUMIPSState { */ int32_t CP0_Random; int32_t CP0_VPEControl; -#define CP0VPECo_YSI 21 -#define CP0VPECo_GSI 20 -#define CP0VPECo_EXCPT 16 -#define CP0VPECo_TE 15 -#define CP0VPECo_TargTC 0 +#define CP0VPECo_YSI 21 +#define CP0VPECo_GSI 20 +#define CP0VPECo_EXCPT 16 +#define CP0VPECo_TE 15 +#define CP0VPECo_TargTC 0 int32_t CP0_VPEConf0; -#define CP0VPEC0_M 31 -#define CP0VPEC0_XTC 21 -#define CP0VPEC0_TCS 19 -#define CP0VPEC0_SCS 18 -#define CP0VPEC0_DSC 17 -#define CP0VPEC0_ICS 16 -#define CP0VPEC0_MVP 1 -#define CP0VPEC0_VPA 0 +#define CP0VPEC0_M 31 +#define CP0VPEC0_XTC 21 +#define CP0VPEC0_TCS 19 +#define CP0VPEC0_SCS 18 +#define CP0VPEC0_DSC 17 +#define CP0VPEC0_ICS 16 +#define CP0VPEC0_MVP 1 +#define CP0VPEC0_VPA 0 int32_t CP0_VPEConf1; -#define CP0VPEC1_NCX 20 -#define CP0VPEC1_NCP2 10 -#define CP0VPEC1_NCP1 0 +#define CP0VPEC1_NCX 20 +#define CP0VPEC1_NCP2 10 +#define CP0VPEC1_NCP1 0 target_ulong CP0_YQMask; target_ulong CP0_VPESchedule; target_ulong CP0_VPEScheFBack; int32_t CP0_VPEOpt; -#define CP0VPEOpt_IWX7 15 -#define CP0VPEOpt_IWX6 14 -#define CP0VPEOpt_IWX5 13 -#define CP0VPEOpt_IWX4 12 -#define CP0VPEOpt_IWX3 11 -#define CP0VPEOpt_IWX2 10 -#define CP0VPEOpt_IWX1 9 -#define CP0VPEOpt_IWX0 8 -#define CP0VPEOpt_DWX7 7 -#define CP0VPEOpt_DWX6 6 -#define CP0VPEOpt_DWX5 5 -#define CP0VPEOpt_DWX4 4 -#define CP0VPEOpt_DWX3 3 -#define CP0VPEOpt_DWX2 2 -#define CP0VPEOpt_DWX1 1 -#define CP0VPEOpt_DWX0 0 +#define CP0VPEOpt_IWX7 15 +#define CP0VPEOpt_IWX6 14 +#define CP0VPEOpt_IWX5 13 +#define CP0VPEOpt_IWX4 12 +#define CP0VPEOpt_IWX3 11 +#define CP0VPEOpt_IWX2 10 +#define CP0VPEOpt_IWX1 9 +#define CP0VPEOpt_IWX0 8 +#define CP0VPEOpt_DWX7 7 +#define CP0VPEOpt_DWX6 6 +#define CP0VPEOpt_DWX5 5 +#define CP0VPEOpt_DWX4 4 +#define CP0VPEOpt_DWX3 3 +#define CP0VPEOpt_DWX2 2 +#define CP0VPEOpt_DWX1 1 +#define CP0VPEOpt_DWX0 0 /* * CP0 Register 2 */ @@ -625,33 +625,33 @@ struct CPUMIPSState { #define CP0PC_PSN 0 /* 5..0 */ int32_t CP0_SRSConf0_rw_bitmask; int32_t CP0_SRSConf0; -#define CP0SRSC0_M 31 -#define CP0SRSC0_SRS3 20 -#define CP0SRSC0_SRS2 10 -#define CP0SRSC0_SRS1 0 +#define CP0SRSC0_M 31 +#define CP0SRSC0_SRS3 20 +#define CP0SRSC0_SRS2 10 +#define CP0SRSC0_SRS1 0 int32_t CP0_SRSConf1_rw_bitmask; int32_t CP0_SRSConf1; -#define CP0SRSC1_M 31 -#define CP0SRSC1_SRS6 20 -#define CP0SRSC1_SRS5 10 -#define CP0SRSC1_SRS4 0 +#define CP0SRSC1_M 31 +#define CP0SRSC1_SRS6 20 +#define CP0SRSC1_SRS5 10 +#define CP0SRSC1_SRS4 0 int32_t CP0_SRSConf2_rw_bitmask; int32_t CP0_SRSConf2; -#define CP0SRSC2_M 31 -#define CP0SRSC2_SRS9 20 -#define CP0SRSC2_SRS8 10 -#define CP0SRSC2_SRS7 0 +#define CP0SRSC2_M 31 +#define CP0SRSC2_SRS9 20 +#define CP0SRSC2_SRS8 10 +#define CP0SRSC2_SRS7 0 int32_t CP0_SRSConf3_rw_bitmask; int32_t CP0_SRSConf3; -#define CP0SRSC3_M 31 -#define CP0SRSC3_SRS12 20 -#define CP0SRSC3_SRS11 10 -#define CP0SRSC3_SRS10 0 +#define CP0SRSC3_M 31 +#define CP0SRSC3_SRS12 20 +#define CP0SRSC3_SRS11 10 +#define CP0SRSC3_SRS10 0 int32_t CP0_SRSConf4_rw_bitmask; int32_t CP0_SRSConf4; -#define CP0SRSC4_SRS15 20 -#define CP0SRSC4_SRS14 10 -#define CP0SRSC4_SRS13 0 +#define CP0SRSC4_SRS15 20 +#define CP0SRSC4_SRS14 10 +#define CP0SRSC4_SRS13 0 /* * CP0 Register 7 */ @@ -1065,7 +1065,7 @@ static inline MIPSCPU *mips_env_get_cpu(CPUMIPSState = *env) =20 #define ENV_OFFSET offsetof(MIPSCPU, env) =20 -void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf); +void mips_cpu_list(FILE *f, fprintf_function cpu_fprintf); =20 #define cpu_signal_handler cpu_mips_signal_handler #define cpu_list mips_cpu_list @@ -1090,7 +1090,7 @@ static inline int hflags_mmu_index(uint32_t hflags) } } =20 -static inline int cpu_mmu_index (CPUMIPSState *env, bool ifetch) +static inline int cpu_mmu_index(CPUMIPSState *env, bool ifetch) { return hflags_mmu_index(env->hflags); } @@ -1182,7 +1182,7 @@ void cpu_mips_soft_irq(CPUMIPSState *env, int irq, in= t level); void itc_reconfigure(struct MIPSITUState *tag); =20 /* helper.c */ -target_ulong exception_resume_pc (CPUMIPSState *env); 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[2.103.80.5]) by smtp.gmail.com with ESMTPSA id g13sm7398293wmh.11.2019.04.12.18.13.53 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 12 Apr 2019 18:13:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Jl7grZRlcRQRHYnUtEAgI42E5FYoB/4xEw8V0mnj7jQ=; b=EkwMKK8b4RrwPIGW42asFdqaWveLVgO3w7MX4pBc9fhs1DA7rV01A/sa4jsT0zXb1O KtuRhO3qa84a4ArOL0PMy3CM+gMpCMxUrSjMTMnm7CBrxS7OfkT+bAH+93uQA13pGWyB apg0whG7+xbIRgqyTTqaxv1IFGlCIk5SBzLvo+CRzhSLSk1DmQUqOVKZjNfcxS2wLOH/ 72Rxi9gcx0YJDJ7Fa0U2gkikoFIuDepq15AIwhiK4tVVAB8pKeSjlfeyTmNjanNdSLBS yiEz68Y4rnTL2tUaGxQFOcHrqmw/5B/S+HcXHto2djGGXidNHy8PsMvDpt05wGVTMlaA 2B6w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Jl7grZRlcRQRHYnUtEAgI42E5FYoB/4xEw8V0mnj7jQ=; b=hTL/EDfIl3Y2O+W2KgozzlWXXHeOnZaVg2BAvrKVQvCbOfui5Oh8nTqxcjDBU0g8nt yocwkyRUCYGz9K1RBJTcplFfacEmFvgP1xcwBI5HjEFCMi6SN64F36avqnpIFsJOP6rA R9a1isyA50j1oGsV94SYloU7YSJjGXLvkcHVQs+n3rc0qtAjaas3XojLZPPBJfvXy9n/ C7wGCBUh9WgoFnR0IWtzerM6x+1Ged5rGHqzPpdUP4Wduz0WV6U91qyyX3DRd2Dshoe0 27zXLRjPzIA5/QCX0Fs5nuetTQ6QE67Otv8Jbom6dDCpJ+R3bvxcL1iDoFmHWfacu/t0 O1EQ== X-Gm-Message-State: APjAAAW2HHJ4L+JBPxQoD6RUXKZdPLLvLiZr+atEOr0SKNmnO3zRzymI c80AH/pEgy/6rnxABvSAmjprHMeW7Mmc X-Google-Smtp-Source: APXvYqyByGpOFF1U8ssc+Ww/MV71A50kGa4wa6r8LvtVcBbLMmIuNH9J0PIWltJLkc8cfK/uNl7HeA== X-Received: by 2002:a1c:2109:: with SMTP id h9mr13869692wmh.68.1555118033879; Fri, 12 Apr 2019 18:13:53 -0700 (PDT) From: Jules Irenge To: qemu-devel@nongnu.org Date: Sat, 13 Apr 2019 02:13:01 +0100 Message-Id: <20190413011302.6610-3-jbi.octave@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190413011302.6610-1-jbi.octave@gmail.com> References: <20190413011302.6610-1-jbi.octave@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::344 Subject: [Qemu-devel] [PATCH v4 2/3] target/mips: realign comments to fix checkpatch warnings X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: arikalo@wavecomp.com, Jules Irenge , aurelien@aurel32.net, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Realign comments to fix warnings issued by checkpatc.pl tool "WARNING: Block comments use a leading /* on a separate line" within "target/mips/cpu.h" file. Signed-off-by: Jules Irenge --- target/mips/cpu.h | 34 ++++++++++++++++++++++------------ 1 file changed, 22 insertions(+), 12 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 4bfa24bda0..57af560e34 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -37,7 +37,8 @@ union fpr_t { /* FPU/MSA register mapping is not tested on big-endian hosts. */ wr_t wr; /* vector data */ }; -/* define FP_ENDIAN_IDX to access the same location +/* + *define FP_ENDIAN_IDX to access the same location * in the fpr_t union regardless of the host endianness */ #if defined(HOST_WORDS_BIGENDIAN) @@ -963,9 +964,11 @@ struct CPUMIPSState { /* TMASK defines different execution modes */ #define MIPS_HFLAG_TMASK 0x1F5807FF #define MIPS_HFLAG_MODE 0x00007 /* execution modes */ - /* The KSU flags must be the lowest bits in hflags. The flag order - must be the same as defined for CP0 Status. This allows to use - the bits as the value of mmu_idx. */ + /* + * The KSU flags must be the lowest bits in hflags. The flag order + * must be the same as defined for CP0 Status. This allows to use + * the bits as the value of mmu_idx. + */ #define MIPS_HFLAG_KSU 0x00003 /* kernel/supervisor/user mode mask */ #define MIPS_HFLAG_UM 0x00002 /* user mode flag */ #define MIPS_HFLAG_SM 0x00001 /* supervisor mode flag */ @@ -975,18 +978,22 @@ struct CPUMIPSState { #define MIPS_HFLAG_CP0 0x00010 /* CP0 enabled */ #define MIPS_HFLAG_FPU 0x00020 /* FPU enabled */ #define MIPS_HFLAG_F64 0x00040 /* 64-bit FPU enabled */ - /* True if the MIPS IV COP1X instructions can be used. This also - controls the non-COP1X instructions RECIP.S, RECIP.D, RSQRT.S - and RSQRT.D. */ + /* + * True if the MIPS IV COP1X instructions can be used. This also + * controls the non-COP1X instructions RECIP.S, RECIP.D, RSQRT.S + * and RSQRT.D. + */ #define MIPS_HFLAG_COP1X 0x00080 /* COP1X instructions enabled */ #define MIPS_HFLAG_RE 0x00100 /* Reversed endianness */ #define MIPS_HFLAG_AWRAP 0x00200 /* 32-bit compatibility address wrapping= */ #define MIPS_HFLAG_M16 0x00400 /* MIPS16 mode flag */ #define MIPS_HFLAG_M16_SHIFT 10 - /* If translation is interrupted between the branch instruction and + /* + * If translation is interrupted between the branch instruction and * the delay slot, record what type of branch it is so that we can * resume translation properly. It might be possible to reduce - * this from three bits to two. */ + * this from three bits to two. + */ #define MIPS_HFLAG_BMASK_BASE 0x803800 #define MIPS_HFLAG_B 0x00800 /* Unconditional branch */ #define MIPS_HFLAG_BC 0x01000 /* Conditional branch */ @@ -1073,8 +1080,10 @@ void mips_cpu_list(FILE *f, fprintf_function cpu_fpr= intf); extern void cpu_wrdsp(uint32_t rs, uint32_t mask_num, CPUMIPSState *env); extern uint32_t cpu_rddsp(uint32_t mask_num, CPUMIPSState *env); =20 -/* MMU modes definitions. We carefully match the indices with our - hflags layout. */ +/* + * MMU modes definitions. We carefully match the indices with our + * hflags layout. + */ #define MMU_MODE0_SUFFIX _kernel #define MMU_MODE1_SUFFIX _super #define MMU_MODE2_SUFFIX _user @@ -1097,7 +1106,8 @@ static inline int cpu_mmu_index(CPUMIPSState *env, bo= ol ifetch) =20 #include "exec/cpu-all.h" =20 -/* Memory access type : +/* + * Memory access type : * may be needed for precise access rights control and precise exceptions. */ enum { --=20 2.20.1 From nobody Sat Apr 20 06:48:22 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1555118274; cv=none; d=zoho.com; s=zohoarc; b=RtQeN4YWAqDQWWQ66xQ+0Vh+NS6rLIYsYhAySQ0f0rJ8RPTHn6ha40+domPRoyakPkXb5Sajr2Dsp7opytScG8kCvjx31zY6maVV1l6LxBsrMAkv+xC/44kEX0fxvzodT6lUN+B+mLXusoPUVlhKZ4rUy2nGDYwQSFDl8Ui88yI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1555118274; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=ZdbakEXzpU8tzbmrc5OWOUi1IpM4Ik4V2F+KY4JS/+8=; b=KMhx8BvwaI0zyFSUDaZUrNpJihBbgvueviOgkZj/0xh7cunby8o6lDJF5aibAIgz8ViwftO4c2aIuqYgXXc1ewEE8z7bP5eKk+XCcB/fJfQn5PQKnasIzYG/Mdgeclp1JLXDElhX8JuCgfVHYXrgmIpbz70uXCI/dscFZLfgQWA= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1555118274651220.51259816246784; Fri, 12 Apr 2019 18:17:54 -0700 (PDT) Received: from localhost ([127.0.0.1]:45007 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hF7Il-0002vF-Ok for importer@patchew.org; Fri, 12 Apr 2019 21:17:51 -0400 Received: from eggs.gnu.org ([209.51.188.92]:36741) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hF7F3-0008Ue-29 for qemu-devel@nongnu.org; Fri, 12 Apr 2019 21:14:02 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hF7F1-0000kx-BJ for qemu-devel@nongnu.org; Fri, 12 Apr 2019 21:14:00 -0400 Received: from mail-wm1-x341.google.com ([2a00:1450:4864:20::341]:51479) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hF7F1-0000kL-2W for qemu-devel@nongnu.org; Fri, 12 Apr 2019 21:13:59 -0400 Received: by mail-wm1-x341.google.com with SMTP id 4so13300837wmf.1 for ; Fri, 12 Apr 2019 18:13:58 -0700 (PDT) Received: from ninjahub.lan (host-2-103-80-5.as13285.net. [2.103.80.5]) by smtp.gmail.com with ESMTPSA id g13sm7398293wmh.11.2019.04.12.18.13.56 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 12 Apr 2019 18:13:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ZdbakEXzpU8tzbmrc5OWOUi1IpM4Ik4V2F+KY4JS/+8=; b=lMy1VDn7OuYpE6GgJ54z83fk5KgXAaX72NJRbwjy3WIro110VUcP4gfmwll5f/aLJc kKNVN5IvfL794oS56xSi0HgSLOXZLCu7+Du32Fo+i8uK3WHSZ3Dzl+UgBgbUnSNu/gI9 +kGPFeCMQTnQi93QoSbrUrgjGoyhJ09jKCDVf8fQmPthDq9Ky8pP6UOAWTucjSJuJ65h I7PWh1uJIY5iBnIODOHr6BUfOIW+WxVAsENAvvDeX6q2etBqUCbd2hFOiUKTeLUaIgER MR+1yjToll4dauX6Y50U3hGt+n75vPo4jnCCx1l2bMrDDQrteRDLxZ/M5giWw+Z8pUHC Uk6w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZdbakEXzpU8tzbmrc5OWOUi1IpM4Ik4V2F+KY4JS/+8=; b=WmcLqnslaTpNNavrm9xGV08gG02hQofQWGB8x5zJuttviIWu73hc4OaxmpuhC1OIRD PpiO2BeH15Krs2xIhoqE8HST4WSRSxe1D9QAgfqItULIjRqcobSsMP698Qqp+1TwgpP+ srDbciVhcDySneP7Giha2mWXVCdyRvq9pv7kZDARmv/fuIlvOd/T8E2HwP2E+0pBDbix mMhJmdNiis1KSK2w+vwTe0SPi4SsehUXWq79kduTCDFDgFw+LdN1x2kN3rX9g9h2NULs z20EOINswOmkCKSC1YSdDqTjOBMUuFhc2f9cdqEZN+A+DWbGNci9N178zL7pQykVvMtm tDxQ== X-Gm-Message-State: APjAAAVJTUJBHk+hr8GQt3FlsS6hJbPgfBMXul1aHXncUWQRXNI1zF8I mQ+crgZyvbZsu12tmnIY6vxngXMXXsbz X-Google-Smtp-Source: APXvYqxhxo/1C/1CrBp3KwQy+VPHEEXCaoSLtzxGUaaG8WtN8UWMHjGHAqxZ5PzZwqA0z3cNcZ9m3g== X-Received: by 2002:a7b:c301:: with SMTP id k1mr13543481wmj.37.1555118037084; Fri, 12 Apr 2019 18:13:57 -0700 (PDT) From: Jules Irenge To: qemu-devel@nongnu.org Date: Sat, 13 Apr 2019 02:13:02 +0100 Message-Id: <20190413011302.6610-4-jbi.octave@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190413011302.6610-1-jbi.octave@gmail.com> References: <20190413011302.6610-1-jbi.octave@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 Subject: [Qemu-devel] [PATCH v4 3/3] target/mips: wrap lines to fix checkpatch errors X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: arikalo@wavecomp.com, Jules Irenge , aurelien@aurel32.net, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Wrap lines to fix errors issued by checkpatch.pl tool "ERROR: line over 90 characters" within "target/mips/cpu.h" file. Signed-off-by: Jules Irenge --- target/mips/cpu.h | 25 +++++++++++++++++++------ 1 file changed, 19 insertions(+), 6 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 57af560e34..c1abce33c3 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -72,15 +72,28 @@ struct CPUMIPSFPUContext { #define FCR31_FS 24 #define FCR31_ABS2008 19 #define FCR31_NAN2008 18 -#define SET_FP_COND(num, env) do { ((env).fcr31) |=3D ((num) ? (1 << (= (num) + 24)) : (1 << 23)); } while (0) -#define CLEAR_FP_COND(num, env) do { ((env).fcr31) &=3D ~((num) ? (1 << = ((num) + 24)) : (1 << 23)); } while (0) -#define GET_FP_COND(env) ((((env).fcr31 >> 24) & 0xfe) | (((env).f= cr31 >> 23) & 0x1)) +#define SET_FP_COND(num, env) do { ((env).fcr31) |=3D \ + ((num) ? (1 << ((num) + 24)) :\ + (1 << 23));\ + } while (0) +#define CLEAR_FP_COND(num, env) do { ((env).fcr31) &=3D \ + ~((num) ? (1 << ((num) + 24)) :\ + (1 << 23));\ + } while (0) +#define GET_FP_COND(env) ((((env).fcr31 >> 24) & 0xfe) |\ + (((env).fcr31 >> 23) & 0x1)) #define GET_FP_CAUSE(reg) (((reg) >> 12) & 0x3f) #define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f) #define GET_FP_FLAGS(reg) (((reg) >> 2) & 0x1f) -#define SET_FP_CAUSE(reg, v) do { (reg) =3D ((reg) & ~(0x3f << 12)) |= ((v & 0x3f) << 12); } while (0) -#define SET_FP_ENABLE(reg, v) do { (reg) =3D ((reg) & ~(0x1f << 7)) |= ((v & 0x1f) << 7); } while (0) -#define SET_FP_FLAGS(reg, v) do { (reg) =3D ((reg) & ~(0x1f << 2)) |= ((v & 0x1f) << 2); } while (0) +#define SET_FP_CAUSE(reg, v) do { (reg) =3D ((reg) & ~(0x3f << 12)) |\ + ((v & 0x3f) << 12); \ + } while (0) +#define SET_FP_ENABLE(reg, v) do { (reg) =3D ((reg) & ~(0x1f << 7)) |\ + ((v & 0x1f) << 7); \ + } while (0) +#define SET_FP_FLAGS(reg, v) do { (reg) =3D ((reg) & ~(0x1f << 2)) |\ + ((v & 0x1f) << 2); \ + } while (0) #define UPDATE_FP_FLAGS(reg, v) do { (reg) |=3D ((v & 0x1f) << 2); } whi= le (0) #define FP_INEXACT 1 #define FP_UNDERFLOW 2 --=20 2.20.1