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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id y132sm6932581wmg.38.2019.04.11.08.39.43 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 11 Apr 2019 08:39:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:mime-version :content-transfer-encoding; bh=DCRADAn52YQB0i1Vcag5VquhM34iiUI7ee/x7IVTB+I=; b=w93VzOhjHNXoT40RlJkosHDhMfGSasHqeNuNb1iQ47/8o3D9mWd5aQktuA1FBfqTEX 02CK4EMU5HiW4hOi3OYFVbezZWea8HueruYgLo5Fk76TxhuKhGtpKnbr/Sn1OedSCJ0x SalAIq0brIfMWylnXK+K9pRkJl4xPgRCiehFB8Ci5NC2QfQyUhBPeq3CZ6a9ZTNkkY6g /pKjXKRak0fVNlMM9/hpgt5p+ngxYWuTdrf71yI0XqRgLTZ12LsCAOlsMFQi4KzH3Y0C TqwbYtgfeyueWCQwnzsAc8r3Vn7D7p2UBy3dwsNreqIi3y27HQWDGj0CvIRNn4uENni1 OTeA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:mime-version :content-transfer-encoding; bh=DCRADAn52YQB0i1Vcag5VquhM34iiUI7ee/x7IVTB+I=; b=s22dNceMb7V8On/93vt7pZUt1ACvjRJbjJLk3cUzrWa1n9ialwXRJRmc/SVvA7DyK/ mAJqVypqWbwp6t5/Lm8va5Xy4q1KUgZVnlvcdzyAA9/Z74oSwOiW8bOqvig86W+iAqTD VfftUodJemZ/am+R/yNA/xFhG4fGYv9/fb/yFKODpeSoyn27Bvi0lYqBHNwiHUwYvjbq BZFYdidV3C+O+OcnOBV98i1xWJ060IxUZGf5biGwmVjfv5uY966+gdbesLoJFEM21dGs 3J4VcVU8CESZPOvyYyMZ4c8Ru+1rjZUOcMs3Ysi1t4GtlydfR23g55QpaUK5n18GkLBn GizA== X-Gm-Message-State: APjAAAVsUBBo2rFaW8iUMV5JhzR26XQVVXMOrzb2MLOArsJquD7X9ZQB 7smkfjf4N5z0IgsGx2nVblIL1A== X-Google-Smtp-Source: APXvYqwHBa4OBkdWxoeL2q/kLerwbXsxIU6+xK9/x11RsjjTGYqHgXkNWH7yNut/e9JpLzgJWz7gEQ== X-Received: by 2002:adf:f68d:: with SMTP id v13mr31103487wrp.6.1554997184884; Thu, 11 Apr 2019 08:39:44 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Thu, 11 Apr 2019 16:39:42 +0100 Message-Id: <20190411153942.4533-1-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 Subject: [Qemu-devel] [PATCH] target/arm: Implement NSACR gating of floating point X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The NSACR register allows secure code to configure the FPU to be inaccessible to non-secure code. If the NSACR.CP10 bit is set then: * NS accesses to the FPU trap as UNDEF (ie to NS EL1 or EL2) * CPACR.{CP10,CP11} behave as if RAZ/WI * HCPTR.{TCP11,TCP10} behave as if RAO/WI Note that we do not implement the NSACR.NSASEDIS bit which gates only access to Advanced SIMD, in the same way that we don't implement the equivalent CPACR.ASEDIS and HCPTR.TASE. Signed-off-by: Peter Maydell --- I noticed we were missing NSACR handling here while looking at M profile floating point, but it turns out that M profile NSACR isn't really the same, so the two don't share code. This patch fixes the A-profile NSACR handling. Note that this only affects CPUs with an AArch32 EL3. target/arm/helper.c | 75 +++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 73 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index a0dd1f99974..26105f13e70 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -903,9 +903,36 @@ static void cpacr_write(CPUARMState *env, const ARMCPR= egInfo *ri, } value &=3D mask; } + + /* + * For A-profile AArch32 EL3 (but not M-profile secure mode), if NSACR= .CP10 + * is 0 then CPACR.{CP11,CP10} ignore writes and read as 0b00. + */ + if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && + !arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) { + value &=3D ~(0xf << 20); + value |=3D env->cp15.cpacr_el1 & (0xf << 20); + } + env->cp15.cpacr_el1 =3D value; } =20 +static uint64_t cpacr_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + /* + * For A-profile AArch32 EL3 (but not M-profile secure mode), if NSACR= .CP10 + * is 0 then CPACR.{CP11,CP10} ignore writes and read as 0b00. + */ + uint64_t value =3D env->cp15.cpacr_el1; + + if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && + !arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) { + value &=3D ~(0xf << 20); + } + return value; +} + + static void cpacr_reset(CPUARMState *env, const ARMCPRegInfo *ri) { /* Call cpacr_write() so that we reset with the correct RAO bits set @@ -971,7 +998,7 @@ static const ARMCPRegInfo v6_cp_reginfo[] =3D { { .name =3D "CPACR", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .crn =3D 1, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 2, .accessfn =3D cpac= r_access, .access =3D PL1_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.cpac= r_el1), - .resetfn =3D cpacr_reset, .writefn =3D cpacr_write }, + .resetfn =3D cpacr_reset, .writefn =3D cpacr_write, .readfn =3D cpac= r_read }, REGINFO_SENTINEL }; =20 @@ -4656,6 +4683,36 @@ uint64_t arm_hcr_el2_eff(CPUARMState *env) return ret; } =20 +static void cptr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* + * For A-profile AArch32 EL3, if NSACR.CP10 + * is 0 then HCPTR.{TCP11,TCP10} ignore writes and read as 1. + */ + if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && + !arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) { + value &=3D ~(0x3 << 10); + value |=3D env->cp15.cptr_el[2] & (0x3 << 10); + } + env->cp15.cptr_el[2] =3D value; +} + +static uint64_t cptr_el2_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + /* + * For A-profile AArch32 EL3, if NSACR.CP10 + * is 0 then HCPTR.{TCP11,TCP10} ignore writes and read as 1. + */ + uint64_t value =3D env->cp15.cptr_el[2]; + + if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && + !arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) { + value &=3D ~(0x3 << 10); + } + return value; +} + static const ARMCPRegInfo el2_cp_reginfo[] =3D { { .name =3D "HCR_EL2", .state =3D ARM_CP_STATE_AA64, .type =3D ARM_CP_IO, @@ -4703,7 +4760,8 @@ static const ARMCPRegInfo el2_cp_reginfo[] =3D { { .name =3D "CPTR_EL2", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 2, .access =3D PL2_RW, .accessfn =3D cptr_access, .resetvalue =3D 0, - .fieldoffset =3D offsetof(CPUARMState, cp15.cptr_el[2]) }, + .fieldoffset =3D offsetof(CPUARMState, cp15.cptr_el[2]), + .readfn =3D cptr_el2_read, .writefn =3D cptr_el2_write }, { .name =3D "MAIR_EL2", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 10, .crm =3D 2, .opc2 =3D 0, .access =3D PL2_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.mair= _el[2]), @@ -12804,6 +12862,19 @@ int fp_exception_el(CPUARMState *env, int cur_el) break; } =20 + /* + * The NSACR allows A-profile AArch32 EL3 and M-profile secure mode + * to control non-secure access to the FPU. It doesn't have any + * effect if EL3 is AArch64 or if EL3 doesn't exist at all. + */ + if ((arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && + cur_el <=3D 2 && !arm_is_secure_below_el3(env))) { + if (!extract32(env->cp15.nsacr, 10, 1)) { + /* FP insns act as UNDEF */ + return cur_el =3D=3D 2 ? 2 : 1; + } + } + /* For the CPTR registers we don't need to guard with an ARM_FEATURE * check because zero bits in the registers mean "don't trap". */ --=20 2.20.1