From nobody Sat May 18 20:37:11 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1554969780; cv=none; d=zoho.com; s=zohoarc; b=AxULfDB9gQXYuTGdjM9HlMRzIl4jPQaDjDSG4lymgecnK401+idDqvdb/RkwUp5wQudhHoWZ8qoapsnTwVUhbgu5FWShH1S7X9vI8TIOYYPjAEvaP6qM/E4HcwL6bUXZ0VVCI0PMoaH9mv7hdrkfXnmcK9/4Q7yCoBQT4d02i4Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1554969780; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=QqSjHsK9Qhmd28aPcJRN8CBO9cktTEV81SLmRqRMFlM=; b=JaxoR1YxteXeZq9xODmk4oMzPdaQSErqrqu5uc+woOTEL5d99GQoU84TU36JrV1RiOZuSxRGGp+Q9KZjvDrVfzQEU3KowfTCgBEO3iGEdIbgDBO4YN9fv9Kw3w6YnE9WN3TU8VXnNvaENVpCqjNLIwt5wH1ZzWMhIkN/BlWm7Hs= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=null header.from= header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1554969780961682.1916748207032; Thu, 11 Apr 2019 01:03:00 -0700 (PDT) Received: from localhost ([127.0.0.1]:43575 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hEUfc-0000k4-S9 for importer@patchew.org; Thu, 11 Apr 2019 04:02:52 -0400 Received: from eggs.gnu.org ([209.51.188.92]:48212) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hEUdk-0007jZ-Cy for qemu-devel@nongnu.org; Thu, 11 Apr 2019 04:01:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hEUdf-00086g-GQ for qemu-devel@nongnu.org; Thu, 11 Apr 2019 04:00:56 -0400 Received: from 9.mo5.mail-out.ovh.net ([178.32.96.204]:47170) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hEUdZ-00080d-Pr for qemu-devel@nongnu.org; Thu, 11 Apr 2019 04:00:47 -0400 Received: from player779.ha.ovh.net (unknown [10.109.160.143]) by mo5.mail-out.ovh.net (Postfix) with ESMTP id 6BC6E22864D for ; Thu, 11 Apr 2019 10:00:41 +0200 (CEST) Received: from kaod.org (lfbn-tou-1-40-22.w86-201.abo.wanadoo.fr [86.201.133.22]) (Authenticated sender: clg@kaod.org) by player779.ha.ovh.net (Postfix) with ESMTPSA id 1814348B8B6A; Thu, 11 Apr 2019 08:00:31 +0000 (UTC) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Thu, 11 Apr 2019 09:59:59 +0200 Message-Id: <20190411080004.8690-2-clg@kaod.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190411080004.8690-1-clg@kaod.org> References: <20190411080004.8690-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 17593593420494113766 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgeduuddrudekgdduvddtucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucesvcftvggtihhpihgvnhhtshculddquddttddm Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 178.32.96.204 Subject: [Qemu-devel] [PATCH 1/6] target/ppc: Don't check UPRT in radix mode when in HV real mode X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, Suraj Jitindar Singh , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Benjamin Herrenschmidt It appears that during kexec, we run for a while in hypervisor real mode with LPCR:HR set and LPCR:UPRT clear, which trips the assertion in ppc_radix64_handle_mmu_fault(). First this shouldn't be an assertion, it's a guest error. Then we shouldn't be checking these things in hypervisor real mode (or in virtual hypervisor guest real mode which is similar) as the real HW won't use those LPCR bits in those cases anyway, so technically it's ok to have this discrepancy. Signed-off-by: Benjamin Herrenschmidt Signed-off-by: C=C3=A9dric Le Goater --- target/ppc/mmu-radix64.c | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/target/ppc/mmu-radix64.c b/target/ppc/mmu-radix64.c index ca1fb2673f93..cac076ee92d9 100644 --- a/target/ppc/mmu-radix64.c +++ b/target/ppc/mmu-radix64.c @@ -228,10 +228,10 @@ int ppc_radix64_handle_mmu_fault(PowerPCCPU *cpu, vad= dr eaddr, int rwx, ppc_v3_pate_t pate; =20 assert((rwx =3D=3D 0) || (rwx =3D=3D 1) || (rwx =3D=3D 2)); - assert(ppc64_use_proc_tbl(cpu)); =20 - /* Real Mode Access */ - if (((rwx =3D=3D 2) && (msr_ir =3D=3D 0)) || ((rwx !=3D 2) && (msr_dr = =3D=3D 0))) { + /* HV or virtual hypervisor Real Mode Access */ + if ((msr_hv || cpu->vhyp) && + (((rwx =3D=3D 2) && (msr_ir =3D=3D 0)) || ((rwx !=3D 2) && (msr_dr= =3D=3D 0)))) { /* In real mode top 4 effective addr bits (mostly) ignored */ raddr =3D eaddr & 0x0FFFFFFFFFFFFFFFULL; =20 @@ -241,6 +241,16 @@ int ppc_radix64_handle_mmu_fault(PowerPCCPU *cpu, vadd= r eaddr, int rwx, return 0; } =20 + /* + * Check UPRT (we avoid the check in real mode to deal with + * transitional states during kexec. + */ + if (!ppc64_use_proc_tbl(cpu)) { + qemu_log_mask(LOG_GUEST_ERROR, + "LPCR:UPRT not set in radix mode ! LPCR=3D%016lx\n", + env->spr[SPR_LPCR]); + } + /* Virtual Mode Access - get the fully qualified address */ if (!ppc_radix64_get_fully_qualified_addr(env, eaddr, &lpid, &pid)) { ppc_radix64_raise_segi(cpu, rwx, eaddr); --=20 2.20.1 From nobody Sat May 18 20:37:11 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1554969921; cv=none; d=zoho.com; s=zohoarc; b=UFhu8Fl5mlv/f72dSzQ0wccjpP/9BK3S5Wljse4N2wVKMQmZV0H7vNmWS6sh/yw423Ms5pn4PbMqsI4MwiDNBkhfWyX08w+flQFYa+JsCwtebeTpPMFyHX8c3CxCrasYMdqP/AJjgobLu2dEZ+a35mJ6QDG05/NO27Wd3ugO4fw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; 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Thu, 11 Apr 2019 04:05:17 -0400 Received: from eggs.gnu.org ([209.51.188.92]:48252) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hEUdl-0007kp-Sf for qemu-devel@nongnu.org; Thu, 11 Apr 2019 04:00:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hEUdk-0008AS-OR for qemu-devel@nongnu.org; Thu, 11 Apr 2019 04:00:57 -0400 Received: from 2.mo68.mail-out.ovh.net ([46.105.52.162]:49650) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hEUdk-00086V-AM for qemu-devel@nongnu.org; Thu, 11 Apr 2019 04:00:56 -0400 Received: from player779.ha.ovh.net (unknown [10.109.160.230]) by mo68.mail-out.ovh.net (Postfix) with ESMTP id 943A1121D05 for ; Thu, 11 Apr 2019 10:00:50 +0200 (CEST) Received: from kaod.org (lfbn-tou-1-40-22.w86-201.abo.wanadoo.fr [86.201.133.22]) (Authenticated sender: clg@kaod.org) by player779.ha.ovh.net (Postfix) with ESMTPSA id 600D248B8C5C; Thu, 11 Apr 2019 08:00:41 +0000 (UTC) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Thu, 11 Apr 2019 10:00:00 +0200 Message-Id: <20190411080004.8690-3-clg@kaod.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190411080004.8690-1-clg@kaod.org> References: <20190411080004.8690-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 17596126697323531238 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgeduuddrudekgdduvdduucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucesvcftvggtihhpihgvnhhtshculddquddttddm Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 46.105.52.162 Subject: [Qemu-devel] [PATCH 2/6] ppc/spapr: Use proper HPTE accessors for H_READ X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, Suraj Jitindar Singh , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Benjamin Herrenschmidt Signed-off-by: Benjamin Herrenschmidt Signed-off-by: C=C3=A9dric Le Goater --- hw/ppc/spapr_hcall.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c index be8044a92f2f..7761d4a841af 100644 --- a/hw/ppc/spapr_hcall.c +++ b/hw/ppc/spapr_hcall.c @@ -304,8 +304,8 @@ static target_ulong h_read(PowerPCCPU *cpu, SpaprMachin= eState *spapr, { target_ulong flags =3D args[0]; target_ulong ptex =3D args[1]; - uint8_t *hpte; int i, ridx, n_entries =3D 1; + const ppc_hash_pte64_t *hptes; =20 if (!valid_ptex(cpu, ptex)) { return H_PARAMETER; @@ -317,13 +317,12 @@ static target_ulong h_read(PowerPCCPU *cpu, SpaprMach= ineState *spapr, n_entries =3D 4; } =20 - hpte =3D spapr->htab + (ptex * HASH_PTE_SIZE_64); - + hptes =3D ppc_hash64_map_hptes(cpu, ptex, n_entries); for (i =3D 0, ridx =3D 0; i < n_entries; i++) { - args[ridx++] =3D ldq_p(hpte); - args[ridx++] =3D ldq_p(hpte + (HASH_PTE_SIZE_64/2)); - hpte +=3D HASH_PTE_SIZE_64; + args[ridx++] =3D ppc_hash64_hpte0(cpu, hptes, i); + args[ridx++] =3D ppc_hash64_hpte1(cpu, hptes, i); } + ppc_hash64_unmap_hptes(cpu, hptes, ptex, n_entries); =20 return H_SUCCESS; } --=20 2.20.1 From nobody Sat May 18 20:37:11 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1554969945; cv=none; d=zoho.com; s=zohoarc; b=YO1T8SSGPMdjutkeOc6FG1sMbFF4/BI6qjuuGIDLz73rWaCBBQ8egSpoED2qm3xiUD8Hdl3kDn020/Uuc93g8Yn5ksG9m1xAVSMYgDwh8Fwy1UFF0yuLsmb3SZCvj8wR46oa7I8rllEPG0PvCl6mRAdhrrCMEO8TENRxmeX/HF4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; 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Thu, 11 Apr 2019 04:05:39 -0400 Received: from eggs.gnu.org ([209.51.188.92]:48334) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hEUdu-0007q5-Jr for qemu-devel@nongnu.org; Thu, 11 Apr 2019 04:01:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hEUds-0008Ez-LC for qemu-devel@nongnu.org; Thu, 11 Apr 2019 04:01:06 -0400 Received: from 9.mo173.mail-out.ovh.net ([46.105.72.44]:42532) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hEUdq-0008DT-MK for qemu-devel@nongnu.org; Thu, 11 Apr 2019 04:01:03 -0400 Received: from player779.ha.ovh.net (unknown [10.109.143.72]) by mo173.mail-out.ovh.net (Postfix) with ESMTP id 70B04FD94A for ; Thu, 11 Apr 2019 10:01:00 +0200 (CEST) Received: from kaod.org (lfbn-tou-1-40-22.w86-201.abo.wanadoo.fr [86.201.133.22]) (Authenticated sender: clg@kaod.org) by player779.ha.ovh.net (Postfix) with ESMTPSA id 871A648B8CEF; Thu, 11 Apr 2019 08:00:50 +0000 (UTC) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Thu, 11 Apr 2019 10:00:01 +0200 Message-Id: <20190411080004.8690-4-clg@kaod.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190411080004.8690-1-clg@kaod.org> References: <20190411080004.8690-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 17598941447023725542 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgeduuddrudekgdduvdduucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucesvcftvggtihhpihgvnhhtshculddquddttddm Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 46.105.72.44 Subject: [Qemu-devel] [PATCH 3/6] ppc/hash64: Rework R and C bit updates X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, Suraj Jitindar Singh , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Benjamin Herrenschmidt With MT-TCG, we are now running translation in a racy way, thus we need to mimic hardware when it comes to updating the R and C bits, by doing byte stores. The current "store_hpte" abstraction is ill suited for this, we replace it with two separate callbacks for setting R and C. Signed-off-by: Benjamin Herrenschmidt Signed-off-by: C=C3=A9dric Le Goater --- include/hw/ppc/spapr.h | 2 ++ target/ppc/cpu.h | 4 +-- target/ppc/mmu-hash64.h | 2 -- hw/ppc/spapr.c | 41 +++++++++++++++++++--- hw/ppc/spapr_hcall.c | 13 +++---- target/ppc/mmu-hash64.c | 76 ++++++++++++++++++++++++----------------- 6 files changed, 93 insertions(+), 45 deletions(-) diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h index 9331f5e0b955..7e32f309c2be 100644 --- a/include/hw/ppc/spapr.h +++ b/include/hw/ppc/spapr.h @@ -784,6 +784,8 @@ void spapr_reallocate_hpt(SpaprMachineState *spapr, int= shift, Error **errp); void spapr_clear_pending_events(SpaprMachineState *spapr); int spapr_max_server_number(SpaprMachineState *spapr); +void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex, + uint64_t pte0, uint64_t pte1); =20 /* DRC callbacks. */ void spapr_core_release(DeviceState *dev); diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 07cea7268c0c..a4420636dde0 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1268,8 +1268,8 @@ struct PPCVirtualHypervisorClass { void (*unmap_hptes)(PPCVirtualHypervisor *vhyp, const ppc_hash_pte64_t *hptes, hwaddr ptex, int n); - void (*store_hpte)(PPCVirtualHypervisor *vhyp, hwaddr ptex, - uint64_t pte0, uint64_t pte1); + void (*hpte_set_c)(PPCVirtualHypervisor *vhyp, hwaddr ptex, uint64_t p= te1); + void (*hpte_set_r)(PPCVirtualHypervisor *vhyp, hwaddr ptex, uint64_t p= te1); void (*get_pate)(PPCVirtualHypervisor *vhyp, ppc_v3_pate_t *entry); target_ulong (*encode_hpt_for_kvm_pr)(PPCVirtualHypervisor *vhyp); }; diff --git a/target/ppc/mmu-hash64.h b/target/ppc/mmu-hash64.h index 6b555b72200f..bc362964122d 100644 --- a/target/ppc/mmu-hash64.h +++ b/target/ppc/mmu-hash64.h @@ -10,8 +10,6 @@ int ppc_store_slb(PowerPCCPU *cpu, target_ulong slot, hwaddr ppc_hash64_get_phys_page_debug(PowerPCCPU *cpu, target_ulong addr); int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr address, int rw, int mmu_idx); -void ppc_hash64_store_hpte(PowerPCCPU *cpu, hwaddr ptex, - uint64_t pte0, uint64_t pte1); void ppc_hash64_tlb_flush_hpte(PowerPCCPU *cpu, target_ulong pte_index, target_ulong pte0, target_ulong pte1); diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index b81e237635cd..c56939a43b64 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -1520,10 +1520,10 @@ static void spapr_unmap_hptes(PPCVirtualHypervisor = *vhyp, /* Nothing to do for qemu managed HPT */ } =20 -static void spapr_store_hpte(PPCVirtualHypervisor *vhyp, hwaddr ptex, - uint64_t pte0, uint64_t pte1) +void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex, + uint64_t pte0, uint64_t pte1) { - SpaprMachineState *spapr =3D SPAPR_MACHINE(vhyp); + SpaprMachineState *spapr =3D SPAPR_MACHINE(cpu->vhyp); hwaddr offset =3D ptex * HASH_PTE_SIZE_64; =20 if (!spapr->htab) { @@ -1551,6 +1551,38 @@ static void spapr_store_hpte(PPCVirtualHypervisor *v= hyp, hwaddr ptex, } } =20 +static void spapr_hpte_set_c(PPCVirtualHypervisor *vhyp, hwaddr ptex, + uint64_t pte1) +{ + hwaddr offset =3D ptex * HASH_PTE_SIZE_64 + 15; + SpaprMachineState *spapr =3D SPAPR_MACHINE(vhyp); + + if (!spapr->htab) { + /* There should always be a hash table when this is called */ + error_report("spapr_hpte_set_c called with no hash table !"); + return; + } + + /* The HW performs a non-atomic byte update */ + stb_p(spapr->htab + offset, (pte1 & 0xff) | 0x80); +} + +static void spapr_hpte_set_r(PPCVirtualHypervisor *vhyp, hwaddr ptex, + uint64_t pte1) +{ + hwaddr offset =3D ptex * HASH_PTE_SIZE_64 + 14; + SpaprMachineState *spapr =3D SPAPR_MACHINE(vhyp); + + if (!spapr->htab) { + /* There should always be a hash table when this is called */ + error_report("spapr_hpte_set_r called with no hash table !"); + return; + } + + /* The HW performs a non-atomic byte update */ + stb_p(spapr->htab + offset, ((pte1 >> 8) & 0xff) | 0x01); +} + int spapr_hpt_shift_for_ramsize(uint64_t ramsize) { int shift; @@ -4291,7 +4323,8 @@ static void spapr_machine_class_init(ObjectClass *oc,= void *data) vhc->hpt_mask =3D spapr_hpt_mask; vhc->map_hptes =3D spapr_map_hptes; vhc->unmap_hptes =3D spapr_unmap_hptes; - vhc->store_hpte =3D spapr_store_hpte; + vhc->hpte_set_c =3D spapr_hpte_set_c; + vhc->hpte_set_r =3D spapr_hpte_set_r; vhc->get_pate =3D spapr_get_pate; vhc->encode_hpt_for_kvm_pr =3D spapr_encode_hpt_for_kvm_pr; xic->ics_get =3D spapr_ics_get; diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c index 7761d4a841af..a27c9a01aa97 100644 --- a/hw/ppc/spapr_hcall.c +++ b/hw/ppc/spapr_hcall.c @@ -118,7 +118,7 @@ static target_ulong h_enter(PowerPCCPU *cpu, SpaprMachi= neState *spapr, ppc_hash64_unmap_hptes(cpu, hptes, ptex, 1); } =20 - ppc_hash64_store_hpte(cpu, ptex + slot, pteh | HPTE64_V_HPTE_DIRTY, pt= el); + spapr_store_hpte(cpu, ptex + slot, pteh | HPTE64_V_HPTE_DIRTY, ptel); =20 args[0] =3D ptex + slot; return H_SUCCESS; @@ -131,7 +131,8 @@ typedef enum { REMOVE_HW =3D 3, } RemoveResult; =20 -static RemoveResult remove_hpte(PowerPCCPU *cpu, target_ulong ptex, +static RemoveResult remove_hpte(PowerPCCPU *cpu + , target_ulong ptex, target_ulong avpn, target_ulong flags, target_ulong *vp, target_ulong *rp) @@ -155,7 +156,7 @@ static RemoveResult remove_hpte(PowerPCCPU *cpu, target= _ulong ptex, } *vp =3D v; *rp =3D r; - ppc_hash64_store_hpte(cpu, ptex, HPTE64_V_HPTE_DIRTY, 0); + spapr_store_hpte(cpu, ptex, HPTE64_V_HPTE_DIRTY, 0); ppc_hash64_tlb_flush_hpte(cpu, ptex, v, r); return REMOVE_SUCCESS; } @@ -289,13 +290,13 @@ static target_ulong h_protect(PowerPCCPU *cpu, SpaprM= achineState *spapr, r |=3D (flags << 55) & HPTE64_R_PP0; r |=3D (flags << 48) & HPTE64_R_KEY_HI; r |=3D flags & (HPTE64_R_PP | HPTE64_R_N | HPTE64_R_KEY_LO); - ppc_hash64_store_hpte(cpu, ptex, - (v & ~HPTE64_V_VALID) | HPTE64_V_HPTE_DIRTY, 0); + spapr_store_hpte(cpu, ptex, + (v & ~HPTE64_V_VALID) | HPTE64_V_HPTE_DIRTY, 0); ppc_hash64_tlb_flush_hpte(cpu, ptex, v, r); /* Flush the tlb */ check_tlb_flush(env, true); /* Don't need a memory barrier, due to qemu's global lock */ - ppc_hash64_store_hpte(cpu, ptex, v | HPTE64_V_HPTE_DIRTY, r); + spapr_store_hpte(cpu, ptex, v | HPTE64_V_HPTE_DIRTY, r); return H_SUCCESS; } =20 diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index 8956ad55d96f..b4a27d46e382 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -724,6 +724,39 @@ static void ppc_hash64_set_dsi(CPUState *cs, uint64_t = dar, uint64_t dsisr) } =20 =20 +static void ppc_hash64_set_r(PowerPCCPU *cpu, hwaddr ptex, uint64_t pte1) +{ + hwaddr base, offset =3D ptex * HASH_PTE_SIZE_64 + 16; + + if (cpu->vhyp) { + PPCVirtualHypervisorClass *vhc =3D + PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); + vhc->hpte_set_r(cpu->vhyp, ptex, pte1); + return; + } + base =3D ppc_hash64_hpt_base(cpu); + + + /* The HW performs a non-atomic byte update */ + stb_phys(CPU(cpu)->as, base + offset, ((pte1 >> 8) & 0xff) | 0x01); +} + +static void ppc_hash64_set_c(PowerPCCPU *cpu, hwaddr ptex, uint64_t pte1) +{ + hwaddr base, offset =3D ptex * HASH_PTE_SIZE_64 + 15; + + if (cpu->vhyp) { + PPCVirtualHypervisorClass *vhc =3D + PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); + vhc->hpte_set_c(cpu->vhyp, ptex, pte1); + return; + } + base =3D ppc_hash64_hpt_base(cpu); + + /* The HW performs a non-atomic byte update */ + stb_phys(CPU(cpu)->as, base + offset, (pte1 & 0xff) | 0x80); +} + int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx, int mmu_idx) { @@ -734,7 +767,6 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr = eaddr, hwaddr ptex; ppc_hash_pte64_t pte; int exec_prot, pp_prot, amr_prot, prot; - uint64_t new_pte1; const int need_prot[] =3D {PAGE_READ, PAGE_WRITE, PAGE_EXEC}; hwaddr raddr; =20 @@ -882,19 +914,19 @@ skip_slb_search: =20 /* 6. Update PTE referenced and changed bits if necessary */ =20 - new_pte1 =3D pte.pte1 | HPTE64_R_R; /* set referenced bit */ - if (rwx =3D=3D 1) { - new_pte1 |=3D HPTE64_R_C; /* set changed (dirty) bit */ - } else { - /* - * Treat the page as read-only for now, so that a later write - * will pass through this function again to set the C bit - */ - prot &=3D ~PAGE_WRITE; + if (!(pte.pte1 & HPTE64_R_R)) { + ppc_hash64_set_r(cpu, ptex, pte.pte1); } - - if (new_pte1 !=3D pte.pte1) { - ppc_hash64_store_hpte(cpu, ptex, pte.pte0, new_pte1); + if (!(pte.pte1 & HPTE64_R_C)) { + if (rwx =3D=3D 1) { + ppc_hash64_set_c(cpu, ptex, pte.pte1); + } else { + /* + * Treat the page as read-only for now, so that a later write + * will pass through this function again to set the C bit + */ + prot &=3D ~PAGE_WRITE; + } } =20 /* 7. Determine the real address from the PTE */ @@ -953,24 +985,6 @@ hwaddr ppc_hash64_get_phys_page_debug(PowerPCCPU *cpu,= target_ulong addr) & TARGET_PAGE_MASK; } =20 -void ppc_hash64_store_hpte(PowerPCCPU *cpu, hwaddr ptex, - uint64_t pte0, uint64_t pte1) -{ - hwaddr base; - hwaddr offset =3D ptex * HASH_PTE_SIZE_64; - - if (cpu->vhyp) { - PPCVirtualHypervisorClass *vhc =3D - PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); - vhc->store_hpte(cpu->vhyp, ptex, pte0, pte1); - return; - } - base =3D ppc_hash64_hpt_base(cpu); - - stq_phys(CPU(cpu)->as, base + offset, pte0); - stq_phys(CPU(cpu)->as, base + offset + HASH_PTE_SIZE_64 / 2, pte1); -} - void ppc_hash64_tlb_flush_hpte(PowerPCCPU *cpu, target_ulong ptex, target_ulong pte0, target_ulong pte1) { --=20 2.20.1 From nobody Sat May 18 20:37:11 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1554970075; cv=none; d=zoho.com; s=zohoarc; b=GPov677SqeRgOKXCqKSojTRXsCTavZZ9exaVzjvO38Ip7ZFJOA+xJGxPru1I5/smG2C6EE/Gt2WvD4U7AgF1u2PIjUKPoKx0n3Rr75rYj7Y2AjIr3FCCrc2IGOwGXZbCdiVoFcza7mntMT2RIDnZRuTLGWGd7s3OXx32MDYw4Es= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1554970075; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=SixO0UMAKSgsO/3athTzxIo1pMzA+glty4bulHn2Zao=; b=cHxHyPtJ2DP8FngzeBVV9yAmR8OXigfUCsEXsY1EIE5w+2pHfLMt6vXqaygJrIAG9i8nWBVU446K6AMDinFDl4/8ctV7nykM+14sYJVUngYz0qBgWUf5PNi1TGR2FQhYT19I767ps/l+k9iA9my0qehrZdh+npGq4oqdVjJaIBs= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=null header.from= header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 155497007539025.591823486656494; Thu, 11 Apr 2019 01:07:55 -0700 (PDT) Received: from localhost ([127.0.0.1]:43664 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hEUkR-0004rM-8t for importer@patchew.org; Thu, 11 Apr 2019 04:07:51 -0400 Received: from eggs.gnu.org ([209.51.188.92]:48394) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hEUe1-00085x-UL for qemu-devel@nongnu.org; Thu, 11 Apr 2019 04:01:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hEUe0-0008JO-Ot for qemu-devel@nongnu.org; Thu, 11 Apr 2019 04:01:13 -0400 Received: from 10.mo178.mail-out.ovh.net ([46.105.76.150]:53005) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hEUe0-0008Hb-FC for qemu-devel@nongnu.org; Thu, 11 Apr 2019 04:01:12 -0400 Received: from player779.ha.ovh.net (unknown [10.109.146.175]) by mo178.mail-out.ovh.net (Postfix) with ESMTP id 877765BE7B for ; Thu, 11 Apr 2019 10:01:09 +0200 (CEST) Received: from kaod.org (lfbn-tou-1-40-22.w86-201.abo.wanadoo.fr [86.201.133.22]) (Authenticated sender: clg@kaod.org) by player779.ha.ovh.net (Postfix) with ESMTPSA id 70D0848B8D7F; Thu, 11 Apr 2019 08:01:00 +0000 (UTC) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Thu, 11 Apr 2019 10:00:02 +0200 Message-Id: <20190411080004.8690-5-clg@kaod.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190411080004.8690-1-clg@kaod.org> References: <20190411080004.8690-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 17601474719029169126 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgeduuddrudekgdduvddtucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucesvcftvggtihhpihgvnhhtshculddquddttddm Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 46.105.76.150 Subject: [Qemu-devel] [PATCH 4/6] ppc/hash32: Rework R and C bit updates X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, Suraj Jitindar Singh , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Benjamin Herrenschmidt With MT-TCG, we are now running translation in a racy way, thus we need to mimic hardware when it comes to updating the R and C bits, by doing byte stores. Signed-off-by: Benjamin Herrenschmidt Signed-off-by: C=C3=A9dric Le Goater --- target/ppc/mmu-hash32.c | 45 ++++++++++++++++++++++++++++------------- 1 file changed, 31 insertions(+), 14 deletions(-) diff --git a/target/ppc/mmu-hash32.c b/target/ppc/mmu-hash32.c index 3f4dee835e2d..55cf156a0b49 100644 --- a/target/ppc/mmu-hash32.c +++ b/target/ppc/mmu-hash32.c @@ -345,6 +345,24 @@ static hwaddr ppc_hash32_pteg_search(PowerPCCPU *cpu, = hwaddr pteg_off, return -1; } =20 +static void ppc_hash32_set_r(PowerPCCPU *cpu, hwaddr pte_offset, uint32_t = pte1) +{ + target_ulong base =3D ppc_hash32_hpt_base(cpu); + hwaddr offset =3D pte_offset + 6; + + /* The HW performs a non-atomic byte update */ + stb_phys(CPU(cpu)->as, base + offset, ((pte1 >> 8) & 0xff) | 0x01); +} + +static void ppc_hash32_set_c(PowerPCCPU *cpu, hwaddr pte_offset, uint64_t = pte1) +{ + target_ulong base =3D ppc_hash32_hpt_base(cpu); + hwaddr offset =3D pte_offset + 7; + + /* The HW performs a non-atomic byte update */ + stb_phys(CPU(cpu)->as, base + offset, (pte1 & 0xff) | 0x80); +} + static hwaddr ppc_hash32_htab_lookup(PowerPCCPU *cpu, target_ulong sr, target_ulong eaddr, ppc_hash_pte32_t *pte) @@ -403,7 +421,6 @@ int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, vaddr = eaddr, int rwx, hwaddr pte_offset; ppc_hash_pte32_t pte; int prot; - uint32_t new_pte1; const int need_prot[] =3D {PAGE_READ, PAGE_WRITE, PAGE_EXEC}; hwaddr raddr; =20 @@ -519,20 +536,20 @@ int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, vadd= r eaddr, int rwx, =20 /* 8. Update PTE referenced and changed bits if necessary */ =20 - new_pte1 =3D pte.pte1 | HPTE32_R_R; /* set referenced bit */ - if (rwx =3D=3D 1) { - new_pte1 |=3D HPTE32_R_C; /* set changed (dirty) bit */ - } else { - /* - * Treat the page as read-only for now, so that a later write - * will pass through this function again to set the C bit - */ - prot &=3D ~PAGE_WRITE; - } - - if (new_pte1 !=3D pte.pte1) { - ppc_hash32_store_hpte1(cpu, pte_offset, new_pte1); + if (!(pte.pte1 & HPTE32_R_R)) { + ppc_hash32_set_r(cpu, pte_offset, pte.pte1); } + if (!(pte.pte1 & HPTE32_R_C)) { + if (rwx =3D=3D 1) { + ppc_hash32_set_c(cpu, pte_offset, pte.pte1); + } else { + /* + * Treat the page as read-only for now, so that a later write + * will pass through this function again to set the C bit + */ + prot &=3D ~PAGE_WRITE; + } + } =20 /* 9. Determine the real address from the PTE */ =20 --=20 2.20.1 From nobody Sat May 18 20:37:11 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1554969794; cv=none; d=zoho.com; s=zohoarc; b=boVV8kSf2lHfy8PpEBWMw32CYfKQjBlOiADqFxKnFk56WP/1v2b9MwW13sA85BfaQMEWcPrSj8yhl/y7/7NDJRaS0z+Qey0mrGfJ4rn+sKiv2OeOMkAg5fH4YeftqIR3JGvuez6EED7BR8jOB2FOGzjVVv0N+azbhkLM85aHmQU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1554969794; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=M6cmkZLMdTSf7l1OJVVf8LmD/WA7f/MpG5W/bJr0Ls8=; b=GC6TON2CCE0Je8naqLngWbMYH2+KZYgLpnIZ+UEPFPGJF9kpY6vJ6n3kuhfExovJZ/UkFh+jRX/e/803Tkh/QX+kJb2uwJ+/CRjFPas7DhawAfYumKBuTbmKAqy0j3aGy7ELfjlwgTx0azw7rKXA+2Mw0tz0u4dt/3NNhu45wKk= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=null header.from= header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1554969794299205.72738501301433; Thu, 11 Apr 2019 01:03:14 -0700 (PDT) Received: from localhost ([127.0.0.1]:43577 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hEUfv-0000ve-AT for importer@patchew.org; Thu, 11 Apr 2019 04:03:11 -0400 Received: from eggs.gnu.org ([209.51.188.92]:48434) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hEUeA-0008N5-2o for qemu-devel@nongnu.org; Thu, 11 Apr 2019 04:01:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hEUe8-0008Ny-0J for qemu-devel@nongnu.org; Thu, 11 Apr 2019 04:01:22 -0400 Received: from 10.mo69.mail-out.ovh.net ([46.105.73.241]:33211) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hEUe7-0008Mt-Hr for qemu-devel@nongnu.org; Thu, 11 Apr 2019 04:01:19 -0400 Received: from player779.ha.ovh.net (unknown [10.109.159.152]) by mo69.mail-out.ovh.net (Postfix) with ESMTP id C12104E3E3 for ; Thu, 11 Apr 2019 10:01:16 +0200 (CEST) Received: from kaod.org (lfbn-tou-1-40-22.w86-201.abo.wanadoo.fr [86.201.133.22]) (Authenticated sender: clg@kaod.org) by player779.ha.ovh.net (Postfix) with ESMTPSA id 7FE1148B8E83; Thu, 11 Apr 2019 08:01:09 +0000 (UTC) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Thu, 11 Apr 2019 10:00:03 +0200 Message-Id: <20190411080004.8690-6-clg@kaod.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190411080004.8690-1-clg@kaod.org> References: <20190411080004.8690-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 17603445047195175910 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgeduuddrudekgdduvdduucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucesvcftvggtihhpihgvnhhtshculddquddttddm Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 46.105.73.241 Subject: [Qemu-devel] [PATCH 5/6] memory_ldst: Add atomic ops for PTE updates X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, Suraj Jitindar Singh , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Benjamin Herrenschmidt On some architectures, PTE updates for dirty and changed bits need to be performed atomically. This adds a couple of address_space_cmpxchg* helpers for that purpose. Signed-off-by: Benjamin Herrenschmidt Signed-off-by: C=C3=A9dric Le Goater Reviewed-by: David Gibson --- include/exec/memory_ldst.inc.h | 6 +++ memory_ldst.inc.c | 80 ++++++++++++++++++++++++++++++++++ 2 files changed, 86 insertions(+) diff --git a/include/exec/memory_ldst.inc.h b/include/exec/memory_ldst.inc.h index 272c20f02eae..f3cfa7e9a622 100644 --- a/include/exec/memory_ldst.inc.h +++ b/include/exec/memory_ldst.inc.h @@ -28,6 +28,12 @@ extern uint64_t glue(address_space_ldq, SUFFIX)(ARG1_DEC= L, hwaddr addr, MemTxAttrs attrs, MemTxResult *result); extern void glue(address_space_stl_notdirty, SUFFIX)(ARG1_DECL, hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result); +extern uint32_t glue(address_space_cmpxchgl_notdirty, SUFFIX)(ARG1_DECL, + hwaddr addr, uint32_t old, uint32_t new, MemTxAttrs attrs, + MemTxResult *result); +extern uint32_t glue(address_space_cmpxchgq_notdirty, SUFFIX)(ARG1_DECL, + hwaddr addr, uint64_t old, uint64_t new, MemTxAttrs attrs, + MemTxResult *result); extern void glue(address_space_stw, SUFFIX)(ARG1_DECL, hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result); extern void glue(address_space_stl, SUFFIX)(ARG1_DECL, diff --git a/memory_ldst.inc.c b/memory_ldst.inc.c index acf865b900d7..1d58d2fea67d 100644 --- a/memory_ldst.inc.c +++ b/memory_ldst.inc.c @@ -320,6 +320,86 @@ void glue(address_space_stl_notdirty, SUFFIX)(ARG1_DEC= L, RCU_READ_UNLOCK(); } =20 +/* This is meant to be used for atomic PTE updates under MT-TCG */ +uint32_t glue(address_space_cmpxchgl_notdirty, SUFFIX)(ARG1_DECL, + hwaddr addr, uint32_t old, uint32_t new, MemTxAttrs attrs, + MemTxResult *result) +{ + uint8_t *ptr; + MemoryRegion *mr; + hwaddr l =3D 4; + hwaddr addr1; + MemTxResult r; + uint8_t dirty_log_mask; + + /* Must test result */ + assert(result); + + RCU_READ_LOCK(); + mr =3D TRANSLATE(addr, &addr1, &l, true, attrs); + if (l < 4 || !memory_access_is_direct(mr, true)) { + r =3D MEMTX_ERROR; + } else { + uint32_t orig =3D old; + + ptr =3D qemu_map_ram_ptr(mr->ram_block, addr1); + old =3D atomic_cmpxchg(ptr, orig, new); + + if (old =3D=3D orig) { + dirty_log_mask =3D memory_region_get_dirty_log_mask(mr); + dirty_log_mask &=3D ~(1 << DIRTY_MEMORY_CODE); + cpu_physical_memory_set_dirty_range(memory_region_get_ram_addr= (mr) + + addr, 4, dirty_log_mask); + } + r =3D MEMTX_OK; + } + *result =3D r; + RCU_READ_UNLOCK(); + + return old; +} + +#ifdef CONFIG_ATOMIC64 +/* This is meant to be used for atomic PTE updates under MT-TCG */ +uint32_t glue(address_space_cmpxchgq_notdirty, SUFFIX)(ARG1_DECL, + hwaddr addr, uint64_t old, uint64_t new, MemTxAttrs attrs, + MemTxResult *result) +{ + uint8_t *ptr; + MemoryRegion *mr; + hwaddr l =3D 8; + hwaddr addr1; + MemTxResult r; + uint8_t dirty_log_mask; + + /* Must test result */ + assert(result); + + RCU_READ_LOCK(); + mr =3D TRANSLATE(addr, &addr1, &l, true, attrs); + if (l < 8 || !memory_access_is_direct(mr, true)) { + r =3D MEMTX_ERROR; + } else { + uint32_t orig =3D old; + + ptr =3D qemu_map_ram_ptr(mr->ram_block, addr1); + old =3D atomic_cmpxchg(ptr, orig, new); + + if (old =3D=3D orig) { + dirty_log_mask =3D memory_region_get_dirty_log_mask(mr); + dirty_log_mask &=3D ~(1 << DIRTY_MEMORY_CODE); + cpu_physical_memory_set_dirty_range(memory_region_get_ram_addr= (mr) + + addr, 8, dirty_log_mask); + } + r =3D MEMTX_OK; + } + *result =3D r; + RCU_READ_UNLOCK(); + + return old; +} +#endif /* CONFIG_ATOMIC64 */ + /* warning: addr must be aligned */ static inline void glue(address_space_stl_internal, SUFFIX)(ARG1_DECL, hwaddr addr, uint32_t val, MemTxAttrs attrs, --=20 2.20.1 From nobody Sat May 18 20:37:11 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; 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Thu, 11 Apr 2019 08:01:16 +0000 (UTC) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Thu, 11 Apr 2019 10:00:04 +0200 Message-Id: <20190411080004.8690-7-clg@kaod.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190411080004.8690-1-clg@kaod.org> References: <20190411080004.8690-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 17605696843720854502 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgeduuddrudekgdduvddtucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucesvcftvggtihhpihgvnhhtshculddquddttddm Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 46.105.34.113 Subject: [Qemu-devel] [PATCH 6/6] ppc: Fix radix RC updates X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, Suraj Jitindar Singh , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Benjamin Herrenschmidt They should be atomic for MTTCG. Note: a real POWER9 core doesn't actually implement atomic PTE updates, it always fault for SW to handle it. Only the nest MMU (used by some accelerator devices and GPUs) implements those HW updates. However, the architecture does allow the core to do it, and doing so in TCG is faster than letting the guest do it. Signed-off-by: Benjamin Herrenschmidt Signed-off-by: C=C3=A9dric Le Goater --- target/ppc/cpu.h | 1 + target/ppc/mmu-radix64.c | 70 +++++++++++++++++++++++++++++++++------- 2 files changed, 60 insertions(+), 11 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index a4420636dde0..5b4249ebdcbf 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -503,6 +503,7 @@ typedef struct ppc_v3_pate_t { #define DSISR_AMR 0x00200000 /* Unsupported Radix Tree Configuration */ #define DSISR_R_BADCONFIG 0x00080000 +#define DSISR_ATOMIC_RC 0x00040000 =20 /* SRR1 error code fields */ =20 diff --git a/target/ppc/mmu-radix64.c b/target/ppc/mmu-radix64.c index cac076ee92d9..458085d79ee0 100644 --- a/target/ppc/mmu-radix64.c +++ b/target/ppc/mmu-radix64.c @@ -28,6 +28,15 @@ #include "mmu-radix64.h" #include "mmu-book3s-v3.h" =20 +static inline bool ppc_radix64_hw_rc_updates(CPUPPCState *env) +{ +#ifdef CONFIG_ATOMIC64 + return true; +#else + return !qemu_tcg_mttcg_enabled(); +#endif +} + static bool ppc_radix64_get_fully_qualified_addr(CPUPPCState *env, vaddr e= addr, uint64_t *lpid, uint64_t = *pid) { @@ -136,11 +145,19 @@ static bool ppc_radix64_check_prot(PowerPCCPU *cpu, i= nt rwx, uint64_t pte, return true; } =20 + /* Check RC bits if necessary */ + if (!ppc_radix64_hw_rc_updates(env)) { + if (!(pte & R_PTE_R) || ((rwx =3D=3D 1) && !(pte & R_PTE_C))) { + *fault_cause |=3D DSISR_ATOMIC_RC; + return true; + } + } + return false; } =20 -static void ppc_radix64_set_rc(PowerPCCPU *cpu, int rwx, uint64_t pte, - hwaddr pte_addr, int *prot) +static uint64_t ppc_radix64_set_rc(PowerPCCPU *cpu, int rwx, uint64_t pte, + hwaddr pte_addr) { CPUState *cs =3D CPU(cpu); uint64_t npte; @@ -149,17 +166,39 @@ static void ppc_radix64_set_rc(PowerPCCPU *cpu, int r= wx, uint64_t pte, =20 if (rwx =3D=3D 1) { /* Store/Write */ npte |=3D R_PTE_C; /* Set change bit */ - } else { + } + if (pte =3D=3D npte) { + return pte; + } + +#ifdef CONFIG_ATOMIC64 + if (qemu_tcg_mttcg_enabled()) { + uint64_t old_be =3D cpu_to_be32(pte); + uint64_t new_be =3D cpu_to_be32(npte); + MemTxResult result; + uint64_t old_ret; + + old_ret =3D address_space_cmpxchgq_notdirty(cs->as, pte_addr, + old_be, new_be, + MEMTXATTRS_UNSPECIFIED, + &result); + if (result =3D=3D MEMTX_OK) { + if (old_ret !=3D old_be && old_ret !=3D new_be) { + return 0; + } + return npte; + } + /* - * Treat the page as read-only for now, so that a later write - * will pass through this function again to set the C bit. + * Do we need to support this case where PTEs aren't in RAM ? + * + * For now fallback to non-atomic case */ - *prot &=3D ~PAGE_WRITE; } +#endif =20 - if (pte ^ npte) { /* If pte has changed then write it back */ - stq_phys(cs->as, pte_addr, npte); - } + stq_phys(cs->as, pte_addr, npte); + return npte; } =20 static uint64_t ppc_radix64_walk_tree(PowerPCCPU *cpu, vaddr eaddr, @@ -288,6 +327,7 @@ int ppc_radix64_handle_mmu_fault(PowerPCCPU *cpu, vaddr= eaddr, int rwx, =20 /* Walk Radix Tree from Process Table Entry to Convert EA to RA */ page_size =3D PRTBE_R_GET_RTS(prtbe0); + restart: pte =3D ppc_radix64_walk_tree(cpu, eaddr & R_EADDR_MASK, prtbe0 & PRTBE_R_RPDB, prtbe0 & PRTBE_R_RP= DS, &raddr, &page_size, &fault_cause, &pte_add= r); @@ -298,8 +338,16 @@ int ppc_radix64_handle_mmu_fault(PowerPCCPU *cpu, vadd= r eaddr, int rwx, } =20 /* Update Reference and Change Bits */ - ppc_radix64_set_rc(cpu, rwx, pte, pte_addr, &prot); - + if (ppc_radix64_hw_rc_updates(env)) { + pte =3D ppc_radix64_set_rc(cpu, rwx, pte, pte_addr); + if (!pte) { + goto restart; + } + } + /* If the page doesn't have C, treat it as read only */ + if (!(pte & R_PTE_C)) { + prot &=3D ~PAGE_WRITE; + } tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK, prot, mmu_idx, 1UL << page_size); return 0; --=20 2.20.1