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[2.103.80.5]) by smtp.gmail.com with ESMTPSA id z10sm2966029wmi.15.2019.04.05.09.09.49 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 05 Apr 2019 09:09:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=pA28vCbZx6lzm3kJbSa2/z8AMN5bASGS+zrnO8I7fu0=; b=Gf8xXzB+QtjPvJhRtFwRMUcJAC+fO59ePj1Ro5I3XScybLf238JhuyYWdzmimv+rNn 2EomjDcD2R5EmEHbAilLoZ/bE3t8d+4A/u7vpcSxmNMXmOTUfAW0jJge+qD+JpH/239f Z8bB8h2hS/eVpkkcVu7ijA9p1ZAS5xGcHld4U3Ch4frf+ovU4GxH8wVZkI4Fcqv0ghHl ePC/6ez5VfYnbvezwVAd+pv6HZn9BFoYUWxzc3P6nVX86GNa+kliw+B5dH5LBIlYiU8t Gc7OqKzBleTie5mEADZttYBTcySzaXOw/nwpn+I8FfvIDMJ5fmOdTvkjqzLAh7E3qw5E tYng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=pA28vCbZx6lzm3kJbSa2/z8AMN5bASGS+zrnO8I7fu0=; b=trlRK9Va0E2UVPoDqBzMNp+ghtFWAy5Fz8vDnQW5sI27yQgIQsu1kbfZE3xRjJ9V7L TfdWxwWnmkfFppmEwVOI96fQt+wtnWBG3Qhwn8YSG+04bt+nYk8Ol9Eqpp8j131mSMyQ 668amNw4+8YLP/KkPIKb5P6deNvBljUNp935YQNVx+NWKO7a51u2Ft33ipt3ir3f28op 91wiiuopkhOMbEtJN2XaupRMcktJe/6sqiIKgeo94M4viAnF7F3RQHZ8jXjSyy/k/JFY nYhx3nByBo8vzSMhyOn+cKSOGCuOQdAAKj8WQaHPe+O4GwLos6RplGe6I94Yq9zMsDlJ Ou5g== X-Gm-Message-State: APjAAAX4cnwS9gLRaqlwl6F+fUZG5k+MDfp5T8FpEQ/tfaHKAegUSsBd wSf1nyeCFzy1ydYGYSABkg== X-Google-Smtp-Source: APXvYqwY+I90hozICd1wJGoHAcIllHqDDHo+z+EbbL/il5u/gmuUawKk97EDiPOHciVvM/SF3z9cKQ== X-Received: by 2002:a5d:4446:: with SMTP id x6mr8856393wrr.147.1554480590982; Fri, 05 Apr 2019 09:09:50 -0700 (PDT) From: Jules Irenge To: amarkovic@wavecomp.com Date: Fri, 5 Apr 2019 17:09:35 +0100 Message-Id: <20190405160938.27494-2-jbi.octave@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190405160938.27494-1-jbi.octave@gmail.com> References: <20190405160938.27494-1-jbi.octave@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 Subject: [Qemu-devel] [PATCH v3 1/4] target/mips: realign comments to fix checkpatch warnings X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: arikalo@wavecomp.com, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Realign comments to fix warnings issued by checkpatch.pl tool "WARNING: Block comments use a leading /* on a separate line" within "target/mips/cpu.h" file. Signed-off-by: Jules Irenge --- target/mips/cpu.h | 34 ++++++++++++++++++++++------------ 1 file changed, 22 insertions(+), 12 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index a10eeb0de3..5dd71dbe21 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -37,7 +37,8 @@ union fpr_t { /* FPU/MSA register mapping is not tested on big-endian hosts. */ wr_t wr; /* vector data */ }; -/* define FP_ENDIAN_IDX to access the same location +/* + * define FP_ENDIAN_IDX to access the same location * in the fpr_t union regardless of the host endianness */ #if defined(HOST_WORDS_BIGENDIAN) @@ -963,9 +964,11 @@ struct CPUMIPSState { /* TMASK defines different execution modes */ #define MIPS_HFLAG_TMASK 0x1F5807FF #define MIPS_HFLAG_MODE 0x00007 /* execution modes */ - /* The KSU flags must be the lowest bits in hflags. The flag order - must be the same as defined for CP0 Status. This allows to use - the bits as the value of mmu_idx. */ + /* + * The KSU flags must be the lowest bits in hflags. The flag order + * must be the same as defined for CP0 Status. This allows to use + * the bits as the value of mmu_idx. + */ #define MIPS_HFLAG_KSU 0x00003 /* kernel/supervisor/user mode mask */ #define MIPS_HFLAG_UM 0x00002 /* user mode flag */ #define MIPS_HFLAG_SM 0x00001 /* supervisor mode flag */ @@ -975,18 +978,22 @@ struct CPUMIPSState { #define MIPS_HFLAG_CP0 0x00010 /* CP0 enabled */ #define MIPS_HFLAG_FPU 0x00020 /* FPU enabled */ #define MIPS_HFLAG_F64 0x00040 /* 64-bit FPU enabled */ - /* True if the MIPS IV COP1X instructions can be used. This also - controls the non-COP1X instructions RECIP.S, RECIP.D, RSQRT.S - and RSQRT.D. */ + /* + * True if the MIPS IV COP1X instructions can be used. This also + * controls the non-COP1X instructions RECIP.S, RECIP.D, RSQRT.S + * and RSQRT.D. + */ #define MIPS_HFLAG_COP1X 0x00080 /* COP1X instructions enabled */ #define MIPS_HFLAG_RE 0x00100 /* Reversed endianness */ #define MIPS_HFLAG_AWRAP 0x00200 /* 32-bit compatibility address wrapping= */ #define MIPS_HFLAG_M16 0x00400 /* MIPS16 mode flag */ #define MIPS_HFLAG_M16_SHIFT 10 - /* If translation is interrupted between the branch instruction and + /* + * If translation is interrupted between the branch instruction and * the delay slot, record what type of branch it is so that we can * resume translation properly. It might be possible to reduce - * this from three bits to two. */ + * this from three bits to two. + */ #define MIPS_HFLAG_BMASK_BASE 0x803800 #define MIPS_HFLAG_B 0x00800 /* Unconditional branch */ #define MIPS_HFLAG_BC 0x01000 /* Conditional branch */ @@ -1073,8 +1080,10 @@ void mips_cpu_list (FILE *f, fprintf_function cpu_fp= rintf); extern void cpu_wrdsp(uint32_t rs, uint32_t mask_num, CPUMIPSState *env); extern uint32_t cpu_rddsp(uint32_t mask_num, CPUMIPSState *env); =20 -/* MMU modes definitions. We carefully match the indices with our - hflags layout. */ +/* + * MMU modes definitions. We carefully match the indices with our + * hflags layout. + */ #define MMU_MODE0_SUFFIX _kernel #define MMU_MODE1_SUFFIX _super #define MMU_MODE2_SUFFIX _user @@ -1097,7 +1106,8 @@ static inline int cpu_mmu_index (CPUMIPSState *env, b= ool ifetch) =20 #include "exec/cpu-all.h" =20 -/* Memory access type : +/* + * Memory access type : * may be needed for precise access rights control and precise exceptions. */ enum { --=20 2.20.1 From nobody Sun Oct 12 19:05:06 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1554480848630481.5361262561456; Fri, 5 Apr 2019 09:14:08 -0700 (PDT) Received: from localhost ([127.0.0.1]:44226 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hCRTZ-0005zf-9R for importer@patchew.org; Fri, 05 Apr 2019 12:13:57 -0400 Received: from eggs.gnu.org ([209.51.188.92]:40046) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hCRQY-00047t-6K for qemu-devel@nongnu.org; Fri, 05 Apr 2019 12:10:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hCRQQ-0001oa-AG for qemu-devel@nongnu.org; Fri, 05 Apr 2019 12:10:46 -0400 Received: from mail-wm1-x341.google.com ([2a00:1450:4864:20::341]:39957) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hCRPf-0000Mp-9W for qemu-devel@nongnu.org; Fri, 05 Apr 2019 12:10:39 -0400 Received: by mail-wm1-x341.google.com with SMTP id z24so7843669wmi.5 for ; Fri, 05 Apr 2019 09:09:53 -0700 (PDT) Received: from ninjatsu.lan (host-2-103-80-5.as13285.net. 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X-Received-From: 2a00:1450:4864:20::341 Subject: [Qemu-devel] [PATCH v3 2/4] target/mips: add or remove space to fix checkpatch errors X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: arikalo@wavecomp.com, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Add or remove space to fix errors issued by checkpatch.pl tool "ERROR: spaces required around ..." "ERROR: space required after that" "ERROR: space required before the open parenthesis" "ERROR: space prohibited between function name and open parenthesis" within "target/mips/cpu.h" file. Signed-off-by: Jules Irenge --- target/mips/cpu.h | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 5dd71dbe21..0d2718d7bf 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -22,10 +22,10 @@ typedef struct CPUMIPSTLBContext CPUMIPSTLBContext; =20 typedef union wr_t wr_t; union wr_t { - int8_t b[MSA_WRLEN/8]; - int16_t h[MSA_WRLEN/16]; - int32_t w[MSA_WRLEN/32]; - int64_t d[MSA_WRLEN/64]; + int8_t b[MSA_WRLEN / 8]; + int16_t h[MSA_WRLEN / 16]; + int32_t w[MSA_WRLEN / 32]; + int64_t d[MSA_WRLEN / 64]; }; =20 typedef union fpr_t fpr_t; @@ -72,16 +72,16 @@ struct CPUMIPSFPUContext { #define FCR31_FS 24 #define FCR31_ABS2008 19 #define FCR31_NAN2008 18 -#define SET_FP_COND(num,env) do { ((env).fcr31) |=3D ((num) ? (1 << ((= num) + 24)) : (1 << 23)); } while(0) -#define CLEAR_FP_COND(num,env) do { ((env).fcr31) &=3D ~((num) ? (1 << (= (num) + 24)) : (1 << 23)); } while(0) +#define SET_FP_COND(num, env) do { ((env).fcr31) |=3D ((num) ? (1 << (= (num) + 24)) : (1 << 23)); } while (0) +#define CLEAR_FP_COND(num, env) do { ((env).fcr31) &=3D ~((num) ? (1 << = ((num) + 24)) : (1 << 23)); } while (0) #define GET_FP_COND(env) ((((env).fcr31 >> 24) & 0xfe) | (((env).f= cr31 >> 23) & 0x1)) #define GET_FP_CAUSE(reg) (((reg) >> 12) & 0x3f) #define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f) #define GET_FP_FLAGS(reg) (((reg) >> 2) & 0x1f) -#define SET_FP_CAUSE(reg,v) do { (reg) =3D ((reg) & ~(0x3f << 12)) | = ((v & 0x3f) << 12); } while(0) -#define SET_FP_ENABLE(reg,v) do { (reg) =3D ((reg) & ~(0x1f << 7)) | = ((v & 0x1f) << 7); } while(0) -#define SET_FP_FLAGS(reg,v) do { (reg) =3D ((reg) & ~(0x1f << 2)) | = ((v & 0x1f) << 2); } while(0) -#define UPDATE_FP_FLAGS(reg,v) do { (reg) |=3D ((v & 0x1f) << 2); } whil= e(0) +#define SET_FP_CAUSE(reg, v) do { (reg) =3D ((reg) & ~(0x3f << 12)) |= ((v & 0x3f) << 12); } while (0) +#define SET_FP_ENABLE(reg, v) do { (reg) =3D ((reg) & ~(0x1f << 7)) |= ((v & 0x1f) << 7); } while (0) +#define SET_FP_FLAGS(reg, v) do { (reg) =3D ((reg) & ~(0x1f << 2)) |= ((v & 0x1f) << 2); } while (0) +#define UPDATE_FP_FLAGS(reg, v) do { (reg) |=3D ((v & 0x1f) << 2); } whi= le (0) #define FP_INEXACT 1 #define FP_UNDERFLOW 2 #define FP_OVERFLOW 4 @@ -1072,7 +1072,7 @@ static inline MIPSCPU *mips_env_get_cpu(CPUMIPSState = *env) =20 #define ENV_OFFSET offsetof(MIPSCPU, env) =20 -void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf); +void mips_cpu_list(FILE *f, fprintf_function cpu_fprintf); =20 #define cpu_signal_handler cpu_mips_signal_handler #define cpu_list mips_cpu_list @@ -1099,7 +1099,7 @@ static inline int hflags_mmu_index(uint32_t hflags) } } =20 -static inline int cpu_mmu_index (CPUMIPSState *env, bool ifetch) +static inline int cpu_mmu_index(CPUMIPSState *env, bool ifetch) { return hflags_mmu_index(env->hflags); } @@ -1107,7 +1107,7 @@ static inline int cpu_mmu_index (CPUMIPSState *env, b= ool ifetch) #include "exec/cpu-all.h" =20 /* - * Memory access type : + * Memory access type: * may be needed for precise access rights control and precise exceptions. */ enum { @@ -1192,7 +1192,7 @@ void cpu_mips_soft_irq(CPUMIPSState *env, int irq, in= t level); void itc_reconfigure(struct MIPSITUState *tag); =20 /* helper.c */ -target_ulong exception_resume_pc (CPUMIPSState *env); +target_ulong exception_resume_pc(CPUMIPSState *env); =20 static inline void restore_snan_bit_mode(CPUMIPSState *env) { --=20 2.20.1 From nobody Sun Oct 12 19:05:06 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1554480745042980.1432656227903; Fri, 5 Apr 2019 09:12:25 -0700 (PDT) Received: from localhost ([127.0.0.1]:44213 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hCRRv-0004vs-Nn for importer@patchew.org; Fri, 05 Apr 2019 12:12:15 -0400 Received: from eggs.gnu.org ([209.51.188.92]:40072) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hCRQY-00047x-7k for qemu-devel@nongnu.org; Fri, 05 Apr 2019 12:10:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hCRQR-0001qN-Pf for qemu-devel@nongnu.org; Fri, 05 Apr 2019 12:10:49 -0400 Received: from mail-wm1-x341.google.com ([2a00:1450:4864:20::341]:51818) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hCRPf-0000Ox-EW for qemu-devel@nongnu.org; Fri, 05 Apr 2019 12:10:40 -0400 Received: by mail-wm1-x341.google.com with SMTP id 4so7294842wmf.1 for ; Fri, 05 Apr 2019 09:09:54 -0700 (PDT) Received: from ninjatsu.lan (host-2-103-80-5.as13285.net. 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X-Received-From: 2a00:1450:4864:20::341 Subject: [Qemu-devel] [PATCH v3 3/4] target/mips: wrap lines to fix checkpatch errors X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: arikalo@wavecomp.com, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Wrap lines to fix errors issued by checkpatch.pl tool "ERROR: line over 90 characters" within "target/mips/cpu.h" file. Signed-off-by: Jules Irenge --- target/mips/cpu.h | 25 +++++++++++++++++++------ 1 file changed, 19 insertions(+), 6 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 0d2718d7bf..e2f421359a 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -72,15 +72,28 @@ struct CPUMIPSFPUContext { #define FCR31_FS 24 #define FCR31_ABS2008 19 #define FCR31_NAN2008 18 -#define SET_FP_COND(num, env) do { ((env).fcr31) |=3D ((num) ? (1 << (= (num) + 24)) : (1 << 23)); } while (0) -#define CLEAR_FP_COND(num, env) do { ((env).fcr31) &=3D ~((num) ? (1 << = ((num) + 24)) : (1 << 23)); } while (0) -#define GET_FP_COND(env) ((((env).fcr31 >> 24) & 0xfe) | (((env).f= cr31 >> 23) & 0x1)) +#define SET_FP_COND(num, env) do { ((env).fcr31) |=3D \ + ((num) ? (1 << ((num) + 24)) : \ + (1 << 23)); \ + } while (0) +#define CLEAR_FP_COND(num, env) do { ((env).fcr31) &=3D \ + ~((num) ? (1 << ((num) + 24)) :\ + (1 << 23)); \ + } while (0) +#define GET_FP_COND(env) ((((env).fcr31 >> 24) & 0xfe) | \ + (((env).fcr31 >> 23) & 0x1)) #define GET_FP_CAUSE(reg) (((reg) >> 12) & 0x3f) #define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f) #define GET_FP_FLAGS(reg) (((reg) >> 2) & 0x1f) -#define SET_FP_CAUSE(reg, v) do { (reg) =3D ((reg) & ~(0x3f << 12)) |= ((v & 0x3f) << 12); } while (0) -#define SET_FP_ENABLE(reg, v) do { (reg) =3D ((reg) & ~(0x1f << 7)) |= ((v & 0x1f) << 7); } while (0) -#define SET_FP_FLAGS(reg, v) do { (reg) =3D ((reg) & ~(0x1f << 2)) |= ((v & 0x1f) << 2); } while (0) +#define SET_FP_CAUSE(reg, v) do { (reg) =3D ((reg) & ~(0x3f << 12)) |= \ + ((v & 0x3f) << 12); \ + } while (0) +#define SET_FP_ENABLE(reg, v) do { (reg) =3D ((reg) & ~(0x1f << 7)) |\ + ((v & 0x1f) << 7);\ + } while (0) +#define SET_FP_FLAGS(reg, v) do { (reg) =3D ((reg) & ~(0x1f << 2)) |\ + ((v & 0x1f) << 2);\ + } while (0) #define UPDATE_FP_FLAGS(reg, v) do { (reg) |=3D ((v & 0x1f) << 2); } whi= le (0) #define FP_INEXACT 1 #define FP_UNDERFLOW 2 --=20 2.20.1 From nobody Sun Oct 12 19:05:06 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1554480933307654.4877153152374; Fri, 5 Apr 2019 09:15:33 -0700 (PDT) Received: from localhost ([127.0.0.1]:44266 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hCRV5-0007Jb-8Q for importer@patchew.org; Fri, 05 Apr 2019 12:15:31 -0400 Received: from eggs.gnu.org ([209.51.188.92]:40122) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hCRQa-000496-7n for qemu-devel@nongnu.org; Fri, 05 Apr 2019 12:10:53 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hCRQY-0001w6-7E for qemu-devel@nongnu.org; Fri, 05 Apr 2019 12:10:51 -0400 Received: from mail-wm1-x342.google.com ([2a00:1450:4864:20::342]:54870) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hCRPh-0000Qi-Gn for qemu-devel@nongnu.org; Fri, 05 Apr 2019 12:10:42 -0400 Received: by mail-wm1-x342.google.com with SMTP id c1so7278535wml.4 for ; Fri, 05 Apr 2019 09:09:56 -0700 (PDT) Received: from ninjatsu.lan (host-2-103-80-5.as13285.net. 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X-Received-From: 2a00:1450:4864:20::342 Subject: [Qemu-devel] [PATCH v3 4/4] target/mips: replace tab code indent with spaces to fix checkpatch errors X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: arikalo@wavecomp.com, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Replace tab code indent with spaces to fix errors issued by checkpatch.pl t= ool "ERROR: code indent should never use tabs" within "target/mips/cpu.h" file. Signed-off-by: Jules Irenge --- target/mips/cpu.h | 138 +++++++++++++++++++++++----------------------- 1 file changed, 69 insertions(+), 69 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index e2f421359a..03ebdba90f 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -109,25 +109,25 @@ struct CPUMIPSFPUContext { typedef struct CPUMIPSMVPContext CPUMIPSMVPContext; struct CPUMIPSMVPContext { int32_t CP0_MVPControl; -#define CP0MVPCo_CPA 3 -#define CP0MVPCo_STLB 2 -#define CP0MVPCo_VPC 1 -#define CP0MVPCo_EVP 0 +#define CP0MVPCo_CPA 3 +#define CP0MVPCo_STLB 2 +#define CP0MVPCo_VPC 1 +#define CP0MVPCo_EVP 0 int32_t CP0_MVPConf0; -#define CP0MVPC0_M 31 -#define CP0MVPC0_TLBS 29 -#define CP0MVPC0_GS 28 -#define CP0MVPC0_PCP 27 -#define CP0MVPC0_PTLBE 16 -#define CP0MVPC0_TCA 15 -#define CP0MVPC0_PVPE 10 -#define CP0MVPC0_PTC 0 +#define CP0MVPC0_M 31 +#define CP0MVPC0_TLBS 29 +#define CP0MVPC0_GS 28 +#define CP0MVPC0_PCP 27 +#define CP0MVPC0_PTLBE 16 +#define CP0MVPC0_TCA 15 +#define CP0MVPC0_PVPE 10 +#define CP0MVPC0_PTC 0 int32_t CP0_MVPConf1; -#define CP0MVPC1_CIM 31 -#define CP0MVPC1_CIF 30 -#define CP0MVPC1_PCX 20 -#define CP0MVPC1_PCP2 10 -#define CP0MVPC1_PCP1 0 +#define CP0MVPC1_CIM 31 +#define CP0MVPC1_CIF 30 +#define CP0MVPC1_PCX 20 +#define CP0MVPC1_PCP2 10 +#define CP0MVPC1_PCP1 0 }; =20 typedef struct mips_def_t mips_def_t; @@ -495,44 +495,44 @@ struct CPUMIPSState { */ int32_t CP0_Random; int32_t CP0_VPEControl; -#define CP0VPECo_YSI 21 -#define CP0VPECo_GSI 20 -#define CP0VPECo_EXCPT 16 -#define CP0VPECo_TE 15 -#define CP0VPECo_TargTC 0 +#define CP0VPECo_YSI 21 +#define CP0VPECo_GSI 20 +#define CP0VPECo_EXCPT 16 +#define CP0VPECo_TE 15 +#define CP0VPECo_TargTC 0 int32_t CP0_VPEConf0; -#define CP0VPEC0_M 31 -#define CP0VPEC0_XTC 21 -#define CP0VPEC0_TCS 19 -#define CP0VPEC0_SCS 18 -#define CP0VPEC0_DSC 17 -#define CP0VPEC0_ICS 16 -#define CP0VPEC0_MVP 1 -#define CP0VPEC0_VPA 0 +#define CP0VPEC0_M 31 +#define CP0VPEC0_XTC 21 +#define CP0VPEC0_TCS 19 +#define CP0VPEC0_SCS 18 +#define CP0VPEC0_DSC 17 +#define CP0VPEC0_ICS 16 +#define CP0VPEC0_MVP 1 +#define CP0VPEC0_VPA 0 int32_t CP0_VPEConf1; -#define CP0VPEC1_NCX 20 -#define CP0VPEC1_NCP2 10 -#define CP0VPEC1_NCP1 0 +#define CP0VPEC1_NCX 20 +#define CP0VPEC1_NCP2 10 +#define CP0VPEC1_NCP1 0 target_ulong CP0_YQMask; target_ulong CP0_VPESchedule; target_ulong CP0_VPEScheFBack; int32_t CP0_VPEOpt; -#define CP0VPEOpt_IWX7 15 -#define CP0VPEOpt_IWX6 14 -#define CP0VPEOpt_IWX5 13 -#define CP0VPEOpt_IWX4 12 -#define CP0VPEOpt_IWX3 11 -#define CP0VPEOpt_IWX2 10 -#define CP0VPEOpt_IWX1 9 -#define CP0VPEOpt_IWX0 8 -#define CP0VPEOpt_DWX7 7 -#define CP0VPEOpt_DWX6 6 -#define CP0VPEOpt_DWX5 5 -#define CP0VPEOpt_DWX4 4 -#define CP0VPEOpt_DWX3 3 -#define CP0VPEOpt_DWX2 2 -#define CP0VPEOpt_DWX1 1 -#define CP0VPEOpt_DWX0 0 +#define CP0VPEOpt_IWX7 15 +#define CP0VPEOpt_IWX6 14 +#define CP0VPEOpt_IWX5 13 +#define CP0VPEOpt_IWX4 12 +#define CP0VPEOpt_IWX3 11 +#define CP0VPEOpt_IWX2 10 +#define CP0VPEOpt_IWX1 9 +#define CP0VPEOpt_IWX0 8 +#define CP0VPEOpt_DWX7 7 +#define CP0VPEOpt_DWX6 6 +#define CP0VPEOpt_DWX5 5 +#define CP0VPEOpt_DWX4 4 +#define CP0VPEOpt_DWX3 3 +#define CP0VPEOpt_DWX2 2 +#define CP0VPEOpt_DWX1 1 +#define CP0VPEOpt_DWX0 0 /* * CP0 Register 2 */ @@ -639,33 +639,33 @@ struct CPUMIPSState { #define CP0PC_PSN 0 /* 5..0 */ int32_t CP0_SRSConf0_rw_bitmask; int32_t CP0_SRSConf0; -#define CP0SRSC0_M 31 -#define CP0SRSC0_SRS3 20 -#define CP0SRSC0_SRS2 10 -#define CP0SRSC0_SRS1 0 +#define CP0SRSC0_M 31 +#define CP0SRSC0_SRS3 20 +#define CP0SRSC0_SRS2 10 +#define CP0SRSC0_SRS1 0 int32_t CP0_SRSConf1_rw_bitmask; int32_t CP0_SRSConf1; -#define CP0SRSC1_M 31 -#define CP0SRSC1_SRS6 20 -#define CP0SRSC1_SRS5 10 -#define CP0SRSC1_SRS4 0 +#define CP0SRSC1_M 31 +#define CP0SRSC1_SRS6 20 +#define CP0SRSC1_SRS5 10 +#define CP0SRSC1_SRS4 0 int32_t CP0_SRSConf2_rw_bitmask; int32_t CP0_SRSConf2; -#define CP0SRSC2_M 31 -#define CP0SRSC2_SRS9 20 -#define CP0SRSC2_SRS8 10 -#define CP0SRSC2_SRS7 0 +#define CP0SRSC2_M 31 +#define CP0SRSC2_SRS9 20 +#define CP0SRSC2_SRS8 10 +#define CP0SRSC2_SRS7 0 int32_t CP0_SRSConf3_rw_bitmask; int32_t CP0_SRSConf3; -#define CP0SRSC3_M 31 -#define CP0SRSC3_SRS12 20 -#define CP0SRSC3_SRS11 10 -#define CP0SRSC3_SRS10 0 +#define CP0SRSC3_M 31 +#define CP0SRSC3_SRS12 20 +#define CP0SRSC3_SRS11 10 +#define CP0SRSC3_SRS10 0 int32_t CP0_SRSConf4_rw_bitmask; int32_t CP0_SRSConf4; -#define CP0SRSC4_SRS15 20 -#define CP0SRSC4_SRS14 10 -#define CP0SRSC4_SRS13 0 +#define CP0SRSC4_SRS15 20 +#define CP0SRSC4_SRS14 10 +#define CP0SRSC4_SRS13 0 /* * CP0 Register 7 */ @@ -691,7 +691,7 @@ struct CPUMIPSState { * CP0 Register 10 */ target_ulong CP0_EntryHi; -#define CP0EnHi_EHINV 10 +#define CP0EnHi_EHINV 10 target_ulong CP0_EntryHi_ASID_mask; /* * CP0 Register 11 --=20 2.20.1