From nobody Sun May 19 12:26:29 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1554399756567431.03695019309407; Thu, 4 Apr 2019 10:42:36 -0700 (PDT) Received: from localhost ([127.0.0.1]:57999 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hC6Nf-0000LT-Dw for importer@patchew.org; Thu, 04 Apr 2019 13:42:27 -0400 Received: from eggs.gnu.org ([209.51.188.92]:59593) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hC6Kv-0006rg-6a for qemu-devel@nongnu.org; Thu, 04 Apr 2019 13:39:38 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hC6Kt-0007Uo-VC for qemu-devel@nongnu.org; Thu, 04 Apr 2019 13:39:37 -0400 Received: from mail-wm1-x344.google.com ([2a00:1450:4864:20::344]:39972) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hC6Kt-0007Rz-Ly for qemu-devel@nongnu.org; Thu, 04 Apr 2019 13:39:35 -0400 Received: by mail-wm1-x344.google.com with SMTP id z24so4424479wmi.5 for ; Thu, 04 Apr 2019 10:39:33 -0700 (PDT) Received: from ninjatsu.public.libraries.mcc ([91.235.65.22]) by smtp.gmail.com with ESMTPSA id i28sm56290924wrc.32.2019.04.04.10.39.30 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 04 Apr 2019 10:39:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=pA28vCbZx6lzm3kJbSa2/z8AMN5bASGS+zrnO8I7fu0=; b=njfA3J45n+8l6j3HhdJzW6c916kaons/kI/X+OgTXkZhm7zpXZUOVL6Tx2ExZZQtCR rrPIlywonpQrJ5rRTUSmOv16rFHD2MMYsk6SM96OB4frYDwkBwYrRDSKyaYjAaYTZrAy FLX79eRiiuqj7x03VHVD4xvd1xvD9UPICAvqq5GEEVzps92YnhfvPoSloLiXsXZSmcBo Tdy5k9Q/m3/Njv2tH+pH6HtaidzH1m3cvFUYoOAJfXk1JddrYJQv8TTuk846nY/ExKnr 5YVkbkQGUBN1TTxoMI5mtCY1vSOA2LsCVLbFtb7u2S9wC/8HMcO5Rk47b1rsV45NFm0T qxbg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=pA28vCbZx6lzm3kJbSa2/z8AMN5bASGS+zrnO8I7fu0=; b=BeQxo80VVB448Kz5caDw+u8fSfodSYsOqNwUS/g2RUcjVuoaZqlirKNKwwf/4Rz630 x9r/xMlYgjyoyoBODjtrL1PWOVwSg6ePnDhjDhOrEplpBQ0o7ceC5Kqh6UEdpTCMMUYe 1VS0g8WJJUwObmpmhP9vQCJIijItNFKzZQLbCN7z3+/xqJtHe4Udy60A4ku7HV9s1TY3 vqekuxfeAXttHqdlYgqR+wH/WogdTRqReFPlircV3inhgcF3Qg/EF5VrcU0N0okfWV52 sHl5kUmbcYw+NM3XdL8LrMnGb4HaGC05iAd8y4IW+PRsBgAVKwJoIXCwgC2ic1nxnPr5 lCzQ== X-Gm-Message-State: APjAAAVNSJh3x48kIsdPUAzMY29A1CtIkdsH6XROO2aK7PAEFDbwkleX 7+bRITlFk8HwDcDov1x9omKWGqhADg== X-Google-Smtp-Source: APXvYqwkL1NJ3vZ9c2JC1S2+5Jr2eAWuuGYTC4lA1CPNl18dz//BOeyLEQAv4VGFmnKdgtdFlRur8g== X-Received: by 2002:a1c:804c:: with SMTP id b73mr4824552wmd.116.1554399572288; Thu, 04 Apr 2019 10:39:32 -0700 (PDT) From: Jules Irenge To: amarkovic@wavecomp.com Date: Thu, 4 Apr 2019 18:39:20 +0100 Message-Id: <20190404173921.30841-2-jbi.octave@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190404173921.30841-1-jbi.octave@gmail.com> References: <20190404173921.30841-1-jbi.octave@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::344 Subject: [Qemu-devel] [PATCH v2 1/2] target/mips: realign comments to fix checkpatch warnings X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: arikalo@wavecomp.com, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Realign comments to fix warnings issued by checkpatch.pl tool "WARNING: Block comments use a leading /* on a separate line" within "target/mips/cpu.h" file. Signed-off-by: Jules Irenge Reviewed-by: Aleksandar Markovic --- target/mips/cpu.h | 34 ++++++++++++++++++++++------------ 1 file changed, 22 insertions(+), 12 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index a10eeb0de3..5dd71dbe21 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -37,7 +37,8 @@ union fpr_t { /* FPU/MSA register mapping is not tested on big-endian hosts. */ wr_t wr; /* vector data */ }; -/* define FP_ENDIAN_IDX to access the same location +/* + * define FP_ENDIAN_IDX to access the same location * in the fpr_t union regardless of the host endianness */ #if defined(HOST_WORDS_BIGENDIAN) @@ -963,9 +964,11 @@ struct CPUMIPSState { /* TMASK defines different execution modes */ #define MIPS_HFLAG_TMASK 0x1F5807FF #define MIPS_HFLAG_MODE 0x00007 /* execution modes */ - /* The KSU flags must be the lowest bits in hflags. The flag order - must be the same as defined for CP0 Status. This allows to use - the bits as the value of mmu_idx. */ + /* + * The KSU flags must be the lowest bits in hflags. The flag order + * must be the same as defined for CP0 Status. This allows to use + * the bits as the value of mmu_idx. + */ #define MIPS_HFLAG_KSU 0x00003 /* kernel/supervisor/user mode mask */ #define MIPS_HFLAG_UM 0x00002 /* user mode flag */ #define MIPS_HFLAG_SM 0x00001 /* supervisor mode flag */ @@ -975,18 +978,22 @@ struct CPUMIPSState { #define MIPS_HFLAG_CP0 0x00010 /* CP0 enabled */ #define MIPS_HFLAG_FPU 0x00020 /* FPU enabled */ #define MIPS_HFLAG_F64 0x00040 /* 64-bit FPU enabled */ - /* True if the MIPS IV COP1X instructions can be used. This also - controls the non-COP1X instructions RECIP.S, RECIP.D, RSQRT.S - and RSQRT.D. */ + /* + * True if the MIPS IV COP1X instructions can be used. This also + * controls the non-COP1X instructions RECIP.S, RECIP.D, RSQRT.S + * and RSQRT.D. + */ #define MIPS_HFLAG_COP1X 0x00080 /* COP1X instructions enabled */ #define MIPS_HFLAG_RE 0x00100 /* Reversed endianness */ #define MIPS_HFLAG_AWRAP 0x00200 /* 32-bit compatibility address wrapping= */ #define MIPS_HFLAG_M16 0x00400 /* MIPS16 mode flag */ #define MIPS_HFLAG_M16_SHIFT 10 - /* If translation is interrupted between the branch instruction and + /* + * If translation is interrupted between the branch instruction and * the delay slot, record what type of branch it is so that we can * resume translation properly. It might be possible to reduce - * this from three bits to two. */ + * this from three bits to two. + */ #define MIPS_HFLAG_BMASK_BASE 0x803800 #define MIPS_HFLAG_B 0x00800 /* Unconditional branch */ #define MIPS_HFLAG_BC 0x01000 /* Conditional branch */ @@ -1073,8 +1080,10 @@ void mips_cpu_list (FILE *f, fprintf_function cpu_fp= rintf); extern void cpu_wrdsp(uint32_t rs, uint32_t mask_num, CPUMIPSState *env); extern uint32_t cpu_rddsp(uint32_t mask_num, CPUMIPSState *env); =20 -/* MMU modes definitions. We carefully match the indices with our - hflags layout. */ +/* + * MMU modes definitions. We carefully match the indices with our + * hflags layout. + */ #define MMU_MODE0_SUFFIX _kernel #define MMU_MODE1_SUFFIX _super #define MMU_MODE2_SUFFIX _user @@ -1097,7 +1106,8 @@ static inline int cpu_mmu_index (CPUMIPSState *env, b= ool ifetch) =20 #include "exec/cpu-all.h" =20 -/* Memory access type : +/* + * Memory access type : * may be needed for precise access rights control and precise exceptions. */ enum { --=20 2.20.1 From nobody Sun May 19 12:26:29 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1554399665614207.45874792378197; Thu, 4 Apr 2019 10:41:05 -0700 (PDT) Received: from localhost ([127.0.0.1]:57989 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hC6MF-0007XA-RJ for importer@patchew.org; Thu, 04 Apr 2019 13:40:59 -0400 Received: from eggs.gnu.org ([209.51.188.92]:59591) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hC6Kv-0006rf-41 for qemu-devel@nongnu.org; Thu, 04 Apr 2019 13:39:38 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hC6Kt-0007Ui-Uy for qemu-devel@nongnu.org; Thu, 04 Apr 2019 13:39:37 -0400 Received: from mail-wm1-x343.google.com ([2a00:1450:4864:20::343]:35217) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hC6Kt-0007Sb-Jq for qemu-devel@nongnu.org; Thu, 04 Apr 2019 13:39:35 -0400 Received: by mail-wm1-x343.google.com with SMTP id y197so4428977wmd.0 for ; Thu, 04 Apr 2019 10:39:34 -0700 (PDT) Received: from ninjatsu.public.libraries.mcc ([91.235.65.22]) by smtp.gmail.com with ESMTPSA id i28sm56290924wrc.32.2019.04.04.10.39.32 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 04 Apr 2019 10:39:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=WHVNVRdz4ITDCkE6NMpCjuOMQ74U7RPYVINFoj4kcaI=; b=rAVuLPnghNhBVhGmto4tHqV2s41OLm2FKJXrLe9ykR/My4B3cFM/i7ZdQBeUYjA/CY UG7Hbg3jM03Wbi3T7zNVqm/pZorSaCsE8BhYW5YHsE/nL0JU6BtOefmcNaZluWMx4MSG HudiYrA6mUMFr3gCQYxuv0JyNfrk0h7xzGmbAX+t0P3msLy/aK9c/gXr7NxGS31MOwQ5 v15wp3Guv6h+DVZMRZitrRU6Ced2lupaIPYeQlw2Q46Fr/dnK3Vasn8a4SsKW88vaCmy fxSGSZZLTWHGF0a3YEkqJaBIB5W3rR4KsSo7I7wKfRZYSgTos350m9Eu/ag574r1UN8c xpzw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=WHVNVRdz4ITDCkE6NMpCjuOMQ74U7RPYVINFoj4kcaI=; b=MaA6o5qVCIubtK3OCSln2FJ1QuA31dqiUS9m8J2gT9q64QFVFcay76tDkIOq8/5+Qu uCekWkjtw47rx+WHbMjwQfF/AQX54sRv6+Nq0Ei6vasDEs7GnHhNQC6fg3WKYPM29EIE IfSrWeuiIFML7tTBHlDIlMRBwzE3l2j7e0byaXXzpXfkSNcbb7qDmKGWGO9wW7c8HLxI CmbiU81WtjWWMYnv69jtL1NFuPXKCTc1e1cXJbxydiwOgy7HrC9rUubTJ0kNR6jVjQyY CkLt9429pKqohn21P0FJnKl4wbgGsoyIw8yvAjx/2HbJ9QXqakkwvKZYddPTPPQFBu97 9Piw== X-Gm-Message-State: APjAAAUlIWTdqzQLGRetA9hGbhU9GM6X90EfmvwmICx8eBZAtUmhJoiw 4xAVmqIUJYgLtr5mWK2+iA== X-Google-Smtp-Source: APXvYqzLgQceda3bAi78WaF4nnUWCytNPr7sYxtCpqcVU0LCjV0mTPkJzG2p8wzqppivQF9+fo4xRA== X-Received: by 2002:a1c:23cc:: with SMTP id j195mr4661399wmj.74.1554399573085; Thu, 04 Apr 2019 10:39:33 -0700 (PDT) From: Jules Irenge To: amarkovic@wavecomp.com Date: Thu, 4 Apr 2019 18:39:21 +0100 Message-Id: <20190404173921.30841-3-jbi.octave@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190404173921.30841-1-jbi.octave@gmail.com> References: <20190404173921.30841-1-jbi.octave@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 Subject: [Qemu-devel] [PATCH v2 2/2] target/mips: add or remove space to fix checkpatch errors X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: arikalo@wavecomp.com, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Add or remove space to fix errors issued by checkpatch.pl tool "ERROR: spaces required around ..." "ERROR: space required after that" "ERROR: space required before the open parenthesis" "ERROR: space prohibited between function name and open parenthesis" within "target/mips/cpu.h" file. Signed-off-by: Jules Irenge --- target/mips/cpu.h | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 5dd71dbe21..0d2718d7bf 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -22,10 +22,10 @@ typedef struct CPUMIPSTLBContext CPUMIPSTLBContext; =20 typedef union wr_t wr_t; union wr_t { - int8_t b[MSA_WRLEN/8]; - int16_t h[MSA_WRLEN/16]; - int32_t w[MSA_WRLEN/32]; - int64_t d[MSA_WRLEN/64]; + int8_t b[MSA_WRLEN / 8]; + int16_t h[MSA_WRLEN / 16]; + int32_t w[MSA_WRLEN / 32]; + int64_t d[MSA_WRLEN / 64]; }; =20 typedef union fpr_t fpr_t; @@ -72,16 +72,16 @@ struct CPUMIPSFPUContext { #define FCR31_FS 24 #define FCR31_ABS2008 19 #define FCR31_NAN2008 18 -#define SET_FP_COND(num,env) do { ((env).fcr31) |=3D ((num) ? (1 << ((= num) + 24)) : (1 << 23)); } while(0) -#define CLEAR_FP_COND(num,env) do { ((env).fcr31) &=3D ~((num) ? (1 << (= (num) + 24)) : (1 << 23)); } while(0) +#define SET_FP_COND(num, env) do { ((env).fcr31) |=3D ((num) ? (1 << (= (num) + 24)) : (1 << 23)); } while (0) +#define CLEAR_FP_COND(num, env) do { ((env).fcr31) &=3D ~((num) ? (1 << = ((num) + 24)) : (1 << 23)); } while (0) #define GET_FP_COND(env) ((((env).fcr31 >> 24) & 0xfe) | (((env).f= cr31 >> 23) & 0x1)) #define GET_FP_CAUSE(reg) (((reg) >> 12) & 0x3f) #define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f) #define GET_FP_FLAGS(reg) (((reg) >> 2) & 0x1f) -#define SET_FP_CAUSE(reg,v) do { (reg) =3D ((reg) & ~(0x3f << 12)) | = ((v & 0x3f) << 12); } while(0) -#define SET_FP_ENABLE(reg,v) do { (reg) =3D ((reg) & ~(0x1f << 7)) | = ((v & 0x1f) << 7); } while(0) -#define SET_FP_FLAGS(reg,v) do { (reg) =3D ((reg) & ~(0x1f << 2)) | = ((v & 0x1f) << 2); } while(0) -#define UPDATE_FP_FLAGS(reg,v) do { (reg) |=3D ((v & 0x1f) << 2); } whil= e(0) +#define SET_FP_CAUSE(reg, v) do { (reg) =3D ((reg) & ~(0x3f << 12)) |= ((v & 0x3f) << 12); } while (0) +#define SET_FP_ENABLE(reg, v) do { (reg) =3D ((reg) & ~(0x1f << 7)) |= ((v & 0x1f) << 7); } while (0) +#define SET_FP_FLAGS(reg, v) do { (reg) =3D ((reg) & ~(0x1f << 2)) |= ((v & 0x1f) << 2); } while (0) +#define UPDATE_FP_FLAGS(reg, v) do { (reg) |=3D ((v & 0x1f) << 2); } whi= le (0) #define FP_INEXACT 1 #define FP_UNDERFLOW 2 #define FP_OVERFLOW 4 @@ -1072,7 +1072,7 @@ static inline MIPSCPU *mips_env_get_cpu(CPUMIPSState = *env) =20 #define ENV_OFFSET offsetof(MIPSCPU, env) =20 -void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf); +void mips_cpu_list(FILE *f, fprintf_function cpu_fprintf); =20 #define cpu_signal_handler cpu_mips_signal_handler #define cpu_list mips_cpu_list @@ -1099,7 +1099,7 @@ static inline int hflags_mmu_index(uint32_t hflags) } } =20 -static inline int cpu_mmu_index (CPUMIPSState *env, bool ifetch) +static inline int cpu_mmu_index(CPUMIPSState *env, bool ifetch) { return hflags_mmu_index(env->hflags); } @@ -1107,7 +1107,7 @@ static inline int cpu_mmu_index (CPUMIPSState *env, b= ool ifetch) #include "exec/cpu-all.h" =20 /* - * Memory access type : + * Memory access type: * may be needed for precise access rights control and precise exceptions. */ enum { @@ -1192,7 +1192,7 @@ void cpu_mips_soft_irq(CPUMIPSState *env, int irq, in= t level); void itc_reconfigure(struct MIPSITUState *tag); =20 /* helper.c */ -target_ulong exception_resume_pc (CPUMIPSState *env); +target_ulong exception_resume_pc(CPUMIPSState *env); =20 static inline void restore_snan_bit_mode(CPUMIPSState *env) { --=20 2.20.1