From nobody Mon Nov 10 06:10:14 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1554391222797418.2356462515256; Thu, 4 Apr 2019 08:20:22 -0700 (PDT) Received: from localhost ([127.0.0.1]:56293 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hC4A3-0001Ba-P0 for importer@patchew.org; Thu, 04 Apr 2019 11:20:15 -0400 Received: from eggs.gnu.org ([209.51.188.92]:54654) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hC48l-00083l-2E for qemu-devel@nongnu.org; Thu, 04 Apr 2019 11:18:56 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hC48j-0000gL-5C for qemu-devel@nongnu.org; Thu, 04 Apr 2019 11:18:54 -0400 Received: from mail-wr1-x441.google.com ([2a00:1450:4864:20::441]:45470) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hC48h-0000QD-39 for qemu-devel@nongnu.org; Thu, 04 Apr 2019 11:18:51 -0400 Received: by mail-wr1-x441.google.com with SMTP id s15so4239954wra.12 for ; Thu, 04 Apr 2019 08:18:42 -0700 (PDT) Received: from ninjatsu.public.libraries.mcc ([91.235.65.22]) by smtp.gmail.com with ESMTPSA id z140sm24374445wmc.27.2019.04.04.08.18.40 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 04 Apr 2019 08:18:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=pA28vCbZx6lzm3kJbSa2/z8AMN5bASGS+zrnO8I7fu0=; b=eLQK/moYsoY8wQUZhJsJC6vwp1e6nas4hIsas6+sQvgeLQwiVBDCmBtWt0IHr6c6RG VRQMRFwNFfWwauAjDN2W6SNsYN1RDgMRlq611hY/x9zvHEcOh8BQbCkLk/ccYp40YiNC xPSU/yLe+6W8cPvxWHPY/6BfF6vHqxXvfnqbyyVT3h83NtbARwKTHjFcMe6TCv+LbdcP n97YINbnKfpKM5sGPhGn29QtpwsY5MoqXmQJZDC1jB+6rKaKa9/oH0hZhxaGYhQFcw+8 re8xVzsb+iTYgIr4Zh+gotuTtXaXSIeOQ9K8v6D7XNWaIMDzHcp4fV/mewLc06CNAbGV Qteg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=pA28vCbZx6lzm3kJbSa2/z8AMN5bASGS+zrnO8I7fu0=; b=Yl99U0DiEymyiC1HX/Sb4ely7MsKSVGVOx01F9pPulXJQRFF8B1oLIZaq6q5Z6c6sH 7jyhDqolsRxWbVET0c3G7exY7UOoWcBntvMvL+8aphx3Zm/NB/83gJTW6d3K8k3GLLeB aLcAm4lzA5B2HivfOOGKr1kso3biqEwEwgMDYebMana5TxHspQpM2tU1Sqsg73DfjIF/ TGuoAn+W43rloFSgpxb78Juj+86XxFjuFnqV2VPpHKm6805pxTbmLwOolC2cKi4Wu/Gw gDTJEEAPmnNVdnexUv5J5hc/9sX29OotOXmd5ob5xL1wl4FH+hqErrOIFyLKpe2McBZw pzBw== X-Gm-Message-State: APjAAAWt79+ALGUKE4hLtc0KpaNqBSZruhgxk+mYHD0ArLWCZN8pNYPz jS8lK2N6eWl4ZebfRke+xg== X-Google-Smtp-Source: APXvYqwkwfODkfM5Fv/12KoOHJ8ulihU+5CvBhFdewPg+jhZ063Gk+Aiy9bqk7+JhiAyJweJKA/qeA== X-Received: by 2002:a5d:488d:: with SMTP id g13mr4506213wrq.119.1554391121292; Thu, 04 Apr 2019 08:18:41 -0700 (PDT) From: Jules Irenge To: amarkovic@wavecomp.com Date: Thu, 4 Apr 2019 16:18:33 +0100 Message-Id: <20190404151833.20021-1-jbi.octave@gmail.com> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 Subject: [Qemu-devel] [PATCH] target/mips: realign comments to fix checkpatch warnings X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: arikalo@wavecomp.com, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Realign comments to fix warnings issued by checkpatch.pl tool "WARNING: Block comments use a leading /* on a separate line" within "target/mips/cpu.h" file. Signed-off-by: Jules Irenge --- target/mips/cpu.h | 34 ++++++++++++++++++++++------------ 1 file changed, 22 insertions(+), 12 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index a10eeb0de3..5dd71dbe21 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -37,7 +37,8 @@ union fpr_t { /* FPU/MSA register mapping is not tested on big-endian hosts. */ wr_t wr; /* vector data */ }; -/* define FP_ENDIAN_IDX to access the same location +/* + * define FP_ENDIAN_IDX to access the same location * in the fpr_t union regardless of the host endianness */ #if defined(HOST_WORDS_BIGENDIAN) @@ -963,9 +964,11 @@ struct CPUMIPSState { /* TMASK defines different execution modes */ #define MIPS_HFLAG_TMASK 0x1F5807FF #define MIPS_HFLAG_MODE 0x00007 /* execution modes */ - /* The KSU flags must be the lowest bits in hflags. The flag order - must be the same as defined for CP0 Status. This allows to use - the bits as the value of mmu_idx. */ + /* + * The KSU flags must be the lowest bits in hflags. The flag order + * must be the same as defined for CP0 Status. This allows to use + * the bits as the value of mmu_idx. + */ #define MIPS_HFLAG_KSU 0x00003 /* kernel/supervisor/user mode mask */ #define MIPS_HFLAG_UM 0x00002 /* user mode flag */ #define MIPS_HFLAG_SM 0x00001 /* supervisor mode flag */ @@ -975,18 +978,22 @@ struct CPUMIPSState { #define MIPS_HFLAG_CP0 0x00010 /* CP0 enabled */ #define MIPS_HFLAG_FPU 0x00020 /* FPU enabled */ #define MIPS_HFLAG_F64 0x00040 /* 64-bit FPU enabled */ - /* True if the MIPS IV COP1X instructions can be used. This also - controls the non-COP1X instructions RECIP.S, RECIP.D, RSQRT.S - and RSQRT.D. */ + /* + * True if the MIPS IV COP1X instructions can be used. This also + * controls the non-COP1X instructions RECIP.S, RECIP.D, RSQRT.S + * and RSQRT.D. + */ #define MIPS_HFLAG_COP1X 0x00080 /* COP1X instructions enabled */ #define MIPS_HFLAG_RE 0x00100 /* Reversed endianness */ #define MIPS_HFLAG_AWRAP 0x00200 /* 32-bit compatibility address wrapping= */ #define MIPS_HFLAG_M16 0x00400 /* MIPS16 mode flag */ #define MIPS_HFLAG_M16_SHIFT 10 - /* If translation is interrupted between the branch instruction and + /* + * If translation is interrupted between the branch instruction and * the delay slot, record what type of branch it is so that we can * resume translation properly. It might be possible to reduce - * this from three bits to two. */ + * this from three bits to two. + */ #define MIPS_HFLAG_BMASK_BASE 0x803800 #define MIPS_HFLAG_B 0x00800 /* Unconditional branch */ #define MIPS_HFLAG_BC 0x01000 /* Conditional branch */ @@ -1073,8 +1080,10 @@ void mips_cpu_list (FILE *f, fprintf_function cpu_fp= rintf); extern void cpu_wrdsp(uint32_t rs, uint32_t mask_num, CPUMIPSState *env); extern uint32_t cpu_rddsp(uint32_t mask_num, CPUMIPSState *env); =20 -/* MMU modes definitions. We carefully match the indices with our - hflags layout. */ +/* + * MMU modes definitions. We carefully match the indices with our + * hflags layout. + */ #define MMU_MODE0_SUFFIX _kernel #define MMU_MODE1_SUFFIX _super #define MMU_MODE2_SUFFIX _user @@ -1097,7 +1106,8 @@ static inline int cpu_mmu_index (CPUMIPSState *env, b= ool ifetch) =20 #include "exec/cpu-all.h" =20 -/* Memory access type : +/* + * Memory access type : * may be needed for precise access rights control and precise exceptions. */ enum { --=20 2.20.1