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X-Received-From: 2a00:1450:4864:20::442 Subject: [Qemu-devel] [PATCH 1/5] target/mips: add space to fix checkpatch errors X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: arikalo@wavecomp.com, qemu-devel@nongnu.org, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Add space to fix errors reported by checkpatch.pl tool "ERROR: spaces required around that ..." "ERROR: space required before the open parenthesis" "ERROR: space required after that ..." Signed-off-by: Jules Irenge --- target/mips/cpu.h | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index a10eeb0de3..2429fe80ac 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -22,10 +22,10 @@ typedef struct CPUMIPSTLBContext CPUMIPSTLBContext; =20 typedef union wr_t wr_t; union wr_t { - int8_t b[MSA_WRLEN/8]; - int16_t h[MSA_WRLEN/16]; - int32_t w[MSA_WRLEN/32]; - int64_t d[MSA_WRLEN/64]; + int8_t b[MSA_WRLEN / 8]; + int16_t h[MSA_WRLEN / 16]; + int32_t w[MSA_WRLEN / 32]; + int64_t d[MSA_WRLEN / 64]; }; =20 typedef union fpr_t fpr_t; @@ -71,16 +71,16 @@ struct CPUMIPSFPUContext { #define FCR31_FS 24 #define FCR31_ABS2008 19 #define FCR31_NAN2008 18 -#define SET_FP_COND(num,env) do { ((env).fcr31) |=3D ((num) ? (1 << ((= num) + 24)) : (1 << 23)); } while(0) -#define CLEAR_FP_COND(num,env) do { ((env).fcr31) &=3D ~((num) ? (1 << (= (num) + 24)) : (1 << 23)); } while(0) +#define SET_FP_COND(num, env) do { ((env).fcr31) |=3D ((num) ? (1 << ((= num) + 24)) : (1 << 23)); } while (0) +#define CLEAR_FP_COND(num, env) do { ((env).fcr31) &=3D ~((num) ? (1 << = ((num) + 24)) : (1 << 23)); } while (0) #define GET_FP_COND(env) ((((env).fcr31 >> 24) & 0xfe) | (((env).f= cr31 >> 23) & 0x1)) #define GET_FP_CAUSE(reg) (((reg) >> 12) & 0x3f) #define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f) #define GET_FP_FLAGS(reg) (((reg) >> 2) & 0x1f) -#define SET_FP_CAUSE(reg,v) do { (reg) =3D ((reg) & ~(0x3f << 12)) | = ((v & 0x3f) << 12); } while(0) -#define SET_FP_ENABLE(reg,v) do { (reg) =3D ((reg) & ~(0x1f << 7)) | = ((v & 0x1f) << 7); } while(0) -#define SET_FP_FLAGS(reg,v) do { (reg) =3D ((reg) & ~(0x1f << 2)) | = ((v & 0x1f) << 2); } while(0) -#define UPDATE_FP_FLAGS(reg,v) do { (reg) |=3D ((v & 0x1f) << 2); } whil= e(0) +#define SET_FP_CAUSE(reg, v) do { (reg) =3D ((reg) & ~(0x3f << 12)) |= ((v & 0x3f) << 12); } while (0) +#define SET_FP_ENABLE(reg, v) do { (reg) =3D ((reg) & ~(0x1f << 7)) |= ((v & 0x1f) << 7); } while (0) +#define SET_FP_FLAGS(reg, v) do { (reg) =3D ((reg) & ~(0x1f << 2)) |= ((v & 0x1f) << 2); } while (0) +#define UPDATE_FP_FLAGS(reg, v) do { (reg) |=3D ((v & 0x1f) << 2); } whi= le (0) #define FP_INEXACT 1 #define FP_UNDERFLOW 2 #define FP_OVERFLOW 4 --=20 2.20.1 From nobody Sat Apr 27 10:44:59 2024 Delivered-To: importer@patchew.org Received-SPF: temperror (zoho.com: Error in retrieving data from DNS) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1554296227584201.95442013140962; Wed, 3 Apr 2019 05:57:07 -0700 (PDT) Received: from localhost ([127.0.0.1]:40598 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hBfRk-0001kM-AB for importer@patchew.org; Wed, 03 Apr 2019 08:56:52 -0400 Received: from eggs.gnu.org ([209.51.188.92]:43536) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hBfMA-0005bo-EM for qemu-devel@nongnu.org; Wed, 03 Apr 2019 08:51:07 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hBfM9-0004A7-AX for qemu-devel@nongnu.org; Wed, 03 Apr 2019 08:51:06 -0400 Received: from mail-wr1-x443.google.com ([2a00:1450:4864:20::443]:37417) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hBfM9-00049U-2t for qemu-devel@nongnu.org; Wed, 03 Apr 2019 08:51:05 -0400 Received: by mail-wr1-x443.google.com with SMTP id w10so21161635wrm.4 for ; Wed, 03 Apr 2019 05:51:05 -0700 (PDT) Received: from ninjatsu.lan (host-2-103-80-5.as13285.net. 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X-Received-From: 2a00:1450:4864:20::443 Subject: [Qemu-devel] [PATCH 2/5] target/mips: realign comments to fix checkpatch warnings X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: arikalo@wavecomp.com, qemu-devel@nongnu.org, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Realign comments to fix warnings issued by checkpatch.pl tool "WARNING: Block comments use a leading /* on a separate line" within "target/mips/cpu.h" file. Signed-off-by: Jules Irenge --- target/mips/cpu.h | 34 ++++++++++++++++++++++------------ 1 file changed, 22 insertions(+), 12 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 2429fe80ac..bfa595c8a9 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -37,7 +37,8 @@ union fpr_t { /* FPU/MSA register mapping is not tested on big-endian hosts. */ wr_t wr; /* vector data */ }; -/* define FP_ENDIAN_IDX to access the same location +/* + * define FP_ENDIAN_IDX to access the same location * in the fpr_t union regardless of the host endianness */ #if defined(HOST_WORDS_BIGENDIAN) @@ -963,9 +964,11 @@ struct CPUMIPSState { /* TMASK defines different execution modes */ #define MIPS_HFLAG_TMASK 0x1F5807FF #define MIPS_HFLAG_MODE 0x00007 /* execution modes */ - /* The KSU flags must be the lowest bits in hflags. The flag order - must be the same as defined for CP0 Status. This allows to use - the bits as the value of mmu_idx. */ + /* + * The KSU flags must be the lowest bits in hflags. The flag order + * must be the same as defined for CP0 Status. This allows to use + * the bits as the value of mmu_idx. + */ #define MIPS_HFLAG_KSU 0x00003 /* kernel/supervisor/user mode mask */ #define MIPS_HFLAG_UM 0x00002 /* user mode flag */ #define MIPS_HFLAG_SM 0x00001 /* supervisor mode flag */ @@ -975,18 +978,22 @@ struct CPUMIPSState { #define MIPS_HFLAG_CP0 0x00010 /* CP0 enabled */ #define MIPS_HFLAG_FPU 0x00020 /* FPU enabled */ #define MIPS_HFLAG_F64 0x00040 /* 64-bit FPU enabled */ - /* True if the MIPS IV COP1X instructions can be used. This also - controls the non-COP1X instructions RECIP.S, RECIP.D, RSQRT.S - and RSQRT.D. */ + /* + * True if the MIPS IV COP1X instructions can be used. This also + * controls the non-COP1X instructions RECIP.S, RECIP.D, RSQRT.S + * and RSQRT.D. + */ #define MIPS_HFLAG_COP1X 0x00080 /* COP1X instructions enabled */ #define MIPS_HFLAG_RE 0x00100 /* Reversed endianness */ #define MIPS_HFLAG_AWRAP 0x00200 /* 32-bit compatibility address wrapping= */ #define MIPS_HFLAG_M16 0x00400 /* MIPS16 mode flag */ #define MIPS_HFLAG_M16_SHIFT 10 - /* If translation is interrupted between the branch instruction and + /* + * If translation is interrupted between the branch instruction and * the delay slot, record what type of branch it is so that we can * resume translation properly. It might be possible to reduce - * this from three bits to two. */ + * this from three bits to two. =20 + */ #define MIPS_HFLAG_BMASK_BASE 0x803800 #define MIPS_HFLAG_B 0x00800 /* Unconditional branch */ #define MIPS_HFLAG_BC 0x01000 /* Conditional branch */ @@ -1073,8 +1080,10 @@ void mips_cpu_list (FILE *f, fprintf_function cpu_fp= rintf); extern void cpu_wrdsp(uint32_t rs, uint32_t mask_num, CPUMIPSState *env); extern uint32_t cpu_rddsp(uint32_t mask_num, CPUMIPSState *env); =20 -/* MMU modes definitions. We carefully match the indices with our - hflags layout. */ +/* + * MMU modes definitions. We carefully match the indices with our + * hflags layout. + */ #define MMU_MODE0_SUFFIX _kernel #define MMU_MODE1_SUFFIX _super #define MMU_MODE2_SUFFIX _user @@ -1097,7 +1106,8 @@ static inline int cpu_mmu_index (CPUMIPSState *env, b= ool ifetch) =20 #include "exec/cpu-all.h" =20 -/* Memory access type : +/*=20 + * Memory access type : * may be needed for precise access rights control and precise exceptions. */ enum { --=20 2.20.1 From nobody Sat Apr 27 10:44:59 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 155429600288368.81199324671434; Wed, 3 Apr 2019 05:53:22 -0700 (PDT) Received: from localhost ([127.0.0.1]:39578 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hBfOI-0007B1-P0 for importer@patchew.org; Wed, 03 Apr 2019 08:53:18 -0400 Received: from eggs.gnu.org ([209.51.188.92]:43550) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hBfMB-0005cV-7v for qemu-devel@nongnu.org; Wed, 03 Apr 2019 08:51:10 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hBfM9-0004AY-Uh for qemu-devel@nongnu.org; Wed, 03 Apr 2019 08:51:07 -0400 Received: from mail-wr1-x442.google.com ([2a00:1450:4864:20::442]:36858) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hBfM9-00049z-LX for qemu-devel@nongnu.org; Wed, 03 Apr 2019 08:51:05 -0400 Received: by mail-wr1-x442.google.com with SMTP id y13so21204280wrd.3 for ; Wed, 03 Apr 2019 05:51:05 -0700 (PDT) Received: from ninjatsu.lan (host-2-103-80-5.as13285.net. [2.103.80.5]) by smtp.gmail.com with ESMTPSA id z7sm12255955wml.40.2019.04.03.05.51.03 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 03 Apr 2019 05:51:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=KepB6sTRXjqBuiT63n7eAfXyuJSsQ0FVpEXbv1IxK0Y=; b=YQI+gFCWxLKbZ3Aed4TUpnjQLGefRL/iO9a45SX7AkHqfEZc5AH4KZyZvguutbL+8O CE9YOv6p4917uZS1eMzSo1sik/OXQYw3KcnDwSXthgh2WNV7/ELm5uzURjFrFNc46gFH r3aXI9xOkVDJoH2tfgvy8zJ2WnkFbX72z575HoucMcqyBGYPMxb32yKQHvDhx/1758eb jQuV2eZMsnK/lj3YsbEnp5L78vt6NUbqDAAlUNnuZKXQ0kcbYbI5lLaGuydyKMKhmOPF mrb4SN1qkiROMj9xPaYDIJlj6b0gHuLo4FMkklxDWUlt+0r5U3S+Aro9ikSOxet9StDD 1FeA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=KepB6sTRXjqBuiT63n7eAfXyuJSsQ0FVpEXbv1IxK0Y=; b=kxrOE4lvtHla7gVlwarHsmsbXC00k/TxVfTs31UImQu2w+96LtlzOsZ0QkYNp352DB 7YfxaUlk4KUNmTne9LUzqXn6tLAA+RKqot49cfpyJe+vVtnpoRUQOau4Na/GBnEP2vM3 1ybPtZ3cKB7AwIG74aZ0dHIk4re3dECv5k5ZllgpGLw0lzEMDuAMM+yU287+iYWWIUaY 4MtMKnVKYZ1ccqaNp+jr9MMqI9v5WBbUx7Qesg45OP7RZPO+5t0ThLimlSnsHXhAGkz/ ftt9XfDHjT2CNI9swKcx0Pu4vaphu2NqXXGsA6o39oz9T+hpucsCNVa3vYi754UcMTx1 cLwg== X-Gm-Message-State: APjAAAWQPDDAbsvPvHNvxCPgxETf9x7ssF2qwSGyrHpV/gJTpWOG0+Cf DBnwqEEF5/kGwvM+YO9lkg== X-Google-Smtp-Source: APXvYqxx5HL42RNVanoS5gL063YRsQpbAdhPMIjcBWhJh/iR40G3XbHgpciFz3xskVllRKp3OHvpjw== X-Received: by 2002:adf:cd92:: with SMTP id q18mr48227499wrj.134.1554295864612; Wed, 03 Apr 2019 05:51:04 -0700 (PDT) From: Jules Irenge To: amarkovic@wavecomp.com Date: Wed, 3 Apr 2019 13:50:53 +0100 Message-Id: <20190403125055.26564-4-jbi.octave@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190403125055.26564-1-jbi.octave@gmail.com> References: <20190403125055.26564-1-jbi.octave@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 Subject: [Qemu-devel] [PATCH 3/5] target/mips: replace indentation with space to fix checkpatch errors X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: arikalo@wavecomp.com, qemu-devel@nongnu.org, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Replace indentation with space to fix errors issued by checkpatch.pl tool "ERROR: code indent should never use tabs" within "target/mips/cpu.h" file. Signed-off-by: Jules Irenge Reviewed-by: Aleksandar Markovic --- target/mips/cpu.h | 136 +++++++++++++++++++++++----------------------- 1 file changed, 68 insertions(+), 68 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index bfa595c8a9..c4278b3ffe 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -96,25 +96,25 @@ struct CPUMIPSFPUContext { typedef struct CPUMIPSMVPContext CPUMIPSMVPContext; struct CPUMIPSMVPContext { int32_t CP0_MVPControl; -#define CP0MVPCo_CPA 3 -#define CP0MVPCo_STLB 2 -#define CP0MVPCo_VPC 1 -#define CP0MVPCo_EVP 0 +#define CP0MVPCo_CPA 3 +#define CP0MVPCo_STLB 2 +#define CP0MVPCo_VPC 1 +#define CP0MVPCo_EVP 0 int32_t CP0_MVPConf0; -#define CP0MVPC0_M 31 -#define CP0MVPC0_TLBS 29 -#define CP0MVPC0_GS 28 -#define CP0MVPC0_PCP 27 -#define CP0MVPC0_PTLBE 16 -#define CP0MVPC0_TCA 15 -#define CP0MVPC0_PVPE 10 -#define CP0MVPC0_PTC 0 +#define CP0MVPC0_M 31 +#define CP0MVPC0_TLBS 29 +#define CP0MVPC0_GS 28 +#define CP0MVPC0_PCP 27 +#define CP0MVPC0_PTLBE 16 +#define CP0MVPC0_TCA 15 +#define CP0MVPC0_PVPE 10 +#define CP0MVPC0_PTC 0 int32_t CP0_MVPConf1; -#define CP0MVPC1_CIM 31 -#define CP0MVPC1_CIF 30 -#define CP0MVPC1_PCX 20 -#define CP0MVPC1_PCP2 10 -#define CP0MVPC1_PCP1 0 +#define CP0MVPC1_CIM 31 +#define CP0MVPC1_CIF 30 +#define CP0MVPC1_PCX 20 +#define CP0MVPC1_PCP2 10 +#define CP0MVPC1_PCP1 0 }; =20 typedef struct mips_def_t mips_def_t; @@ -482,44 +482,44 @@ struct CPUMIPSState { */ int32_t CP0_Random; int32_t CP0_VPEControl; -#define CP0VPECo_YSI 21 -#define CP0VPECo_GSI 20 -#define CP0VPECo_EXCPT 16 -#define CP0VPECo_TE 15 -#define CP0VPECo_TargTC 0 +#define CP0VPECo_YSI 21 +#define CP0VPECo_GSI 20 +#define CP0VPECo_EXCPT 16 +#define CP0VPECo_TE 15 +#define CP0VPECo_TargTC 0 int32_t CP0_VPEConf0; -#define CP0VPEC0_M 31 -#define CP0VPEC0_XTC 21 -#define CP0VPEC0_TCS 19 -#define CP0VPEC0_SCS 18 -#define CP0VPEC0_DSC 17 -#define CP0VPEC0_ICS 16 -#define CP0VPEC0_MVP 1 -#define CP0VPEC0_VPA 0 +#define CP0VPEC0_M 31 +#define CP0VPEC0_XTC 21 +#define CP0VPEC0_TCS 19 +#define CP0VPEC0_SCS 18 +#define CP0VPEC0_DSC 17 +#define CP0VPEC0_ICS 16 +#define CP0VPEC0_MVP 1 +#define CP0VPEC0_VPA 0 int32_t CP0_VPEConf1; -#define CP0VPEC1_NCX 20 -#define CP0VPEC1_NCP2 10 -#define CP0VPEC1_NCP1 0 +#define CP0VPEC1_NCX 20 +#define CP0VPEC1_NCP2 10 +#define CP0VPEC1_NCP1 0 target_ulong CP0_YQMask; target_ulong CP0_VPESchedule; target_ulong CP0_VPEScheFBack; int32_t CP0_VPEOpt; -#define CP0VPEOpt_IWX7 15 -#define CP0VPEOpt_IWX6 14 -#define CP0VPEOpt_IWX5 13 -#define CP0VPEOpt_IWX4 12 -#define CP0VPEOpt_IWX3 11 -#define CP0VPEOpt_IWX2 10 -#define CP0VPEOpt_IWX1 9 -#define CP0VPEOpt_IWX0 8 -#define CP0VPEOpt_DWX7 7 -#define CP0VPEOpt_DWX6 6 -#define CP0VPEOpt_DWX5 5 -#define CP0VPEOpt_DWX4 4 -#define CP0VPEOpt_DWX3 3 -#define CP0VPEOpt_DWX2 2 -#define CP0VPEOpt_DWX1 1 -#define CP0VPEOpt_DWX0 0 +#define CP0VPEOpt_IWX7 15 +#define CP0VPEOpt_IWX6 14 +#define CP0VPEOpt_IWX5 13 +#define CP0VPEOpt_IWX4 12 +#define CP0VPEOpt_IWX3 11 +#define CP0VPEOpt_IWX2 10 +#define CP0VPEOpt_IWX1 9 +#define CP0VPEOpt_IWX0 8 +#define CP0VPEOpt_DWX7 7 +#define CP0VPEOpt_DWX6 6 +#define CP0VPEOpt_DWX5 5 +#define CP0VPEOpt_DWX4 4 +#define CP0VPEOpt_DWX3 3 +#define CP0VPEOpt_DWX2 2 +#define CP0VPEOpt_DWX1 1 +#define CP0VPEOpt_DWX0 0 /* * CP0 Register 2 */ @@ -626,33 +626,33 @@ struct CPUMIPSState { #define CP0PC_PSN 0 /* 5..0 */ int32_t CP0_SRSConf0_rw_bitmask; int32_t CP0_SRSConf0; -#define CP0SRSC0_M 31 -#define CP0SRSC0_SRS3 20 -#define CP0SRSC0_SRS2 10 -#define CP0SRSC0_SRS1 0 +#define CP0SRSC0_M 31 +#define CP0SRSC0_SRS3 20 +#define CP0SRSC0_SRS2 10 +#define CP0SRSC0_SRS1 0 int32_t CP0_SRSConf1_rw_bitmask; int32_t CP0_SRSConf1; -#define CP0SRSC1_M 31 -#define CP0SRSC1_SRS6 20 -#define CP0SRSC1_SRS5 10 -#define CP0SRSC1_SRS4 0 +#define CP0SRSC1_M 31 +#define CP0SRSC1_SRS6 20 +#define CP0SRSC1_SRS5 10 +#define CP0SRSC1_SRS4 0 int32_t CP0_SRSConf2_rw_bitmask; int32_t CP0_SRSConf2; -#define CP0SRSC2_M 31 -#define CP0SRSC2_SRS9 20 -#define CP0SRSC2_SRS8 10 -#define CP0SRSC2_SRS7 0 +#define CP0SRSC2_M 31 +#define CP0SRSC2_SRS9 20 +#define CP0SRSC2_SRS8 10 +#define CP0SRSC2_SRS7 0 int32_t CP0_SRSConf3_rw_bitmask; int32_t CP0_SRSConf3; -#define CP0SRSC3_M 31 -#define CP0SRSC3_SRS12 20 -#define CP0SRSC3_SRS11 10 -#define CP0SRSC3_SRS10 0 +#define CP0SRSC3_M 31 +#define CP0SRSC3_SRS12 20 +#define CP0SRSC3_SRS11 10 +#define CP0SRSC3_SRS10 0 int32_t CP0_SRSConf4_rw_bitmask; int32_t CP0_SRSConf4; -#define CP0SRSC4_SRS15 20 -#define CP0SRSC4_SRS14 10 -#define CP0SRSC4_SRS13 0 +#define CP0SRSC4_SRS15 20 +#define CP0SRSC4_SRS14 10 +#define CP0SRSC4_SRS13 0 /* * CP0 Register 7 */ --=20 2.20.1 From nobody Sat Apr 27 10:44:59 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1554296002918799.075222954982; Wed, 3 Apr 2019 05:53:22 -0700 (PDT) Received: from localhost ([127.0.0.1]:39566 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hBfOG-00078s-NT for importer@patchew.org; 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X-Received-From: 2a00:1450:4864:20::443 Subject: [Qemu-devel] [PATCH 4/5] target/mips: remove space to fix checkpatch errors X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: arikalo@wavecomp.com, qemu-devel@nongnu.org, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Remove space to fix errors issued by checkpatch.pl tool "ERROR: space prohibited between function name and open parenthesis" "ERROR: trailing white space" within "target/mips/cpu.h" file. Signed-off-by: Jules Irenge --- target/mips/cpu.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index c4278b3ffe..238a67c405 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -992,7 +992,7 @@ struct CPUMIPSState { * If translation is interrupted between the branch instruction and * the delay slot, record what type of branch it is so that we can * resume translation properly. It might be possible to reduce - * this from three bits to two. =20 + * this from three bits to two. */ #define MIPS_HFLAG_BMASK_BASE 0x803800 #define MIPS_HFLAG_B 0x00800 /* Unconditional branch */ @@ -1072,7 +1072,7 @@ static inline MIPSCPU *mips_env_get_cpu(CPUMIPSState = *env) =20 #define ENV_OFFSET offsetof(MIPSCPU, env) =20 -void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf); +void mips_cpu_list(FILE *f, fprintf_function cpu_fprintf); =20 #define cpu_signal_handler cpu_mips_signal_handler #define cpu_list mips_cpu_list @@ -1099,14 +1099,14 @@ static inline int hflags_mmu_index(uint32_t hflags) } } =20 -static inline int cpu_mmu_index (CPUMIPSState *env, bool ifetch) +static inline int cpu_mmu_index(CPUMIPSState *env, bool ifetch) { return hflags_mmu_index(env->hflags); } =20 #include "exec/cpu-all.h" =20 -/*=20 +/* * Memory access type : * may be needed for precise access rights control and precise exceptions. */ @@ -1192,7 +1192,7 @@ void cpu_mips_soft_irq(CPUMIPSState *env, int irq, in= t level); void itc_reconfigure(struct MIPSITUState *tag); =20 /* helper.c */ -target_ulong exception_resume_pc (CPUMIPSState *env); +target_ulong exception_resume_pc(CPUMIPSState *env); =20 static inline void restore_snan_bit_mode(CPUMIPSState *env) { --=20 2.20.1 From nobody Sat Apr 27 10:44:59 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1554296231728487.4256511444139; Wed, 3 Apr 2019 05:57:11 -0700 (PDT) Received: from localhost ([127.0.0.1]:40661 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hBfRw-0001v0-O8 for importer@patchew.org; Wed, 03 Apr 2019 08:57:04 -0400 Received: from eggs.gnu.org ([209.51.188.92]:43571) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hBfMD-0005dP-24 for qemu-devel@nongnu.org; Wed, 03 Apr 2019 08:51:10 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hBfMC-0004C2-4B for qemu-devel@nongnu.org; Wed, 03 Apr 2019 08:51:09 -0400 Received: from mail-wr1-x441.google.com ([2a00:1450:4864:20::441]:39355) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hBfMB-0004BP-Ri for qemu-devel@nongnu.org; Wed, 03 Apr 2019 08:51:08 -0400 Received: by mail-wr1-x441.google.com with SMTP id j9so21176925wrn.6 for ; Wed, 03 Apr 2019 05:51:07 -0700 (PDT) Received: from ninjatsu.lan (host-2-103-80-5.as13285.net. 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X-Received-From: 2a00:1450:4864:20::441 Subject: [Qemu-devel] [PATCH 5/5] target/mips: wrap line into multiple lines to to fix checkpatch errors X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: arikalo@wavecomp.com, qemu-devel@nongnu.org, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Wrap line into multiple lines to fix errors issued by checkpatch.pl tool ERROR: line over 90 characters" within "target/mips/cpu.h" file. Signed-off-by: Jules Irenge --- target/mips/cpu.h | 25 +++++++++++++++++++------ 1 file changed, 19 insertions(+), 6 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 238a67c405..56b0105574 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -72,15 +72,28 @@ struct CPUMIPSFPUContext { #define FCR31_FS 24 #define FCR31_ABS2008 19 #define FCR31_NAN2008 18 -#define SET_FP_COND(num, env) do { ((env).fcr31) |=3D ((num) ? (1 << ((= num) + 24)) : (1 << 23)); } while (0) -#define CLEAR_FP_COND(num, env) do { ((env).fcr31) &=3D ~((num) ? (1 << = ((num) + 24)) : (1 << 23)); } while (0) -#define GET_FP_COND(env) ((((env).fcr31 >> 24) & 0xfe) | (((env).f= cr31 >> 23) & 0x1)) +#define SET_FP_COND(num, env) do { ((env).fcr31) |=3D \ + ((num) ? (1 << ((num) + 24)) : \ + (1 << 23)); \ + } while (0) +#define CLEAR_FP_COND(num, env) do { ((env).fcr31) &=3D \ + ~((num) ? (1 << ((num) + 24)) : \ + (1 << 23)); \ + } while (0) +#define GET_FP_COND(env) ((((env).fcr31 >> 24) & 0xfe) | \ + (((env).fcr31 >> 23) & 0x1)) #define GET_FP_CAUSE(reg) (((reg) >> 12) & 0x3f) #define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f) #define GET_FP_FLAGS(reg) (((reg) >> 2) & 0x1f) -#define SET_FP_CAUSE(reg, v) do { (reg) =3D ((reg) & ~(0x3f << 12)) |= ((v & 0x3f) << 12); } while (0) -#define SET_FP_ENABLE(reg, v) do { (reg) =3D ((reg) & ~(0x1f << 7)) |= ((v & 0x1f) << 7); } while (0) -#define SET_FP_FLAGS(reg, v) do { (reg) =3D ((reg) & ~(0x1f << 2)) |= ((v & 0x1f) << 2); } while (0) +#define SET_FP_CAUSE(reg, v) do { (reg) =3D ((reg) & ~(0x3f << 12)) |= \ + ((v & 0x3f) << 12); \ + } while (0) +#define SET_FP_ENABLE(reg, v) do { (reg) =3D ((reg) & ~(0x1f << 7)) |= \ + ((v & 0x1f) << 7); \ + } while (0) +#define SET_FP_FLAGS(reg, v) do { (reg) =3D ((reg) & ~(0x1f << 2)) |= \ + ((v & 0x1f) << 2); \ + } while (0) #define UPDATE_FP_FLAGS(reg, v) do { (reg) |=3D ((v & 0x1f) << 2); } whi= le (0) #define FP_INEXACT 1 #define FP_UNDERFLOW 2 --=20 2.20.1