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X-Received-From: 2607:f8b0:4864:20::643 Subject: [Qemu-devel] [PATCH 23/26] target/xtensa: Convert to CPUClass::tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Max Filippov Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Cc: Max Filippov Signed-off-by: Richard Henderson --- target/xtensa/cpu.h | 5 +-- target/xtensa/cpu.c | 5 ++- target/xtensa/helper.c | 74 +++++++++++++++++++++--------------------- 3 files changed, 42 insertions(+), 42 deletions(-) diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 4d8152682f..8ac6f8eeca 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -552,8 +552,9 @@ static inline XtensaCPU *xtensa_env_get_cpu(const CPUXt= ensaState *env) #define ENV_OFFSET offsetof(XtensaCPU, env) =20 =20 -int xtensa_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, int s= ize, - int mmu_idx); +bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); void xtensa_cpu_do_interrupt(CPUState *cpu); bool xtensa_cpu_exec_interrupt(CPUState *cpu, int interrupt_request); void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr= addr, diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index a54dbe4260..da1236377e 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -181,9 +181,8 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void= *data) cc->gdb_read_register =3D xtensa_cpu_gdb_read_register; cc->gdb_write_register =3D xtensa_cpu_gdb_write_register; cc->gdb_stop_before_watchpoint =3D true; -#ifdef CONFIG_USER_ONLY - cc->handle_mmu_fault =3D xtensa_cpu_handle_mmu_fault; -#else + cc->tlb_fill =3D xtensa_cpu_tlb_fill; +#ifndef CONFIG_USER_ONLY cc->do_unaligned_access =3D xtensa_cpu_do_unaligned_access; cc->get_phys_page_debug =3D xtensa_cpu_get_phys_page_debug; cc->do_transaction_failed =3D xtensa_cpu_do_transaction_failed; diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c index f4867a9b56..3dcab54fbf 100644 --- a/target/xtensa/helper.c +++ b/target/xtensa/helper.c @@ -237,24 +237,49 @@ void xtensa_cpu_list(FILE *f, fprintf_function cpu_fp= rintf) } } =20 -#ifdef CONFIG_USER_ONLY - -int xtensa_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int= rw, - int mmu_idx) +bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) { XtensaCPU *cpu =3D XTENSA_CPU(cs); CPUXtensaState *env =3D &cpu->env; + target_ulong vaddr =3D address; + int ret; =20 - qemu_log_mask(CPU_LOG_INT, - "%s: rw =3D %d, address =3D 0x%08" VADDR_PRIx ", size = =3D %d\n", - __func__, rw, address, size); - env->sregs[EXCVADDR] =3D address; - env->sregs[EXCCAUSE] =3D rw ? STORE_PROHIBITED_CAUSE : LOAD_PROHIBITED= _CAUSE; - cs->exception_index =3D EXC_USER; - return 1; +#ifdef CONFIG_USER_ONLY + ret =3D (access_type =3D=3D MMU_DATA_STORE ? + STORE_PROHIBITED_CAUSE : LOAD_PROHIBITED_CAUSE); +#else + uint32_t paddr; + uint32_t page_size; + unsigned access; + + ret =3D xtensa_get_physical_addr(env, true, vaddr, access_type, mmu_id= x, + &paddr, &page_size, &access); + + qemu_log_mask(CPU_LOG_MMU, "%s(%08x, %d, %d) -> %08x, ret =3D %d\n", + __func__, vaddr, access_type, mmu_idx, paddr, ret); + + if (ret =3D=3D 0) { + tlb_set_page(cs, vaddr & TARGET_PAGE_MASK, paddr & TARGET_PAGE_MAS= K, + access, mmu_idx, page_size); + return true; + } + if (probe) { + return false; + } +#endif + + cpu_restore_state(cs, retaddr, true); + HELPER(exception_cause_vaddr)(env, env->pc, ret, vaddr); } =20 -#else +#ifndef CONFIG_USER_ONLY +void tlb_fill(CPUState *cs, target_ulong vaddr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) +{ + xtensa_cpu_tlb_fill(cs, vaddr, size, access_type, mmu_idx, false, reta= ddr); +} =20 void xtensa_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, @@ -272,31 +297,6 @@ void xtensa_cpu_do_unaligned_access(CPUState *cs, } } =20 -void tlb_fill(CPUState *cs, target_ulong vaddr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - XtensaCPU *cpu =3D XTENSA_CPU(cs); - CPUXtensaState *env =3D &cpu->env; - uint32_t paddr; - uint32_t page_size; - unsigned access; - int ret =3D xtensa_get_physical_addr(env, true, vaddr, access_type, mm= u_idx, - &paddr, &page_size, &access); - - qemu_log_mask(CPU_LOG_MMU, "%s(%08x, %d, %d) -> %08x, ret =3D %d\n", - __func__, vaddr, access_type, mmu_idx, paddr, ret); - - if (ret =3D=3D 0) { - tlb_set_page(cs, - vaddr & TARGET_PAGE_MASK, - paddr & TARGET_PAGE_MASK, - access, mmu_idx, page_size); - } else { - cpu_restore_state(cs, retaddr, true); - HELPER(exception_cause_vaddr)(env, env->pc, ret, vaddr); - } -} - void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr= addr, unsigned size, MMUAccessType access_= type, int mmu_idx, MemTxAttrs attrs, --=20 2.17.1