From nobody Tue Feb 10 02:00:21 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1554263968767721.1897810792915; Tue, 2 Apr 2019 20:59:28 -0700 (PDT) Received: from localhost ([127.0.0.1]:54875 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hBX3b-0006xe-4F for importer@patchew.org; Tue, 02 Apr 2019 23:59:23 -0400 Received: from eggs.gnu.org ([209.51.188.92]:48725) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hBWpJ-00031q-NX for qemu-devel@nongnu.org; Tue, 02 Apr 2019 23:44:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hBWpI-00005X-Cn for qemu-devel@nongnu.org; Tue, 02 Apr 2019 23:44:37 -0400 Received: from mail-pl1-x641.google.com ([2607:f8b0:4864:20::641]:39396) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hBWpI-0008WA-59 for qemu-devel@nongnu.org; Tue, 02 Apr 2019 23:44:36 -0400 Received: by mail-pl1-x641.google.com with SMTP id b65so7312868plb.6 for ; Tue, 02 Apr 2019 20:44:36 -0700 (PDT) Received: from cloudburst.imgcgcw.net ([147.50.13.10]) by smtp.gmail.com with ESMTPSA id z6sm26753214pgo.31.2019.04.02.20.44.32 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 02 Apr 2019 20:44:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=w70bbHQzT+7HnMGIXg0cJi7OJv7Pp3pD0PUOZFKz1Ws=; b=PS/U3kRJhxCe0D+7YI+igq8A3154U98cOMEoZvMYPzxzIdP+/pGLRN0s1zkjjfwKYH dOSd5yLy4g+PsyYxVzORFINDLOzJCKRLLzQASxjk/DiHzEeyEIh+5TKrHtU2jyo1OZVO 4/VDDVEbduYTj70uabkOkcXlRwXwds/9nL76Q86dXqi5mxtgpE+4qYgE5niiCScQogQd rsuKS8ovoIgwMB+XVvhXXD/s8lU0cpTI+K4gWI7/hzVOfUIrzIKJ5JCVf9wS9HDWVD6i XBfe65cN7yCjMCnc8Chq85zlFx703UG6vk1EJp7fFsB71tFC6plLBReTGqFRnqqBvG1U BgAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=w70bbHQzT+7HnMGIXg0cJi7OJv7Pp3pD0PUOZFKz1Ws=; b=Tlsv/PANuLniZ4VuYaXekOUbthQM2luCai3H6+rykNPBuzuTRiNGjJqqBSUWHHy3MZ I2HAkmPi7+1PhjP+isOqIbTW5gv2zMd5LaE3KJQa+FTXkXwhAJDpUEc7eHg8cNMzxgT1 9Qc1OljIYjMS1OwW3GmACiAq6+WDiM50vkudKXMDRpFOKxsHZ8VyhXRQ8vBkBR5Sp5aJ vX3hPa7x//mnlyjlLd9/TlXOtbv2zimNk74LhK4WcrV8eqFJ68glkYAxM8m6mGE2GCqn GZJMsr1Lqi2aLCkfh7Jrvf5IcyDYe6l7CcVRLuYgPH9ZVg0Q5f9njWaKAwTUajnlAPOp b4wA== X-Gm-Message-State: APjAAAWSWQE7/ujnJlPVIFK9wIxDMrkdVa1grwP8F++3VMm8EJJyoSx9 7Lu3vwtlzoWU6GJG2DyKBI84V/EY6zlsJA== X-Google-Smtp-Source: APXvYqyXQf+gI/OXl1U/l7JiVC8RNkUXM2eWWCQvycYj3Fero+AnQRy+6wyCSYLpGj1MUR8quii6Xg== X-Received: by 2002:a17:902:2bab:: with SMTP id l40mr74192068plb.273.1554263074966; Tue, 02 Apr 2019 20:44:34 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 3 Apr 2019 10:43:48 +0700 Message-Id: <20190403034358.21999-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190403034358.21999-1-richard.henderson@linaro.org> References: <20190403034358.21999-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::641 Subject: [Qemu-devel] [PATCH 16/26] target/riscv: Convert to CPUClass::tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Palmer Dabbelt , qemu-riscv@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Note that env->pc is removed from the qemu_log as that value is garbage. The PC isn't recovered until cpu_restore_state, called from cpu_loop_exit_restore, called from riscv_raise_exception. Cc: qemu-riscv@nongnu.org Cc: Palmer Dabbelt Cc: Alistair Francis Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 5 +++-- target/riscv/cpu.c | 5 ++--- target/riscv/cpu_helper.c | 46 ++++++++++++++++++--------------------- 3 files changed, 26 insertions(+), 30 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 20bce8742e..40c1254408 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -261,8 +261,9 @@ hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vad= dr addr); void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr); -int riscv_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, - int rw, int mmu_idx); +bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); char *riscv_isa_string(RISCVCPU *cpu); void riscv_cpu_list(FILE *f, fprintf_function cpu_fprintf); =20 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index d61bce6d55..e9f569c665 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -355,9 +355,8 @@ static void riscv_cpu_class_init(ObjectClass *c, void *= data) #endif cc->gdb_stop_before_watchpoint =3D true; cc->disas_set_info =3D riscv_cpu_disas_set_info; -#ifdef CONFIG_USER_ONLY - cc->handle_mmu_fault =3D riscv_cpu_handle_mmu_fault; -#else + cc->tlb_fill =3D riscv_cpu_tlb_fill; +#ifndef CONFIG_USER_ONLY cc->do_unaligned_access =3D riscv_cpu_do_unaligned_access; cc->get_phys_page_debug =3D riscv_cpu_get_phys_page_debug; #endif diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index b17f169681..2535435260 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -379,53 +379,49 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vadd= r addr, riscv_raise_exception(env, cs->exception_index, retaddr); } =20 -/* called by qemu's softmmu to fill the qemu tlb */ void tlb_fill(CPUState *cs, target_ulong addr, int size, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) { - int ret; - ret =3D riscv_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu_id= x); - if (ret =3D=3D TRANSLATE_FAIL) { - RISCVCPU *cpu =3D RISCV_CPU(cs); - CPURISCVState *env =3D &cpu->env; - riscv_raise_exception(env, cs->exception_index, retaddr); - } + riscv_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retadd= r); } - #endif =20 -int riscv_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, - int rw, int mmu_idx) +bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) { +#ifndef CONFIG_USER_ONLY RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; -#if !defined(CONFIG_USER_ONLY) hwaddr pa =3D 0; int prot; -#endif int ret =3D TRANSLATE_FAIL; =20 - qemu_log_mask(CPU_LOG_MMU, - "%s pc " TARGET_FMT_lx " ad %" VADDR_PRIx " rw %d mmu_idx \ - %d\n", __func__, env->pc, address, rw, mmu_idx); + qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n", + __func__, address, access_type, mmu_idx); + + ret =3D get_physical_address(env, &pa, &prot, address, access_type, mm= u_idx); =20 -#if !defined(CONFIG_USER_ONLY) - ret =3D get_physical_address(env, &pa, &prot, address, rw, mmu_idx); qemu_log_mask(CPU_LOG_MMU, - "%s address=3D%" VADDR_PRIx " ret %d physical " TARGET_FMT_plx - " prot %d\n", __func__, address, ret, pa, prot); + "%s address=3D%" VADDR_PRIx " ret %d physical " TARGET_F= MT_plx + " prot %d\n", __func__, address, ret, pa, prot); + if (riscv_feature(env, RISCV_FEATURE_PMP) && - !pmp_hart_has_privs(env, pa, TARGET_PAGE_SIZE, 1 << rw)) { + !pmp_hart_has_privs(env, pa, TARGET_PAGE_SIZE, 1 << access_type)) { ret =3D TRANSLATE_FAIL; } if (ret =3D=3D TRANSLATE_SUCCESS) { tlb_set_page(cs, address & TARGET_PAGE_MASK, pa & TARGET_PAGE_MASK, prot, mmu_idx, TARGET_PAGE_SIZE); - } else if (ret =3D=3D TRANSLATE_FAIL) { - raise_mmu_exception(env, address, rw); + return true; + } else if (probe) { + return false; + } else { + raise_mmu_exception(env, address, access_type); + riscv_raise_exception(env, cs->exception_index, retaddr); } #else - switch (rw) { + switch (access_type) { case MMU_INST_FETCH: cs->exception_index =3D RISCV_EXCP_INST_PAGE_FAULT; break; @@ -436,8 +432,8 @@ int riscv_cpu_handle_mmu_fault(CPUState *cs, vaddr addr= ess, int size, cs->exception_index =3D RISCV_EXCP_STORE_PAGE_FAULT; break; } + cpu_loop_exit_restore(cs, retaddr); #endif - return ret; } =20 /* --=20 2.17.1