From nobody Sun Apr 28 14:24:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1554185266107582.5292558519312; Mon, 1 Apr 2019 23:07:46 -0700 (PDT) Received: from localhost ([127.0.0.1]:52815 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hBCaF-0005hP-6z for importer@patchew.org; Tue, 02 Apr 2019 02:07:43 -0400 Received: from eggs.gnu.org ([209.51.188.92]:37333) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hBCWL-0002QJ-MM for qemu-devel@nongnu.org; Tue, 02 Apr 2019 02:03:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hBCWK-0004ss-BK for qemu-devel@nongnu.org; Tue, 02 Apr 2019 02:03:41 -0400 Received: from ozlabs.org ([203.11.71.1]:36903) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hBC9z-0008Q6-K9; Tue, 02 Apr 2019 01:40:38 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 44YJ2l0Mq9z9sTS; Tue, 2 Apr 2019 16:40:31 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1554183631; bh=RmCVysMV24gNZ7avpBiZeB2tTfq2kuUFJwMOS1Wxilo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=neSXsgT9233CH/xn2gzypnQnLwmygRdWZ9KA143wEWEnzwNm4wPaymXi/j8/KnYfN 0zwrj8H4Dgrlm4kg4YftnUAoP5XQlMSMEzZp2AfwoO6m4iRD22AJi+md2GmnsBIyPX y/d4CsLKHu9Zxwcicc/tbB6KkMwSO7UDC3l2lb48= From: David Gibson To: qemu-devel@nongnu.org, Alex Williamson , Marcel Apfelbaum , "Michael S. Tsirkin" , Greg Kurz Date: Tue, 2 Apr 2019 16:40:24 +1100 Message-Id: <20190402054028.20926-2-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190402054028.20926-1-david@gibson.dropbear.id.au> References: <20190402054028.20926-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 203.11.71.1 Subject: [Qemu-devel] [RFC for-4.1 1/5] pci: Allow PCI bus subtypes to support extended config space accesses X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Greg Kurz Some PHB implementations, eg. PAPR used on pseries machine, act like a regular PCI bus rather than a PCIe bus, but allow access to the PCIe extended config space anyway. Introduce a new PCI bus class method to modelize this behaviour and use it when adjusting the config space size limit during accesses. No behaviour change for existing PCI bus types. Signed-off-by: Greg Kurz Message-Id: <155414130271.574858.4253514266378127489.stgit@bahia.lan> Signed-off-by: David Gibson --- hw/pci/pci.c | 24 ++++++++++++++++++++++++ hw/pci/pci_host.c | 2 +- include/hw/pci/pci.h | 2 ++ include/hw/pci/pci_bus.h | 1 + 4 files changed, 28 insertions(+), 1 deletion(-) diff --git a/hw/pci/pci.c b/hw/pci/pci.c index 35451c1e99..6d13ef877b 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -147,6 +147,11 @@ static uint16_t pcibus_numa_node(PCIBus *bus) return NUMA_NODE_UNASSIGNED; } =20 +static bool pcibus_allows_extended_config_space(PCIBus *bus) +{ + return false; +} + static void pci_bus_class_init(ObjectClass *klass, void *data) { BusClass *k =3D BUS_CLASS(klass); @@ -162,6 +167,7 @@ static void pci_bus_class_init(ObjectClass *klass, void= *data) pbc->is_root =3D pcibus_is_root; pbc->bus_num =3D pcibus_num; pbc->numa_node =3D pcibus_numa_node; + pbc->allows_extended_config_space =3D pcibus_allows_extended_config_sp= ace; } =20 static const TypeInfo pci_bus_info =3D { @@ -182,9 +188,22 @@ static const TypeInfo conventional_pci_interface_info = =3D { .parent =3D TYPE_INTERFACE, }; =20 +static bool pciebus_allows_extended_config_space(PCIBus *bus) +{ + return true; +} + +static void pcie_bus_class_init(ObjectClass *klass, void *data) +{ + PCIBusClass *pbc =3D PCI_BUS_CLASS(klass); + + pbc->allows_extended_config_space =3D pciebus_allows_extended_config_s= pace; +} + static const TypeInfo pcie_bus_info =3D { .name =3D TYPE_PCIE_BUS, .parent =3D TYPE_PCI_BUS, + .class_init =3D pcie_bus_class_init, }; =20 static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num); @@ -401,6 +420,11 @@ bool pci_bus_is_root(PCIBus *bus) return PCI_BUS_GET_CLASS(bus)->is_root(bus); } =20 +bool pci_bus_allows_extended_config_space(PCIBus *bus) +{ + return PCI_BUS_GET_CLASS(bus)->allows_extended_config_space(bus); +} + void pci_root_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState *p= arent, const char *name, MemoryRegion *address_space_mem, diff --git a/hw/pci/pci_host.c b/hw/pci/pci_host.c index 5f5345dbac..9d64b2e12f 100644 --- a/hw/pci/pci_host.c +++ b/hw/pci/pci_host.c @@ -54,7 +54,7 @@ static inline PCIDevice *pci_dev_find_by_addr(PCIBus *bus= , uint32_t addr) static void pci_adjust_config_limit(PCIBus *bus, uint32_t *limit) { if (*limit > PCI_CONFIG_SPACE_SIZE) { - if (!pci_bus_is_express(bus)) { + if (!pci_bus_allows_extended_config_space(bus)) { *limit =3D PCI_CONFIG_SPACE_SIZE; return; } diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index d87f5f93e9..0abb06b357 100644 --- a/include/hw/pci/pci.h +++ b/include/hw/pci/pci.h @@ -396,6 +396,8 @@ typedef PCIINTxRoute (*pci_route_irq_fn)(void *opaque, = int pin); =20 bool pci_bus_is_express(PCIBus *bus); bool pci_bus_is_root(PCIBus *bus); +bool pci_bus_allows_extended_config_space(PCIBus *bus); + void pci_root_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState *p= arent, const char *name, MemoryRegion *address_space_mem, diff --git a/include/hw/pci/pci_bus.h b/include/hw/pci/pci_bus.h index dfb75752cb..f6df834170 100644 --- a/include/hw/pci/pci_bus.h +++ b/include/hw/pci/pci_bus.h @@ -18,6 +18,7 @@ typedef struct PCIBusClass { bool (*is_root)(PCIBus *bus); int (*bus_num)(PCIBus *bus); uint16_t (*numa_node)(PCIBus *bus); + bool (*allows_extended_config_space)(PCIBus *bus); } PCIBusClass; =20 struct PCIBus { --=20 2.20.1 From nobody Sun Apr 28 14:24:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1554185156028565.8751384649328; Mon, 1 Apr 2019 23:05:56 -0700 (PDT) Received: from localhost ([127.0.0.1]:52220 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hBCYR-0003gq-3C for importer@patchew.org; Tue, 02 Apr 2019 02:05:51 -0400 Received: from eggs.gnu.org ([209.51.188.92]:36774) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hBCVO-0000z0-27 for qemu-devel@nongnu.org; Tue, 02 Apr 2019 02:02:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hBCVM-0004Kz-LE for qemu-devel@nongnu.org; Tue, 02 Apr 2019 02:02:41 -0400 Received: from ozlabs.org ([2401:3900:2:1::2]:57045) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hBC9z-0008QR-K7; Tue, 02 Apr 2019 01:40:38 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 44YJ2m2K2kz9sTX; Tue, 2 Apr 2019 16:40:31 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1554183632; bh=1DpSJflGttozTwD1QCIUlACzcmviQkzl8ouc8v5EL1w=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=PPJrCqZWDNMyYATKqxHTRfv6jGvrlmjZS1W+lSPatad9+tR3//feVPsMAnPbdhZc/ G2YY/V/yyVHZsbu2SE2XOt81yWlrQKUm1UZFuIxt0FbuHoqj6eJD6G1r8PVdf7AZYG B6To2rl4sMgSo7Bl8Ipir8NzIj0DSY4MBvU1ClXY= From: David Gibson To: qemu-devel@nongnu.org, Alex Williamson , Marcel Apfelbaum , "Michael S. Tsirkin" , Greg Kurz Date: Tue, 2 Apr 2019 16:40:25 +1100 Message-Id: <20190402054028.20926-3-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190402054028.20926-1-david@gibson.dropbear.id.au> References: <20190402054028.20926-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 Subject: [Qemu-devel] [RFC for-4.1 2/5] spapr_pci: Fix extended config space accesses X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Greg Kurz The PAPR PHB acts as a legacy PCI bus but it allows PCIe extended config space accesses anyway (for pseries-2.9 and newer machine types). Introduce a specific PCI bus subtype to inform the common PCI code about that. Fixes: c2077e2ca0da7 Signed-off-by: Greg Kurz Message-Id: <155414130834.574858.16502276132110219890.stgit@bahia.lan> Signed-off-by: David Gibson --- hw/ppc/spapr_pci.c | 26 +++++++++++++++++++++++++- 1 file changed, 25 insertions(+), 1 deletion(-) diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c index b63ed9d8da..2e76d8cbd8 100644 --- a/hw/ppc/spapr_pci.c +++ b/hw/ppc/spapr_pci.c @@ -1638,6 +1638,28 @@ static void spapr_phb_unrealize(DeviceState *dev, Er= ror **errp) memory_region_del_subregion(get_system_memory(), &sphb->mem32window); } =20 +static bool spapr_phb_allows_extended_config_space(PCIBus *bus) +{ + SpaprPhbState *sphb =3D SPAPR_PCI_HOST_BRIDGE(BUS(bus)->parent); + + return sphb->pcie_ecs; +} + +static void spapr_phb_root_bus_class_init(ObjectClass *klass, void *data) +{ + PCIBusClass *pbc =3D PCI_BUS_CLASS(klass); + + pbc->allows_extended_config_space =3D spapr_phb_allows_extended_config= _space; +} + +#define TYPE_SPAPR_PHB_ROOT_BUS "spapr-pci-host-bridge-root-bus" + +static const TypeInfo spapr_phb_root_bus_info =3D { + .name =3D TYPE_SPAPR_PHB_ROOT_BUS, + .parent =3D TYPE_PCI_BUS, + .class_init =3D spapr_phb_root_bus_class_init, +}; + static void spapr_phb_realize(DeviceState *dev, Error **errp) { /* We don't use SPAPR_MACHINE() in order to exit gracefully if the user @@ -1742,7 +1764,8 @@ static void spapr_phb_realize(DeviceState *dev, Error= **errp) bus =3D pci_register_root_bus(dev, NULL, pci_spapr_set_irq, pci_spapr_map_irq, sphb, &sphb->memspace, &sphb->iospace, - PCI_DEVFN(0, 0), PCI_NUM_PINS, TYPE_PCI_BU= S); + PCI_DEVFN(0, 0), PCI_NUM_PINS, + TYPE_SPAPR_PHB_ROOT_BUS); phb->bus =3D bus; qbus_set_hotplug_handler(BUS(phb->bus), OBJECT(sphb), NULL); =20 @@ -2325,6 +2348,7 @@ void spapr_pci_rtas_init(void) static void spapr_pci_register_types(void) { type_register_static(&spapr_phb_info); + type_register_static(&spapr_phb_root_bus_info); } =20 type_init(spapr_pci_register_types) --=20 2.20.1 From nobody Sun Apr 28 14:24:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1554185018102802.1754117382291; Mon, 1 Apr 2019 23:03:38 -0700 (PDT) Received: from localhost ([127.0.0.1]:51633 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hBCWC-0001JK-1J for importer@patchew.org; Tue, 02 Apr 2019 02:03:32 -0400 Received: from eggs.gnu.org ([209.51.188.92]:36156) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hBCUR-000891-SQ for qemu-devel@nongnu.org; Tue, 02 Apr 2019 02:01:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hBCR7-0002T4-E9 for qemu-devel@nongnu.org; Tue, 02 Apr 2019 01:58:18 -0400 Received: from ozlabs.org ([2401:3900:2:1::2]:34311) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hBC9z-0008QJ-Gl; Tue, 02 Apr 2019 01:40:39 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 44YJ2m0qx9z9sTY; Tue, 2 Apr 2019 16:40:31 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1554183632; bh=ANslDpwZiSU3e7rjPJqviTFIdF0c/Qo6+msbVqzKkFc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=FyCBDjmaAhWjd68RFA32j9fErlNLOdaoVO3mIe/JVmTbXWuBnzd1TUvUb2UoWZAV4 GXQg8LMLeyoqXoxmWhTYhJ2Y3//6b251m713sry85NPvxl/5TcByuMjRu2JO5HsOqy C5UVR120JLOfkCI2aUVCKq8qrpiQzKbl+0oBK2MU= From: David Gibson To: qemu-devel@nongnu.org, Alex Williamson , Marcel Apfelbaum , "Michael S. Tsirkin" , Greg Kurz Date: Tue, 2 Apr 2019 16:40:26 +1100 Message-Id: <20190402054028.20926-4-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190402054028.20926-1-david@gibson.dropbear.id.au> References: <20190402054028.20926-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 Subject: [Qemu-devel] [RFC for-4.1 3/5] pcie: Remove redundant test in pcie_mmcfg_data_read() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" This function has an explicit test for accesses above the device's config size, in which case it returns ~0x0. But pci_host_config_read_common() which it is about to call already has checks against the config space limit and likewise returns ~0x0 in that case. So, remove the redundant test. Signed-off-by: David Gibson --- hw/pci/pcie_host.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/hw/pci/pcie_host.c b/hw/pci/pcie_host.c index 553db56778..8f4435838e 100644 --- a/hw/pci/pcie_host.c +++ b/hw/pci/pcie_host.c @@ -70,11 +70,6 @@ static uint64_t pcie_mmcfg_data_read(void *opaque, } addr =3D PCIE_MMCFG_CONFOFFSET(mmcfg_addr); limit =3D pci_config_size(pci_dev); - if (limit <=3D addr) { - /* conventional pci device can be behind pcie-to-pci bridge. - 256 <=3D addr < 4K has no effects. */ - return ~0x0; - } return pci_host_config_read_common(pci_dev, addr, limit, len); } =20 --=20 2.20.1 From nobody Sun Apr 28 14:24:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1554185021740453.86622942115594; Mon, 1 Apr 2019 23:03:41 -0700 (PDT) Received: from localhost ([127.0.0.1]:51664 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hBCWH-0001i4-Nv for importer@patchew.org; Tue, 02 Apr 2019 02:03:37 -0400 Received: from eggs.gnu.org ([209.51.188.92]:36156) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hBCUT-000891-LT for qemu-devel@nongnu.org; Tue, 02 Apr 2019 02:01:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hBCR0-0002Mr-F5 for qemu-devel@nongnu.org; Tue, 02 Apr 2019 01:58:11 -0400 Received: from ozlabs.org ([2401:3900:2:1::2]:41107) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hBC9z-0008QI-Iv; Tue, 02 Apr 2019 01:40:38 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 44YJ2l4tTNz9sSY; Tue, 2 Apr 2019 16:40:31 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1554183631; bh=r0k79GFoaBOjYo2MOK8ANFRnb/vmoPZkxjIORHFRSRA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Uuw0LlSd6JvgsruVe9B1BhHDQGrjdA+XisIw9RbYNstdfWg+6G0AroMx78p4Cy/5I mLokfqWVYL+BjjToS8XYD27WB2gwS0FaaMM5alGdK7WVhqQoRpNl/X4SkQHXhjW7m3 CdjiPCOartvEc36jzyND9iCZfZGa3NbDOPQAeSKM= From: David Gibson To: qemu-devel@nongnu.org, Alex Williamson , Marcel Apfelbaum , "Michael S. Tsirkin" , Greg Kurz Date: Tue, 2 Apr 2019 16:40:27 +1100 Message-Id: <20190402054028.20926-5-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190402054028.20926-1-david@gibson.dropbear.id.au> References: <20190402054028.20926-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 Subject: [Qemu-devel] [RFC for-4.1 4/5] pci: Simplify pci_bus_is_root() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marcel Apfelbaum , qemu-ppc@nongnu.org, clg@kaod.org, Peter Xu , David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" pci_bus_is_root() currently relies on a method in the PCIBusClass. But it's always known if a PCI bus is a root bus when we create it, so using a dynamic method is overkill. This replaces it with an IS_ROOT bit in a new flags field, which is set on root buses and otherwise clear. As a bonus this removes the special is_root logic from pci_expander_bridge, since it already creates its bus as a root bus. Signed-off-by: David Gibson Reviewed-by: Marcel Apfelbaum Reviewed-by: Peter Xu Reviewed-by: Greg Kurz --- hw/pci-bridge/pci_expander_bridge.c | 6 ------ hw/pci/pci.c | 14 ++------------ hw/virtio/virtio-pci.c | 1 + include/hw/pci/pci.h | 1 - include/hw/pci/pci_bus.h | 12 +++++++++++- 5 files changed, 14 insertions(+), 20 deletions(-) diff --git a/hw/pci-bridge/pci_expander_bridge.c b/hw/pci-bridge/pci_expand= er_bridge.c index e62de4218f..ca66bc721a 100644 --- a/hw/pci-bridge/pci_expander_bridge.c +++ b/hw/pci-bridge/pci_expander_bridge.c @@ -66,11 +66,6 @@ static int pxb_bus_num(PCIBus *bus) return pxb->bus_nr; } =20 -static bool pxb_is_root(PCIBus *bus) -{ - return true; /* by definition */ -} - static uint16_t pxb_bus_numa_node(PCIBus *bus) { PXBDev *pxb =3D convert_to_pxb(bus->parent_dev); @@ -83,7 +78,6 @@ static void pxb_bus_class_init(ObjectClass *class, void *= data) PCIBusClass *pbc =3D PCI_BUS_CLASS(class); =20 pbc->bus_num =3D pxb_bus_num; - pbc->is_root =3D pxb_is_root; pbc->numa_node =3D pxb_bus_numa_node; } =20 diff --git a/hw/pci/pci.c b/hw/pci/pci.c index 6d13ef877b..ea5941fb22 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -129,14 +129,9 @@ static void pci_bus_unrealize(BusState *qbus, Error **= errp) vmstate_unregister(NULL, &vmstate_pcibus, bus); } =20 -static bool pcibus_is_root(PCIBus *bus) -{ - return !bus->parent_dev; -} - static int pcibus_num(PCIBus *bus) { - if (pcibus_is_root(bus)) { + if (pci_bus_is_root(bus)) { return 0; /* pci host bridge */ } return bus->parent_dev->config[PCI_SECONDARY_BUS]; @@ -164,7 +159,6 @@ static void pci_bus_class_init(ObjectClass *klass, void= *data) k->unrealize =3D pci_bus_unrealize; k->reset =3D pcibus_reset; =20 - pbc->is_root =3D pcibus_is_root; pbc->bus_num =3D pcibus_num; pbc->numa_node =3D pcibus_numa_node; pbc->allows_extended_config_space =3D pcibus_allows_extended_config_sp= ace; @@ -398,6 +392,7 @@ static void pci_root_bus_init(PCIBus *bus, DeviceState = *parent, bus->slot_reserved_mask =3D 0x0; bus->address_space_mem =3D address_space_mem; bus->address_space_io =3D address_space_io; + bus->flags |=3D PCI_BUS_IS_ROOT; =20 /* host bridge */ QLIST_INIT(&bus->child); @@ -415,11 +410,6 @@ bool pci_bus_is_express(PCIBus *bus) return object_dynamic_cast(OBJECT(bus), TYPE_PCIE_BUS); } =20 -bool pci_bus_is_root(PCIBus *bus) -{ - return PCI_BUS_GET_CLASS(bus)->is_root(bus); -} - bool pci_bus_allows_extended_config_space(PCIBus *bus) { return PCI_BUS_GET_CLASS(bus)->allows_extended_config_space(bus); diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c index cb44e19b67..942173d830 100644 --- a/hw/virtio/virtio-pci.c +++ b/hw/virtio/virtio-pci.c @@ -20,6 +20,7 @@ #include "standard-headers/linux/virtio_pci.h" #include "hw/virtio/virtio.h" #include "hw/pci/pci.h" +#include "hw/pci/pci_bus.h" #include "qapi/error.h" #include "qemu/error-report.h" #include "hw/pci/msi.h" diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index 0abb06b357..33ccce320c 100644 --- a/include/hw/pci/pci.h +++ b/include/hw/pci/pci.h @@ -395,7 +395,6 @@ typedef PCIINTxRoute (*pci_route_irq_fn)(void *opaque, = int pin); #define TYPE_PCIE_BUS "PCIE" =20 bool pci_bus_is_express(PCIBus *bus); -bool pci_bus_is_root(PCIBus *bus); bool pci_bus_allows_extended_config_space(PCIBus *bus); =20 void pci_root_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState *p= arent, diff --git a/include/hw/pci/pci_bus.h b/include/hw/pci/pci_bus.h index f6df834170..aea98d5040 100644 --- a/include/hw/pci/pci_bus.h +++ b/include/hw/pci/pci_bus.h @@ -15,14 +15,19 @@ typedef struct PCIBusClass { BusClass parent_class; /*< public >*/ =20 - bool (*is_root)(PCIBus *bus); int (*bus_num)(PCIBus *bus); uint16_t (*numa_node)(PCIBus *bus); bool (*allows_extended_config_space)(PCIBus *bus); } PCIBusClass; =20 +enum PCIBusFlags { + /* This bus is the root of a PCI domain */ + PCI_BUS_IS_ROOT =3D 0x0001, +}; + struct PCIBus { BusState qbus; + enum PCIBusFlags flags; PCIIOMMUFunc iommu_fn; void *iommu_opaque; uint8_t devfn_min; @@ -47,4 +52,9 @@ struct PCIBus { Notifier machine_done; }; =20 +static inline bool pci_bus_is_root(PCIBus *bus) +{ + return !!(bus->flags & PCI_BUS_IS_ROOT); +} + #endif /* QEMU_PCI_BUS_H */ --=20 2.20.1 From nobody Sun Apr 28 14:24:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1554186294543914.3640193744399; Mon, 1 Apr 2019 23:24:54 -0700 (PDT) Received: from localhost ([127.0.0.1]:57506 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hBCqp-0002tW-4Y for importer@patchew.org; Tue, 02 Apr 2019 02:24:51 -0400 Received: from eggs.gnu.org ([209.51.188.92]:42148) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hBCoh-0001UJ-QC for qemu-devel@nongnu.org; Tue, 02 Apr 2019 02:22:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hBCik-0000qJ-8Q for qemu-devel@nongnu.org; Tue, 02 Apr 2019 02:16:31 -0400 Received: from ozlabs.org ([203.11.71.1]:38515) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hBCA5-0008TQ-JB; Tue, 02 Apr 2019 01:40:42 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 44YJ2m4Z01z9sTV; Tue, 2 Apr 2019 16:40:31 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1554183632; bh=97XawjvFbjiWgIlxkck7yuDkhnP7D1VTdVIC2GTyGpg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=aaI5tpdmoWav9hv3AzdKz4/3pmGsJ5ROivgn/M6TxgZoTjvZ1MpcxBoqKNJOUq/t2 vBjNexZBpB0wr5KlWHAoI5Od99t3qkc3Sy3W5xd/QPDPb90IQBK24LOjm/Hr04HnNj cZQpqCIWSr8WCurY8f5dfdbRX6QeFCYqeYm0yD+w= From: David Gibson To: qemu-devel@nongnu.org, Alex Williamson , Marcel Apfelbaum , "Michael S. Tsirkin" , Greg Kurz Date: Tue, 2 Apr 2019 16:40:28 +1100 Message-Id: <20190402054028.20926-6-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190402054028.20926-1-david@gibson.dropbear.id.au> References: <20190402054028.20926-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 203.11.71.1 Subject: [Qemu-devel] [RFC for-4.1 5/5] pcie: Simplify pci_adjust_config_limit() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Since c2077e2c "pci: Adjust PCI config limit based on bus topology", pci_adjust_config_limit() has been used in the config space read and write paths to only permit access to extended config space on buses which permit it. Specifically it prevents access on devices below a vanilla-PCI bus via some combination of bridges, even if both the host bridge and the device itself are PCI-E. It accomplishes this with a somewhat complex call up the chain of bridges to see if any of them prohibit extended config space access. This is overly complex, since we can always know if the bus will support such access at the point it is constructed. This patch simplifies the test by using a flag in the PCIBus instance indicating wither extended configuration space is accessible. It is always false for vanilla PCI buses. For PCI-E buses, it is true for root buses and equal to the parent bus's's capability otherwise. This should cause no behavioural change. Signed-off-by: David Gibson --- hw/pci/pci.c | 36 ++++++++++++++++++++++-------------- hw/pci/pci_host.c | 13 +++---------- hw/ppc/spapr_pci.c | 24 +++++++++--------------- include/hw/pci/pci_bus.h | 3 ++- 4 files changed, 36 insertions(+), 40 deletions(-) diff --git a/hw/pci/pci.c b/hw/pci/pci.c index ea5941fb22..420496571e 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -120,6 +120,25 @@ static void pci_bus_realize(BusState *qbus, Error **er= rp) vmstate_register(NULL, -1, &vmstate_pcibus, bus); } =20 +static void pcie_bus_realize(BusState *qbus, Error **errp) +{ + PCIBus *bus =3D PCI_BUS(qbus); + + pci_bus_realize(qbus, errp); + + /* a PCI-E bus can supported extended config space if it's the + * root bus, or if the bus/bridge above it does as well */ + if (pci_bus_is_root(bus)) { + bus->flags |=3D PCI_BUS_EXTENDED_CONFIG_SPACE; + } else { + PCIBus *parent_bus =3D pci_get_bus(bus->parent_dev); + + if (pci_bus_allows_extended_config_space(parent_bus)) { + bus->flags |=3D PCI_BUS_EXTENDED_CONFIG_SPACE; + } + } +} + static void pci_bus_unrealize(BusState *qbus, Error **errp) { PCIBus *bus =3D PCI_BUS(qbus); @@ -142,11 +161,6 @@ static uint16_t pcibus_numa_node(PCIBus *bus) return NUMA_NODE_UNASSIGNED; } =20 -static bool pcibus_allows_extended_config_space(PCIBus *bus) -{ - return false; -} - static void pci_bus_class_init(ObjectClass *klass, void *data) { BusClass *k =3D BUS_CLASS(klass); @@ -161,7 +175,6 @@ static void pci_bus_class_init(ObjectClass *klass, void= *data) =20 pbc->bus_num =3D pcibus_num; pbc->numa_node =3D pcibus_numa_node; - pbc->allows_extended_config_space =3D pcibus_allows_extended_config_sp= ace; } =20 static const TypeInfo pci_bus_info =3D { @@ -182,16 +195,11 @@ static const TypeInfo conventional_pci_interface_info= =3D { .parent =3D TYPE_INTERFACE, }; =20 -static bool pciebus_allows_extended_config_space(PCIBus *bus) -{ - return true; -} - static void pcie_bus_class_init(ObjectClass *klass, void *data) { - PCIBusClass *pbc =3D PCI_BUS_CLASS(klass); + BusClass *k =3D BUS_CLASS(klass); =20 - pbc->allows_extended_config_space =3D pciebus_allows_extended_config_s= pace; + k->realize =3D pcie_bus_realize; } =20 static const TypeInfo pcie_bus_info =3D { @@ -412,7 +420,7 @@ bool pci_bus_is_express(PCIBus *bus) =20 bool pci_bus_allows_extended_config_space(PCIBus *bus) { - return PCI_BUS_GET_CLASS(bus)->allows_extended_config_space(bus); + return !!(bus->flags & PCI_BUS_EXTENDED_CONFIG_SPACE); } =20 void pci_root_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState *p= arent, diff --git a/hw/pci/pci_host.c b/hw/pci/pci_host.c index 9d64b2e12f..5f3497256c 100644 --- a/hw/pci/pci_host.c +++ b/hw/pci/pci_host.c @@ -53,16 +53,9 @@ static inline PCIDevice *pci_dev_find_by_addr(PCIBus *bu= s, uint32_t addr) =20 static void pci_adjust_config_limit(PCIBus *bus, uint32_t *limit) { - if (*limit > PCI_CONFIG_SPACE_SIZE) { - if (!pci_bus_allows_extended_config_space(bus)) { - *limit =3D PCI_CONFIG_SPACE_SIZE; - return; - } - - if (!pci_bus_is_root(bus)) { - PCIDevice *bridge =3D pci_bridge_get_device(bus); - pci_adjust_config_limit(pci_get_bus(bridge), limit); - } + if ((*limit > PCI_CONFIG_SPACE_SIZE) && + !pci_bus_allows_extended_config_space(bus)) { + *limit =3D PCI_CONFIG_SPACE_SIZE; } } =20 diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c index 2e76d8cbd8..23d70ca6fe 100644 --- a/hw/ppc/spapr_pci.c +++ b/hw/ppc/spapr_pci.c @@ -1638,26 +1638,11 @@ static void spapr_phb_unrealize(DeviceState *dev, E= rror **errp) memory_region_del_subregion(get_system_memory(), &sphb->mem32window); } =20 -static bool spapr_phb_allows_extended_config_space(PCIBus *bus) -{ - SpaprPhbState *sphb =3D SPAPR_PCI_HOST_BRIDGE(BUS(bus)->parent); - - return sphb->pcie_ecs; -} - -static void spapr_phb_root_bus_class_init(ObjectClass *klass, void *data) -{ - PCIBusClass *pbc =3D PCI_BUS_CLASS(klass); - - pbc->allows_extended_config_space =3D spapr_phb_allows_extended_config= _space; -} - #define TYPE_SPAPR_PHB_ROOT_BUS "spapr-pci-host-bridge-root-bus" =20 static const TypeInfo spapr_phb_root_bus_info =3D { .name =3D TYPE_SPAPR_PHB_ROOT_BUS, .parent =3D TYPE_PCI_BUS, - .class_init =3D spapr_phb_root_bus_class_init, }; =20 static void spapr_phb_realize(DeviceState *dev, Error **errp) @@ -1766,6 +1751,15 @@ static void spapr_phb_realize(DeviceState *dev, Erro= r **errp) &sphb->memspace, &sphb->iospace, PCI_DEVFN(0, 0), PCI_NUM_PINS, TYPE_SPAPR_PHB_ROOT_BUS); + + /* + * Despite resembling a vanilla PCI bus in most ways, the PAPR + * para-virtualized PCI bus *does* permit PCI-E extended config + * space access + */ + if (sphb->pcie_ecs) { + bus->flags |=3D PCI_BUS_EXTENDED_CONFIG_SPACE; + } phb->bus =3D bus; qbus_set_hotplug_handler(BUS(phb->bus), OBJECT(sphb), NULL); =20 diff --git a/include/hw/pci/pci_bus.h b/include/hw/pci/pci_bus.h index aea98d5040..3c0be4c420 100644 --- a/include/hw/pci/pci_bus.h +++ b/include/hw/pci/pci_bus.h @@ -17,12 +17,13 @@ typedef struct PCIBusClass { =20 int (*bus_num)(PCIBus *bus); uint16_t (*numa_node)(PCIBus *bus); - bool (*allows_extended_config_space)(PCIBus *bus); } PCIBusClass; =20 enum PCIBusFlags { /* This bus is the root of a PCI domain */ PCI_BUS_IS_ROOT =3D 0x0001, + /* PCIe extended configuration space is accessible on this bus */ + PCI_BUS_EXTENDED_CONFIG_SPACE =3D 0x0002, }; =20 struct PCIBus { --=20 2.20.1