From nobody Tue Feb 10 05:14:27 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 155408866954227.68682271877242; Sun, 31 Mar 2019 20:17:49 -0700 (PDT) Received: from localhost ([127.0.0.1]:34392 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hAnSD-0002bh-AV for importer@patchew.org; Sun, 31 Mar 2019 23:17:45 -0400 Received: from eggs.gnu.org ([209.51.188.92]:38997) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hAnN1-0006oN-2T for qemu-devel@nongnu.org; Sun, 31 Mar 2019 23:12:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hAnMz-0002rp-QI for qemu-devel@nongnu.org; Sun, 31 Mar 2019 23:12:23 -0400 Received: from mail-pg1-x544.google.com ([2607:f8b0:4864:20::544]:33487) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hAnMz-0002qw-FL for qemu-devel@nongnu.org; Sun, 31 Mar 2019 23:12:21 -0400 Received: by mail-pg1-x544.google.com with SMTP id b12so4005876pgk.0 for ; Sun, 31 Mar 2019 20:12:20 -0700 (PDT) Received: from cloudburst.imgcgcw.net ([147.50.13.10]) by smtp.gmail.com with ESMTPSA id c1sm11843954pfd.114.2019.03.31.20.12.17 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 31 Mar 2019 20:12:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=JUQH54WlqWGm8qyK2Q0VFVzTkdAZArTzYx2vwJJCIVI=; b=GD0V5uMURb1QM+rZt7wGIQ5Met93OWvQpXKF0JN9RT/Y/FDsmy6j4ZF9YkmR2At3Z9 g5ExvDJcQSzya65ef+53d1P+TQKS611GqCOiGOBVxe6D0hN7NIl63IGsbv97V8yz5xQp nJOhbXBZradEvA41045luL20QmPiejGtbu9p3bXVJWjC1ohyUnC7gR97OHH3CVLPZE4n yfTW/1WV71rprSsELS3BKgHKApID/3xrXVff1PBD0VZ3xFg/XNW5ExzFZEYqUsL/S1zX ptS2G4sqYdVSdnM+wv1nyu5kfoN14IpuyfxnnAPvdzyrTm01pO59thqTqi6/oJC5E7/M miGg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=JUQH54WlqWGm8qyK2Q0VFVzTkdAZArTzYx2vwJJCIVI=; b=okqGe7fk7QEHkHbsR27tF/1Hco6fjYhvZKjdDtIoZ055/beRVzg9BeLPwss4X2rOhT 9NPE+sgxLIKgftBVQu2yC4ttrlcJaow+zqXTx5aP6F5N+1f80XgDoJJ3RGrsfZnHX98X RLAhX+mxIncnZdudIJdzxhpJcTPJqa20jllweNDyeKgjX3l+MyebQYi+XMLuhH6OXlB0 LCgn1zno4tTej4B6k0zfQnnyLLo60/CanGdSN8VxvMcStQfNH8lYe8rjdZtfu7db+R1M 0GQPMmFNJzsC60WP1nxHo3VIuvnH1SjkOyx+q8/zjicX4V26iVezR0yAPb02ES89lXvz ouoA== X-Gm-Message-State: APjAAAU7pZwMVIRqmtMRQ1qvvFnU42uzot/isSP1c6HUR9+d47822DkO FYywZmFxjQ4JK/hUlDxL2Ykm9nLW433Hsg== X-Google-Smtp-Source: APXvYqzTdRFtojuCNnW0xKO8vqyCJzYlwSorBVwiCOXuftNt4+vRJznWLwcfd1+uv72nUQCt8npZag== X-Received: by 2002:a63:d5f:: with SMTP id 31mr12260960pgn.208.1554088339769; Sun, 31 Mar 2019 20:12:19 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 1 Apr 2019 10:11:51 +0700 Message-Id: <20190401031155.21293-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190401031155.21293-1-richard.henderson@linaro.org> References: <20190401031155.21293-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::544 Subject: [Qemu-devel] [PATCH for-4.1 4/8] target/riscv: Merge argument decode for RVC shifti X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: kbastian@mail.uni-paderborn.de, palmer@sifive.com, Alistair.Francis@wdc.com, qemu-riscv@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Special handling for IMM=3D=3D0 is the only difference between RVC shifti and RVI shifti. This can be handled with !function. Signed-off-by: Richard Henderson Reviewed-by: Palmer Dabbelt --- target/riscv/insn_trans/trans_rvc.inc.c | 47 ------------------------- target/riscv/translate.c | 6 ++++ target/riscv/insn16.decode | 12 +++---- 3 files changed, 12 insertions(+), 53 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvc.inc.c b/target/riscv/insn_tr= ans/trans_rvc.inc.c index dfb46a2348..691b1e2725 100644 --- a/target/riscv/insn_trans/trans_rvc.inc.c +++ b/target/riscv/insn_trans/trans_rvc.inc.c @@ -97,37 +97,6 @@ static bool trans_c_addi16sp_lui(DisasContext *ctx, arg_= c_addi16sp_lui *a) return false; } =20 -static bool trans_c_srli(DisasContext *ctx, arg_c_srli *a) -{ - int shamt =3D a->shamt; - if (shamt =3D=3D 0) { - /* For RV128 a shamt of 0 means a shift by 64 */ - shamt =3D 64; - } - /* Ensure, that shamt[5] is zero for RV32 */ - if (shamt >=3D TARGET_LONG_BITS) { - return false; - } - - arg_srli arg =3D { .rd =3D a->rd, .rs1 =3D a->rd, .shamt =3D a->shamt = }; - return trans_srli(ctx, &arg); -} - -static bool trans_c_srai(DisasContext *ctx, arg_c_srai *a) -{ - int shamt =3D a->shamt; - if (shamt =3D=3D 0) { - /* For RV128 a shamt of 0 means a shift by 64 */ - shamt =3D 64; - } - /* Ensure, that shamt[5] is zero for RV32 */ - if (shamt >=3D TARGET_LONG_BITS) { - return false; - } - - arg_srai arg =3D { .rd =3D a->rd, .rs1 =3D a->rd, .shamt =3D a->shamt = }; - return trans_srai(ctx, &arg); -} =20 static bool trans_c_subw(DisasContext *ctx, arg_c_subw *a) { @@ -147,22 +116,6 @@ static bool trans_c_addw(DisasContext *ctx, arg_c_addw= *a) #endif } =20 -static bool trans_c_slli(DisasContext *ctx, arg_c_slli *a) -{ - int shamt =3D a->shamt; - if (shamt =3D=3D 0) { - /* For RV128 a shamt of 0 means a shift by 64 */ - shamt =3D 64; - } - /* Ensure, that shamt[5] is zero for RV32 */ - if (shamt >=3D TARGET_LONG_BITS) { - return false; - } - - arg_slli arg =3D { .rd =3D a->rd, .rs1 =3D a->rd, .shamt =3D a->shamt = }; - return trans_slli(ctx, &arg); -} - static bool trans_c_flwsp_ldsp(DisasContext *ctx, arg_c_flwsp_ldsp *a) { #ifdef TARGET_RISCV32 diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 9e016d8e50..a1cd29f80f 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -538,6 +538,12 @@ static int ex_rvc_register(int reg) return 8 + reg; } =20 +static int ex_rvc_shifti(int imm) +{ + /* For RV128 a shamt of 0 means a shift by 64. */ + return imm ? imm : 64; +} + /* Include the auto-generated decoder for 32 bit insn */ #include "decode_insn32.inc.c" =20 diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode index d0cc778bc9..add9cf3923 100644 --- a/target/riscv/insn16.decode +++ b/target/riscv/insn16.decode @@ -30,7 +30,7 @@ %imm_cb 12:s1 5:2 2:1 10:2 3:2 !function=3Dex_shift_1 %imm_cj 12:s1 8:1 9:2 6:1 7:1 2:1 11:1 3:3 !function=3Dex_shift_1 =20 -%nzuimm_6bit 12:1 2:5 +%shimm_6bit 12:1 2:5 !function=3Dex_rvc_shifti %uimm_6bit_ld 2:3 12:1 5:2 !function=3Dex_shift_3 %uimm_6bit_lw 2:2 12:1 4:3 !function=3Dex_shift_2 %uimm_6bit_sd 7:3 10:3 !function=3Dex_shift_3 @@ -94,9 +94,9 @@ uimm_sdsp=3D%uimm_6bit_sd rs2=3D%rs2_5 =20 @c_shift ... . .. ... ..... .. \ - &shift rd=3D%rs1_3 rs1=3D%rs1_3 shamt=3D%nzuimm_6bit + &shift rd=3D%rs1_3 rs1=3D%rs1_3 shamt=3D%shimm_6bit @c_shift2 ... . .. ... ..... .. \ - &shift rd=3D%rd rs1=3D%rd shamt=3D%nzuimm_6bit + &shift rd=3D%rd rs1=3D%rd shamt=3D%shimm_6bit =20 @c_andi ... . .. ... ..... .. &i imm=3D%imm_ci rs1=3D%rs1_3 rd=3D%= rs1_3 =20 @@ -114,8 +114,8 @@ addi 000 . ..... ..... 01 @ci c_jal_addiw 001 . ..... ..... 01 @ci #Note: parse rd and/or imm ma= nually addi 010 . ..... ..... 01 @c_li c_addi16sp_lui 011 . ..... ..... 01 @c_addi16sp_lui # shares opc with= C.LUI -c_srli 100 . 00 ... ..... 01 @c_shift -c_srai 100 . 01 ... ..... 01 @c_shift +srli 100 . 00 ... ..... 01 @c_shift +srai 100 . 01 ... ..... 01 @c_shift andi 100 . 10 ... ..... 01 @c_andi sub 100 0 11 ... 00 ... 01 @cs_2 xor 100 0 11 ... 01 ... 01 @cs_2 @@ -128,7 +128,7 @@ beq 110 ... ... ..... 01 @cb_z bne 111 ... ... ..... 01 @cb_z =20 # *** RV64C Standard Extension (Quadrant 2) *** -c_slli 000 . ..... ..... 10 @c_shift2 +slli 000 . ..... ..... 10 @c_shift2 fld 001 . ..... ..... 10 @c_ldsp lw 010 . ..... ..... 10 @c_lwsp c_flwsp_ldsp 011 . ..... ..... 10 @c_flwsp_ldsp #C.LDSP:RV64;C.FLWS= P:RV32 --=20 2.17.1