From nobody Mon Feb 9 08:10:27 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1553840510156914.3884114423088; Thu, 28 Mar 2019 23:21:50 -0700 (PDT) Received: from localhost ([127.0.0.1]:47243 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h9ktc-0007Fo-Rb for importer@patchew.org; Fri, 29 Mar 2019 02:21:44 -0400 Received: from eggs.gnu.org ([209.51.188.92]:50040) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h9ks1-00067f-TN for qemu-devel@nongnu.org; Fri, 29 Mar 2019 02:20:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1h9kml-0007xy-9r for qemu-devel@nongnu.org; Fri, 29 Mar 2019 02:14:40 -0400 Received: from mx1.redhat.com ([209.132.183.28]:54998) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1h9kml-0007xe-0O for qemu-devel@nongnu.org; Fri, 29 Mar 2019 02:14:39 -0400 Received: from smtp.corp.redhat.com (int-mx07.intmail.prod.int.phx2.redhat.com [10.5.11.22]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 217363092645; Fri, 29 Mar 2019 06:14:38 +0000 (UTC) Received: from xz-x1.nay.redhat.com (dhcp-14-116.nay.redhat.com [10.66.14.116]) by smtp.corp.redhat.com (Postfix) with ESMTP id ABBB91001DC0; Fri, 29 Mar 2019 06:14:35 +0000 (UTC) From: Peter Xu To: qemu-devel@nongnu.org Date: Fri, 29 Mar 2019 14:14:22 +0800 Message-Id: <20190329061422.7926-3-peterx@redhat.com> In-Reply-To: <20190329061422.7926-1-peterx@redhat.com> References: <20190329061422.7926-1-peterx@redhat.com> X-Scanned-By: MIMEDefang 2.84 on 10.5.11.22 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.43]); Fri, 29 Mar 2019 06:14:38 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH v2 2/2] intel_iommu: Drop extended root field X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Yi Liu , Yi Sun , "Michael S . Tsirkin" , Jason Wang , "Dr . David Alan Gilbert" , peterx@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" VTD_RTADDR_RTT is dropped even by the VT-d spec, so QEMU should probably do the same thing (after all we never really implemented it). Since we've had a field for that in the migration stream, to keep compatibility we need to fill the hole up. Please refer to VT-d spec 10.4.6. Signed-off-by: Peter Xu Acked-by: Dr. David Alan Gilbert Reviewed-by: Liu, Yi L --- hw/i386/intel_iommu.c | 6 ++---- hw/i386/intel_iommu_internal.h | 1 - hw/i386/trace-events | 2 +- include/hw/i386/intel_iommu.h | 1 - 4 files changed, 3 insertions(+), 7 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 21c6176b4a..1e452e5861 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -1718,12 +1718,11 @@ error: static void vtd_root_table_setup(IntelIOMMUState *s) { s->root =3D vtd_get_quad_raw(s, DMAR_RTADDR_REG); - s->root_extended =3D s->root & VTD_RTADDR_RTT; s->root &=3D VTD_RTADDR_ADDR_MASK(s->aw_bits); =20 vtd_update_scalable_state(s); =20 - trace_vtd_reg_dmar_root(s->root, s->root_extended); + trace_vtd_reg_dmar_root(s->root, s->root_scalable); } =20 static void vtd_iec_notify_all(IntelIOMMUState *s, bool global, @@ -2982,7 +2981,7 @@ static const VMStateDescription vtd_vmstate =3D { VMSTATE_UINT16(next_frcd_reg, IntelIOMMUState), VMSTATE_UINT8_ARRAY(csr, IntelIOMMUState, DMAR_REG_SIZE), VMSTATE_UINT8(iq_last_desc_type, IntelIOMMUState), - VMSTATE_BOOL(root_extended, IntelIOMMUState), + VMSTATE_UNUSED(1), /* bool root_extended is obsolete by VT-d = */ VMSTATE_BOOL(dmar_enabled, IntelIOMMUState), VMSTATE_BOOL(qi_enabled, IntelIOMMUState), VMSTATE_BOOL(intr_enabled, IntelIOMMUState), @@ -3493,7 +3492,6 @@ static void vtd_init(IntelIOMMUState *s) memset(s->womask, 0, DMAR_REG_SIZE); =20 s->root =3D 0; - s->root_extended =3D false; s->root_scalable =3D false; s->dmar_enabled =3D false; s->intr_enabled =3D false; diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index 1160618177..c1235a7063 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -171,7 +171,6 @@ #define VTD_CCMD_FM(val) (((val) >> 32) & 3ULL) =20 /* RTADDR_REG */ -#define VTD_RTADDR_RTT (1ULL << 11) #define VTD_RTADDR_SMT (1ULL << 10) #define VTD_RTADDR_ADDR_MASK(aw) (VTD_HAW_MASK(aw) ^ 0xfffULL) =20 diff --git a/hw/i386/trace-events b/hw/i386/trace-events index 83f8369778..c8bc464bc5 100644 --- a/hw/i386/trace-events +++ b/hw/i386/trace-events @@ -45,7 +45,7 @@ vtd_pt_enable_fast_path(uint16_t sid, bool success) "sid = 0x%"PRIu16" %d" vtd_irq_generate(uint64_t addr, uint64_t data) "addr 0x%"PRIx64" data 0x%"= PRIx64 vtd_reg_read(uint64_t addr, uint64_t size) "addr 0x%"PRIx64" size 0x%"PRIx= 64 vtd_reg_write(uint64_t addr, uint64_t size, uint64_t val) "addr 0x%"PRIx64= " size 0x%"PRIx64" value 0x%"PRIx64 -vtd_reg_dmar_root(uint64_t addr, bool extended) "addr 0x%"PRIx64" extended= %d" +vtd_reg_dmar_root(uint64_t addr, bool scalable) "addr 0x%"PRIx64" scalable= %d" vtd_reg_ir_root(uint64_t addr, uint32_t size) "addr 0x%"PRIx64" size 0x%"P= RIx32 vtd_reg_write_gcmd(uint32_t status, uint32_t val) "status 0x%"PRIx32" valu= e 0x%"PRIx32 vtd_reg_write_fectl(uint32_t value) "value 0x%"PRIx32 diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h index c11e3d5b34..199a813eee 100644 --- a/include/hw/i386/intel_iommu.h +++ b/include/hw/i386/intel_iommu.h @@ -231,7 +231,6 @@ struct IntelIOMMUState { bool scalable_mode; /* RO - is Scalable Mode supported? */ =20 dma_addr_t root; /* Current root table pointer */ - bool root_extended; /* Type of root table (extended or not= ) */ bool root_scalable; /* Type of root table (scalable or not= ) */ bool dmar_enabled; /* Set if DMA remapping is enabled */ =20 --=20 2.17.1