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[66.75.72.255]) by smtp.gmail.com with ESMTPSA id f1sm280911pgl.35.2019.03.28.16.04.14 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 28 Mar 2019 16:04:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=aSbnWBUt+OyqJcHJJ8p6fou8PhhPa6kAtdIjzElNQEo=; b=dFR6Bk1dOngzzFYCFEAY8ruOhMJuADMZCWuGgTPoWBX8EH9afGQyxWc5ymE9YdQaj4 gjHkW88QIPFK8Cts3TpmZ4dtSr4iuxbBqJ5SmHEHd8ocMUNeTrJ+aqtZ/AX+MDBX/Rwr tzlY2EkkF/VdE10QBybHi34ck3Bw79aCXSLyniSsEQpw/laYge29NQNUv80EpFAJinzW /byXtqjLn0KR1Ii8uS97jfRAuVsa1OXk2LQfMPVJVvHkzN0SfG6P6rqOPwPvKapPr7EZ LJfljioxcgFShw0YGcxnRD1fetqEVfyDzZhgaw6HlFnzHA5LZUNYh6nyibNegXBV/88e omog== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=aSbnWBUt+OyqJcHJJ8p6fou8PhhPa6kAtdIjzElNQEo=; b=TBLaYEULKRTbnUo6uNXWsF23ZzHbiVpiqaosjCfvoFQLpSyETAZcZUaN6hQMthtd3l xlxmqXTM+LS6ZaUBpuhdIe29zXxYcSW9vHrjJeT6Bq7jsNaGDSsi2UhlDSY8ejpPEwSb 7zEO7Z5ctvmQ8x0cVICMk1NyyrXuvi5uPDCt598TMNy6qDG0EuWg0cGSlWks6Mq7w5yG 3xkxpmr2JPP/QiQclZB2GjSZ7y8ooAsmHmLBkU81bNyWvLIL/Rz5a1UXR2aUJ7SY9Vvg U6kFNsd19m+GutMut6qk4+GsOPtYSmRcjSk7TSRvaz0RaVOusldyBe+IMKQhB5NU96CR RDdw== X-Gm-Message-State: APjAAAV1F0C4hoPXjUkt8pe9LNjKESPV4DtsrKi3YlxzKf/Ggi0OqHgF hJf6YgoScuwDGI2OsrVdN1Ur5a1lakQ= X-Google-Smtp-Source: APXvYqxY5pw3bXQeP4rv6o0IHn6MVWfDTj9AStD2L37ksRnCwhYObg5jSEEre8UmQxSqlKCJ+sMJcQ== X-Received: by 2002:a17:902:e101:: with SMTP id cc1mr5463079plb.129.1553814255595; Thu, 28 Mar 2019 16:04:15 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 28 Mar 2019 13:03:32 -1000 Message-Id: <20190328230404.12909-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190328230404.12909-1-richard.henderson@linaro.org> References: <20190328230404.12909-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::644 Subject: [Qemu-devel] [PATCH for-4.1 v2 04/36] cpu: Define CPUArchState with typedef X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" For all targets, do this just before including exec/cpu-all.h. Acked-by: Alistair Francis Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/alpha/cpu.h | 4 ++-- target/arm/cpu.h | 4 ++-- target/cris/cpu.h | 4 ++-- target/hppa/cpu.h | 4 ++-- target/i386/cpu.h | 5 ++--- target/lm32/cpu.h | 5 ++--- target/m68k/cpu.h | 4 ++-- target/microblaze/cpu.h | 5 ++--- target/mips/cpu.h | 6 ++---- target/moxie/cpu.h | 4 ++-- target/nios2/cpu.h | 5 ++--- target/openrisc/cpu.h | 4 ++-- target/ppc/cpu.h | 4 ++-- target/riscv/cpu.h | 4 ++-- target/s390x/cpu.h | 8 ++++---- target/sh4/cpu.h | 4 ++-- target/sparc/cpu.h | 4 ++-- target/tilegx/cpu.h | 4 ++-- target/tricore/cpu.h | 6 +----- target/unicore32/cpu.h | 4 ++-- target/xtensa/cpu.h | 4 ++-- 21 files changed, 43 insertions(+), 53 deletions(-) diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index e4aacbe5a3..fac622aa02 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -26,8 +26,6 @@ =20 #define ALIGNED_ONLY =20 -#define CPUArchState struct CPUAlphaState - /* Alpha processors have a weak memory model */ #define TCG_GUEST_DEFAULT_MO (0) =20 @@ -302,6 +300,8 @@ void alpha_cpu_do_unaligned_access(CPUState *cpu, vaddr= addr, #define cpu_list alpha_cpu_list #define cpu_signal_handler cpu_alpha_signal_handler =20 +typedef CPUAlphaState CPUArchState; + #include "exec/cpu-all.h" =20 enum { diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 12af124159..e043fd3f97 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -29,8 +29,6 @@ /* ARM processors have a weak memory model */ #define TCG_GUEST_DEFAULT_MO (0) =20 -#define CPUArchState struct CPUARMState - #define EXCP_UDEF 1 /* undefined instruction */ #define EXCP_SWI 2 /* software interrupt */ #define EXCP_PREFETCH_ABORT 3 @@ -3045,6 +3043,8 @@ static inline bool arm_cpu_data_is_big_endian(CPUARMS= tate *env) } } =20 +typedef CPUARMState CPUArchState; + #include "exec/cpu-all.h" =20 /* Bit usage in the TB flags field: bit 31 indicates whether we are diff --git a/target/cris/cpu.h b/target/cris/cpu.h index 832796d457..95662c36b2 100644 --- a/target/cris/cpu.h +++ b/target/cris/cpu.h @@ -25,8 +25,6 @@ #include "cpu-qom.h" #include "exec/cpu-defs.h" =20 -#define CPUArchState struct CPUCRISState - #define EXCP_NMI 1 #define EXCP_GURU 2 #define EXCP_BUSFAULT 3 @@ -286,6 +284,8 @@ int cris_cpu_handle_mmu_fault(CPUState *cpu, vaddr addr= ess, int size, int rw, #define SFR_RW_MM_TLB_LO env->pregs[PR_SRS]][5 #define SFR_RW_MM_TLB_HI env->pregs[PR_SRS]][6 =20 +typedef CPUCRISState CPUArchState; + #include "exec/cpu-all.h" =20 static inline void cpu_get_tb_cpu_state(CPUCRISState *env, target_ulong *p= c, diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index fe97786de1..7c1d1e0a0e 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -31,8 +31,6 @@ basis. It's probably easier to fall back to a strong memory model. */ #define TCG_GUEST_DEFAULT_MO TCG_MO_ALL =20 -#define CPUArchState struct CPUHPPAState - #define ALIGNED_ONLY #define MMU_KERNEL_IDX 0 #define MMU_USER_IDX 3 @@ -232,6 +230,8 @@ static inline HPPACPU *hppa_env_get_cpu(CPUHPPAState *e= nv) #define ENV_GET_CPU(e) CPU(hppa_env_get_cpu(e)) #define ENV_OFFSET offsetof(HPPACPU, env) =20 +typedef CPUHPPAState CPUArchState; + #include "exec/cpu-all.h" =20 static inline int cpu_mmu_index(CPUHPPAState *env, bool ifetch) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 6716958276..84ca69ea1a 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1,4 +1,3 @@ - /* * i386 virtual CPU header * @@ -44,8 +43,6 @@ #define ELF_MACHINE_UNAME "i686" #endif =20 -#define CPUArchState struct CPUX86State - enum { R_EAX =3D 0, R_ECX =3D 1, @@ -1752,6 +1749,8 @@ static inline target_long lshift(target_long x, int n) /* translate.c */ void tcg_x86_init(void); =20 +typedef CPUX86State CPUArchState; + #include "exec/cpu-all.h" #include "svm.h" =20 diff --git a/target/lm32/cpu.h b/target/lm32/cpu.h index 3c9c8a904c..5b24cfcc1f 100644 --- a/target/lm32/cpu.h +++ b/target/lm32/cpu.h @@ -24,9 +24,6 @@ #include "cpu-qom.h" #include "exec/cpu-defs.h" =20 -#define CPUArchState struct CPULM32State - -struct CPULM32State; typedef struct CPULM32State CPULM32State; =20 static inline int cpu_mmu_index(CPULM32State *env, bool ifetch) @@ -259,6 +256,8 @@ bool lm32_cpu_do_semihosting(CPUState *cs); int lm32_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int = rw, int mmu_idx); =20 +typedef CPULM32State CPUArchState; + #include "exec/cpu-all.h" =20 static inline void cpu_get_tb_cpu_state(CPULM32State *env, target_ulong *p= c, diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index 6bf44604b5..48c051c7d2 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -25,8 +25,6 @@ #include "exec/cpu-defs.h" #include "cpu-qom.h" =20 -#define CPUArchState struct CPUM68KState - #define OS_BYTE 0 #define OS_WORD 1 #define OS_LONG 2 @@ -537,6 +535,8 @@ void m68k_cpu_unassigned_access(CPUState *cs, hwaddr ad= dr, bool is_write, bool is_exec, int is_asi, unsigned size); =20 +typedef CPUM68KState CPUArchState; + #include "exec/cpu-all.h" =20 /* TB flags */ diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index c8a9d4b146..dddd58e165 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -25,9 +25,6 @@ #include "exec/cpu-defs.h" #include "fpu/softfloat-types.h" =20 -#define CPUArchState struct CPUMBState - -struct CPUMBState; typedef struct CPUMBState CPUMBState; #if !defined(CONFIG_USER_ONLY) #include "mmu.h" @@ -368,6 +365,8 @@ static inline int cpu_mmu_index (CPUMBState *env, bool = ifetch) int mb_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int rw, int mmu_idx); =20 +typedef CPUMBState CPUArchState; + #include "exec/cpu-all.h" =20 static inline void cpu_get_tb_cpu_state(CPUMBState *env, target_ulong *pc, diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 1cd59e31f7..608ae23289 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -3,8 +3,6 @@ =20 #define ALIGNED_ONLY =20 -#define CPUArchState struct CPUMIPSState - #include "qemu-common.h" #include "cpu-qom.h" #include "exec/cpu-defs.h" @@ -13,8 +11,6 @@ =20 #define TCG_GUEST_DEFAULT_MO (0) =20 -struct CPUMIPSState; - typedef struct CPUMIPSTLBContext CPUMIPSTLBContext; =20 /* MSA Context */ @@ -1094,6 +1090,8 @@ static inline int cpu_mmu_index (CPUMIPSState *env, b= ool ifetch) return hflags_mmu_index(env->hflags); } =20 +typedef CPUMIPSState CPUArchState; + #include "exec/cpu-all.h" =20 /* Memory access type : diff --git a/target/moxie/cpu.h b/target/moxie/cpu.h index b060c69e38..10ba6aa7be 100644 --- a/target/moxie/cpu.h +++ b/target/moxie/cpu.h @@ -23,8 +23,6 @@ #include "qemu-common.h" #include "exec/cpu-defs.h" =20 -#define CPUArchState struct CPUMoxieState - #define MOXIE_EX_DIV0 0 #define MOXIE_EX_BAD 1 #define MOXIE_EX_IRQ 2 @@ -120,6 +118,8 @@ static inline int cpu_mmu_index(CPUMoxieState *env, boo= l ifetch) return 0; } =20 +typedef CPUMoxieState CPUArchState; + #include "exec/cpu-all.h" =20 static inline void cpu_get_tb_cpu_state(CPUMoxieState *env, target_ulong *= pc, diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 50fb5fef46..2b4bd25d65 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -24,9 +24,6 @@ #include "exec/cpu-defs.h" #include "qom/cpu.h" =20 -#define CPUArchState struct CPUNios2State - -struct CPUNios2State; typedef struct CPUNios2State CPUNios2State; #if !defined(CONFIG_USER_ONLY) #include "mmu.h" @@ -246,6 +243,8 @@ static inline int cpu_interrupts_enabled(CPUNios2State = *env) return env->regs[CR_STATUS] & CR_STATUS_PIE; } =20 +typedef CPUNios2State CPUArchState; + #include "exec/cpu-all.h" =20 static inline void cpu_get_tb_cpu_state(CPUNios2State *env, target_ulong *= pc, diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 9bd137d9a2..9bd583f13a 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -24,8 +24,6 @@ #include "exec/cpu-defs.h" #include "qom/cpu.h" =20 -#define CPUArchState struct CPUOpenRISCState - /* cpu_openrisc_map_address_* in CPUOpenRISCTLBContext need this decl. */ struct OpenRISCCPU; =20 @@ -365,6 +363,8 @@ void cpu_openrisc_count_stop(OpenRISCCPU *cpu); #define OPENRISC_CPU_TYPE_NAME(model) model OPENRISC_CPU_TYPE_SUFFIX #define CPU_RESOLVING_TYPE TYPE_OPENRISC_CPU =20 +typedef CPUOpenRISCState CPUArchState; + #include "exec/cpu-all.h" =20 #define TB_FLAGS_SM SR_SM diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 1867215b0f..18825ebafc 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -32,8 +32,6 @@ #define TARGET_PAGE_BITS_64K 16 #define TARGET_PAGE_BITS_16M 24 =20 -#define CPUArchState struct CPUPPCState - #if defined (TARGET_PPC64) #define PPC_ELF_MACHINE EM_PPC64 #else @@ -1366,6 +1364,8 @@ void ppc_compat_add_property(Object *obj, const char = *name, Error **errp); #endif /* defined(TARGET_PPC64) */ =20 +typedef CPUPPCState CPUArchState; + #include "exec/cpu-all.h" =20 /*************************************************************************= ****/ diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 7d9b07ebc0..df71872a82 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -27,8 +27,6 @@ =20 #define TCG_GUEST_DEFAULT_MO 0 =20 -#define CPUArchState struct CPURISCVState - #define TYPE_RISCV_CPU "riscv-cpu" =20 #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU @@ -325,6 +323,8 @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations = *ops); =20 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); =20 +typedef CPURISCVState CPUArchState; + #include "exec/cpu-all.h" =20 #endif /* RISCV_CPU_H */ diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index 2ef3134177..00b9e6d3b8 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -28,13 +28,9 @@ =20 #define ELF_MACHINE_UNAME "S390X" =20 -#define CPUArchState struct CPUS390XState - /* The z/Architecture has a strong memory model with some store-after-load= re-ordering */ #define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) =20 -#include "exec/cpu-all.h" - #define TARGET_INSN_START_EXTRA_WORDS 1 =20 #define MMU_MODE0_SUFFIX _primary @@ -796,4 +792,8 @@ void s390_init_sigp(void); /* outside of target/s390x/ */ S390CPU *s390_cpu_addr2state(uint16_t cpu_addr); =20 +typedef CPUS390XState CPUArchState; + +#include "exec/cpu-all.h" + #endif diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index 894b6c6df9..788de6e22a 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -36,8 +36,6 @@ #define SH_CPU_SH7750_ALL (SH_CPU_SH7750 | SH_CPU_SH7750S | SH_CPU_SH7750R) #define SH_CPU_SH7751_ALL (SH_CPU_SH7751 | SH_CPU_SH7751R) =20 -#define CPUArchState struct CPUSH4State - #define SR_MD 30 #define SR_RB 29 #define SR_BL 28 @@ -282,6 +280,8 @@ static inline int cpu_mmu_index (CPUSH4State *env, bool= ifetch) } } =20 +typedef CPUSH4State CPUArchState; + #include "exec/cpu-all.h" =20 /* Memory access type */ diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index a2975928d5..41c39578c2 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -14,8 +14,6 @@ #define TARGET_DPREGS 32 #endif =20 -#define CPUArchState struct CPUSPARCState - /*#define EXCP_INTERRUPT 0x100*/ =20 /* trap definitions */ @@ -731,6 +729,8 @@ static inline int cpu_pil_allowed(CPUSPARCState *env1, = int pil) #endif } =20 +typedef CPUSPARCState CPUArchState; + #include "exec/cpu-all.h" =20 #ifdef TARGET_SPARC64 diff --git a/target/tilegx/cpu.h b/target/tilegx/cpu.h index 429a6c6b43..2fbf14d508 100644 --- a/target/tilegx/cpu.h +++ b/target/tilegx/cpu.h @@ -23,8 +23,6 @@ #include "qemu-common.h" #include "exec/cpu-defs.h" =20 -#define CPUArchState struct CPUTLGState - /* TILE-Gx common register alias */ #define TILEGX_R_RE 0 /* 0 register, for function/syscall return val= ue */ #define TILEGX_R_ERR 1 /* 1 register, for syscall errno flag */ @@ -152,6 +150,8 @@ static inline TileGXCPU *tilegx_env_get_cpu(CPUTLGState= *env) /* TILE-Gx memory attributes */ #define MMU_USER_IDX 0 /* Current memory operation is in user mode */ =20 +typedef CPUTLGState CPUArchState; + #include "exec/cpu-all.h" =20 void tilegx_tcg_init(void); diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h index 67dc3b6272..c958deedd9 100644 --- a/target/tricore/cpu.h +++ b/target/tricore/cpu.h @@ -25,10 +25,6 @@ #include "exec/cpu-defs.h" #include "tricore-defs.h" =20 -#define CPUArchState struct CPUTriCoreState - -struct CPUTriCoreState; - struct tricore_boot_info; =20 typedef struct tricore_def_t tricore_def_t; @@ -383,7 +379,7 @@ static inline int cpu_mmu_index(CPUTriCoreState *env, b= ool ifetch) return 0; } =20 - +typedef CPUTriCoreState CPUArchState; =20 #include "exec/cpu-all.h" =20 diff --git a/target/unicore32/cpu.h b/target/unicore32/cpu.h index 9ee7798465..68323b9541 100644 --- a/target/unicore32/cpu.h +++ b/target/unicore32/cpu.h @@ -16,8 +16,6 @@ #include "cpu-qom.h" #include "exec/cpu-defs.h" =20 -#define CPUArchState struct CPUUniCore32State - typedef struct CPUUniCore32State { /* Regs for current mode. */ uint32_t regs[32]; @@ -154,6 +152,8 @@ static inline int cpu_mmu_index(CPUUniCore32State *env,= bool ifetch) return (env->uncached_asr & ASR_M) =3D=3D ASR_MODE_USER ? 1 : 0; } =20 +typedef CPUUniCore32State CPUArchState; + #include "exec/cpu-all.h" =20 #define UNICORE32_CPU_TYPE_SUFFIX "-" TYPE_UNICORE32_CPU diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 93440357b0..40e4f1f568 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -38,8 +38,6 @@ /* Xtensa processors have a weak memory model */ #define TCG_GUEST_DEFAULT_MO (0) =20 -#define CPUArchState struct CPUXtensaState - enum { /* Additional instructions */ XTENSA_OPTION_CODE_DENSITY, @@ -789,6 +787,8 @@ static inline void cpu_get_tb_cpu_state(CPUXtensaState = *env, target_ulong *pc, } } =20 +typedef CPUXtensaState CPUArchState; + #include "exec/cpu-all.h" =20 #endif --=20 2.17.1